US4949176A - Method and apparatus for DPCM video signal compression and transmission - Google Patents

Method and apparatus for DPCM video signal compression and transmission Download PDF

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US4949176A
US4949176A US07/167,186 US16718688A US4949176A US 4949176 A US4949176 A US 4949176A US 16718688 A US16718688 A US 16718688A US 4949176 A US4949176 A US 4949176A
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video signal
error
words
signal
input
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David F. Levy
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Sony Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/02—Delta modulation, i.e. one-bit differential modulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/124—Quantisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding

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  • This invention relates to differential pulse code modulation (DPCM) apparatus, and to methods of establishing the transfer function of a compressor in such apparatus.
  • DPCM differential pulse code modulation
  • DPCM offers the possibility of data rate reduction, when storing or transmitting a video signal.
  • a proposed digital slow motion processor is required to store several seconds of a video signal in random access memory. This involves a very large amount of data and requires a correspondingly large amount of random access memory. If the number of bits required to represent each picture element (pel) of the video signal could be reduced, without unacceptable degradation in the quality of the picture derIved from the reproduced video signal, then the amount of random access memory required could be reduced or the time duration of the stored video signal could be increased.
  • FIG. 1 of the accompanying drawings is a block diagram of a DPCM apparatus for processing an input video signal X(i), already in pulse code modulated (PCM) form, to produce a DPCM output video signal TX for storage (or transmission).
  • the input video signal X(i) comprises successive digital words, in this example 8-bit words, which represent successive samples and are obtained by sampling and pulse code modulating an analogue video signal. It is assumed that the bits of each word arrIve in parallel and are processed in parallel within the apparatus of FIG. 1. Accordingly, it is to be understood that the elements shown in FIG. 1 (and in the subsequent FIGS.) are, where approprIate, connected by multi-bit buses or highways.
  • DPCM relies on accurate prediction of each input sample of the input video signal X(i), based on one or more samples that have been previously received. (Some prediction schemes suitable for a video signal are described below.) A predicted value of each input sample is subtracted from the input sample and the resultant dIfference or error signal E(i) is compressed, and then stored or transmitted. A predicted value signal X(p), comprising successive predicted sample values which are to be subtracted from successive input samples is obtained from a predictor 1 by expanding the compressed error signal E(i), and adding the result to the predicted value signal X(p).
  • the predicted value sIgnal X(p) is subtracted from the input video signal X(i) in an error or difference signal generating means, which is in the form of a two-input adder 2 arranged to act as a subtractor, to produce the error signal E(i) which comprises a sequence of words each representing the error or difference between an input sample word of the input video signal X(i) and a predicted value of that input sample word.
  • the error signal E(i) is compressed by a compressor 3 to words of fewer bits to form the output video signal TX that can be stored or transmitted.
  • the output video signal TX is also passed to an expander 4, which simulates an expander provided in apparatus for receiving the output video signal TX, so as to produce a received vIdeo signal RX.
  • the received video signal RX is supplied to one input of a two-input adder 5.
  • the output of the adder 5, at which appears a received error sIgnal X(o) is connected to an input of the predictor 1.
  • the predictor 1 produces the predicted value signal X(p), which is supplied to the adder 2 so as to be subtracted from the input video signal X(i), and is also supplied to the other input of the adder 5 so as to be added lo the received video signal RX to produce the received error signal X(o).
  • the apparatus of FIG. 1 further comprises a clock pulse generator (not shown) which causes the above sequence of operatIons to be performed during each of a plurality of successive clock periods equal to the time spacing T of successive input sample words of the input video signal X(i).
  • a clock pulse generator (not shown) which causes the above sequence of operatIons to be performed during each of a plurality of successive clock periods equal to the time spacing T of successive input sample words of the input video signal X(i).
  • FIG. 2 of the accompanying drawings which is a block diagram of a modified DPCM apparatus for processing an input video signal X(i)
  • the compressor 3 and the expander 4 of the apparatus of FIG. 1 may be implemented together in the form of a compander 11 which compresses and expands the error signal E(i) to produce the received video signal RX.
  • This modified apparatus also requires a separate compressor 12, having characteristics similar to the compressor 3 of FIG. 1, for producing the output video signal TX.
  • one of the most important features is the characteristic of the compander 11, which characteristic is of course repeated in the combined effect of the compressor 12 and the associated expander in the receiving apparatus.
  • the video sIgnal represents a picture the spectral content of which is substantially unpredictable, and therefore a compander having a transfer function based on the spectral content of standard test pictures does not necessarily give a particularly good result.
  • One object of the present InventIon Is to provIde an Improved dIfferential pulse code modulation apparatus.
  • Another object of the present invention is to provide a differential pulse code modulation apparatus wherein the transfer function of a compander uses a minimized number of quantization levels.
  • Another object of the present invention is to provide an improved method of establishing the transfer function of a compressor in a differential pulse code modulation apparatus.
  • a differential pulse code modulation apparatus comprising: error signal generating means for receiving an input video signal comprising successive words representing video samples, and being operative to produce therefrom an error signal of which successive words each represent a difference between a word of the input video signal and a predicted value therefor;
  • adding means for adding successive words of the received video signal to successive words of a predicted value signal representing said predicted values to produce a received error sIgnal;
  • the transfer function of said means for compressing and expanding the error signal having been established in dependence on the minimum numbers of quantization levels required to quantize a picture element of a video signal without the quantization levels being visually apparent, for each of a range of input frequencies of said video signal.
  • FIGS. 1 and 2 are block diagrams of respective DPCM apparatus
  • FIG. 3 is a quantization graph of the number of quantizatIon levels requIred against input frequencies
  • FIG. 4 is a predictor error magnitude graph for full amplitude inputs against diagonal spatial frequencies
  • FIG. 5 is a step size graph of maximum required quantization step sizes against predictor errors
  • FIG. 6 is a diagram illustrating the construction of quantization steps for a compander
  • FIG. 7 is a diagram of the limit case of quantization steps for a compander
  • FIG. 8 shows diagrammatically part of a sample array of a video signal
  • FIGS. 9-1 through 9-3 are a composite computer-generated plot of predictor error against vertical and horizontal frequencies.
  • FIGS. 10 and 11 are block diagrams of respective embodiments of DPCM apparatus according to the present invention.
  • an extremely fast edge consisting of an instantaneous transition from black to white. This could in fact be represented by a single bit where, for example, ⁇ 0 ⁇ represents black and ⁇ 1 ⁇ represents white.
  • ⁇ 0 ⁇ represents black
  • ⁇ 1 ⁇ represents white.
  • a uniform transItIon from black to white extending over one complete horizontal line period. This might he considered as a ramp function with a period equal to one horizontal line period. It is generally accepted that to represent this requires eight bits, because approximately 256 different luminance levels are required to give the appearance to the human eye of a stepless transition from black to white.
  • the compander and the predictor should not be considered as separate units, because the performance of the predictor will affect the magnitude of the error signal E(i), depending on the direction of the spatial frequencies In the Image which the video signal represents. Because of this it is preferable for the characteristics of the compander to be matched to the predictor's worst case direction of prediction.
  • FIG. 4 is a predictor error magnitude graph showing the magnitude of the maximum error along the diagonal axis of a two-dimensional predictor simulation (described below in connection with FIG. 9). The maximum error percentages are plotted as ordinates against diagonal frequencies as a fraction of the sampling frequency Fs as abscissae.
  • a step size graph for the compander is generated as shown in FIG. 5.
  • This division causes the predictor errors expressed as percentages to become the abscissae, and the ordinates are the required maximum quantization step sizes required in the compander for a given predictor error.
  • the graph of FIG. 5 indicates the number of quantization levels required in the compander for a given predictor error, and the predictor error is known because it is proportional, according to the law of FIG. 4, to the input frequency. For example, as indicated by the dotted lines in FIG. 5, when the predictor error is 50%, then approximately thirtyfive quantization levels are required in the compander.
  • the step size graph of FIG. 5 is then used to desIgn the required limit case compander in which the quantizatIon effect due to the reduction in the number of bits should be just masked by the effect of high spatial frequency.
  • the error signal E(i) supplied to the compander 11 can have any value in the range, in hexadecimal, of minus FF or plus FF.
  • the top graph is the step size graph of FIG. 5 with the ordinates compressed. Below this is a graph of the compander characteristic with outputs shown as ordinates and inputs shown as abscissae, both being in hexadecimal.
  • the output must be FF and the steps must follow the straight line from the point FF/FF back to the origin.
  • the maximum step size graph at the top of FIG. 6 is therefore scaled by multiplying each value by the same number, and the above method is repeated with the object of reducing the number of steps to 32 or just below, which can be represented by five bits.
  • scaling can be effected to enable the compander output to be represented by some different number of bits such as three or four, although it should be understood that such compression cannot be achieved without a greater degradation in picture quality.
  • a table is generated showing how any input error signal in the range +255 to -255 is to be converted to one of (say) 32 outputs which are designated 0 to 31 and represented by a 5-bit output.
  • the compressor 12 of FIG. 2 is therefore implemented as a memory, preferably a programmable read-only memory (PROM), holding a look-up table, and which on receiving an 8-bit input in the (decimal) range -255 to +255 converts this to a 5-bit output.
  • the compander 11 of FIG. 2 is implemented as a like PROM plus a further PROM holding a look-up table, and which on receiving a 5-bit input supplies the corresponding 8-bIt output.
  • a PROM similar to this latter PROM in the compander 11 is provIded in the apparatus receiving the received video signal TX.
  • the predictor 1 of FIGS. 1 and 2 will now he further considered.
  • the predictor 1 has to predict the value of each input sample of the input video signal X(i), based on one or more samples that have been previously received.
  • the options available are to use previous samples In one or two spatial dimensions, with or without samples from the temporal dimension, that is, from a previous field or fields. For simplicity only predictors using previous samples In one or two spatial dImensIons will be considered here, although it will readily be understood that the invention can be applied to DPCM apparatus using other predictors.
  • FIG. 8 shows diagrammatically part of a sample array of a video signal. If x is the sample to be predicted then a one-dimensional predictor may take:
  • a two-dimensional predictor may, for example, take:
  • the predictor output can lie outside the normal sample range (0 to 255) and provision needs to be made for dealing with any such overflow or underflow.
  • each number represents the centre point of a range. For example 0 is 0 to 5% error, 3 is 25 to 35% error, and A is 95 to 100% error. A cross-section from the origin to the point of maximum error gives the predictor error magnitude graph shown in FIG. 4.
  • the loop calculation time that Is the time taken to perform the series of operatIons performed upon the arrival of each word of the input video signal X(i), must not exceed the data period of the signal X(i), namely the spacing T of the words of the input video signal X(i).
  • the critical path that determines the loop calculation time is represented in FIGS. 1 and 2 by hatched lines.
  • the loop calculation time is governed by the times involved in performing the addition operations in the adders 2 and 5, the time involved in reading the PROMs, and the time delay in the predictor 1.
  • each predicted input sample value is the received previous value
  • the predictor 1 is a delay element which imposes a delay, represented mathematically as Z -1 , equal to the spacing T.
  • the delay element is a latch (more specifically, a group of parallel-operating latches equal in number to the number of bits in each input word) triggered at the spacing T.
  • the loop calculation time is governed by the times involved in performing the addition operations in the adders 2 and 5, the time involved in reading the PROMs, and the set-up and propagation times of the latch used for the predictor 1. If, for example, the DPCM apparatus In FIG.
  • TTL transistor-transistor logic
  • the predictor 1 will be of more complex form using several previous samples. This introduces further elements into the critical path, thus increasing the loop calculation time.
  • FIG. 10 shows an embodiment of DPCM apparatus with the predictor 1 shown implemented in a generalised way for using a plurality (n+1) of previous samples to produce each predicted sample value.
  • the predictor 1 is shoWn as comprising (n+1) latches (Z -1 delay elements) LO to Ln connected in tandem.
  • An output of each of the latches LO to Ln is connected to a respective one of (n+1) multipliers MO to Mn in which a sample transmitted from the associated latch is multiplied by a respective one of (n+1) multi-bit weighting coefficients ko to kn before being passed to a summing means 31.
  • the summing means 31 adds together the (n+1) inputs it receives from the multipliers MO to Mn to produce the predicted value signal X(p).
  • the predictor 1 of FIG. 10 functions as follows. During successive clock periods, samples arriving from the adder 5 are stepped through the latches LO to Ln In a manner resembling the operation of a shift register. Thus, at any time, the latches LO to Ln hold the previous (n+1) samples of the received error signal X(o) from the adder 5. During each clock period, the contents of all of the latches LO to Ln are read into the multipliers MO to Mn and multiplied therein by the respective weighting coefficients ko to kn, the values of which are selected to weight the (n+1) samples so as to give a desired prediction characteristic. The resultant (n+1) product words or samples from the multipliers MO to Mn are passed to the summing means 31 and, still during the same clock period, are all summed together to produce a single predicted sample of the predicted sample signal X(p).
  • the number of latches (Z -1 delay elements) In the predictor 1 can be chosen at will In accordance with the desIred accuracy of prediction.
  • the predIctor 1 of FIG. 10 resembles a finite impulse response (FIR) filter as employed in image signal processing, and known techniques for designing such filters may be used in implementing the predictor 1 of FIG. 10.
  • FIR finite impulse response
  • the critical path for the loop calculation time is shown by hatched lines.
  • Weighting coefficients ko and kn are binary coefficients, that is, have a value 2 p where p is an integer.
  • p is an integer.
  • the binary coefficient may be fractional or greater than unity, the range for p (in the case of an 8-bit word) being from -7 to +.
  • the time taken in the summing means 31 to add together the (n+1) products is generally significantly greater than the time taken for effecting multiplication, even when the weighting coefficients are non-binary, and therefore generally has a greater adverse effect on the loop calculation time.
  • the reason for this is that the summing means 31 has to be constituted, when the number of samples processed by the predictor 1 is greater than two, by an assembly of adders which each can add only two words, and at least some of these adders have to operate in sequence within the same clock period.
  • FIG. 11 An embodIment of DPCM apparatus according to the present invention and comprising such a predIctor is shown in FIG. 11 and includes a predictor 41 which, like the predictor 1 of the apparatus of FIG. 10, comprises latches LO to Ln and multipliers Mo to Mn supplied with respective weighting coefficients ko to kn.
  • the predictor 41 further comprises adders AO, A1, A2, A3, etc. As shown in FIG. 11, the adders AO, etc., the multipliers MO, etc. and the latches (delay elements) L1, etc. are arranged so as to form a ladder network.
  • the received error signal X(o) is applied via the latch LO to a first side of the ladder network such that each word from the latch LO is applied simultaneously to all of the multipliers MO etc., which are arranged in the rungs of the ladder network.
  • the adders AO, etc. are arranged at the nodes of the second side of the ladder network and the latches L1, etc. are arranged between the adders in the second side of the ladder network.
  • the same word of the received error signal X(o), as supplied by the latch LO, is supplied to and weighted by each of the multipliers MO, etc.
  • the weighted words are added in the adders AO, etc. (which operate substantially simultaneously with one another) to a word stored in the latches L1, etc. during a previous clock cycle.
  • each weighted word works its way along the upper half of the ladder network from left to right in FIG. 11, it has added thereto, during each successive clock cycle, a weighted word from a subsequent clock cycle.
  • the output word produced by the predictor 41 (that Is, from the adder AO) Is the result of addition, with appropriate weighting, of input words received during the appropriate number of previous clock periods. That is, as in FIG. 10, each word produced by the predictor 41 (from the adder AO) is a predicted value of an input word based upon a plurality of successive words of the received error signal X(o).
  • the various addition steps have been performed during a succession of clock cycles as the word was stepped along the ladder network, by the simultaneously operated adders A0, etc., instead of being performed sequentially at the end of each clock cycle.
  • the critical path corresponding to the loop calculation time is depicted in FIG. 11 by hatched lines.
  • the loop calculation time is governed by the times involved in performing the addition operations in the adders 2 and 5, the time involved in reading the PROM of the compander 11 and the set-up and propagation times of a single latch, namely the latch LO. Additionally, the loop calculation time is governed by the times taken for the operation of a single multiplier (the multiplier MO) and a single adder (the adder AO).
  • the loop calculation time of around 70 ns in the case of the simple (one latch) predictor is increased, in the case of FIG. 11, to around 90 ns If the weighting coefficients are binary and to somewhere over 100 ns if the weighting coefficients are non binary. Note, however, that the loop calculation time is not, in contrast to FIG. 10, increased as the number of taps (that is, the number of samples of the received error word used to calculate each predicted value) is increased.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
US07/167,186 1987-03-30 1988-03-11 Method and apparatus for DPCM video signal compression and transmission Expired - Lifetime US4949176A (en)

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GB8707556A GB2203012B (en) 1987-03-30 1987-03-30 Differential pulse code modulation
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JP (1) JPS63253786A (de)
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Cited By (6)

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Publication number Priority date Publication date Assignee Title
US5159448A (en) * 1990-11-20 1992-10-27 Sony Corporation Highly efficient coding apparatus
US5262878A (en) * 1991-06-14 1993-11-16 General Instrument Corporation Method and apparatus for compressing digital still picture signals
US5357278A (en) * 1993-01-14 1994-10-18 Sony Electronics, Inc. Integrated linear/non-linear static and controllable dynamic companding
US5436732A (en) * 1991-09-26 1995-07-25 Fuji Xerox Co., Ltd. Image data processing system
US5469517A (en) * 1992-01-21 1995-11-21 Nec Corporation Motion compensation circuit
EP0779742A3 (de) * 1995-12-12 1997-12-03 RCA Thomson Licensing Corporation Geräuschschätzungs- und Geräuschreduzierungsgerät zur Videosignalverarbeitung

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GB8826463D0 (en) * 1988-11-11 1988-12-14 Rca Licensing Corp Technique for actv side-panel noise reduction
US5005082A (en) * 1989-10-03 1991-04-02 General Electric Company Video signal compander adaptively responsive to predictions of the video signal processed
US5258928A (en) * 1990-05-03 1993-11-02 Rca Thomson Licensing Corporation Parts efficient memory based functional circuit having selectable transfer characteristics
US5122868A (en) * 1990-10-18 1992-06-16 General Electric Company Side panel signal processor for a widescreen television system
US5237591A (en) * 1991-08-19 1993-08-17 At&T Bell Laboratories Circuit for digitally adding loss to a signal

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US4519085A (en) * 1981-10-27 1985-05-21 Thomson-Csf Differential data coding and decoding process and system restricting propagation of transmission errors
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US4742391A (en) * 1987-01-16 1988-05-03 Cubic Corporation DPCM video signal compression and transmission system and method
US4788692A (en) * 1985-06-20 1988-11-29 Fujitsu Limited Adaptive differential pulse code modulation system
US4791483A (en) * 1987-11-20 1988-12-13 The Grass Valley Group, Inc. Adaptive differential pulse code modulation video encoder
US4831636A (en) * 1985-06-28 1989-05-16 Fujitsu Limited Coding transmission equipment for carrying out coding with adaptive quantization

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US4519085A (en) * 1981-10-27 1985-05-21 Thomson-Csf Differential data coding and decoding process and system restricting propagation of transmission errors
US4788692A (en) * 1985-06-20 1988-11-29 Fujitsu Limited Adaptive differential pulse code modulation system
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Cited By (7)

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Publication number Priority date Publication date Assignee Title
US5159448A (en) * 1990-11-20 1992-10-27 Sony Corporation Highly efficient coding apparatus
US5262878A (en) * 1991-06-14 1993-11-16 General Instrument Corporation Method and apparatus for compressing digital still picture signals
US5436732A (en) * 1991-09-26 1995-07-25 Fuji Xerox Co., Ltd. Image data processing system
US5469517A (en) * 1992-01-21 1995-11-21 Nec Corporation Motion compensation circuit
US5357278A (en) * 1993-01-14 1994-10-18 Sony Electronics, Inc. Integrated linear/non-linear static and controllable dynamic companding
US6285710B1 (en) 1993-10-13 2001-09-04 Thomson Licensing S.A. Noise estimation and reduction apparatus for video signal processing
EP0779742A3 (de) * 1995-12-12 1997-12-03 RCA Thomson Licensing Corporation Geräuschschätzungs- und Geräuschreduzierungsgerät zur Videosignalverarbeitung

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GB2203012B (en) 1991-02-20
FR2613559A1 (fr) 1988-10-07
GB2203012A (en) 1988-10-05
FR2613559B1 (fr) 1996-06-07
DE3810916A1 (de) 1988-10-13
KR950012979B1 (ko) 1995-10-24
JPS63253786A (ja) 1988-10-20
DE3810916C2 (de) 1997-03-13
GB8707556D0 (en) 1987-05-07
KR880012022A (ko) 1988-10-31

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