US4870372A - AGC delay on an integrated circuit - Google Patents

AGC delay on an integrated circuit Download PDF

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Publication number
US4870372A
US4870372A US07/196,946 US19694688A US4870372A US 4870372 A US4870372 A US 4870372A US 19694688 A US19694688 A US 19694688A US 4870372 A US4870372 A US 4870372A
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United States
Prior art keywords
transistors
signal
agc
circuit
amplifier
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Expired - Lifetime
Application number
US07/196,946
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English (en)
Inventor
Richard R. Suter
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Seiko Instruments Inc
Cufer Asset Ltd LLC
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AT&E Corp
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Priority to US07/196,946 priority Critical patent/US4870372A/en
Assigned to AT&E CORPORATION, A CORP. OF DE reassignment AT&E CORPORATION, A CORP. OF DE ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: SUTER, RICHARD R.
Priority to CA000600010A priority patent/CA1323659C/en
Priority to AU34916/89A priority patent/AU608198B2/en
Priority to EP19890108945 priority patent/EP0342671A3/de
Priority to JP1124645A priority patent/JPH0222906A/ja
Application granted granted Critical
Publication of US4870372A publication Critical patent/US4870372A/en
Assigned to SEIKO CORPORATION reassignment SEIKO CORPORATION SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: AT & E CORPORATION, A CORP. OF DE
Assigned to SEIKO EPSON CORPORATION reassignment SEIKO EPSON CORPORATION SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: AT&E CORPORATION, A CORPORATION OF DELAWARE
Assigned to SEIKO EPSON CORPORATION, SEIKO CORPORATION reassignment SEIKO EPSON CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: AT&E CORPORATION
Assigned to SEIKO INSTRUMENTS INC. reassignment SEIKO INSTRUMENTS INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SEIKO EPSON CORPORATION, SEIKO CORPORATION
Anticipated expiration legal-status Critical
Assigned to SEIKO INSTRUMENTS INC. reassignment SEIKO INSTRUMENTS INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SEIKO EPSON CORPORATION, SEIKO HOLDINGS CORPORATION
Assigned to SEIKO HOLDINGS CORPORATION reassignment SEIKO HOLDINGS CORPORATION CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: SEIKO CORPORATION
Assigned to PROTOCOL-IP.COM, L.L.C. reassignment PROTOCOL-IP.COM, L.L.C. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SEIKO INSTRUMENTS INC.
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/20—Automatic control
    • H03G3/30—Automatic control in amplifiers having semiconductor devices
    • H03G3/3052—Automatic control in amplifiers having semiconductor devices in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver
    • H03G3/3068—Circuits generating control signals for both R.F. and I.F. stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G1/00—Details of arrangements for controlling amplification
    • H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
    • H03G1/0017—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid-state elements
    • H03G1/0023—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid-state elements in emitter-coupled or cascode amplifiers

Definitions

  • the present invention relates to radio receivers, and more particularly relates to the automatic gain control (AGC) circuitry used in such receivers.
  • AGC automatic gain control
  • Radio receivers and amplifiers have an AGC feature for reducing the amplification of one or more gain stages to compensate for the varying levels of signal intensity that may be received.
  • AGC circuits permit modern receivers to have dynamic ranges in excess of 100 dB.
  • the noise figure of the receiver becomes an important consideration.
  • the receiver noise figure is most directly affected by the gain of the receiver front end. Consequently, it is desirable to operate the front ends of sensitive receivers at maximum gains and to gain control subsequent stages. Only after the received signal strength is so large that noise figure is not an important issue should gain reduction occur in the front end stage.
  • a representative AGC control circuit may include two transistors in a differential common-emitter configuration. The bases of the transistors are driven from a signal related to the amplitude of signal being received by the receiver. The collectors of the transistors provide a differential AGC output signal controllably offset from the input signal by a voltage determined by the area ratio between the two transistors.
  • the differential configuration is preferably employed to reject common mode signals and thus to improve noise immunity.
  • FIG. 1 is a block diagram showing an exemplary receiver configuration employing the AGC control system of the present invention.
  • FIG. 2 is a chart showing gain reduction in first and second cascaded gain stages as a function of received signal strength in a receiver using an AGC circuit according to the present invention.
  • FIG. 3 is an electrical schematic diagram of an AGC circuit according to the present invention.
  • FIG. 4 is an alternative receiver configuration employing an AGC system according to the present invention.
  • FIG. 5 is an electrical schematic diagram showing AGC circuitry to control two stages independently.
  • FIG. 6 is a schematic diagram showing the AGC circuitry of the present invention fabricated in integrated circuit form.
  • a basic receiver topology which includes first and second cascaded amplifier stages 10, 12
  • amplifier 10 may be the RF front end stage and amplifier 12 may be one or more amplifiers in the IF amplifier. Coupled to an output 14 of amplifier 12 is an amplitude detector stage 16. Amplitude detector stage 16 produces a differential output signal on first and second output lines 18, 20, the magnitude of which is related to the amplitude of the signal output from amplifier stage 12.
  • the output signal provided on lines 18 and 20 is applied directly to an AGC input 22 of second amplifier stage 12.
  • the gain of second amplifier stage 12 decreases, thereby reducing fluctuations in the output signal provided to line 14.
  • the amplifier stages 10, 12 are designed to begin substantial gain reductions when the AGC voltages applied thereto exceed zero volts.
  • the gain at zero volts AGC may be from zero to three dB below maximum, a value still considered relatively insignificant.
  • the gain of second amplifier stage 12 be reduced prior to the reduction of gain in amplifier stage 10 if system noise figure is to be optimized.
  • the chart shown in FIG. 2 illustrates an exemplary relationship between the AGC signals applied to the first and second amplifier stages to accomplish this effect.
  • the first amplifier stage 10 does not have any significant gain reduction when the signal from amplitude detector 16 is below a threshold indicated as V o .
  • the second amplifier stage 12 steadily reduces its gain as the signal from amplitude detector 16 increases.
  • first amplifier 10 operates at substantially full gain until the received signal strength is large enough that system noise figure is not important. Only after the signal exceeds the threshold indicated by V o do both amplifier stages reduce gain.
  • the slope of the line indicating the gain reduction in second amplifier 12 is solely a function of the amplifier's response to AGC signals.
  • the slope of the line indicating the gain reduction in first amplifier 10 can be controlled by the transfer characteristics of the AGC control circuit that provides the AGC voltage to the first amplifier.
  • second amplifier stage 12 begins AGC control without any threshold.
  • An AGC control circuit 24, however, is connected to lines 18 and 20 and delays the onset of significant gain reduction in first amplifier stage 10 until the signal from amplitude detector 16 exceeds the threshold V o shown in the chart of FIG. 2.
  • FIG. 3 shows an electrical schematic representation of AGC control circuit 24.
  • This circuit comprises first and second transistors 26, 28 arranged in a differential configuration with an optional gain setting element 29 coupling the emitters.
  • the bases of transistors 26, 28 are driven from lines 18, 20 from amplitude detector 16.
  • the AGC output signals are provided from the transistor collectors to output lines 30, 32.
  • the circuitry is symmetrical, producing a mirroring of the currents in the two complementary halves 34, 36.
  • the complementary halves are not identical. Instead, in the preferred embodiment, one of transistors 26, 28 has a saturation current different from the other.
  • V t is a thermal voltage constant (0.026 volts at room temperature)
  • I c is collector current
  • I s is the saturation current of the transistor device. Since the difference in voltage between lines 18 and 20 is equal to the difference in V be between transistors 26 and 28, the above equation makes clear that:
  • the collector currents of transistors 26 and 28 must be equal (assuming the circuits 34, 36 are otherwise identical). The collector currents will be equal when the differential voltage applied on lines 18, 20 is equal to the ⁇ V be value above.
  • the signal applied to input lines 18, 20 required to produce a zero volt output signal on lines 30, 32 is eighteen millivolts.
  • an AGC signal of up to eighteen millivolts can be present on lines 18, 20 (and thus applied to reduce the gain of second amplifier stage 12) before the AGC signal applied to first amplifier stage 10 rises above zero volts.
  • AGC action in the two stages is staggered relative to each other as a function of received signal strength.
  • second amplifier stage 12 is AGC controlled directly from the output of amplitude detector 16.
  • second amplifier stage 12 will begin gain reduction when any signal is present.
  • gain stage 12 can be designed to ignore AGC signals below a predetermined threshold.
  • An alternative approach is to include an AGC control circuit such as that illustrated in FIG. 3 within amplitude detector 16 so that a gain reducing signal does not appear on lines 18 and 20 until the amplitude of signal output by second amplifier 12 exceeds a predetermined threshold.
  • Illustrated AGC control circuit 24 can then be cascaded onto the output of the AGC control circuit in the amplitude detector 16.
  • Still another technique for effecting the AGC staggering result is to use the arrangement shown in FIG. 4.
  • the output signal on lines 18, 20 from amplitude detector 16 is not applied directly to AGC inputs 22 of second amplifier stage 12.
  • an AGC control circuit 24' such as that shown in FIG. 3, is interposed.
  • AGC control circuit 24' can be designed, for example, with a 2:1 area ratio so that the circuit does not provide a gain-reducing signal to second amplifier stage 12 until the signal on lines 18, 20 exceeds eighteen millivolts.
  • a separate AGC control circuit 24" can be interposed between lines 18, 20 and the AGC inputs 46 of first amplifier stage 10.
  • AGC control circuit 24" should have an area ratio in excess of the 2:1 ratio used by stage 24' so that a gain-reducing signal is not applied to the first amplifier stage 10 until the signal on lines 18, 20 exceeds, for example, 50 millivolts.
  • the AGC control circuit of FIG. 3 can be replicated as many time as there are stages needing different AGC voltages, the circuit of FIG. 5 can alternatively be used. It will be recognized that the transistors Q 1 and Q 2 in FIG. 5 are arranged in substantially the same fashion as are the transistors in FIG. 3. The AGC control voltage for the first gain-controlled stage is taken from their output terminals.
  • a second AGC voltage is produced in FIG. 5 by making a double use of Q 2 . That is, a second AGC control circuit is formed simply by adding one more transistor, Q 3 , to the circuit and taking the second AGC voltage from the outputs of Q 2 and Q 3 . (This arrangement assumes, of course, that the current drawn by the gain-controlled amplifiers from the AGC lines is negligible so as to not upset circuit operation).
  • the topology used in FIG. 5 again is shown with an optional gain determining resistor R gain1 interposed between the emitters of transistors Q 1 and Q 2 .
  • the ratio of the load resistors Z L1 , Z L2 to R gain1 can be selected to control the slope of the gain reduction curve (i.e. such as those shown in FIG. 2), and thus the rate at which gain reduction occurs for a given change in received signal strength.
  • FM communications receivers are typically not gain controlled. Instead, their amplifiers are run at maximum amplification and gain control is effected by hard clipping or limiting of the amplified signal. It has been found in the present application, which uses a relatively small aperture antenna in a wristwatch paging receiver, that the effects of multipath are minimized if the receiver is gain controlled rather than relying on typical FM limiter technology.
  • the preferred embodiment of the invention is to use integrated circuit construction on a common substrate.
  • IC fabrication techniques do not allow precise control over individual component characteristics, very good control can be obtained between the ratios of certain components. It is the controlled ratioing between components that permits the characteristics of the present invention to be accurately tailored, not the absolute value of any component per se.
  • the present invention can accurately and repeatably sequence the onset of gain reduction in a series of gain controlled amplifiers implemented on an integrated circuit for the purpose of maximizing the dynamic range of the resultant amplifier chain. This sequencing, or delaying the onset of gain reduction to the input stage.

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  • Control Of Amplification And Gain Control (AREA)
  • Circuits Of Receivers In General (AREA)
US07/196,946 1988-05-20 1988-05-20 AGC delay on an integrated circuit Expired - Lifetime US4870372A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US07/196,946 US4870372A (en) 1988-05-20 1988-05-20 AGC delay on an integrated circuit
CA000600010A CA1323659C (en) 1988-05-20 1989-05-17 Agc delay on an integrated circuit
AU34916/89A AU608198B2 (en) 1988-05-20 1989-05-18 Agc delay on an integrated circuit
EP19890108945 EP0342671A3 (de) 1988-05-20 1989-05-18 Automatische Verstärkungsregelung mit Verzögerung auf einer integrierten Schaltung
JP1124645A JPH0222906A (ja) 1988-05-20 1989-05-19 Ａｇｃ回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/196,946 US4870372A (en) 1988-05-20 1988-05-20 AGC delay on an integrated circuit

Publications (1)

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US4870372A true US4870372A (en) 1989-09-26

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Family Applications (1)

Application Number Title Priority Date Filing Date
US07/196,946 Expired - Lifetime US4870372A (en) 1988-05-20 1988-05-20 AGC delay on an integrated circuit

Country Status (5)

Country Link
US (1) US4870372A (de)
EP (1) EP0342671A3 (de)
JP (1) JPH0222906A (de)
AU (1) AU608198B2 (de)
CA (1) CA1323659C (de)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5126688A (en) * 1990-03-20 1992-06-30 Oki Electric Co., Ltd. Power amplifying apparatus for wireless transmitter
US6009129A (en) * 1997-02-28 1999-12-28 Nokia Mobile Phones Device and method for detection and reduction of intermodulation distortion
US6559717B1 (en) * 2001-06-13 2003-05-06 Lsi Logic Corporation Method and/or architecture for implementing a variable gain amplifier control
US20040105033A1 (en) * 2002-12-02 2004-06-03 Broadcom Corporation Amplifier assembly including variable gain amplifier, parallel programmable amplifiers, and AGC
US20050130617A1 (en) * 2002-12-02 2005-06-16 Broadcom Corporation Variable-gain low noise amplifier for digital terrestrial applications
US20060132235A1 (en) * 2002-08-06 2006-06-22 Sony Corporation Gain-controlled amplifier, receiver circuit and radio communication device
US7183845B2 (en) 2002-12-02 2007-02-27 Broadcom Corporation Gain control methods and systems in an amplifier assembly
US20100073572A1 (en) * 2002-12-02 2010-03-25 Broadcom Corporation Variable-gain low noise amplifier for digital terrestrial applications
CN101072058B (zh) * 1994-12-16 2011-01-19 高通股份有限公司 提高接收机抗扰度的装置和接收机电路
US9000845B2 (en) 2012-10-26 2015-04-07 Em Microelectronic-Marin S.A. Automatic gain control electronic circuit with dual slope for an amplifier

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE59108179D1 (de) * 1991-02-05 1996-10-17 Siemens Ag Integrierbare Schaltungsanordnung zum Detektieren eines Nutzsignales innerhalb eines verrauschten Eingangssignales
US5637140A (en) * 1995-06-21 1997-06-10 Brother Kogyo Kabushiki Kaisha Water-based ink composition and ink-jet recording process
IL129261A (en) * 1996-09-30 2003-09-17 Qualcomm Inc Method and apparatus for increasing receiver immunity to interference
CN1103135C (zh) * 1997-09-30 2003-03-12 夸尔柯姆股份有限公司 用于增加接收机抗干扰性的方法和装置
JP2003008371A (ja) * 2001-06-19 2003-01-10 Sony Corp Ｒｓｓｉ回路

Citations (4)

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Publication number Priority date Publication date Assignee Title
US4152667A (en) * 1976-12-29 1979-05-01 U.S. Philips Corporation Gain-controlled signal amplifier
US4327333A (en) * 1980-03-17 1982-04-27 National Semiconductor Corporation AGC Current source
US4563597A (en) * 1982-11-22 1986-01-07 Honeywell Inc. Accurate dead band control circuit
US4746873A (en) * 1985-08-22 1988-05-24 Plessey Overseas Limited FM demodulators

Family Cites Families (5)

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Publication number Priority date Publication date Assignee Title
NL170084C (nl) * 1971-03-06 1982-09-16 Philips Nv Televisieontvanger met een geintegreerde schakeling voor het leveren van twee versterkingsregelspanningen.
JPS5684012A (en) * 1979-12-12 1981-07-09 Hitachi Ltd Agc circuit
JPS5922415A (ja) * 1982-07-28 1984-02-04 Fujitsu Ten Ltd 自動利得制御回路
NL8400495A (nl) * 1984-02-16 1985-09-16 Philips Nv In versterking geregelde versterkerinrichting.
JPS60121809A (ja) * 1984-11-12 1985-06-29 Hitachi Ltd 受信機

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4152667A (en) * 1976-12-29 1979-05-01 U.S. Philips Corporation Gain-controlled signal amplifier
US4327333A (en) * 1980-03-17 1982-04-27 National Semiconductor Corporation AGC Current source
US4563597A (en) * 1982-11-22 1986-01-07 Honeywell Inc. Accurate dead band control circuit
US4746873A (en) * 1985-08-22 1988-05-24 Plessey Overseas Limited FM demodulators

Cited By (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5126688A (en) * 1990-03-20 1992-06-30 Oki Electric Co., Ltd. Power amplifying apparatus for wireless transmitter
CN101072058B (zh) * 1994-12-16 2011-01-19 高通股份有限公司 提高接收机抗扰度的装置和接收机电路
US6009129A (en) * 1997-02-28 1999-12-28 Nokia Mobile Phones Device and method for detection and reduction of intermodulation distortion
US6559717B1 (en) * 2001-06-13 2003-05-06 Lsi Logic Corporation Method and/or architecture for implementing a variable gain amplifier control
US20060132235A1 (en) * 2002-08-06 2006-06-22 Sony Corporation Gain-controlled amplifier, receiver circuit and radio communication device
US7196579B2 (en) * 2002-08-06 2007-03-27 Sony Corporation Gain-controlled amplifier, receiver circuit and radio communication device
US20090040059A1 (en) * 2002-12-02 2009-02-12 Broadcom Corporation Apparatus to Monitor Process-Based Parameters of an Integrated Circuit (IC) Substrate
US7634244B2 (en) 2002-12-02 2009-12-15 Broadcom Corporation Variable-gain low noise amplifier for digital terrestrial applications
US20050208910A1 (en) * 2002-12-02 2005-09-22 Broadcom Corporation Variable-gain low noise amplifier for digital terrestrial applications
US20070159244A1 (en) * 2002-12-02 2007-07-12 Broadcom Corporation Gain control methods and systems in an amplifier assembly
US7260377B2 (en) 2002-12-02 2007-08-21 Broadcom Corporation Variable-gain low noise amplifier for digital terrestrial applications
US7471941B2 (en) * 2002-12-02 2008-12-30 Broadcom Corporation Amplifier assembly including variable gain amplifier, parallel programmable amplifiers, and AGC
US20050130617A1 (en) * 2002-12-02 2005-06-16 Broadcom Corporation Variable-gain low noise amplifier for digital terrestrial applications
US7501888B2 (en) 2002-12-02 2009-03-10 Broadcom Corporation Gain control methods and systems in an amplifier assembly
US20090066414A1 (en) * 2002-12-02 2009-03-12 Broadcom Corporation Gain control methods and systems in an amplifier assembly
US7183845B2 (en) 2002-12-02 2007-02-27 Broadcom Corporation Gain control methods and systems in an amplifier assembly
US20100073572A1 (en) * 2002-12-02 2010-03-25 Broadcom Corporation Variable-gain low noise amplifier for digital terrestrial applications
US7791412B2 (en) 2002-12-02 2010-09-07 Broadcom Corporation Gain control methods and systems in an amplifier assembly
US20100277235A1 (en) * 2002-12-02 2010-11-04 Broadcom Corporation Gain Control Methods and Systems in an Amplifier Assembly
US20040105033A1 (en) * 2002-12-02 2004-06-03 Broadcom Corporation Amplifier assembly including variable gain amplifier, parallel programmable amplifiers, and AGC
US7969241B2 (en) 2002-12-02 2011-06-28 Broadcom Corporation Gain control methods and systems in an amplifier assembly
US8094033B2 (en) 2002-12-02 2012-01-10 Broadcom Corporation Apparatus to monitor process-based parameters of an integrated circuit (IC) substrate
US8437720B2 (en) 2002-12-02 2013-05-07 Broadcom Corporation Variable-gain low noise amplifier for digital terrestrial applications
US9000845B2 (en) 2012-10-26 2015-04-07 Em Microelectronic-Marin S.A. Automatic gain control electronic circuit with dual slope for an amplifier

Also Published As

Publication number Publication date
CA1323659C (en) 1993-10-26
AU608198B2 (en) 1991-03-21
EP0342671A3 (de) 1991-03-06
JPH0222906A (ja) 1990-01-25
AU3491689A (en) 1989-11-23
EP0342671A2 (de) 1989-11-23

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