US4789560A - Diffusion stop method for forming silicon oxide during the fabrication of IC devices - Google Patents

Diffusion stop method for forming silicon oxide during the fabrication of IC devices Download PDF

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US4789560A
US4789560A US06/817,233 US81723386A US4789560A US 4789560 A US4789560 A US 4789560A US 81723386 A US81723386 A US 81723386A US 4789560 A US4789560 A US 4789560A
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silicon
oxide
nitride
temperature
oxidation
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Yung-Chau Yen
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Assigned to ADVANCED MICRO DEVICES, INC., A CORP. OF DE. reassignment ADVANCED MICRO DEVICES, INC., A CORP. OF DE. ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: YEN, YUNG-CHAU
Priority to AT86310234T priority patent/ATE196215T1/de
Priority to DE3650747T priority patent/DE3650747T2/de
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Definitions

  • This invention relates to forming silicon oxide from poly-crystalline silicon during the fabrication of integrated circuits, and more particularly to the use of silicon nitride as a diffusion stop.
  • silicon material (either single crystal or poly-crystalline) is converted to silicon oxide insulation material by exposure to oxygen at elevated temperatures. Oxygen reacts with the surface silicon forming silicon oxide (oxide). The oxygen diffuses through this oxide to form more oxide. The silicon is progressively oxidized from the surface inward.
  • An oxide/silicon interface exists between the oxide and the silicon.
  • the interface defines the furthest extent of the oxygen diffusion and oxidation into the interior of the silicon, and therefore is generally oxygen "poor".
  • the limited oxygen condition results in partially oxidized silicon and imperfect oxidation bonds proximate the interface.
  • the interface advances into the silicon as the oxidation step proceeds in the conventional fabrication, and is present in the finished conventional device.
  • the incomplete oxidation results in "loose chemical bonds" which support leakage and breakdown paths during the operation of the device.
  • the conventional oxidation technique does not employ the present silicon nitride diffusion stop.
  • the extent of the silicon to oxide conversion is therefore time and temperature dependent. If the oxidation step is too short or the temperature too low, the resulting oxide layer is thinner than expected. If the oxidation step is too long or the temperature too high, the resulting oxide layer is thicker than expected.
  • the conventional oxidation of single crystal silicon material has additional problems which are overcome by the present nitride diffusion stop.
  • the dopant concentration within the substance portion of each wafer varies slightly from wafer to wafer.
  • the oxidation rate of the substrate silicon is dependent on this dopant concentration, resulting in a non-uniform oxide thickness from wafer to wafer. Wafers with a higher dopant concentration will undergo more oxide conversion than lower dopant wafers during the same oxidation time period.
  • the substrate oxide will be thicker on these higher dopant wafers.
  • the oxide thickness variation is caused by concentration variances, and is present even if the time and temperature conditions remain constant.
  • the conventional oxidation of poly-crystalline silicon material also has additional problems which are overcome by the present nitride diffusion stop. Grain boundaries within the poly accumulate impurities which enhance the local oxidation rate. The resulting oxide is "non-conformal" with the underlying poly. The poly to oxide conversion is greater over each grain boundary because of the enhanced oxidation. The grain boundary regions produce a thicker oxide. The poly to oxide conversion is less over each grain body where the local oxidation rate is not enhanced. The resulting thin oxide regions over the grain bodies are subject to electrical breakdown during operation.
  • FIGS. 1-A to 1-G illustrate the steps of a general diffusion stop method for forming a silicon oxide layer
  • FIGS. 3-A to 3-D and 3-E to 3-G show an isolation trench embodiment of the method of FIG. 1;
  • FIG. 4 shows a storage capacitor trench embodiment of the method of FIG. 1
  • FIG. 1 a general embodiment of the present invention
  • FIG. 3 illustrates the best mode presently contemplated by the inventor for practicing the invention.
  • Alternative embodiments are also briefly described as applicable (FIGS. 3, 4, and 5).
  • Support host 110 may be a single crystal silicon substrate (as shown in FIG. 1) or poly-crystalline silicon formed latter in the fabrication (as shown in FIG. 5 ). Silicon substrate 110 may contain dopants at various concentrations to establish conductivity regions forming elements of the fabricated device.
  • Nitride layer 120 may be generated by a suitable technique such as growing thermal nitride on silicon 110 by decomposing a nitrogen bearing gas flow such as ammonia.
  • STEP (1-D) Oxidizing poly 130 forming outer oxide layer 140 by elevating the temperature sufficient to support the oxidation reaction between silicon and oxygen and sufficient to permit oxygen diffusion through oxide 140, while simultaneously exposing poly 130 to an oxygen bearing gas flow such as steam or dry oxygen.
  • the formation of oxide 140 advances inward from outer surface 142 toward nitride 120 as oxygen diffuses through oxide 140.
  • the oxygen poor condition along oxide-silicon interface 146 causes incomplete oxidation along the leading edge of growing oxide 140.
  • the advance rate of oxide 140 into poly 130 is determined primarily by the rapid diffusion rate of oxygen through the increasing silicon oxide of oxide 140.
  • STEP (1-F-1) Driving the oxidation of oxide 140 further to eliminate the partial oxidation states, by continuing the simultaneous temperature and exposure conditions of STEPS 1-D and 1-E.
  • Nitride 120 prevents interface 146 from advancing, while oxygen continues to diffuse into the oxygen poor interior of oxide 140. The oxygen level increases throughout oxide layer 140, eliminating partial oxidation states.
  • STEP (1-G) Completing the fabrication process to obtain an operating device such as transistor 150 (shown in FIG. 1-G).
  • Gate region 152 is implanted in substrate 110 with boron through channels formed by photoresist.
  • Doped poly is deposited on oxide 140 over gate region 152 forming gate electrode 154.
  • the doped poly and oxide 140 and nitride 120 are etched away defining source region 156 and drain region 158.
  • Thin blanket poly 160 is formed, and source 156 and drain 158 are implanted with N type dopant.
  • a thermal cycle is exercised for driving the dopant into substrate 110 and to oxidize blanket poly 160.
  • Blanket glass 162 (P doped) is formed and opened at gate 154, source 156, and drain 158.
  • Metal is deposited into the openings forming gate contact 164, source contact 166, and drain contact 168.
  • Thermal nitride may be grown on host 110 during STEP 1-B by passing ammonia gas over the host at elevated temperatures. Nitrogen from the gas reacts with surface silicon on host 110 to form the surface of nitride 120. The interior of nitride 120 is formed by nitrogen diffusing through the surface and reacting with interior silicon. The growing edge of nitride 120 is from the surface to the interior, and requires diffused nitrogen to advance. As the growing nitride 120 becomes thicker, the supply of diffused nitrogen from the surface decreases. The nitride growth eventually slows to almost zero as shown in the FIG. 2 chart of temperature curves (layer thickness verses time of exposure at selected temperatures). Thermal nitride growth process is self-limiting in thickness. The final thickness depends almost entirely on the growth temperature of the nitride, and is practically independent of time.
  • Nitride layers as thin as 20 Angstroms may be obtained at low growth temperatures. Thin diffusion stop layers are preferred in oxide formation applications to reduce the capacitance and related transient effects.
  • the theoretical lower limit on nitride thickness is determined by the minimum temperature at which the silicon-nitrogen reaction will proceed, subject to substrate native oxide considerations. Thicker nitride layers of from about 20 to about 50 Angstroms may be obtained over a growth temperature range of from about 800 to about 1200 degress Centigrade.
  • the theoretical upper limit on nitride thickness is determined by temperature limitations inherent in fabrication techniques and equipment, subject to the melting point of silicon nitride.
  • Nitride is sensitive to gas impurities, which degrade the dielectric properties of the nitride layer. However in device 150, oxide layer 140 provides the dielectric insulation. Nitride 120 provides a barrier to oxygen in diffusion and impurity out diffusion. Gas impurties on these physical properties of nitride is insignificant.
  • Nitride layer 120 provides an oxygen diffusion stop which protects substrate 110 from oxidation.
  • the oxidation period includes “oxidation”, “driving” and “saturation” (STEPS 1-D, 1-E, 1-F-1, and 1-F-2); and may be extended well beyond saturation without ill effect.
  • the length of the oxidation time period in "non-critical” as long as sufficient time is provided for saturation.
  • the post saturation period remaining after saturation is non-determinative.
  • the oxidation temperature is similarly non-critical. Higher temperatures advance the oxide process faster, resulting in a longer post saturation period. Lower oxidation temperatures slow the oxidation rate, resulting in a shorter post saturation period.
  • the oxidation period was initiated and terminated during the constant temperature portion of the furnace cycle (the main period) in order to maintain the critical oxidation environment.
  • the time and temperature was highly critical. Because of the stopping power of nitride 120, oxidation conditions are no longer so critical.
  • the oxidation period may begin as the temperature is rising (during the ramp-up period), and terminated as the temperature is falling (during the ramp-down period).
  • the main period may be shortened because of the use of the ramp periods to conserve heat.
  • Host 110 Single crystal silicon substrate about 10-15 mils thick (1.00) doped at about 5 ⁇ 10 to the 15th
  • Nitride 120 thermal silicon nitride about 30 Angstroms thick formed by decomposition of pure ammonia for about 60 minutes at about 900 degrees C.
  • the specific oxidation methods 3 and 4 have special application to the formation of stress free substrates for oxide layers in isolation trenches and storage capacitor trenches.
  • the volume expansion involved in the poly to oxide conversion (without a nitride layer) generated corner stress along both 90 degree bottom corners and along both 270 degree upper corners.
  • the present nitride layer prevents oxygen from reaching the substrate, eliminating all direct substrate stress due to oxide expansion.
  • the nitride stop layer defines a boundary which permits the oxidation process to continue without increasing the oxide thickness.
  • the poly to becomes completely oxidized minimizing the "corner stress" heretofore associated with trench oxide. Without, a nitride stop layer between the substrate silicon and the poly, corner stress continued to develope as the oxidation conversion advanced into the substrate.
  • the direct expansion stress in the oxide formed over the nitride is limited by the thinness of the oxide layer. Even in thicker oxide layers, the underlying poly acts as a temporary buffer layer between the increasing oxide layer and the substrate. As the last of the underlying poly is converted into oxide, the overlying oxide has lost significant stress due to the oxidation temperature. This reduced stress remaining in the oxide layer is too small to be induced into the substrate through the nitride as indirect stress.
  • FIG. 3 (FIG. 3)
  • STEP (3-A-1) Providing a suitable single crystal silicon support host 310 for the trench and the remainder of the fabricated device (similar to STEP 1-A).
  • STEP (3-A-2) Providing a trench 312 in substrate 310 by masking followed by a suitable etching technique such as reactive ion etching (RIE).
  • RIE reactive ion etching
  • STEP (3-B) Forming a silicon nitride layer 320 over support host 310 (similar to STEP 1-B).
  • the nitride thickness may be selected from a wide range.
  • Nitride 320 functions primarily as a diffusion stop. A very thin 20 Angstrom layer is functional and a thicker 50 Angstrom layer is also functional.
  • the upper portion of trench sidewalls 312S have better exposure to the ammonia gas then the lower portion of the sidewalls and bottom wall 312B.
  • the nitride deposits faster on the upper sidewalls, which are initially thicker. However, due to the self limiting feature of thermal nitride formation, the slower forming lower regions of the trench catch up.
  • the upper regions reach the maximum thickness first and stabilize.
  • the lower regions continue to grow until they stabilize at the same temperature determined thickness as the upper regions.
  • the nitride forming STEP 3-B may be extended to insure uniform nitride thickness via this self limiting thickness characteristic.
  • STEP (3-C) Forming poly-crystalline silicon layer 330 over nitride 320 by conventional deposition (similar to STEP 1-C).
  • poly 330 functions as an etch stop in STEP 3-F, as well as a diffusion stop in the oxidation steps.
  • Poly 330 and may be selected from a wide range of thicknesses. A resulting oxide having a thickness of 200-300 Anstroms is suitable for typical etch stop situations.
  • STEP (3-D-1) Oxidizing poly 330 forming outer oxide layer 340 by elevating the temperature sufficient to support the oxidation reaction between silicon and oxygen and to permit oxygen diffusion through oxide 340, while simultaneosuly exposing poly 330 to an oxygen bearing gas flow (similar to STEP 1-D).
  • STEP (3-D-4) Saturating the oxidation within oxide layer 340 to eliminate imperfect "loose” bonds (similar to STEP 1-F-2).
  • the thermal conditions promote corner stress reduction as well as improving the chemical bonding.
  • STEP (3-E) Forming undoped poly 350 over oxide 340 having a thickness sufficient to fill trench 312 after oxidation. Because of the volume increase caused by oxidation conversion, poly 350 is typically 1/4 the width of trench 312. For a trench width of 10,000 Angstroms (one micron), a suitable poly thickness is about 250 Angstroms (minus the thickness of nitride 320 and oxide 340 if significant).
  • STEP (3-F) Removing poly 350 from oxide 340 over substrate 310 and over trench bottom 312B, by a suitable directional etching technique such as RIE.
  • STEP (3-G) Oxidizing poly 350 forming outer oxide fill 360 in trench 312 by elevated temperature and oxygen exposure conditions (similar to STEP 3-D). The oxide expansion of poly 350 is outward from flat sidewalls 312S, and does not generate corner stress.
  • STEP (3-K-2) Saturating the oxidation within oxide layer 350 to eliminate imperfect "loose” bonds (similar to STEP 3-D-4).
  • nitride 320 prevents oxygen diffusion into substrate 310 just as in the first oxidation.
  • FIG. 4 (FIG. 4)
  • STEP (4-A-1) Providing a suitable single crystal silicon support host 410 (similar to STEP 3-A).
  • STEP (4-A-2) Providing a trench 412 by masking and etching (similar to STEP 3-A-2).
  • STEP (4-B) Forming a silicon nitride layer 420 over support host 410 (similar to STEP 3-B).
  • nitride 420 functions as the diffusion stop during fabrication, and as a portion of the capacitor dielectric during operation.
  • Nitride 420 and and oxide layer 440 combine dielectric properties to form the capacitor being fabricated.
  • Silicon nitride has a higher dielectric constant than silicon oxide.
  • a higher value capacitor can be fabricated within the alloted substrate space if nitride layer 420 is more than the minimum thickness required for diffusion stop.
  • a nitride 420 thickness of about 300 Angstroms is suitable for enhancing the capacitance.
  • STEP (4-C) Forming poly-crystalline silicon layer 430 over nitride 420 by conventional deposition (similar to STEP 3-C).
  • Poly 430 functions as a capacitor dielectric material, and may be selected from a wide range of thicknesses. Thicknesses of from about 500 Angstroms to about 1,000 Angstroms are suitable for typical IC capacitors.
  • STEP (4-D) Oxidizing poly 430 forming outer oxide layer 440 by elevated temperature and oxygen exposure conditions (similar to STEP 3-D).
  • STEP (4-F-2) Saturating the oxidation within oxide layer 440 to eliminate imperfect "loose” bonds (similar to STEP 1-F-2).
  • STEP (4-G) Forming doped poly 450 over oxide 440 filling trench 412 to form one electrode of the capacitor which cooperates with the substrate electrode through oxide 440.
  • the specific oxidation method 5 (shown in corresponding FIGS. 1-A to 1-F and 5 ) have special application to the formation of floating gate devices.
  • the insulator between the substrate and the floating gate (the first oxide) is formed by STEPS 1-A to 1-F of FIG. 1.
  • the floating gate material is formed on the first oxide.
  • Nitride is formed on the floating gate, and the insulator between the gate and the contact electrode (the second oxide) is formed over the nitride.
  • formation of the second oxide over doped poly resulted non-conformal oxide formation due to the enhanced oxidation regions over the grain boundaries of the poly.
  • the present nitride layer prevents the diffusion of boundary impurities from the gate poly.
  • the resulting second oxide is conformal, without thin breakdown regions.
  • the conventional high oxidation temperature for poly on poly is no longer required to obtain conformal oxide.
  • the low oxidation temperatures permitted by the nitride cause less dopant redistribution.
  • STEP (5-A-1) Providing a suitable single crystal silicon support host 510 (similar to STEP 1-A).
  • STEP (5-B) Forming a first silicon nitride layer 520 over support host 510 (similar to STEP 1-B).
  • STEP (5-C) Forming a first poly-crystalline silicon layer (undoped) over nitride 520 (similar to STEP 1-C).
  • first oxide 540 Oxidizing first poly silicon layer forming first oxide layer 540 by elevated temperature and oxygen exposure conditions (similar to STEP 1-D).
  • First oxide 540 forms the first dielectric of the gate, and has a variable thickness requirement.
  • first oxide 540 may be as thin as 100 Angstorms.
  • oxide 540 may be from 200 to 400 Angstroms.
  • STEP (5-F-2) Saturating the oxidation within oxide layer 540 (similar to STEP 1-F-2).
  • STEP (5-G) Forming doped poly 550 over oxide 540 to form the floating gate material.
  • Gate poly 550 may be as thick as 2,500 Angstroms depending on the application.
  • STEP 5-H Forming a second silicon nitride layer 560 over gate poly 550 (similar to STEP 1-B). Nitride 560 is vapor deposited, and is therefore conformal to the grain irregularities in the surface of gate poly 550.
  • STEP (5-I-1) Forming a second poly-crystalline silicon layer (undoped) over second nitride 560 by conventional deposition (similar to STEP 1-C).
  • the second poly is conformal to nitride 560.
  • STEP (5-I-2) Oxidizing the second poly to form second oxide 570 by elevated temperature and oxygen exposure conditions (similar to STEP 1-D).
  • the oxidation of undoped poly over doped poly resulted in nonconformal oxidation due to dopant enhanced oxidation over the grain boundaries.
  • the presence of nitride 520 prevents impurities in gate poly 550 from affecting the oxidation rate in second oxide 570; and the oxidation is conformal.
  • the thickness of second oxide 570 is uniform, even though the surface is not flat.
  • STEP (5-K-2) Saturating the oxidation within oxide layer 570 (similar to STEP 5-F-2).
  • FIG. 6 (FIG. 6)
  • Nitride formed by LPCVD function as diffusion barriers to prevent oxidation of the underlying substrate material.
  • FIG. 6 shows an MNOS device with nitride 620 deposited on silicon host 610 forming a floating gate.
  • the thin dielectric between substrate 610 and nitride 620 is silicon oxide 614.
  • the dielectric between nitride 620 and contact electrode 670 is silicon oxide 640.
  • oxide 640 from poly
  • nitride 620 prevents the oxidation of host 610.
  • the second dielectric was formed by oxidizing the silicon nitride at a high temperature (1,000 degrees C.), which degraded the floating gate nitride.
  • the nitride prevents advance of the oxide into the substrate, and creates a non-critical oxidation environment.
  • the thickness of the oxide formed is not critically dependent on either time or temperature.
  • the oxidation period may be extended to convert essentially all of the poly to oxide and to perfect the chemical bonds within the oxide.
  • the nitride minimizes impurity out diffusion and boundary dopant segregation.
  • the substrate may be single crystal silicon, or poly crystalline silicon. When oxidizing poly on poly, the nitride prevents grain boundary impurities in the underlying poly from affecting the oxidation rate in the oxidizing poly.
  • the impurities can not diffuse through the nitride into the oxidizing poly.
  • the resulting oxide is conformal to the underlying poly without thin breakdown regions.
  • the conventional high oxidation temperature is no longer required to obtain high quality oxide.
  • the lower oxidation temperatures permitted by the nitride cause less dopant redistribution.
  • the nitride minimizes trench corner stress by isolating the substrate from the oxidation.

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US06/817,233 1986-01-08 1986-01-08 Diffusion stop method for forming silicon oxide during the fabrication of IC devices Expired - Lifetime US4789560A (en)

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US06/817,233 US4789560A (en) 1986-01-08 1986-01-08 Diffusion stop method for forming silicon oxide during the fabrication of IC devices
AT86310234T ATE196215T1 (de) 1986-01-08 1986-12-31 Verfahren zur herstellung integrierter schaltungen unter verwendung einer schicht gegen der diffusion von sauerstoff
DE3650747T DE3650747T2 (de) 1986-01-08 1986-12-31 Verfahren zur Herstellung integrierter Schaltungen unter Verwendung einer Schicht gegen der Diffusion von Sauerstoff
EP86310234A EP0237684B1 (fr) 1986-01-08 1986-12-31 Procédé pour la fabrication de circuits intégrés utilisant une barrière contre la diffusion de l'oxygène
JP62000958A JP2673183B2 (ja) 1986-01-08 1987-01-06 シリコン酸化物を形成する方法

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EP0525650A2 (fr) * 1991-07-29 1993-02-03 Nec Corporation Dispositif semi-conducteur comportant un film isolant pour condensateur et son procédé de fabrication
EP0525650B1 (fr) * 1991-07-29 2001-10-17 Nec Corporation Procédé de fabrication d'un dispositif semi-conducteur comportant un film isolant pour condensateur
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EP0237684A2 (fr) 1987-09-23
JPS62177931A (ja) 1987-08-04
ATE196215T1 (de) 2000-09-15
JP2673183B2 (ja) 1997-11-05
DE3650747D1 (de) 2000-11-16
EP0237684A3 (fr) 1991-01-09
EP0237684B1 (fr) 2000-09-06
DE3650747T2 (de) 2001-04-26

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