US4747083A - Semiconductor memory with segmented word lines - Google Patents

Semiconductor memory with segmented word lines Download PDF

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Publication number
US4747083A
US4747083A US06/625,674 US62567484A US4747083A US 4747083 A US4747083 A US 4747083A US 62567484 A US62567484 A US 62567484A US 4747083 A US4747083 A US 4747083A
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Prior art keywords
word
segment
memory cells
operatively connected
bit
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Expired - Fee Related
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US06/625,674
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English (en)
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Tetsuya Nakajima
Masaki Nagahara
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Fujitsu Ltd
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Fujitsu Ltd
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B61—RAILWAYS
    • B61B—RAILWAY SYSTEMS; EQUIPMENT THEREFOR NOT OTHERWISE PROVIDED FOR
    • B61B1/00—General arrangement of stations, platforms, or sidings; Railway networks; Rail vehicle marshalling systems
    • B61B1/02—General arrangement of stations and platforms including protection devices for the passengers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Definitions

  • the present invention relates to a semiconductor memory device (hereinafter “memory”), more particularly to a memory of a static random access memory (S.RAM) type composed of emitter-coupled-logic (ECL) memory cells.
  • memory semiconductor memory device
  • S.RAM static random access memory
  • ECL emitter-coupled-logic
  • Each word line is divided into a plurality of segmented word lines.
  • Each segmented word line is connected to an individual word driver and provided with memory cells, etc.
  • Each of the segmented word lines carries an individual word current from an individual word driver when the word line is in a selection state.
  • FIG. 1 is a circuit diagram representing a part of a typical semiconductor memory device
  • FIG. 2A is a partial view of a semiconductor memory device equivalent to that of FIG. 1, but drawn somewhat more simply;
  • FIG. 2B is a diagram depicting the distribution of current density in and along a word line of FIG. 2A;
  • FIG. 3 is a general view of a semiconductor memory device according to the present invention, taking an arbitrary word line as an example;
  • FIG. 4A is a circuit diagram of a part of a semiconductor memory device according to a first embodiment of the present invention.
  • FIG. 4B is a diagram depicting the distribution of current density in and along the word line segments of FIG. 4A;
  • FIG. 5 illustrates a detailed example of a known memory cell in FIG. 1
  • FIG. 6 is a more detailed circuit diagram of the semiconductor memory device based on the device illustrated in FIG. 4A;
  • FIG. 7 is a circuit diagram of a part of a semiconductor memory device according to a second embodiment of the present invention.
  • FIG. 8 is a circuit diagram of a part of a semiconductor memory device according to a modification of the second embodiment shown in FIG. 7.
  • FIG. 1 is a circuit diagram representing a part of a typical semiconductor memory device.
  • the memory illustrated in FIG. 1 is specifically an ECL-type S.RAM.
  • reference characters MC indicate memory cells which cooperate with each word line pair WL. Each pair is comprised of word lines W + and W - .
  • Many identical sets of word line pairs WL and memory cells MC are arranged in the direction along which bit line pairs (BL, BL) extend. Thus, many memory cells MC are located at cross points of the word lines and the bit line pairs.
  • These memory cells MC constitute a memory cell array having rows and columns, indicated by MCA.
  • each word line W - is arranged with a respective word line W + as a pair.
  • Each pair of these word lines W + and W - is connected to an individual hold current source HI.
  • the hold current of each source HI maintains the logic "1" or "0" stored in each memory cell MC.
  • Each word line W + is selected by a corresponding word selection signal WS supplied by a word decoder DEC in accordance with an address input AD. The selection is achieved by turning on an individual word driver Q wd connected to the word line W + at its end.
  • similar drivers i.e., bit drivers (mentioned hereinafter) are provided for respective bit line pairs BL, BL, in the memory.
  • FIG. 1 there is significant electromigration in the word lines W + .
  • a relatively large current may flow through each word line W + due to, first, the hold current continually supplied to all the memory cells MC of each word line W + and, second, a discharge current flowing to each discharge current source (DI) every time the word line pair WL is selcted.
  • the above-mentioned large current along the word line W - is the sum of the hold current (I h ) and the discharge current (I d ) and is generated every time the word line W - is in a selection state.
  • a bipolar ECL-type S.RAM exhibits the largest I h and I d currents.
  • the discharge current is useful to effect a quick change from the selection state to the nonselection state.
  • FIG. 2A is a partial view of a semiconductor memory device equivalent to that of FIG. 1, but drawn somewhat more simply.
  • FIG. 2B is a diagram depicting the distribution of current density in and along the word line WL of FIG. 2A.
  • the memory cell array MCA of FIG. 1 is represented simply as a block "MCA" in FIG. 2A.
  • both the hold current source HI and the discharge current source DI are represented simply as a block "IS" in FIG. 2A.
  • the abscissa denotes positions on and along the same word line WL as that of FIG. 2A, and the ordinate denotes a current I flowing therethrough.
  • the peak current density is I max , which iss produced at a current supply side of the word line, i.e., the end of the word line to which the word driver Q wd is connected.
  • FIG. 3 is a general view of a semiconductor memory device according to the present invention, taking an arbitrary word line as an example.
  • the word line WL is divided to form, along its length, a plurality of segmented word lines.
  • Each of the word line segments WL 1 , WL 2 , WL 3 , . . . , WL n except for the first segment WL 1 activated directly by the word driver Q wd1 , is provided with an individual private word driver, i.e., WD 2 , WD 3 . . . WD n .
  • the second private word driver WD 2 is operated in response to the word line signal appearing at the first word line segment WL 1 .
  • the third and following private word drivers WD 3 , . . . , WD n are operated in response to the word line signals appearing at preceding word line segments WL 2 , WL 3 , . . . , WL.sub.(n-1) (not shown), respectively.
  • the memory cell array MCA and the drive current source IS both shown in FIG. 2A, are segmented as MCA 1 , IS 1 ; MCA 2 , IS 2 ; MCA 3 , IS 3 ; . . . and so on.
  • FIG. 4A is a circuit diagram of a part of a semiconductor memory device according to a first embodiment of the present invention.
  • FIG. 4B is a diagram depicting the distribution of current density in and along the word line segments of FIG. 4A.
  • reference characters which are the same as in different figures represent the same components in each figure.
  • FIGS. 4A and 4B will, for simplicity, be made taking as an example a case where the memory is segmented into two blocks. That is, the word line WL is divided to form first and second word line segments WL 1 and WL 2 . Therefore, the memory cells and the current source are also segmented to form MCA 1 , IS 1 and MCA 2 , IS 2 .
  • the word driver Q wd1 is connectedd to the first word line segment WL 1 .
  • the word driver WD 2 of FIG. 3 is specifically comprised of a word driver Q wd2 .
  • Other word drivers WD 3 , . . . , WD n of FIG. 3 are identical to the word driver WD 2 shown in FIG.
  • FIG. 4A i.e., a single transistor Q wd2 .
  • the distribution of current density is as illustrated in FIG. 4B. It is important to note that the peak current density in each of the word line segments WL 1 and WL 2 is approximately halved to I max / 2 , the value I max being that obtained in the prior art device illustrated in FIGS. 2A and 2B.
  • the word driver transistor Q wd2 is directly connected, at its base, to the preceding word line segment, i.e., WL 1 , so as to activate the transistor Q wd2 in response to the word selection signal WS. That is, when the signal WS is received by the word driver Q wd1 , the word line signal appears with an "H" (high) level on the segment WL 1 . The "H" level signal is immediately transferred, via the transistor Q wd2 , to the following word line segment, i.e., WL 2 . Thus, the whole corresponding word line WL is selected.
  • the above construction has the advantage that no separate control line is needed to activate the word driver transistor Q wd2 .
  • the word line WL is segmented into WL 1 and WL 2 with the use of the word driver transistor Q wd2 .
  • the voltage level at the word line segment WL 2 is lowered by V BE from that of the word line segment WL 1 .
  • the character V BE denotes a base-emitter voltage of the word driver transistor Q wd2 .
  • the thus lowered voltage of the segment WL 2 has a deleterious effect on the operation of the memory cell array MCA 2 which will be further explained with reference to FIG. 5.
  • FIG. 5 illustrates a detailed example of the known memory cell MC in FIG. 1.
  • each memory cell MC is comprised of multiemitter transistors Q 1 and Q 2 and loads L 1 and L 2 .
  • Each of the loads comprises a resistor and a Schottky barrier diode connected in parallel.
  • the voltage V WB between the word line Q + and the bit line BL must be higher than a predetermined level to maintain the transistor Q 1 in a conductive state during the selection state of the corresponding word line.
  • the predetermined level V WB mentioned above is equal to the sum of a voltage drop across the load L 2 and the base-emitter voltage of the transistor Q 1 .
  • V WB V WB -V BE
  • V BE denotes the above-mentioned base-emitter voltage of the word driver transistor Q wd2 .
  • an output voltage of each bit driver (mentioned hereinafter) is increased relative to the lowering of V WB , which output voltage is used to determine the voltage of the bit line BL.
  • FIG. 6 is a more detailed circuit diagram of the semiconductor memory device based on the device shown in FIG. 4A.
  • the bit drivers are specifically illustrated with reference characters BD 11 through BD 1n and BD 21 through BD 2n .
  • the bit driver transistors in each of the bit drivers are specifically illustrated with reference characters Q BD .
  • the level shifting means is represented by reference characters LS in the block containing the second MCA 2 . It should be understood that only two blocks B 1 and B 2 are illustrated for simplicity and to conform to the example of FIG. 4A.
  • each of the first bit drivers BD 11 through BD 1n includes a resistor R, transistor Q, diode D, and a constant current source I. This is true for each bit driver in the second block B 2 .
  • the thus lowered voltage V' WB must be restored to the nominal voltage V WB , as in the first block B 1 .
  • the level shift means LS is employed.
  • the level shift means LS can be realized by diodes, as exemplified in the bit drivers BD 21 through BD 2n . As is well known, diodes inherently function to shift the voltage level with a level equal to V BE . Therefore, the bit line level can be lowered by V BE with the use of the diode LS, and the relative voltage V' WB can thereby be increased to V WB .
  • a similar level shifting means LS should comprise two diodes connected in series for producing a shift level of about 2 V.sub. BE.
  • FIG. 7 is a circuit diagram of a part of a semiconductor memory device according to a second embodiment of the present invention.
  • FIG. 7 displays only two blocks for simplicity, as in FIG. 4A.
  • the word driver transistor Q wd2 is not directly connected at its base to the first word line segment WL 1 , but is connected thereto via a buffer gate circuit BG 1 (T, T' and I). This also applies to the following word driver transistors.
  • Each of the buffer gate circuits BG 1 is a differential transistor pair T and T' and a constant current source I commonly connected to transistor emitters.
  • the base of one (T) of the differential transistor pair is connected to the preceding word line segment, i.e., WL 1 , while the base of the other (T') receives a reference voltage V ref and its collector is connected to the base of the word driver transistor Q wd2 .
  • the buffer gate circuit BG 1 Due to the presence of the buffer gate circuit BG 1 , the voltage at the second word line segment WL 2 , i.e., the emitter voltage of the word driver transistor Q wd2 is not lowered by V BE , but the word line voltage level of the segment WL 1 is tranferred as it is to the word line segment WL 2 . That is, the "H" level of WL 1 during the selection state is the same as the "H" level of the segment WL 2 .
  • the word driver transistor Q wd1 When the word line WL is not selected, the word driver transistor Q wd1 is not activated. Accordingly, the level of the segment WL 1 is maintained at the "L" (low) level. Therefore, the transistor T of the differential transistor pair is also not activated. Conversely, the other transistor T' is activated. Thus, the word driver transistor Q wd2 is not activated. Accordingly, the word line segment WL 2 is also left in the nonselection state and is of the "L" level.
  • the word driver transistor Q wd1 is activated to increase the voltage level of the segment WL 1 toward the "H" level. Due to the "H" level of the segment WL 1 , the transistor T is activated, while the transistor T' is not activated. At this time, the base voltage of the transistor Q wd2 increases approximately up to the power source level V cc . Therefore, the voltage level ("H") of the segment WL 2 reaches as high as the voltage level ("H") of the segment WL 1 to hold the selection state i.e. V cc -V BE .
  • each of the word line segments WL 2 , WL 3 , . . . provides a sufficiently high level of "H" during the selection state. This is true regardless of the number of the segments.
  • FIG. 8 is a circuit diagram of a part of a semiconductor memory device according to a modification of the second embodiment illustrated in FIG. 7.
  • a buffer gate circuit BG 2 is used instead of the circuit BG 1 of FIG. 7.
  • the circuit BG 2 performs an identical role as the circuit BG 1 mentioned above. That is, the "H" level at the word line segment WL 1 can be transferred, as it is, to the segment WL 2 .
  • each of the buffer gates BG 2 is comprised of a PNP transistor T 1 and an NPN transistor T 2 .
  • the PNP transistor T 1 is connected, at its base, to the preceding word line segment, i.e., WL 1 .
  • the output of the PNP transistor T 1 is connected to the NPN transistor T 2 at its base.
  • the output of the NPN transistor T 2 is supplied to the base of the word driver transistor Q wd2 .
  • the word driver transistor Q wd1 When the word line WL is not selected, the word driver transistor Q wd1 is not activated. Accordingly, the level of the segment WL 1 is maintained at the "L" (low) level. Therefore, the PNP transistor T 1 is activated. Accordingly the NPN transistor T 2 is also activated, and thus the word driver transistor Q wd2 is not activated. Thus, the word line segment WL 2 is also left in the nonselection state and is of the "L" level.
  • the word driver transistor Q wd1 is activated to increase the voltage level of the segment WL 1 toward the "H" level. Due to the "H" level of the segment WL 1 , the PNP transistor T 1 and the NPN transistor T' are not activated. At this time, the base voltage of the transistor Q wd2 increases approximately up to the power source level V cc . Therefore, the voltage level ("H") of the segment WL 2 reaches as high as the voltage level ("H") of the segment WL 1 to hold the selection state i.e. V cc -V BE . Thus, each of the word line segments WL 2 , WL 3 , . . . provides a sufficiently high level "H" during the selection state. This is true regardless of the number of the segments.
  • the current density in each word line can be considerably reduced. Therefore, the width of each word line can be narrowed further. This enables further miniaturization of an IC memory.
  • the introduction of the individual private word drivers and the buffer gate circuits (BG 1 or BG 2 ) into the IC memory does not obstruct miniaturization because the word lines usually extend in the IC memory with a considerably large length and considerable space can be saved when reducing the widths of such lengthy word lines. The thus saved space is enough to accommodate the word drivers and the buffer gate circuits.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Transportation (AREA)
  • Mechanical Engineering (AREA)
  • Static Random-Access Memory (AREA)
US06/625,674 1983-06-29 1984-06-28 Semiconductor memory with segmented word lines Expired - Fee Related US4747083A (en)

Applications Claiming Priority (2)

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JP58-115881 1983-06-29
JP58115881A JPS6010492A (ja) 1983-06-29 1983-06-29 半導体記憶装置

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EP (1) EP0130793B1 (de)
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KR (1) KR910003595B1 (de)
DE (1) DE3486082T2 (de)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4866673A (en) * 1986-04-17 1989-09-12 Hitachi, Ltd. BI-MOS semiconductor memory having high soft error immunity
US4918662A (en) * 1987-03-27 1990-04-17 Nec Corporation Semiconductor memory device having redundant structure for segmented word line arrangement
US4942555A (en) * 1986-04-17 1990-07-17 Hitachi, Ltd. Bi-MOS semiconductor memory having high soft error immunity
US5222047A (en) * 1987-05-15 1993-06-22 Mitsubishi Denki Kabushiki Kaisha Method and apparatus for driving word line in block access memory
US5506816A (en) * 1994-09-06 1996-04-09 Nvx Corporation Memory cell array having compact word line arrangement
US5717648A (en) * 1993-05-11 1998-02-10 International Business Machines Corporation Fully integrated cache architecture
US5774413A (en) * 1996-12-12 1998-06-30 Cypress Semiconductor Corporation Sensed wordline driver
US6049503A (en) * 1997-10-28 2000-04-11 Lg Semicon Co., Ltd. Wordline driving circuit in semiconductor memory
US6144610A (en) * 1999-04-20 2000-11-07 Winbond Electronics Corporation Distributed circuits to turn off word lines in a memory array
US20060239110A1 (en) * 2004-08-25 2006-10-26 Micron Technology, Inc. Word line driver circuitry and methods for using the same
US20070140037A1 (en) * 2005-08-25 2007-06-21 Arun Khamesra Line driver circuit and method with standby mode of operation
US20090168520A1 (en) * 2007-12-31 2009-07-02 Simtek 3T high density NVDRAM cell
US20090168519A1 (en) * 2007-12-31 2009-07-02 Simtek Architecture of a nvDRAM array and its sense regime
US8929120B2 (en) 2012-08-29 2015-01-06 Micron Technology, Inc. Diode segmentation in memory

Families Citing this family (1)

* Cited by examiner, † Cited by third party
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KR930007185B1 (ko) * 1989-01-13 1993-07-31 가부시키가이샤 도시바 레지스터뱅크회로

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Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4866673A (en) * 1986-04-17 1989-09-12 Hitachi, Ltd. BI-MOS semiconductor memory having high soft error immunity
US4942555A (en) * 1986-04-17 1990-07-17 Hitachi, Ltd. Bi-MOS semiconductor memory having high soft error immunity
US4918662A (en) * 1987-03-27 1990-04-17 Nec Corporation Semiconductor memory device having redundant structure for segmented word line arrangement
US5222047A (en) * 1987-05-15 1993-06-22 Mitsubishi Denki Kabushiki Kaisha Method and apparatus for driving word line in block access memory
US5371714A (en) * 1987-05-15 1994-12-06 Mitsubishi Denki Kabushiki Kaisha Method and apparatus for driving word line in block access memory
US5717648A (en) * 1993-05-11 1998-02-10 International Business Machines Corporation Fully integrated cache architecture
US5506816A (en) * 1994-09-06 1996-04-09 Nvx Corporation Memory cell array having compact word line arrangement
US5774413A (en) * 1996-12-12 1998-06-30 Cypress Semiconductor Corporation Sensed wordline driver
US6049503A (en) * 1997-10-28 2000-04-11 Lg Semicon Co., Ltd. Wordline driving circuit in semiconductor memory
US6144610A (en) * 1999-04-20 2000-11-07 Winbond Electronics Corporation Distributed circuits to turn off word lines in a memory array
US7366051B2 (en) * 2004-08-25 2008-04-29 Micron Technology, Inc. Word line driver circuitry and methods for using the same
US7764567B2 (en) 2004-08-25 2010-07-27 Micron Technology, Inc. Word line driver circuitry and methods for using the same
US20060239110A1 (en) * 2004-08-25 2006-10-26 Micron Technology, Inc. Word line driver circuitry and methods for using the same
US20080181025A1 (en) * 2004-08-25 2008-07-31 Hirokazu Ueda Word line driver circuitry and methods for using the same
US8072834B2 (en) 2005-08-25 2011-12-06 Cypress Semiconductor Corporation Line driver circuit and method with standby mode of operation
US20070140037A1 (en) * 2005-08-25 2007-06-21 Arun Khamesra Line driver circuit and method with standby mode of operation
US8059458B2 (en) 2007-12-31 2011-11-15 Cypress Semiconductor Corporation 3T high density nvDRAM cell
US20090168519A1 (en) * 2007-12-31 2009-07-02 Simtek Architecture of a nvDRAM array and its sense regime
US8064255B2 (en) 2007-12-31 2011-11-22 Cypress Semiconductor Corporation Architecture of a nvDRAM array and its sense regime
US20090168520A1 (en) * 2007-12-31 2009-07-02 Simtek 3T high density NVDRAM cell
US8929120B2 (en) 2012-08-29 2015-01-06 Micron Technology, Inc. Diode segmentation in memory
US9721622B2 (en) 2012-08-29 2017-08-01 Micron Technology, Inc. Systems with memory segmentation and systems with biasing lines to receive same voltages during accessing
US10049705B2 (en) 2012-08-29 2018-08-14 Micron Technology, Inc. Memories having select devices between access lines and in memory cells formed of a same type of circuit element
US10249345B2 (en) 2012-08-29 2019-04-02 Micron Technology, Inc. Memories having select devices between access lines and in memory cells
US10418072B2 (en) 2012-08-29 2019-09-17 Micron Technology, Inc. Memories having select devices between access lines and in memory cells

Also Published As

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EP0130793A3 (en) 1987-09-30
JPS6010492A (ja) 1985-01-19
EP0130793B1 (de) 1993-03-03
KR910003595B1 (ko) 1991-06-07
EP0130793A2 (de) 1985-01-09
DE3486082T2 (de) 1993-06-09
DE3486082D1 (de) 1993-04-08
KR850000126A (ko) 1985-02-25

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