US4710901A - Driving circuit for a shared sense amplifier - Google Patents

Driving circuit for a shared sense amplifier Download PDF

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US4710901A
US4710901A US06/767,193 US76719385A US4710901A US 4710901 A US4710901 A US 4710901A US 76719385 A US76719385 A US 76719385A US 4710901 A US4710901 A US 4710901A
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sense amplifier
bit lines
clock
transistor
clamp
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English (en)
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Masaki Kumanoya
Kazuyasu Fujishima
Katsumi Dosaka
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Assigned to MITSUBISHI DENKI KABUSHIKI KAISHA, reassignment MITSUBISHI DENKI KABUSHIKI KAISHA, ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: DOSAKA, KATSUMI, FUJISHIMA, KAZUYASU, HIDAKA, HIDETO, KUMANOYA, MASAKI, MIYATAKE, HIDESHI, YOSHIHARA, TSUTOMU
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Definitions

  • the present invention relates to a driving circuit for a shared sense amplifier, and more particularly, it relates to a circuit for driving a sense amplifier shared by two pairs of folded bit lines or open bit lines at a high speed.
  • FIG. 1 shows an example of a shared sense amplifier to which the present invention can be applied.
  • a clock ⁇ 3 is supplied to respective sources of transistors 1 and 2.
  • the drain of the transistor 1 is connected to a sense node 9 while the gate thereof is connected to a sense node 10.
  • the drain of the transistor 2 is connected to the sense node 10 while the gate thereof is connected to the sense node 9.
  • These transistors 1 and 2 form a flip-flop type sense amplifier.
  • the sense node 9 is connected to a bit line 3 R through a transfer transistor 7 R and to a bit line 3 L through a transfer transistor 7 L .
  • the sense node 10 is connected to a bit line 4 R through a transfer transistor 8 R and to a bit line 4 L through a transfer transistor 8 L .
  • the transfer transistors 7 R and 8 R are adapted to connect and cut off the bit lines 3 R and 4 R on the right side with and from the sense amplifier, and are on-off controlled by a control clock ⁇ 2R .
  • the transfer transistors 7 L and 8 L are adapted to connect and cut off the bit lines 3 L and 4 L on the left side with and from the sense amplifier, and are on-off controlled by a control clock ⁇ 2L .
  • bit lines 3 R and 4 R form a pair of folded bit lines while the bit lines 3 L and 4 L similarly form another pair of folded bit lines.
  • the sense amplifier which is formed by the transistors 1 and 2 is shared by the two pairs of folded bit lines.
  • the bit lines 3 R and 4 R on the right side of FIG. 1 are respectively connected with sources of transistors 5 R and 6 R .
  • Precharge voltage V R is applied to respective drains of the transistors 5 R and 6 R while a precharge clock ⁇ 1R is supplied to respective gates thereof.
  • These transistors 5 R and 6 R are adapted to charge the bit lines 3 R and 4 R at the precharge voltage V R in response to the precharge clock ⁇ 1R respectively.
  • the bit lines 3 R and 4 R are further connected with memory cells MC 1R and MC NR respectively.
  • the storage content of the memory cell MC 1R is read on the bit line 3 R when a word line WL 1R is selected while the storage content of the memory cell MC NR is read on the bit line 4 R when a word line WL NR is selected.
  • the bit lines 3 R and 4 R are further connected with dummy memory cells DC 1R and DC 2R .
  • intermediate potential between read out potential of information "0" and that of information "1” is read on the bit line 3 R when a dummy word line DWL 1R is selected, while the said intermediate potential is read on the bit line 4 R when a dummy word line DWL 2R is selected with respect to the dummy memory cell DC 2R .
  • bit lines 3 L and 4 L on the left side are connected with read/write lines I/O 1 and I/O 2 respectively through transfer transistors 11 and 12.
  • a clock ⁇ 4 is supplied to respective gates of the transfer transistors 11 and 12.
  • word lines WL 1R ,WL NR , WL 1L and WL NL are shown in FIG. 1, a number N (arbitrarily selected even number) of word lines are present on each side in practice while of the corresponding number N of memory cells MC 1R (MC 1L ) to MC NR (MC NL ), N/2 are connected with the bit lines 3 R (3 L ) and 4 R (4 L ), respectively.
  • circuit as shown in FIG. 1 employs only one sense amplifier, a practical memory is generally formed by a plurality of sense amplifiers which are vertically aligned to form arrays of memory cells.
  • FIG. 2 is a timing chart of an NMOS employed for illustrating the operation of the circuit as shown in FIG. 1.
  • the precharge clock ⁇ 1L is at a high level, whereby the transistors 5 L and 6 L are in ON states and the bit lines 3 L and 4 L are charged at the precharge voltage V L .
  • the precharge clock ⁇ 1R is also at a high level, whereby the bit lines 3 R and 4 R are charged at the precharge voltage V R through the transistors 5 R and 6 R .
  • the clock ⁇ 3 for inactivating the sense amplifier is at a high level, whereby the sense amplifier is retained in the standby state.
  • the potential levels at the selected word line and dummy word line are not immediately increased upon the addressing performed by the address data. This is because the address data are supplied to a decoder (not shown), which increases the potential levels at the selected word line and dummy word line, whereby the increase in the potential levels of the word line and dummy word line is delayed from the addressing by the time required for processing in the decoder.
  • the control clock ⁇ 2L Upon input of the address data, the control clock ⁇ 2L is turned to a low level at a time T 2 before increase of the potential levels at the word line WL 1R and dummy word line DWL 2R , whereby the transfer transistors 7 L and 8 L are both made nonconductive.
  • the sense nodes 9 and 10 are electrically cut off from the bit lines 3 L and 4 L , and the potential levels at the word line WL 1R and dummy word line DWL 2R are increased at a time T 3 .
  • information stored in the memory cell MC 1R is read on the bit line 3 R and the charge stored in the dummy memory cell DC 2R is read on the bit line 4 R respectively.
  • the read information is transferred to the sense nodes 9 and 10 through the transfer transistors 7 R and 8 R during the period when the control clock ⁇ 2R is at a high level to a time T 4 .
  • the level of the control clock ⁇ 2R slightly drops at the time T 4 while impedance levels of the transfer transistors 7 R and 8 R are increased.
  • the clock ⁇ 3 is turned to a low level at a time T 5
  • the sense amplifier formed by the transistors 1 and 2 is activated and the information transferred to the sense nodes 9 and 10 is amplified.
  • the amplified information is returned to the bit lines 3.sub. R and 4 R respectively through the transfer transistors 7 R and 8 R , to be re-written in the memory cell being selected.
  • the control clock ⁇ 2L is again turned to a high level at a time T 6 , whereby the amplified information is transferred to the bit lines 3 L and 4 L through the transfer transistors 7 L and 8 L .
  • the clock ⁇ 4 is turned to a high level at a time T 7 , and the amplified information is transferred to the read/write lines I/O 1 and I/O 2 through the transfer transistors 11 and 12.
  • the word line WL 1R , dummy word line DWL 2R and clock ⁇ 4 return to low levels at a time T 8 and the clocks ⁇ 1R , ⁇ 1L , ⁇ 3 and ⁇ 2R are turned to high levels at a time T 9 , whereby the folded bit lines on both sides are oharged at V R and V L respectively, and the sense amplifier returns to a standby state.
  • the sequential read/write operation is performed in the aforementioned manner.
  • the impedance levels of the transfer transistors 7 R and 8 R are so increased in amplification of the sense amplifier as to reduce capacity loads at the sense nodes 9 and 10 thereby to increase amplification sensitivity.
  • the sense amplifier as shown in FIG. 1 is driven to be shared by two pairs of folded bit lines.
  • the waveforms of the control clocks ⁇ 2R and ⁇ 2L have important functions for driving the shared sense amplifier.
  • the control clock on the non-selected side ( ⁇ 2L in the above case) must be immediately turned to a low level before the potential levels at the selected word lines rise upon the addressing of the memory cells by the address data, i.e., before read-out of the memory cells, to cut off the non-selected bit lines from the sense amplifier. Slow fall of the control clock on the non-selected side delays the read-out from the memory cells, whereby high-speed read-out is disabled.
  • the slow fall of the control clock further delays transfer of the information amplified by the sense amplifier to the read/write lines I/O 1 and I/O 2 , whereby the high-speed read-out is disabled.
  • a driving circuit for a shared sense amplifier which can attain high-speed read-out operation by quickly connecting and cutting off bit lines with and from the sense amplifier.
  • An object of the present invention is to provide a driving circuit for a sense amplifier shared by two pairs of bit lines which can connect and cut off the bit lines with and from the sense amplifier at a high speed thereby to drive the shared sense amplifier at a high speed.
  • the present invention provides a circuit for driving at a high speed a shared sense amplifier including two pairs of bit lines respectively connected with memory cells, a sense amplifier positioned between the two pairs of bit lines for amplifying information read from the memory cells, a first transfer transistor group interposed between one of the pairs of bit lines and the sense amplifier and a second transfer transistor group interposed between the other pair of bit lines and the sense amplifier thereby to share the sense amplifier by the two pairs of bit lines, and the driving circuit comprises a clamp clock generation circuit, a decoder and an on-off control means.
  • the clamp clock generation circuit is adapted to generate a clamp clock which responds at a high speed to addressing of the memory cells
  • the decoder is adapted to decode the clamp clock from the clamp clock generation circuit
  • the on-off control means is adapted to control on-off operations of the first and second transfer transistor groups on the basis of the output from the decoder.
  • the on-off control means includes a clamp means for clamping upon addressing of either of the memory cells the gate potential of the transfer transistor group interposed between the bit lines in the area not connected with the addressed memory cell and the sense amplifier at bit line precharge voltage thereby to turn off the said transfer transistor group.
  • the clamp clock which responds at a high speed to the addressing to produce a control clock from the clamp clock, thereby to control on-off operations of the first and second transfer transistor groups by the control clock, and hence the bit lines on the non-selected side can be cut off from the sense amplifier immediately upon the addressing of the memory cell.
  • the gate voltage at the transfer transistor group is not completely turned to a low level but clamped at the bit line precharge voltage, whereby the time required for cutting off the transfer transistor group can be reduced in comparison with the case where the gate voltage thereof is completely turned to a low level, and the cut off operation can be performed at a higher speed.
  • the bit lines on the non-selected side can reliably be cut off from the sense amplifier within the short interval, thereby to attain high-speed driving of the shared sense amplifier.
  • the gate voltage of the transfer transistor group is clamped at the bit line precharge voltage as hereinabove described so that the said transfer transistor group is automatically turned on by the amplification function of the sense amplifier to re-connect the bit lines on the non-selected side with the sense amplifier, and hence such re-connection can be performed at a higher speed in comparison with the case where voltage is applied to the gate of the transfer transistor group after the operation of the sense amplifier to re-connect the bit lines on the non-selected side with the sense amplifier. Therefore, the content of the memory cell can be externally read immediately after termination of the operation of the sense amplifier, thereby to attain high-speed readout operation.
  • FIG. 1 is a circuit diagram showing an example of a shared sense amplifier to which the present invention can be applied;
  • FIG. 2 is a timing chart for illustrating the general operation for driving the circuit as shown in FIG. 1;
  • FIG. 3 is a timing chart for illustrating the driving operation according to an embodiment of the present invention.
  • FIG. 4 is a circuit diagram showing a part of the embodiment of the present invention, particularly a circuit for generating control clocks;
  • FIG. 5 is a timing chart for illustrating the operation of the circuit as shown in FIG. 4;
  • FIG. 6 is a circuit diagram showing another part of the embodiment of the present invention, particularly a circuit for generating clamp clocks
  • FIG. 7 is a timing chart for illustrating the operation of the circuit as shown in FIG. 6;
  • FIG. 8 is a circuit diagram showing still another part of the embodiment of the present invention, particularly a decode circuit for decoding the clamp clocks outputted from the circuit as shown in FIG. 6 to that shown in FIG. 4;
  • FIG. 9 is a timing chart for illustrating the operation of the circuit as shown in FIG. 8;
  • FIG. 10 is a circuit diagram showing a further part of the embodiment of the present invention, particularly a circuit for generating clocks for driving the circuit as shown in FIG. 4;
  • FIG. 11 is a timing chart for illustrating the operation of the circuit as shown in FIG. 10.
  • FIG. 3 is a timing chart for illustrating the operation performed by an embodiment of the present invention for driving a shared sense amplifier.
  • the basic circuit structure of the shared sense amplifier may be identical to that shown in FIG. 1.
  • precharge clocks ⁇ 1L and ⁇ 1R are both at high levels and hence bit lines 3 R , 4 R , 3 L and 4 L are charged respectively at precharge voltage levels V R and V L .
  • the voltage levels V R and V L are generally set equal to each other, and hence they are hereafter indicated as V REF .
  • the levels of control clocks ⁇ 2L and ⁇ 2R are set higher than the total of the bit line precharge voltage V REF and threshold voltage of transfer transistors.
  • all of the transfer transistors 7 L , 8 L , 7 R and 8 R are in ON states whereby sense nodes 9 and 10 are precharged at V REF .
  • the feature of this driving method resides in that the level of a control clock 100 2L on the non-selected side is not completely turned to a low level, but clamped at the bit line precharge voltage V REF before rise of corresponding word lines upon addressing of memory cells.
  • the bit lines 3 R , 3 L , 4 R and 4 L and sense nodes 9 and 10 are at the potential level of V REF , and hence the transfer transistors 7 L and 8 L are cut off with drains, sources and gates being at the same level by clamping the control clock ⁇ 2L at V REF .
  • cut-off operation can be performed by clamping the level of the control clock ⁇ 2L at V REF at a higher speed than the case where the same is turned to a low level.
  • symbols V 3R and V 3L indicate potential levels at the bit lines 3 R and 3 L respectively, while symbol V 9 indicates the potential level at the sense node 9.
  • precharge clocks ⁇ 1R and ⁇ 1L are turned to low levels, while the potential levels V 3R and V 3L remain at V REF .
  • the control clock ⁇ 2L is clamped at V REF , whereby the transfer transistors 7 L and 8 L are turned off as hereinabove described and the bit line 3 L is electrically cut off from the sense node 9.
  • the control clock ⁇ 2R remains at a high level, whereby the bit line 3 R remains connected with the sense node 9.
  • the potential at a word line WL 1R is increased and the information in the memory cell MC 1R is read on the bit line 3 R .
  • the potential V 3R at the bit line 3 R is slightly lowered by a level determined by the capacitance ratio of the memcry cell MC 1R to the bit line 3 R .
  • the potential at the sense node 9 is slightly lowered in response to this, whereas the transfer transistor 7 L is not turned on since the decreased level is generally smaller than a threshold voltage V TH of the transistors.
  • the clock ⁇ 3 is turned to a low level thereby to activate the sense amplifier, and the potential level V 9 at the sense node 9 begins to be lowered.
  • the control clock ⁇ 2R is lowered to V REF and the bit line 3 R is temporarily cut off from the sense node 9, whereby the capacitive load is reduced and the amplification sensitivity is improved.
  • the potential level V 9 reduced to (V REF -V TH ), whereby the transfer transistors 7 L and 7 R begin to enter ON states and the bit lines 3 L and 3 R are automatically re-connected with the sense node 9.
  • control clocks ⁇ 2R and ⁇ 2L are turned to high levels, i.e., levels higher than V REF at a time T 6 , whereby the transfer transistors 7 R and 7 L are increased in conductivity. Therefore, the information read from the memory cell is sufficiently transmitted to read/write lines in the read-out operation.
  • the bit lines on the non-selected side are cut off from the sense amplifier by clamping the gate voltage of the transfer transistors on the non-selected side at the bit line precharge voltage before rise of potential levels at the word lines upon addressing of the memory cell in the aforementioned operation, whereby attained is a cut-off operation at a higher speed than the case where the gate voltage levels at the transfer transistors are completely turned to low levels.
  • the gate voltage levels at the transfer transistors are so clamped at the bit line precharge voltage level that the transfer transistors are automatically turned on by the amplification function of the sense amplifier and the bit lines on the non-selected side are automatically re-connected with the sense amplifier, whereby the time required for the re-connection of the bit lines on the non-selected side is extremely reduced. Therefore, the content of the memory cell can be outputted to the exterior immediately after the amplification by the sense amplifier, thereby to enable high-speed readout operation.
  • the gate voltage levels at the transfer transistors are made to be higher than the total of the bit line precharge voltage and the threshold voltage levels of the transfer transistors for reading the content of the memory cell to attain a sufficient read-out level in the aforementioned embodiment, and the rise of the gate voltage in this case can be performed in a shorter period than that in the case where the gate voltage levels of the transfer transistors are completely turned to low levels to be then turned to high levels. Thus, such a point also contributes to the high-speed read-out operation.
  • bit line precharge voltage V REF is assumed to be equal to supply voltage V CC .
  • FIG. 4 shows a circuit for generating the control clock ⁇ 2L as shown in FIG. 3.
  • the circuit as shown in FIG. 4 includes transistors Q 1 to Q 8 and capacitors C 1 to C 5 .
  • the drain of the transistor Q 1 receives the supply voltage V CC and the gate receives the precharge clock ⁇ 1L while the source is connected to a node N 2 .
  • the drain of the transistor Q 2 receives an inverted precharge clock ⁇ 1L which is an inverted signal of the precharge clock ⁇ 1L , while the gate receives the supply voltage V CC and the source is connected to the node N 1 .
  • the drain of the transistor Q 3 receives the supply voltage V CC and the gate is connected to the node N 1 while the source is connected to the node N 2 .
  • the drain of the transistor Q 4 receives the supply voltage V CC and the gate is connected to the node N 2 while the source is connected to an output terminal 13, which is adapted to output the control clock ⁇ 2L .
  • the drain of the transistor Q 5 receives the supply voltage V CC and the gate is connected to a node N 3 while the source is connected to the output terminal 13.
  • the drain of the transistor Q 6 receives the supply voltage V CC and the gate is connected to a node N 4 while the source is connected to the node N 3 .
  • the drain of the transistor Q 7 receives the inverted precharge clock ⁇ 1L and the gate receives the supply voltage V CC while the source is connected to the node N 4 .
  • the drain of the transistor Q 8 receives the supply voltage V CC and the gate receives the precharge clock ⁇ 1L while the source is connected to the node N 3 .
  • One end of the capacitor C 1 is connected to the node N 1 while the other end thereof receives in inverted delayed clock ⁇ 3 ', which is an inverted delayed signal of a clock ⁇ 3 .
  • One end of the capacitor C 2 is connected to the node N 2 and the other end thereof receives a clamp clock ⁇ 5L which is hereinafter described in detail.
  • One end of the capacitor C 3 is connected to the output terminal 13, while the other end thereof receives a clock ⁇ 6L which is also hereinafter described.
  • One end of the capacitor C 4 is connected to the node N 3 while the other end thereof receives the inverted clock ⁇ 3 which is the inverted signal of the clock ⁇ 3 .
  • One end of the capacitor C 5 is connected to the node N 4 , while the other end thereof receives the inverted delayed clock ⁇ 3 '.
  • a circuit for generating the control clock ⁇ 2R is in similar structure to the circuit for generating the control clock ⁇ 2L , except that a precharge clock ⁇ 1R and an inverted precharge clock ⁇ 1R are supplied in place of the precharge clock ⁇ 1L and inverted precharge clock ⁇ 1L and a clamp clock ⁇ 5R is supplied in place of the clamp clock ⁇ 5L while a clock ⁇ 6R is supplied in place of the clock ⁇ 6L .
  • FIG. 5 is a timing chart for illustrating the operation of the circuit as shown in FIG. 4. Referring now to FIG. 5, the following description is provided of the operation of the circuit as shown in FIG. 4, in the case where the memory cell on the right side of the sense amplifier is addressed as shown in FIG. 1.
  • the precharge clock ⁇ 1L and clock ⁇ 3 are at high levels, and the output terminal 13 and, thus, the control clock ⁇ 2L are precharged at higher levels than the supply voltage V CC by capacitive coupling of the capacitor C 3 as hereinafter described.
  • the nodes N 2 and N 3 are precharged at the supply voltage V CC by turning-on of the transistors Q 1 and Q 8 , whereas the transistors Q 4 and Q 5 remain in OFF states since the potential levels at the sources thereof are higher than those of the gates.
  • the inverted precharge clock ⁇ 1L is at a low level, and hence the nodes N 1 and N 4 are at low levels through the transistors Q 2 and Q 7 respectively. Therefore, both of the transistors Q 3 and Q 6 are in OFF states.
  • the precharge clock ⁇ 1L is turned to a low level and the inverted precharge clock ⁇ 1L is turned to a high level, whereby the nodes N 1 and N 4 are turned to high levels through the transistors Q 2 and Q 7 .
  • the clamp clock ⁇ 5L is turned to a high level whereby the node N 2 is boosted by capacitive coupling of the capacitor C 2 to a level sufficiently higher than the supply voltage V CC . Therefore, the transistor Q 4 is strongly turned on and the control clock ⁇ 2L is clamped at a high speed from the high level exceeding the supply voltage V CC to the level of the supply voltage V CC .
  • the clock ⁇ 6L is also turned to a low level, whereby the level of the control clock ⁇ 2L is pulled in a low level to be clamped at the level of the supply voltage V CC at a higher speed by capacitive coupling of the capacitor C 3 .
  • the clock ⁇ 3 is turned to a low level and the inverted clock ⁇ 3 is turned to a high level whereby the node N 3 is boosted to a level sufficiently higher than the supply voltage V CC by capacitive coupling of the capacitor C 4 .
  • the transistor Q 5 is strongly turned on, whereas no change takes place since the control clock ⁇ 2L is already clamped at the level of the supply voltage V CC in this case.
  • the inverted delay clock ⁇ 3 ' is turned to a high level whereby the nodes N 1 and N 4 are boosted by levels sufficiently higher than the supply voltage V CC by capacitive coupling of the capacitors C 1 and C 5 . Therefore, the transistors Q 3 and Q 6 are strongly turned on and the nodes N 2 and N 3 are clamped at the level of the supply voltage V CC , whereby the transistors Q 4 and Q 5 are turned off. Then, at the time T 6 , the clock ⁇ 6L is again turned to a high level, whereby the control clock ⁇ 2L is turned to a high level exceeding the supply voltage V CC by capacitive coupling of the capacitor C 3 .
  • the clamp clock ⁇ 5R remains at a low level and the clock ⁇ 6R remains at a high level at the time T 2 , and hence the node N 2 remains at the level of the supply voltage V CC and the control clock ⁇ 2R remains at the high level exceeding the supply voltage V CC .
  • the inverted clock ⁇ 3 is turned to a high level and the clock ⁇ 6R is turned to a low level, whereby the transistor Q 5 is strongly turned on by the capacitor C 4 to clamp the control clock ⁇ 2R at the level of the supply voltage V CC .
  • Such clamping is made at a higher speed by the function of the capacitor C 3 .
  • the operation thereafter is substantially identical to that of the circuit for generating the control clock ⁇ 2L .
  • control clocks ⁇ 2L and ⁇ 2R which can drive the shared sense amplifier as shown in FIG. 1 at a high speed, are obtained by the circuit as shown in FIG. 4.
  • This clamp clock generation circuit is formed by two portions of a ⁇ 5 generation circuit for generating a clamp clock ⁇ 5 in high-speed response to the addressing of the memory cells by the address data and a decode circuit for decoding the clamp clock ⁇ 5 thereby to generate two types of clamp clocks ⁇ 5L and ⁇ 5R .
  • FIG. 6 is a circuit diagram showing definite arrangement of the aforementioned circuit for generating the clamp clock ⁇ 5 .
  • the ⁇ 5 generation circuit includes transistors M 1 to M 11 and a capacitor C 6 .
  • the drain of the transistor M 1 receives the supply voltage V CC and the gate receives the precharge clock ⁇ 1 while the source is connected to the node N 5 .
  • the drain of the transistor M 2 is connected to the node N 5 and the gate receives a first address clock ⁇ A while the source is grounded.
  • the drain of the transistor M 3 is connected to the node N while the gate receives a second address clock ⁇ A and the source is grounded.
  • the drain of the transistor M 4 receives an inverted precharge clock ⁇ 1 which is an inverted signal of the precharge clock ⁇ 1 and the gate is connected with the node N 5 while the source is connected with by node N 6 .
  • the drain of the transistor M 5 is connected with the node N 6 and the gate receives the inverted delayed clock ⁇ 3 ' while the source is grounded.
  • the drain of the transistor M 6 receives the supply voltage V CC and the gate is connected to the node N 6 while the source is connected to a node N 7 .
  • the drain of the transistor M 7 is connected with the node N 7 while the gate receives the inverted delayed clock ⁇ 3 ' and the source is grounded.
  • the drain of the transistor M 8 is connected with the node N 7 and the gate is connected with the node N 5 while the source thereof is grounded.
  • the drain of the transistor M 9 receives the supply voltage V CC while the gate is connected with the node N 7 and the source is connected with an output terminal 14, which outputs the clamp clock ⁇ 5 .
  • the drain of the transistor M 10 is connected with the output terminal 14 and the gate is connected with the node N 5 , while the source is grounded.
  • the drain of the transistor M 11 is connected with the output terminal 14, while the gate receives the inverted delayed clock ⁇ 3 ', and the source is grounded.
  • One end of the capacitor C 6 is connected with the node N 6 and the other end thereof is connected with the node N 7 .
  • Either of the precharge clocks ⁇ 1L and ⁇ 1R as shown in FIG. 1 may serve as the precharge clock ⁇ 1 .
  • an address strobe signal may be employed in place of the precharge clock ⁇ 1 .
  • the first and second address clocks ⁇ A and ⁇ A ' are formed by partial bits extracted from the address data for addressing the memory cell, and the first address clock ⁇ A indicates addressing of the memory cell on the right side of the sense amplifier in FIG. 1 while the second address clock ⁇ A indicates addressing of of the memory cell on the left side of the sense amplifier in FIG. 1.
  • the first address clock ⁇ A is turned to a high level when the memory cell on the right side is addressed while the second address clock ⁇ A is turned to a high level when the memory cell on the left side is addressed.
  • FIG. 7 is a timing chart for illustrating the operation of the circuit as shown in FIG. 6. The operation of the circuit in FIG. 6 is now described with reference to FIG. 7.
  • the precharge clock ⁇ 1 is at a high level and the node N 5 is precharged at a high level through the transistor M 1 . Therefore, the transistors M 4 , M 8 and M 10 are in ON states and the nodes N 6 and N 7 and clamp clock ⁇ 5 are at low levels.
  • the precharge clock ⁇ 1 is turned to a low level and the inverted precharge clock ⁇ 1 is turned to a high level whereby the transistor M 1 is turned off while the node N 5 remains at a high level, and hence the transistor M 4 is retained in an ON state. Therefore, the high-level inverted precharge clock ⁇ 1 is supplied to the node N 6 , which is turned to a high level whereby the transistor M 6 is turned on. However, since the node N 5 remains at a high level, the transistor M 8 is retained in an ON state and the node N 7 is retained at a low level.
  • either the first or second address clock ⁇ A or ⁇ A is turned to a high level whereby either the transistor M 2 or M 3 is turned on to turn the node N 5 to a low level. Therefore, the transistor M 4 is turned off and the node N 6 enters a high floating state.
  • the transistors M 8 and M 10 are turned off whereby the level of the node N 7 begins to be increased. Then the node N 6 is boosted to a higher level by capacitive coupling of the capacitor C 6 , whereby the transistor M 6 is strongly turned on to increase the voltage at the node N 7 to the level of the supply voltage V CC at a high speed.
  • the transistor M 9 is turned on to turn the clamp clock ⁇ 5 to a high level at a high speed. Then, at the time T 6 , the inverted delayed clock ⁇ 3 ' is turned to a high level, whereby the transistors M 5 , M 7 and M 11 are turned on to turn the nodes N 6 and N 7 and clamp clock ⁇ 5 to low levels.
  • the inverted delayed clock ⁇ 3 ' is employed in this embodiment to reset the circuit, such reset operation may be performed by other types of reset clocks.
  • the clamp clock ⁇ 5 which responds at a high speed to the first or second address clock ⁇ A or ⁇ A .
  • FIG. 8 shows an example of the aforementioned decode circuit, particularly a circuit for producing the clamp clock ⁇ 5L .
  • the circuit as shown in FIG. 8 includes transistors M 12 to M 18 .
  • the drain of the transistor M 12 receives the supply voltage V CC while the gate receives the precharge clock ⁇ 1 and the source is connected with a node N 8 .
  • the drain of the transistor M 13 is connected to the node N 8 while the gate receives a second address clock ⁇ A and the source is grounded.
  • the drain of the transistor M 14 receives the clamp clock ⁇ 5 from the circuit as shown in FIG. 6 while the gate is connected with the node N 8 and the source is connected with an output terminal 15, which outputs the clamp clock ⁇ 5L .
  • the drain of the transistor M 15 is connected with the output terminal 15 and the gate is connected with a node N 9 while the source is grounded.
  • the drain of the transistor M 16 receives the supply voltage V CC and the gate receives the precharge clock ⁇ 1 while the source is connected with node N 9 .
  • the drain of the transistor M 17 is connected with the node N 9 and the gate is connected with the output terminal 15 while the source is grounded.
  • the drain of the transistor M 18 is connected with the output terminal 15 while the gate receives a clamp clock ⁇ 5R and the source is grounded.
  • a circuit for producing the clamp clock ⁇ 5R (similarly included in the decode circuit) is in similar structure to the aforementioned circuit as shown in FIG. 8, except that the first address clock ⁇ A is supplied in place of the second address clock ⁇ A and the clamp clock ⁇ 5L is supplied in place of the clamp clock ⁇ 5R .
  • FIG. 9 is a timing chart for illustrating the operation of the circuit as shown in FIG. 8. The operation of the circuit in FIG. 8 is now described with reference to FIG. 9, on such case that the memory cell on the right side of the sense amplifier in FIG. 1 is addressed.
  • the precharge clock ⁇ 1 is at a high level. Therefore, the transistors M 12 and M 16 are in ON states and the nodes N 8 and N 9 are precharged at high levels. Thus, the transistors M 14 and M 15 are turned on and the output terminal 15 and, thus, the clamp clock ⁇ 5L are at low levels. If the memory cell on the right side in FIG. 1 is addressed at the time T 2 , the first address clock ⁇ A is turned to a high level while the second address clock ⁇ A remains at a low level. Therefore, the node N 8 is retained at a high level at the time T 2 , thereby to retain the transistor M 14 in an ON state.
  • the level of the clamp clock ⁇ 5 is directly transmitted to the output terminal 15, and the clamp clock ⁇ 5L presents the same waveform as that of the clamp clock ⁇ 5 .
  • the transistor M 17 is turned on to turn the node N 9 to a low level, whereby the transistor M 15 is in an OFF state.
  • the first address clock ⁇ A rises to a high level at the time T 2 , whereby the transistor M 13 is turned on and the node N 8 is turned to a low level while the transistor M 14 is cut off.
  • the level of the clamp clock ⁇ 5 is not transmitted to the output terminal 15, and the transistor M 17 is not turned on. Therefore, the transistor M 15 remains in an ON state and the clamp clock ⁇ 5R is retained at a low level.
  • the transistor M 18 is in an ON state whereby the clamp clock ⁇ 5R is securely retained at a low level state at least in the high-level period of the clamp clock ⁇ 5L .
  • FIG. 10 shows the circuit for generating the clock ⁇ 6L .
  • the circuit as shown in FIG. 10 includes transistors M 19 to M 27 .
  • the drain of the transistor M 19 receives the supply voltage V CC and the gate receives the precharge clock ⁇ 1 while the source is connected to a node N 10 .
  • the drain of the transistor M 20 is connected with the node N 10 while the gate receives the inverted delayed clock ⁇ 3 ' and the source is grounded.
  • the drain of the transistor M 21 receives the inverted clock ⁇ 3 while the gate is connected with the node N 10 and the source is connected with a node N 11 .
  • the drain of the transistor M 22 is connected with the node N 11 while the gate receives the inverted delayed clock ⁇ 3 ' and the source is grounded.
  • the drain of the transistor M 23 is connected with the node N 11 while the gate receives the precharge clock ⁇ 1 and the source is grounded.
  • the drain of the transistor M 24 receives the supply voltage V CC and the gate receives the precharge clock ⁇ 1 while the source is connected with an output terminal 16, which outputs the clock ⁇ 6L .
  • the drain of the transistor M 25 receives the supply voltage V CC and the gate receives an inverted delayed clock ⁇ 3 " and the source is connected with the output terminal 16.
  • the drain of the transistor M 26 is connected with the output terminal 16 and the gate is connected with the node N 11 while the source is grounded.
  • the drain of the transistor M 27 is connected with the output terminal 16 while the gate receives the clamp clock ⁇ 5L and the source is grounded.
  • the inverted delayed clock ⁇ 3 " is obtained by delaying the inverted delayed clock ⁇ 3 ' further by a prescribed time.
  • a circuit for generating the clock ⁇ 6R is in similar arrangement to that of the circuit as shown in FIG. 10, except that the clamp clock ⁇ 5R is supplied in place of the clamp clock ⁇ 5L .
  • FIG. 11 is a timing chart for illustrating the operation of the circuit as shown in FIG. 10. The operation of the circuit in FIG. 10 is now described with reference to FIG. 11.
  • the precharge clock ⁇ 1 is at a high level and all of the transistors M 19 , M 23 and M 24 are in ON states. Therefore, the node N 10 is at a high level and the node N 11 is at a low level, while the output terminal 16 and, thus, the clock ⁇ 6L are at high levels.
  • the precharge clock ⁇ 1 is turned to a low level, whereby all of the transistors M 19 , M 23 and M 24 are turned off while all of the nodes N 10 and N 11 and output terminal 16 enter floating states and no change is caused in the potential levels.
  • the clamp clock ⁇ 5L is turned to a high level, whereby the transistor M 27 is turned on to turn the output terminal 16 to a low level, whereby the clock ⁇ 6L is turned to a low level.
  • the clock ⁇ 3 is turned to a low level and the inverted clock ⁇ 3 is turned to a high level, and since the node N 10 is at a high level, the node N 11 is turned to a high level through the transistor M 21 . Therefore, the transistor M 26 is turned on, while no change is caused in the clock ⁇ 6L since the output terminal 16 is already at a low level.
  • the inverted delayed clock ⁇ 3 ' is turned to a high level and the clamp clock ⁇ 5L is turned to a low level whereby the transistors M 20 and M 22 are turned on and the transistor M 27 is turned off. Therefore, the nodes N 10 and N 11 are turned to low levels, whereby the transistors M 21 and M 26 are turned off.
  • the inverted delayed clock ⁇ 3 " is turned to a high level, whereby the transistor M 25 is turned on to again turn the output terminal 16 to a high level. Therefore, the clock ⁇ 6L is turned to a high level.
  • the clamp clock ⁇ 5R remains at a low level at the time T 2 , and hence the clock ⁇ 6R remains at a high level.
  • the inverted clock ⁇ 3 is turned to a high level, whereby the transistor M 26 is turned on to turn the output terminal 16 and, thus, the clock ⁇ 6R to low levels.
  • the operation thereafter is substantially identical to that of the circuit as shown in FIG. 10.
  • the driving circuit for a shared sense amplifier is formed by the aforementioned circuits as shown in FIGS. 4, 6, 8 and 10, thereby to generate the control clock ⁇ 2L ( ⁇ 2R ) which can drive the shared sense amplifier at a high speed.
  • bit lines 3 L and 3 R in FIG. 1 are taken as a pair of open bit lines and the bit lines 4 L and 4 R are taken as another pair of open bit lines while a clock corresponding to the control clock ⁇ 2L is inputted in the gates of the transfer transistors 7 L and 7 R and a clock corresponding to the control clock ⁇ 2R is inputted in the gates of the transfer transistors 8 L and 8 R .
  • bit lines 3 L and 4 R may be taken as a pair of open bit lines while taking the bit lines 3 R and 4 L as another pair of open bit lines and inputting a clock corresponding to the control clock ⁇ 2R in the gates of the transfer transistors 7 L and 8 R and a clock corresponding to the control clock ⁇ 2R in the gates of the transfer transistors 8 L and 7 R .

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JP59-172005 1984-08-17
JP59172005A JPS6150284A (ja) 1984-08-17 1984-08-17 シエアドセンスアンプ回路の駆動方法

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US4969125A (en) * 1989-06-23 1990-11-06 International Business Machines Corporation Asynchronous segmented precharge architecture
US4982370A (en) * 1985-10-04 1991-01-01 Mitsubishi Denki Kabushiki Kaisha Shared sense amplifier semiconductor memory
US5058073A (en) * 1988-03-10 1991-10-15 Oki Electric Industry Co., Ltd. CMOS RAM having a complementary channel sense amplifier
US5148399A (en) * 1988-06-28 1992-09-15 Oki Electric Industry Co., Ltd. Sense amplifier circuitry selectively separable from bit lines for dynamic random access memory
US5270591A (en) * 1992-02-28 1993-12-14 Xerox Corporation Content addressable memory architecture and circuits
US5721875A (en) * 1993-11-12 1998-02-24 Intel Corporation I/O transceiver having a pulsed latch receiver circuit
EP0717415A3 (en) * 1994-12-16 1999-08-25 Kabushiki Kaisha Toshiba Semiconductor memory device

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4982370A (en) * 1985-10-04 1991-01-01 Mitsubishi Denki Kabushiki Kaisha Shared sense amplifier semiconductor memory
US5058073A (en) * 1988-03-10 1991-10-15 Oki Electric Industry Co., Ltd. CMOS RAM having a complementary channel sense amplifier
US5148399A (en) * 1988-06-28 1992-09-15 Oki Electric Industry Co., Ltd. Sense amplifier circuitry selectively separable from bit lines for dynamic random access memory
US4969125A (en) * 1989-06-23 1990-11-06 International Business Machines Corporation Asynchronous segmented precharge architecture
US5270591A (en) * 1992-02-28 1993-12-14 Xerox Corporation Content addressable memory architecture and circuits
US5721875A (en) * 1993-11-12 1998-02-24 Intel Corporation I/O transceiver having a pulsed latch receiver circuit
EP0717415A3 (en) * 1994-12-16 1999-08-25 Kabushiki Kaisha Toshiba Semiconductor memory device

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KR900008613B1 (ko) 1990-11-26
KR860002098A (ko) 1986-03-26
JPS6150284A (ja) 1986-03-12
DE3529476C2 (en, 2012) 1990-06-13
DE3529476A1 (de) 1986-02-27

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