US4584636A - AC-to-DC power converter with improved power factor and overvoltage suppression - Google Patents

AC-to-DC power converter with improved power factor and overvoltage suppression Download PDF

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Publication number
US4584636A
US4584636A US06/473,729 US47372983A US4584636A US 4584636 A US4584636 A US 4584636A US 47372983 A US47372983 A US 47372983A US 4584636 A US4584636 A US 4584636A
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United States
Prior art keywords
mode
switching means
flow
power
controllable switching
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Expired - Fee Related
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US06/473,729
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English (en)
Inventor
Takeki Ando
Toshiaki Kurosawa
Hiroaki Kuroha
Yoshio Sakai
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Hitachi Ltd
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Hitachi Ltd
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Assigned to HITACHI, LTD. reassignment HITACHI, LTD. ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: ANDO, TAKEKI, KUROHA, HIROAKI, KUROSAWA, TOSHIAKI, SAKAI, YOSHIO
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/505—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means
    • H02M7/515—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/145—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means
    • H02M7/155—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only
    • H02M7/162—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only in a bridge configuration
    • H02M7/1623—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only in a bridge configuration with control circuit

Definitions

  • This invention relates to an AC-to-DC power converter apparatus.
  • a full wave bridge circuit is generally made up of thyristors, wherein the ignition phase angles of a group of thyristors connected to the positive arm of the circuit and another group of thyristors connected to its negative arm are made equal, the circuit being used to control output voltage by making the phase angle variable.
  • the disadvantage of this method is that the power-factor is worsened, while the ripple component is increased, in regions where DC output voltage is low.
  • the present applicant previously proposed U.S. Pat. No. 4,245,293.
  • the ignition phase angles of the groups of thyristors on the positive and negative sides in the low output voltage region are defined as being different in order to make improvements by causing a short-circuiting mode between both the groups of thyristors.
  • the mode of supplying power to an AC load by connecting controllable switching means with the function of breaking current to the positive arm of a full wave bridge circuit to control the switching means and by rectifying an AC power source and the mode of causing the current flowing through the DC load to flow back at the time of breaking current in the power supplying mode are repeated and AC-to-DC power conversion may be carried out.
  • An object of the present invention is to provide a highly reliable power converter apparatus with the greater power-factor by preventing controllable switching means having a current-breaking function from being destroyed at the time of carrying out AC-to-DC power conversion.
  • the present invention is intended to clarify the fact that, when controllable switching means having a current-breaking function are used to carry out AC-to-DC power conversion by repeating power supplying and flow-back modes, overvoltage is generated on the DC load side at the time of switching both the modes and the overvoltage becomes one of the factors causing the switching means to be destroyed; the feature of the present invention is that it provides a period during which either of supply and flow-back currents are allowed to flow when one mode is switched over to the other so as to suppress the overvoltage on the DC load side.
  • FIGS. 1-9 are diagrams illustrating examples of the present invention.
  • FIG. 1 is a structural diagram of a power converter apparatus.
  • FIG. 2 is a structural diagram of a gate pulse generator circuit.
  • FIG. 3 is an output pulse waveform chart of the NAND circuit.
  • FIG. 4 is a waveform chart illustrating the relation between phase voltage and the output pulse of the gate pulse generator circuit.
  • FIGS. 5A and 5B are a diagram illustrating flow-back and power supply modes in operation.
  • FIG. 6 a waveform chart of a signal in each portion when a pulse signal regulator circuit is not provided.
  • FIG. 7 is a graphic representation explanatory of the characteristics of overvoltage.
  • FIG. 8(A) is a structural diagram of the pulse signal regulator circuit.
  • FIG. 8(B) is an internal configuration of NAND and NOR elements.
  • FIG. 9 is a waveform chart of a signal in each portion when the pulse signal regulator circuit is provided.
  • FIG. 1 is an example of the power converter apparatus according to the present invention, wherein its overall configuration is shown.
  • FIG. 1 there is shown an full wave bridge circuit comprising GTO elements GTOU1-GTOW1 connected to each of its positive arms and thyristors U2-W2 connected to its negative arms.
  • a three-phase AC supply Ea is connected to an AC terminal of the full wave bridge circuit.
  • the DC output voltage Eo of the full wave bridge circuit is applied to a load L including resistance RL, inductance LL, and DC voltage EL.
  • the time constant LL/RL of the load L is assumed to be sufficiently longer than the period of the AC supply and the DC voltage LE is made to have a value lower than the output voltage Eo. For instance, a condition like this is established when an armature circuit as the load L is connected to control a DC motor by means of the full wave bridge circuit.
  • a gate control circuit GC controls the DC output voltage Eo by controlling the GTO elements GTOU1-GTOW1 and thyristors U2-W2 according to a voltage command signal Sv.
  • This gate control circuit GC is mainly made up of a phase-shifted signal generator PS, a chopping signal generator CSG and a gate pulse generator PC.
  • a transformer Tr converts the three-phase supply Ea to line voltages UW, VU, WV having a neutral point and inputs the voltages to phase shifters PU, PV, PW.
  • the input of a phase commanding signal S ⁇ is also given to the phase shifters PU, PV, PW.
  • the phase commanding signal S ⁇ is prepared by a function generator F ⁇ having such an output (shown) that the control angle of lag ⁇ becomes zero within a large range of voltage commanding signals Sv, or a large range of output voltage. Therefore, the phase shifters PU, PV, PW generate a phase pulse corresponding to the phase commanding signal S ⁇ and inputs the pulse to the gate pulse generator circuit PC and chopping signal generator circuit CGS.
  • the positive half wave of the supply Ea and the negative half wave of the supply Ea are generated from pins No. 4 and 2 of the phase shifters PU, PV, PW, respectively.
  • a known pin No. 7 generates pulses GU'1-GW'1, GU'2-GW'2 of the positive and negative half waves of the supply Ea.
  • This pin No. 7 inputs the phase-shifting pulse signals GU'1,-GW'1, GU'2-GW'2 of the positive and negative half waves generated to a synchronizing pulse generator circuit S.
  • This synchronizing pulse generator circuit S is composed of a pulse generator, a flip flop and the like, and drives the pulse generator in synchronism with the phase shifting pulse signals GU'1-GW'2 while generating a synchronizing pulse P6 with frequencies higher than those of the AC supply E ⁇ .
  • This synchrozing pulse P6 is used as a chopping reference pulse of the pulsewidth control phase shifter PP of the GTO element.
  • a pulsewidth commanding signal S P is applied to the GTO pulsewidth control phase shifter PP.
  • This GTO pulsewidth commanding signal S P is obtained from a function generator F P generating such a signal (characteristics are shown) as is provided with small and constant pulsewidth within a small range of voltage commanding signals Sv, or small range of output voltage, and with large pulsewidth within a large range of voltage commanding signals Sv, or a large range of output voltage.
  • the GTO pulsewidth control phase shifter PP generates a chopping signal CS corresponding to the pulsewidth commanding signal S P with the frequency of the synchronizing pulse P6 and inputs the signal to the gate pulse generator circuit PC.
  • the gate pulse generator circuit PC generates pulse signals TGU1-TGW1 for the GTO elements GTOU1-GTOW1 and gate signals TGU2-TGW2 for the thyristors U2-W2 based on the above-mentioned input signals as described later.
  • the pulse signals TGU1-TGW1 is given to a gate signal amplifier GA.
  • the gate signal amplifier GA generates gate pulses GTU1-GTW1 sent to the GTO elements GTOU1-GTOW1.
  • the feature is that the pulse signal regulator circuit PSR is provided in the pulse generator circuit PC so as to regulate the pulse signals TGU1-TGW1 in such a manner that the power supply and flow-back modes of the full wave bridge circuit are overlapped.
  • FIG. 2 The details of the pulse generator circuit PC is subsequently shown in FIG. 2.
  • the pulse generator circuit is the same as what has been disclosed in the British Patent Official Gazette No. 1,076,233.
  • the pulses GU2-GW2 obtained from the terminals of the three phase phase shifter PU-PW are used as the gate signals TGU2-TGW2 for the thyristors U2-W2.
  • FIG. 4 illustrates the waveforms of the gate signals TGU2-TGW2.
  • a group of pulses GU1-GW2 obtained from the terminals 2 and 4 of the three phase phase shifters PU-PW are given to flip flop circuits FFU-FFW to obtain output pulses GU4-GW4.
  • These pulses GU4-GW4 and the chopping signal CS from the chopper signal generator CGS are applied to an inverter circuit NT so that pulses GR4-GW4 with inverted codes and CS can be obtained.
  • a NAND circuit NA3 Based on the above pulses, a NAND circuit NA3 outputs pulses PN1-PN6 shown in FIG. 3. These pulses PN1-PN6 are given to a NOR circuit NR through the pulse signal regulator circuit PSR as described later and the NOR circuit NR outputs the pulses TGU1-TGW1 shown in FIG. 4.
  • the pulses TGU1-TGW1 indicate a period during which each of the GTO elements GTOU1-GTOW1 are conducting.
  • FIG. 4 illustrates the waveforms of the phase voltages U, V, W of the three phase AC supply Ea, pulse signals TGV1-TGW1 and gate signals TGV2-TGW2.
  • the pulse signals TGV1-TGW1 are converted to those which turn on the GTO element at the time of its rising by means of the gate signal amplifier GA and off the element at the time of its decaying, and become the gate signals GTU1-GTW1 for the GTO elements.
  • the pulse signals TGV1-TGW1 indicate a period during which the GTO elements GTOU1-GTOW1 are conducting when they are "1", whereas a period during which the GTO elements GTOU1-GTOW1 are not conducting when they are "0".
  • the operation during a period A in FIG. 4 is such that, because the pulse signal TGU1 and gate signal TGV2 are "1" at first, the GTO element GTOU1 and thyristor V2 conducts, forming the mode in which power is supplied from the supply Ea to the load L.
  • a circuit shown by an actual line in FIG. 5(B) is formed and supply current Is from the supply Ea is allowed to flow along a loop ⁇ 1 .
  • the on-off operations of the above GTOU1 and GTOV1 form a pair and cause the power supply and flow-back modes to be alternately repeated so as to supply DC power to the load L.
  • a capacitor C SU , diode D SU and resistor R SU added to FIG. 5 constitute a known snubber circuit for absorbing overvoltage generated when the GTO element GTOU1 is interruped. Moreover, diodes D U1 , D U2 are intended to protect the GTO element GTOU1 from reverse voltage. These snubber circuit and diodes D U1 , D U2 are provided in each of other GTO elements GTOV1, GTOW2.
  • the conventional pulse signal TGU1-TGW1 as shown in FIG. 6 tends to cause by nature its rising to be delayed and its decaying to be quickened. This is due to the connected capacitor for improving noise resistance and the floating capacitance of a signal line and is the phenomenon necessarily occurred because of the circuit configuration.
  • each one of the pulse signals GU1 and TGV1 is shown in FIG. 6, the same is applied to other pulse signals.
  • the pulse signal TGV1 sharply decays at time t1, whereas the pulse signal TGU1 slowly rises.
  • the pulse signals TGV1 and TGU7 are applied to the gate signal amplifier GA and converted to the gate signals GTV1 and GTU1.
  • the gate signal amplifier GA is known to generate a gate signal when off voltage becomes less than ⁇ V1 and an on gate signal when on voltage exceeds ⁇ V2.
  • the on gate signal is generated in the gate signal GTV1 at the time T2 when the pulse signal TGV1 becomes less than ⁇ V1.
  • the off gate signal is generated in the gate signal GTU1 at time t3; that is, the time difference between the off gate of the gate signal GTV1 and the on gate of the gate signal GTU1 occurs.
  • the constant-current operation of the inductance component LL of the load L causes the flow-back current to flow into the capacitor C SV connected to GTOV1 in parallel during the time difference t.
  • the on gate is generated in the gate signal GTV1 at the time t5. Therefore, the constant current operation of the inductance component LL of the load L in this case causes the current to flow into the capacitor C SU connected to the GTO element GTOU1 in parallel.
  • the charge voltage ⁇ V SU of the capacitor C SU in this case becomes much greater because the supply voltage Ea is added.
  • the charge voltages ⁇ V SU , ⁇ V SV will exceed, as shown in FIG. 7, the threshold voltage Vmax allowable for the GTO elements GTOU1-GTOW1, causing the breakdown of the GTO elements.
  • FIG. 8 shows the configuration of the pulse signal regulator circuit PSR. As shown in FIG. 8, the circuit comprises resistors R1-R6, diodes D1-D6 and capacitors C1-C6.
  • the pulse signal regulator circuit PSR inputs the output pulse signals P N1 -P N6 of the NAND circuit NA3 shown in FIG. 3 and regulates the circuit in such a manner that overlapping occurs when the pulse signals TGU1-TGW1 rise and decay. For this reason, it has been so arranged that the above overvoltage generated in the full wave bridge circuit may be suppressed.
  • the time difference shown in FIG. 6 occurs in the conventional pulse signals TGU1-TGW1. This is due to the capacitor connected for absorbing surge and the floating capacitance of a signal line; this is equivalently shown in FIG. 8(A) by means of capacitors C7-C9.
  • the pulse signals TGU1-TGW1 are prepared by the NOR circuit NR based on the pulse signals P N1 -P N6 shown in FIG. 3. Consequently, in this example, the object of the present invention has been attained by regulating these pulse signals P n1 -P N6 .
  • the pulse signal P N1 rises with the time constant consisting of the internal resistance R9 of the NAND element NAND 1, resistance R1 and capacitor C1.
  • the signal P N1 decays, the charge of the capacitor C1 sharply decays through the diode D1 and the internal transistor T4 of the NAND element NAND1. Therefore, input signal P N1' of the NOR element NOR1 has a pulse slow in rising and quick in decaying.
  • the pulse signal TGU1 rises at the time t1
  • the pulse signal TGV1 decays at the time t2; that is, an overlapped time T becomes available.
  • the pulse signals TGU1 and TGV1, based on the relation between the NOR elements NOR1, NOR2 and the capacitor for absorbing surge and floating capacitance show their waveforms slow in rising and quick in decaying.
  • the power supply mode of the GTO element GTOU1, load L, thyristor V2, and supply Ea occurs on the instant that the operating of interrupting the current If flowing in the flow-black of the GTO elment GTOV1, load L and thyristor V2; that is, as shown in FIG. 9, the flow-back current If is decreasing, while the power supply current Is is increasing.
  • the GTO/element GTOV1 conducts the so-called operation of rectifying the supply, or turningoff as the GTO/element GTOU1 operates, so that an overvoltage because of the inductance LL of the load L will not occur.
  • the above operation is also applicable to a case in which the GTO element GTOV1 is made to conduct by interrupting the GTO element GTOU1, that is, the power supply mode is switched over to the flow-back one, and the overvoltage can be suppressed.
  • switching means having a currentbreaking function are not limited to GTO elements and, as mention has been made in the beginning, known transistors, chopper apparatus and the like may also be employed.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)
  • Rectifiers (AREA)
  • Power Conversion In General (AREA)
  • Control Of Direct Current Motors (AREA)
US06/473,729 1982-03-10 1983-03-09 AC-to-DC power converter with improved power factor and overvoltage suppression Expired - Fee Related US4584636A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP57036471A JPS58154377A (ja) 1982-03-10 1982-03-10 電力変換装置
JP57-36471 1982-03-10

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US4584636A true US4584636A (en) 1986-04-22

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US06/473,729 Expired - Fee Related US4584636A (en) 1982-03-10 1983-03-09 AC-to-DC power converter with improved power factor and overvoltage suppression

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US (1) US4584636A (ru)
JP (1) JPS58154377A (ru)
KR (1) KR900003483B1 (ru)
CA (1) CA1194931A (ru)
GB (1) GB2116786B (ru)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5483141A (en) * 1992-12-03 1996-01-09 Kabushiki Kaisha Toshiba Method and apparatus for controlling refrigerator cycle
US5491624A (en) * 1993-06-29 1996-02-13 Square D Company AC to DC power conversion system
WO2002035703A2 (en) * 2000-10-11 2002-05-02 General Electric Company A system and method for grouped gating control logic

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2140987B (en) * 1983-04-15 1986-11-19 Hitachi Ltd Control apparatus for current type inverter
JPS60156270A (ja) * 1984-01-25 1985-08-16 Hitachi Ltd 電力変換装置の駆動制御装置
JPH0822145B2 (ja) * 1984-06-12 1996-03-04 株式会社日立製作所 電力変換装置
JPH0655032B2 (ja) * 1986-02-03 1994-07-20 株式会社日立製作所 電流型コンバ−タの保護装置
RU2498493C2 (ru) * 2010-12-08 2013-11-10 Государственное образовательное учреждение высшего профессионального образования Самарский государственный технический университет Способ управления тиристорами в реверсивном трехфазном тиристорном электроприводе и устройство для его реализации

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3622862A (en) * 1970-10-22 1971-11-23 Asea Ab By-pass connection of static converters
US3842335A (en) * 1972-05-18 1974-10-15 Asea Ab Static current converter with bypass members
US4245293A (en) * 1977-10-08 1981-01-13 Hitachi, Ltd. Power converter system
US4272807A (en) * 1979-07-20 1981-06-09 Contraves Goerz Corporation Regenerative DC power supply
GB2076233A (en) * 1980-05-16 1981-11-25 Hitachi Ltd Power converter apparatus
US4447868A (en) * 1982-04-05 1984-05-08 General Electric Company Regenerative rectifier circuit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5027939A (ru) * 1973-07-16 1975-03-22

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3622862A (en) * 1970-10-22 1971-11-23 Asea Ab By-pass connection of static converters
US3842335A (en) * 1972-05-18 1974-10-15 Asea Ab Static current converter with bypass members
US4245293A (en) * 1977-10-08 1981-01-13 Hitachi, Ltd. Power converter system
US4272807A (en) * 1979-07-20 1981-06-09 Contraves Goerz Corporation Regenerative DC power supply
GB2076233A (en) * 1980-05-16 1981-11-25 Hitachi Ltd Power converter apparatus
US4361866A (en) * 1980-05-16 1982-11-30 Hitachi, Ltd. Power converter apparatus
US4447868A (en) * 1982-04-05 1984-05-08 General Electric Company Regenerative rectifier circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5483141A (en) * 1992-12-03 1996-01-09 Kabushiki Kaisha Toshiba Method and apparatus for controlling refrigerator cycle
US5491624A (en) * 1993-06-29 1996-02-13 Square D Company AC to DC power conversion system
WO2002035703A2 (en) * 2000-10-11 2002-05-02 General Electric Company A system and method for grouped gating control logic
WO2002035703A3 (en) * 2000-10-11 2002-07-25 Gen Electric A system and method for grouped gating control logic

Also Published As

Publication number Publication date
KR900003483B1 (ko) 1990-05-19
JPS58154377A (ja) 1983-09-13
GB8306345D0 (en) 1983-04-13
CA1194931A (en) 1985-10-08
KR840004321A (ko) 1984-10-10
GB2116786A (en) 1983-09-28
JPH0379951B2 (ru) 1991-12-20
GB2116786B (en) 1985-09-04

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