US4368427A - Digital indication type speedometer - Google Patents

Digital indication type speedometer Download PDF

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Publication number
US4368427A
US4368427A US06/218,834 US21883480A US4368427A US 4368427 A US4368427 A US 4368427A US 21883480 A US21883480 A US 21883480A US 4368427 A US4368427 A US 4368427A
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Prior art keywords
circuit
output
digital
value
indication
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US06/218,834
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English (en)
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Kunihisa Hayashi
Masakazu Moriyama
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Toyota Motor Corp
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Toyota Motor Corp
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Assigned to TOYOTA JIDOSHA KOGYO KABUSHIKI KAISHA reassignment TOYOTA JIDOSHA KOGYO KABUSHIKI KAISHA ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: HAYASHI KUNIHISA, MORIYAMA MASAKAZU
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
    • G01P3/00—Measuring linear or angular speed; Measuring differences of linear or angular speeds
    • G01P3/42—Devices characterised by the use of electric or magnetic means
    • G01P3/44—Devices characterised by the use of electric or magnetic means for measuring angular speed
    • G01P3/48—Devices characterised by the use of electric or magnetic means for measuring angular speed by measuring frequency of generated current or voltage
    • G01P3/481—Devices characterised by the use of electric or magnetic means for measuring angular speed by measuring frequency of generated current or voltage of pulse signals
    • G01P3/489—Digital circuits therefor

Definitions

  • the present invention relates to digital indication type speedometers, and particularly to improvements in a digital indication type speedometer comprising a speed counter for counting speed pulses emitted in proportion to a vehicle speed for a given gate time, an indication register for latching a value to be indicated commensurate to an output from said speed counter and an indicator for indicating the value latched in said indication register.
  • This digital indication type speedometer has such a characteristic feature that the vehicle speed is constantly digitally indicated by the indicator.
  • both of 59 km/h and 60 km/h are alternately indicated.
  • This reaches its worst condition when an intermediate speed between 59 km/h and 60 km/h is set in a cruising speed control device of the vehicle.
  • the response during acceleration or deceleration is taken into consideration, there is a limit in extending the gate time. Consequently, heretofore, there has been selected an intermediate value of a gate time in consideration of both factors as described above. However, the value thus selected could satisfy neither the condition during acceleration or deceleration, nor the condition during running at a constant speed.
  • the present invention has been developed to obviate the abovedescribed disadvantages of the prior art, and has as its object the provision of a digital indication type speedometer capable of making satisfactory indications without presenting any feeling of incompatibility, both in the condition during acceleration or deceleration and the condition during running at a constant speed, and excellent in easiness in reading.
  • a digital indication type speedometer comprising a speed counter for counting speed pulses emitted in proportion to a vehicle speed for a given gate time, an indication register for latching a value to be indicated commensurate to an output from said speed counter and an indicator for indicating the value latched in said indication register is of such an arrangement that a hysteresis processing circuit is provided, which rewrites the value latched in said indication register in accordance with an output of said speed counter only when a difference between the output of said speed counter and the value latched in said indication register is not within tolerance limit upon comparison therebetween.
  • FIG. 1 is a block diagram showing the general arrangement of a first embodiment of the digital indication type speedometer according to the present invention
  • FIG. 2 is a block diagram showing an example of arrangement of the hysteresis processing circuit in the first embodiment
  • FIG. 3 is a diagram showing the waveshapes of the actions of various parts in the first embodiment
  • FIG. 4 is a block diagram showing the general arrangement of a second embodiment of the digital indication type speedometer according to the present invention.
  • FIG. 5 is a block diagram showing a first modification of the hysteresis processing circuit for use in the present invention
  • FIG. 6 is a block diagram showing a second modification thereof.
  • FIG. 7 is a block diagram showing a third modification thereof.
  • a digital indication type speedometer comprises: a speed counter 12 for counting speed pulses 100 emitted in proportion to a vehicle speed through the rotation of the wheel for a given gate time during which an AND gate 10 is opened in response to a gate signal 101; an indication register 14 for latching a value to be indicated in response to an output signal 102 from the speed counter 12; and an indicator 16 comprising any one of an indicating fluorescent tube, a plasma display, a liquid crystal, a luminescent diode and the like for indicating a value 103 latched in the indication register 14; further comprises: a hysteresis processing circuit 18 for emitting a difference signal 104 (a signal indicating the presence of a difference) for rewriting a value latched in the indication register 14 in response to an output signal 102 of the speed counter 12 only when a difference between the output signal 102 from the speed
  • designated at 22 is an OR gate for emitting a logical sum of an output from the hysteresis processing circuit 18 and an output from the zero indication discriminating circuit 20; 24 an AND gate for feeding an output signal 105 of the OR gate 22 to the indication register 14 in response to a latch signal 106 emitted from a timing pulse generating circuit 26 at a timing suitable for rewriting the indication register 14, and 26 the timing pulse generating circuit for feeding a given gate signal 101 to determine the counting time of the speed counter 12, the gate-on timing of which is synchronized with the rise of the speed pulse 100, to the AND gate 10, further feeding the latch signal 106 to the AND gate 24 at a timing suitable for feeding a counted value of the speed counter 12 to the indication register 14 upon counting, and further feeding a reset signal 107 for restoring the counted value of the speed counter 12 to zero to the speed counter 12 upon feeding the abovedescribed counted value.
  • the aforesaid hysteresis processing circuit 18, as shown in FIG. 2 for example, comprises: a digital subtraction circuit 30 for calculating a difference between the output signal 102 of the speed counter 12 and the value 103 latched in the indication register 14; a digital reference circuit 32 for digitally presetting a hysteresis reference value, e.g., 1 km/h or 1 mile/h; a code-converting circuit 34 for code-converting the digital reference value of the digital reference circuit 32 into a value of complement thereof; a first comparison circuit 36 for emitting an output signal 112 based on an output 110 of the result of subtraction of the digital subtraction circuit 30 when the output from the speed counter 12, exceeding the reference value of the digital reference circuit 32, becomes larger than the value latched in the indication register 14; a second comparison circuit 38 for emitting an output signal 113 also based on the output 110 of the result of subtraction of the digital subtraction circuit 30 when the output from the speed counter 12, exceeding the reference value of the digital reference circuit 32, which
  • this hysteresis processing circuit 18 is adapted to seek a difference between the output signal 102 of the speed counter 12 and the value 103 latched in the indication register 14, and, when the difference is not within the tolerance limit, indicate the difference signal 104 as "1.” More specifically, the value 103 latched in the indication register 14 is subtracted from the output signal 102 from the speed counter 12 in the digital subtraction circuit 30, the result of subtraction is compared with the hysteresis reference value in the digital reference circuit 32, i.e., +1 km/h in the first comparison circuit 36, and, when the result of subtraction is larger than the reference value, the output signal 112 from the comparison circuit 36 is indicated as "1.” Furthermore, in the second comparison circuit 38, the result of subtraction of the digital subtraction circuit 30 is compared with a complement value of the reference value of the digital reference circuit 32 sought in the code-converting circuit 34, and, when the result of subtraction is smaller in value than the output from the code-converting circuit 34, the output signal 113
  • the first AND gate 40 When the result of subtraction of the digital subtraction circuit 30 is positive and the positive-negative sign signal 111 is "1," the first AND gate 40 is opened, and, when the result of subtraction of the digital subtraction circuit 30 is negative and the positive-negative sign signal 111 is "0,” the second AND gate 44 is opened.
  • the OR gate 46 is adapted to indicate the difference signal 104 as "1," when either the first AND gate 40 or the second AND gate 44 emits an output.
  • the speed pulses 100 emitted in proportion to the vehicle speed through the rotation of the wheel as shown in FIG. 3(a) are fed to the speed counter 12 through the AND gate 10 and counted for a given time T during which the gate signal 101 from the timing pulse generating circuit 26 as shown in FIG. 3(b) is indicated as "1" to open the AND gate 10.
  • This gate signal 101 is synchoronized with the rise of the speed pulse 100 to be indicated as "1,” continues to be indicated as "1" for the given time T, and thereafter, is indicated as "0.” With this arrangement, the dispersion in values counted by the speed counter is prevented which is caused by the offset of the gate signals 101 relative to the speed pulses 100.
  • the latch signals 106 as shown in FIG. 3(c) is fed to the AND gate 24 from the timing pulse generating circuit 26.
  • the difference between the output signal 102 of the speed counter 12 and the value 103 latched in the indication register 14 is sought in the hysteresis processing circuit 18, and, when the difference thus sought exceeds the reference value preset by the digital reference circuit 32 in either positive or negative direction, the difference signal 104 is indicated as "1.”
  • This difference signal 104 is fed through the OR circuit 22 to the AND gate 24, where it is turned to be the gate signal for the aforesaid latch signal 106.
  • the output from the AND gate 24 is indicated as "1,” and the value latched in the indication register 14 is rewritten in accordance with the output signal 102 (counted value) from the speed counter 12. While, in the case the difference between the output signal 102 of the speed counter 12 and the value 103 latched in the indication register 14 does not exceed the reference value, the value latched in the indication register 14 is not rewritten.
  • the value latched in the indication register 14 is not changed, whereby the indicated value of the indicator 16 is held at a constant value, so that the indication of the indicator 16 can be prevented from flickering during running at a constant speed.
  • the value latched in the indication register 14 is rewritten every moment, so that problems in response during acceleration or deceleration can be eliminated.
  • the provision of the hysteresis processing circuit 18 as described above can prevent the indication of the indicator 16 from flickering. While, in the case, despite the difference between the output from the speed counter 12 and the value latched in the indication register 14 is within the tolerance limit, it is desired to set the value indicated by the indicator 16 to the predetermined value, e.g., when the vehicle is stopped, the value latched in the indication register 14 stays at 1 and does not become zero due to the action of the aforesaid hysteresis processing circuit 18, thereby giving a feeling of incompatibility to the driver. Consequently, in this embodiment, the provision of the zero indication discriminating circuit 20 solves this problem.
  • the zero indication discriminating circuit 20 constantly monitors the output from the speed counter 12, and, when the output signal 102 from the speed counter 12 becomes zero, feeds the zero signal 105 to the OR gate 22 irrespective of the condition of the output from the hysteresis processing circuit 18, the value latched in the indication register 14 is rewritten by the AND gate 24 in accordance with the output signal 102 (0) of the speed counter 12 at a timing corresponding to the latch signal 106 from the timing pulse generating circuit 26, the value latched in the indication register 14 becomes zero, and the indicated value of the indicator 16 become 0 km/h or 0 mile/h.
  • FIG. 4 shows a second embodiment of the present invention in which the abovedescribed requirement is fulfilled.
  • This embodiment is of such an arrangement that the zero indication discriminating circuit 50 emits "1" as the zero indication signal when the output signal 102 of the speed counter 12 reaches a predetermined value, e.g., a value corresponding to 5 km/h or less, and this embodiment further comprises an AND gate 52 for feeding a logical product of the zero indication signal 108 and the latch signal 106 from the timing pulse generating circuit 26 to the indication register 14 as a reset signal and a three input AND gate 56 for feeding a logical product of the zero indication signal 108 inverted by the invertor 54, the latch signal 106 and the difference signal 104 from the hysteresis processing circuit 18 to the indication register 14 as a latch signal.
  • This second embodiment is identical in other respects with the aforesaid first embodiment, so that detailed description thereof will be omitted.
  • the zero indication signal 108 from the zero indication discriminating circuit 50 is indicated as "1.” Consequently, irrespective of the condition of the output from the hysteresis processing circuit 18, when the latch signal 106 from the timing pulse generating circuit 26 is indicated as "1," the value latched in the indication register 14 is forcibly reset to zero, and consequently, the indicated value of the indicator 16 is set at 0 km/h or 0 mile/h in advance of the actual vehicle speed.
  • the hysteresis processing circuits each comprise digital circuits, and the reference values are ones identical with each other in either positive or negative direction.
  • the hysteresis processing circuits are not limited to ones shown in the abovedescribed embodiments.
  • FIG. 5 shows a first modification of the hysteresis processing circuit for use in the present invention.
  • This hysteresis processing circuit 60 comprises: a degital subtraction circuit 30 similar to the one shown in the proceeding embodiment; a digital/analog converter (hereinafter referred to as the "D/A converter") 62 for converting an output 110 (a digital signal) as the result of subtraction in the digital subtraction circuit 30 into an analog signal; an absolute value circuit 64 for obtaining an absolute value of an output from the D/A converter 62; and a comparison circuit 68 for comparing an output from the absolute value circuit 64 with an analog-preset hysteresis reference value in an analog reference circuit 66 and emitting a difference signal 104.
  • D/A converter digital/analog converter
  • an output 110 (a digital signal) as the result of subtraction in the digital subtraction circuit 30 is converted into an analog signal having a voltage which is positive or negative by the D/A converter 62. More specifically, in the case the output signal 102 from the speed counter 12 is larger in value than the value 103 latched in the indication register 14, a positive voltage is supplied, and, in the case the output signal 102 from the speed counter 12 is smaller in value than the value 103 latched in the indication register 14, a negative voltage is supplied.
  • the positive or negative voltage as an output from this D/A converter 62 is obtained by the absolute value circuit 64 as an absolute value, which is compared, in the comparison circuit 68, with the reference value preset in the analog reference circuit 66, and, when the output from the absolute value circuit 64 is larger than the reference value, the difference signal 104 is indicated as "1."
  • FIG. 6 shows a second modification of the hysteresis processing circuit for use in the present invention.
  • This hysteresis processing circuit 70 comprises: a digital subtraction circuit 30 similar to the one shown in the preceding embodiment; a first digital reference circuit 72 for digitally presetting a positive hysteresis reference value; a first comparison circuit 36 similar to the one shown in the preceding embodiment for comparing the positive reference value preset by the first digital reference circuit 72 with the output 110 as the result of subtraction in the digital subtraction circuit 30 and emitting an output signal 112 when the result of subtraction is larger in value than the positive reference value; a second digital reference circuit 74 for digitally presetting a negative hysteresis reference value; a second comparison circuit 38 similar to the one shown in the preceding embodiment for emitting an output signal 113 when the output 110 as the result of subtraction in the digital subtraction circuit 30 is smaller in value than the negative reference value; and an OR gate 76 for emitting a logical sum of outputs from the first
  • the positive reference value is preset at a value different from the negative reference value, so that the actual control of the law in which the control on the positive side is loose but severe on the negative side can be readily dealt with.
  • FIG. 7 shows a third modification of the hysteresis processing circuit for use in the present invention.
  • This hysteresis processing circuit 80 comprises: a digital subtraction circuit 30 similar to the one shown in the preceding embodiment; a D/A converter 62 similar to the one shown in the first modification; a first analog reference circuit 82 for analogously presetting a positive hysteresis reference value; a first comparison circuit 84 for comparing the positive reference value of the first analog reference circuit 82 with an output from the D/A converter 62 and emitting an output when the output from the D/A converter 62 is larger in value than the positive reference value; a second analog reference circuit 86 for analogously presetting a negative hysteresis reference value; a second comparison circuit 88 for comparing the negative reference value of the second analog reference circuit 86 with an output from the D/A converter 62 and emitting an output when the output from the D/A converter 62 is smaller in value than the negative reference value; and an OR gate 90 for emit
  • the positive reference value is preset at a value different from the negative reference value, so that the control of the law can be readily dealt with.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Analogue/Digital Conversion (AREA)
  • Linear Or Angular Velocity Measurement And Their Indicating Devices (AREA)
  • Measuring Frequencies, Analyzing Spectra (AREA)
  • Indication And Recording Devices For Special Purposes And Tariff Metering Devices (AREA)
US06/218,834 1979-12-28 1980-12-22 Digital indication type speedometer Expired - Lifetime US4368427A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP54170606A JPS6029069B2 (ja) 1979-12-28 1979-12-28 デジタル表示式車速計
JP54-170606 1979-12-28

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US4368427A true US4368427A (en) 1983-01-11

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US (1) US4368427A (de)
EP (1) EP0031702B1 (de)
JP (1) JPS6029069B2 (de)
AU (1) AU542417B2 (de)
CA (1) CA1166716A (de)
DE (1) DE3070248D1 (de)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4472775A (en) * 1980-11-20 1984-09-18 Nippondenso Co., Ltd. Display method and system
US4683545A (en) * 1983-08-30 1987-07-28 La Telemecanique Electrique Speed determining process and a device for implementing same
US4800377A (en) * 1987-05-20 1989-01-24 Slade Charles E Speed reducing signal
US5656992A (en) * 1996-03-25 1997-08-12 Mcneill; Sheila Ann Externally mounted vehicle speedometer display
US6018240A (en) * 1997-03-12 2000-01-25 Yazaki Corporation Cross-coil measuring meter driving device having a period range judging means and an after-change supply prevention means
US6333687B1 (en) 1995-05-04 2001-12-25 Labelle Paul J. Automatic underspeed warning system
US20070296478A1 (en) * 2000-06-19 2007-12-27 Silicon Labs Cp Inc. Integrated circuit package including programmable comparators
US10404239B2 (en) 2016-06-03 2019-09-03 Caterpillar Inc. Control system for controlling operation of a machine by imposing shaped hysterisis

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5710455A (en) * 1980-06-23 1982-01-20 Toyota Motor Corp Digital speedometer
JPS60228926A (ja) * 1984-04-26 1985-11-14 Tokyo Electric Co Ltd ラベルプリンタ付き電子料金秤
US4894613A (en) * 1988-09-02 1990-01-16 Hamilton Standard Controls, Inc. Inductive speed sensor having switching hysteresis for increasing the magnitude of a phase shift
DE3927966A1 (de) * 1989-08-24 1991-02-28 Vdo Schindling Verfahren und schaltungsanordnung zur erzeugung einer eingangsgroesse fuer ein kreuzspulanzeigeinstrument
FR2664387B1 (fr) * 1990-07-03 1992-10-23 Cogema Dispositif de controle de l'absence de mouvement d'un appareil electrique portatif.
JPH065556U (ja) * 1992-06-30 1994-01-25 西川産業株式会社 敷用寝具

Citations (3)

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US4151466A (en) * 1977-12-05 1979-04-24 Ford Motor Company Digital speedometer with index counter control of display
US4204157A (en) * 1978-05-12 1980-05-20 Motorola, Inc. Periodic engine speed monitoring circit utilizing sampling circuitry
US4243938A (en) * 1978-10-16 1981-01-06 The Echlin Manufacturing Company Digital bar graph tachometer

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US3908116A (en) * 1974-08-16 1975-09-23 Rockwell International Corp Digital data filter
US3962567A (en) * 1975-01-13 1976-06-08 Trw Inc. Digital display apparatus having jitter correction
US4007419A (en) * 1975-10-02 1977-02-08 Richard Jasmine Digital bicycle speedometer-odometer
US4076999A (en) * 1976-02-19 1978-02-28 General Electric Company Circuit for limiting the spindle speed of a machine
US4091662A (en) * 1977-07-18 1978-05-30 Ervin Mitchel Emanuel Apparatus for testing the performance of electric motors
US4158172A (en) * 1977-12-05 1979-06-12 Ford Motor Company Digital speedometer for indicating velocity in at least two selectable units of measurement

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4151466A (en) * 1977-12-05 1979-04-24 Ford Motor Company Digital speedometer with index counter control of display
US4204157A (en) * 1978-05-12 1980-05-20 Motorola, Inc. Periodic engine speed monitoring circit utilizing sampling circuitry
US4243938A (en) * 1978-10-16 1981-01-06 The Echlin Manufacturing Company Digital bar graph tachometer

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4472775A (en) * 1980-11-20 1984-09-18 Nippondenso Co., Ltd. Display method and system
US4683545A (en) * 1983-08-30 1987-07-28 La Telemecanique Electrique Speed determining process and a device for implementing same
US4800377A (en) * 1987-05-20 1989-01-24 Slade Charles E Speed reducing signal
US6333687B1 (en) 1995-05-04 2001-12-25 Labelle Paul J. Automatic underspeed warning system
US5656992A (en) * 1996-03-25 1997-08-12 Mcneill; Sheila Ann Externally mounted vehicle speedometer display
US6018240A (en) * 1997-03-12 2000-01-25 Yazaki Corporation Cross-coil measuring meter driving device having a period range judging means and an after-change supply prevention means
US20070296478A1 (en) * 2000-06-19 2007-12-27 Silicon Labs Cp Inc. Integrated circuit package including programmable comparators
US7613901B2 (en) * 2000-06-19 2009-11-03 Silicon Labs Cp, Inc. Comparators in IC with programmably controlled positive / negative hysteresis level and open-drain / push-pull output coupled to crossbar switch or rising / falling edge interrupt generation
US10404239B2 (en) 2016-06-03 2019-09-03 Caterpillar Inc. Control system for controlling operation of a machine by imposing shaped hysterisis

Also Published As

Publication number Publication date
AU6585080A (en) 1981-07-02
AU542417B2 (en) 1985-02-21
JPS5694269A (en) 1981-07-30
EP0031702A1 (de) 1981-07-08
DE3070248D1 (en) 1985-04-04
CA1166716A (en) 1984-05-01
EP0031702B1 (de) 1985-02-27
JPS6029069B2 (ja) 1985-07-08

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