US3990090A - Semiconductor controlled rectifier - Google Patents

Semiconductor controlled rectifier Download PDF

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Publication number
US3990090A
US3990090A US05/460,479 US46047974A US3990090A US 3990090 A US3990090 A US 3990090A US 46047974 A US46047974 A US 46047974A US 3990090 A US3990090 A US 3990090A
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layer
semiconductor
electrode
junction
principal surface
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US05/460,479
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Yoshio Terasawa
Shin Kimura
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Hitachi Ltd
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Hitachi Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/192—Base regions of thyristors
    • H10D62/206—Cathode base regions of thyristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/233—Cathode or anode electrodes for thyristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/291—Gate electrodes for thyristors

Definitions

  • the present invention relates to a semiconductor controlled rectifier, and more particularly to a semiconductor controlled rectifier provided with an auxiliary electrode near the gate electrode.
  • a semiconductor controlled rectifier which is turned on in response to a gating signal applied to the gate electrode, comprises a semiconductor substrate having at least four layers of P and N conductivity types, disposed alternately; a pair of main electrodes kept in ohmic contact with the outer surfaces of two outermost layers; and a gate electrode connected with one of the four layers of the substrate. If a gating signal is applied to the gate electrode of such a semiconductor controlled rectifieer with a forward voltage applied between the main electrodes, the four-layer region between the main electrodes is driven from its cut-off (non-conductive) state into its conductive state. The change of state from cut-off to conduction is termed "turn-on".
  • a semiconductor controlled rectifier may be turned on by a signal other than a gating signal.
  • the turn-on of a semiconductor controlled rectifier takes place when the forward applied voltage across the device exceeds the maximum allowable voltage or when the rate of increase of the forward voltage, i.e., dv/dt is too great.
  • the phenomenon that the device is turned on by a forward voltage lower than the maximum allowable voltage makes it impossible for a four-or five-layer, three-or four-terminal device to be controlled in its turn-on operation by a gating signal so that it can not be used in a circuit which is operated at high frequency or draws a heavy current. If a semiconductor controlled rectifier is turned on when the rate of increase of the forward voltage, i.e.
  • the semiconductor device is said, in this specification, to have a small dv/dt capability. If the dv/dt capability is small, it is necessary to reduce the rate of increase of the forward voltage applied between the main electrodes by connecting a capacitor between the main electrodes so as not to turn on the device before a gate signal is applied. In this case, the smaller is the dv/dt, the greater capacitance the capacitor must have. Consequently, the overall size of the device is larger than reasonable. Therefore, it is necessary to make the dv/dt capability as high as possible.
  • FIG. 1 shows a well-known four-layer three-terminal SCR (semiconductor controlled rectifier), i.e. thyristor, which has a large dv/dt capability.
  • a semiconductor substrate 1 of four-layer structure has layers P E , N B , P B and N E .
  • the layer N B has N-type conductivity and forms a base.
  • the layers P E and P B have P-type conductivity, serve as an emitter and a base and form a first and a second PN junctions J 1 and J 2 with the layer N B .
  • the layer N E has N-type conductivity and formed in the P-base layer P B to form a third PN junction with the layer P B .
  • An anode electrode 2 and a cathode electrode 3 are disposed on the P-emitter layer P E and the N-emitter layer N E in ohmic contact therewith.
  • a gate electrode 4 is connected with the surface of the P-base layer P B and a resistor 5 is connected between the cathode 3 and the gate 4.
  • the second PN junction J 2 is inversely biased. Accordingly, the width of a depletion layer formed on both the sides of the PN junction J 2 increases so that displacement current flows.
  • the displacement current increases in proportion to the rate of increase of the forward applied voltage.
  • the increase of the forward applied voltage is accompanied by the increase in the leakage current through the second PN junction J 2 .
  • the third PN junction J 3 is forward biassed due to the displacement current and the leakage current so that carriers are injected from the N-emitter layer N E into the P-base layer P B .
  • the degree of the third PN junction J 3 being forward-biased is greater at the peripheral portion of the N-emitter layer N E where the displacement current and the leakage current from the second PN junction J 2 which are not in registration with the N-emitter layer N E concentrate, than at the central portion of the layer N E . Accordingly, if the rate of increase in the forward applied voltage is high enough, the thyristor is erroneously turned on due to the local turn-on phenomenon taking place at the peripheral portion of the N-emitter layer N E .
  • the resistor 5 connected between the cathode 3 and the gate electrode 4, as shown in FIG. 1, enables the displacement and the leakage currents near the gate electrode 4 to flow through the gate electrode 4 and the resistor 5 into the cathode 3 so that the degree of the third PN junction J 3 being forward biased decreases to suppress the erroneous turn-on action to a certain extent.
  • the smaller is the value of the resistor 5, the greater are the displacement current and the leakage current flowing through the resistor 5 into the cathode 3, so that the effect of suppressing the erroneous turn-on increases.
  • the value of the resistor 5 decreases, the current of the gating signal is by-passed through the resistor 5 to decrease the effective gating current. Therefore, a large-current gating signal is needed to effectively turn the thyristor on. This is one of the drawbacks of a conventional thyristor.
  • the leakage current of an SCR at its forward OFF-state is determined depending upon the temperature of the SCR. Accordingly, if the temperature of the device rises and the device is kept at high temperatures, the leakage current increases to turn on the device before a gating signal is applied. Thus, temperature has the same effect as in case where the dv/dt is high. Consequently, the attempts to avoid the effect is necessarily accompanied by the same drawback as is incurred in case of improving the dv/dt capability.
  • One object of the present invention is to provide a semiconductor controlled rectifier having a novel structure.
  • Another object of the present invention is to provide a novel semiconductor controlled rectifier having a high dv/dt capability.
  • An additional object of the present invention is to provide a novel semiconductor controlled rectifier which is almost free from erroneous turn-on operation due to temperature rise.
  • Yet another object of the present invention is to provide a novel semiconductor controlled rectifier which has a large dv/dt capability with rather a small gating current and which is hardly affected by temperature rise.
  • a further object of the present invention is to provide a novel semiconductor controlled rectifier which is adapted for use in a circuit operated with a high voltage or at high frequencies.
  • Yet an additional object of the present invention is to provide a novel semiconductor controlled rectifier having a high reliability.
  • FIG. 1 shows in longitudinal cross section of a conventional semiconductor controlled rectifier
  • FIG. 2 shows in a plan view a semiconductor controlled rectifier as a first embodiment of the present invention
  • FIG. 3 is a cross section taken along line III--III in FIG. 2;
  • FIG. 4 shows in a plan view a semiconductor controlled rectifier as a second embodiment of the present invention
  • FIG. 5 is a cross section taken along line V--V in FIG. 4;
  • FIG. 6 shows in a plan view a semiconductor controlled rectifier as a third embodiment of the present invention.
  • FIG. 7 is a cross section taken along line VII--VII in FIG. 6;
  • FIG. 8 shows in a plan view a semiconductor controlled rectifier as a fourth embodiment of the present invention.
  • FIG. 9 shows in a plan view a semiconductor controlled rectifier as a fifth embodiment of the present invention.
  • FIG. 10 is a cross section taken along lines X--X in FIG. 9;
  • FIG. 11 shows in a plan view a semiconductor controlled rectifier as a sixth embodiment of the present invention.
  • FIG. 12 is a cross section taken along line XII--XII in FIG. 11;
  • FIG. 13 shows in a plan view a semiconductor controlled rectifier as a seventh embodiment of the present invention.
  • FIG. 14 is a cross section taken along line XIV--XIV in FIG. 13;
  • FIG. 15 shows in a plan view a semiconductor controlled rectifier as a eighth embodiment of the present invention.
  • FIG. 16 is a cross section taken along line XVI--XVI in FIG. 15.
  • a semiconductor controlled rectifier i.e. an SCR for short, in which the displacement current and the leakage current are by-passed through an outer portion of a surface where a gate electrode is provided, and more particularly an SCR in which an auxiliary electrode is provided in addition to a gate electrode on the surface of an intermediate layer of a multi-layer semiconductor substrate, and the displacement current and the leakage current are by-passed through the auxiliary electrode.
  • a semiconductor substrate 11 has, between its principal surfaces 111 and 112, four layers P E , N B , P B and N E having different conductivity types.
  • the layer P E is of P-type conductivity and serves as an emitter layer (hereafter referred to as a P E layer);
  • the layer N B is of N-type conductivity and disposed on the P E layer to serve as a base layer and to form a PN junction J 1 therebetween (hereafter referred to as an N B layer);
  • the layer P B is of P-type conductivity and disposed on the N B layer to serve as a base layer and to form a PN junction J 2 therebetween (hereafter referred to as a P B layer);
  • the layer N E is of N-type conductivity and formed in the P B layer to serve as an emitter layer and to form a PN junction J 3 therebetween (hereafter referred to as an N E layer).
  • a pair of main electrodes 12 and 13 is disposed respectively on the principal surfaces 111 and 112 and kept in ohmic contact with the P E layer and the N E layer.
  • a gate electrode 14 is provided on the P B layer in the principal surface 112.
  • An auxiliary electrode 15 is so disposed on the P B layer in the principal surface 112 as to surround the gate electrode 14 on the side opposite to the main electrode 13.
  • the auxiliary electrode 15 has a portion 151 located near the main electrode 13.
  • the gate electrode 14 is so located on the P B layer that if a gate voltage is applied between the gate electrode 14 and the main electrode 13 with the gate electrode 14 maintained at positive potential, most part of the gate current flows from the gate electrode 14 to the N E layer opposite thereto to initially turn on the part of the N E layer opposite to the gate electrode 14.
  • the circuit design is such that the impedance of the path from the gate electrode 14 to the N E layer is smaller than the impedance of the path from the gate electrode 14, through the auxiliary electrode 15, to the N E layer.
  • the gate electrode 14 is formed nearer to the N E layer than the auxiliary electrode 15.
  • the exposed portion of the PN junctions is coated with a passivation layer, or the side surface 113 is inclined with respect to the PN junctions to form a bevel structure and the semiconductor substrate 11 is housed in a hermetical casing.
  • such structures as necessary for an actual device ready for practical application are not the gist of the invention and they are omitted in the figures.
  • the displacement current and the leakage current through that portion of the PN junction J 2 except the portion lying just below the N E layer are prevented from concentrating on the periphery of the PN junction J 3 opposite to the gate electrode 14 and led through the auxiliary electrode 15 to the main electrode 13.
  • the auxiliary electrode 15 and the main electrode 13 are made proximate to each other in the way shown in the figures and in three ways described above and these ways are termed, in this specification, electric proximity means.
  • FIGS. 4 and 5 show an SCR as a second embodiment of the present invention, in which the portion of the main electrode 13 except the portion opposite to the gate electrode 14 is extended beyond the PN junction J 3 toward the P B layer.
  • This structure has the following merits, as compared with that of the first embodiment: (1) the auxiliary electrode 15 and the main electrode 13 are opposed to each other on the P B layer so that even if the displacement current and the leakage current increase, the most part of the currents flows from the P B layer directly to the main electrode 13 with the result that the device is prevented from being erroneously turned on, and (2) the main electrode 13 is in contact with the P B layer on nearly the entire area of the principal surface 112 of the semiconductor substrate 11 so that the erroneous turn-on at other portions of the N E layer than that opposite to the gate electrode 14 can be prevented.
  • FIGS. 6 and 7 show an SCR as a third embodiment of the present invention, in which the auxiliary electrode 15 is connected with the main electrode 13 at the place remote from the gate electrode 14.
  • the electric resistance between the auxiliary electrode 15 and the main electrode 13 is smaller than in the second embodiment so that the dv/dt capability is further improved.
  • the gate current necessary to turn on the device must be appreciably increased. This problem can be solved by the fourth embodiment of the invention described below.
  • FIG. 8 shows an SCR as a fourth embodiment of the present invention, in which the portion of the P B layer around the gate electrode 14 is made thin through etching or other suitable methods.
  • FIGS. 9 and 10 shown an SCR as a fifth embodiment of the present invention, in which the auxiliary electrode 15 and the main electrode 13 are integrally formed, with the gate electrode 14 provided on the edge of the N E layer.
  • the auxiliary electrode 15 and the main electrode 13 are located opposite to each other with respect to the gate electrode 14. It is preferable to reduce the thickness of the N E layer between the gate electrode 14 and the main electrode 13. This structure can enjoy the same effect as the structures of the foregoing embodiments.
  • the integral formation of the auxiliary electrode 15 and the main electrode 13 may be replaced by other electric proximity means.
  • FIGS. 11 and 12 show an SCR as a sixth embodiment of the present invention, in which the auxiliary electrode 15 is so provided on the P B layer as to encircle the main electrode 13 and the gate electrode 14 and the portions 131 of the main electrode 13 are extended beyond the PN junction J 3 toward the auxiliary electrode 15 at the places remote from the gate electrode 14.
  • the dv/dt capability and the forward blocking voltage are lower than in the structure of the third embodiment shown in FIGS. 6 and 7, but there is an advantage that since the by-pass of the gate current decreases, the gate current necessary to turn on the device can be made smaller.
  • FIGS. 13 and 14 show an SCR as a seventh embodiment of the present invention, in which the amplifying gate configuration is employed.
  • a small region N o of N-type conductivity is formed in the P B layer between the gate electrode 14 and the N E layer
  • the auxiliary electrode 15 is provided on both the surfaces of the P B layer and the small region N o except the portion of the P B layer surface around the gate electrode 14 and the portion of the surface of the small region N o near the gate electrode 14, and the portions 131 of the main electrode 13 are extended beyond the PN junction J 3 toward the auxiliary electrode 15 at the places remote from the gate electrode 14.
  • This structure has an advantage that the initial turn-on over a large area of the N E layer can be caused with a small gate current through the gate electrode 14, as well as the effects obtained by the previous embodiments, and the structure is most suitable for a high power SCR.
  • the auxiliary electrode 15 is shown as encircling the N E layer, but it need not necessarily encircle the N E layer.
  • the shape of the auxiliary electrode 15 should be determined depending upon the area of the initial turn-on region and the required dv/dt capability.
  • the size of each portion 131 and the number of the portions 131 should also be determined for the same reason. Further, in this case, the same result can be obtained even if the portion of the auxiliary electrode 15 between the main electrode 13 and the gate electrode 14 is removed.
  • FIGS. 15 and 16 show an SCR as an eighth embodiment of the present invention, in which the present invention is applied to a device in which PN junctions are exposed in one of the principal surfaces of the semiconductor substrate (i.e. a device of lateral type).
  • the difference of this embodiment from the previous ones is that all the PN junctions J 1 , J 2 and J 3 are exposed in the principal surface 112 while a pair of main electrodes 12 and 13 are in ohmic contact with the P E and N E layers on the principal surface 112.
  • the gate electrode 14 and the auxiliary electrode 15 have structures analogous to those in the previous embodiments and therefore can enjoy the same effects.
  • the present invention can be applied to any SCR that has a PNPN structure and is turned on by a gating signal received at the gate electrode, irrespective of the disposition of the PN junctions (as in the bevel, mesa, planar and lateral types) and the structure of the gate (as in the spot gate, stripe gate, field effect gate, amplifying gate, P-gate and N-gate types).
  • the present invention can be applied to each SCR element of a semiconductor device consisting of two PNPN SCR's formed integrally in the inverse parallel configuration or of a PNPN SCR and a PN junction rectifier formed integrally in the inverse parallel configuration.
  • an improved device with the auxiliary electrode 15 and the portions 131 has a dv/dt capability of 1200 V/ ⁇ s and a forward blocking voltage of 3000 V, which are more than twice compared with those of the conventional device.
  • the dv/dt capability of the conventional device at 20° C is 600 V/ ⁇ s, but the device according to the present invention is not turned on at a forward applied voltage increase rate dv/dt of 600 V/ ⁇ s even at 120° C.
  • the temperature characteristic is much improved according to the present invention.

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US05/460,479 1973-04-18 1974-04-12 Semiconductor controlled rectifier Expired - Lifetime US3990090A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4210924A (en) * 1977-09-14 1980-07-01 Hitachi, Ltd. Semiconductor controlled rectifier with configured cathode to eliminate hot-spots
EP0046578A3 (en) * 1980-08-22 1983-06-22 Tokyo Shibaura Denki Kabushiki Kaisha Power thyristor
US4414559A (en) * 1978-03-31 1983-11-08 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor thyristor device with laterally displaced auxiliary and main cathode regions

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5927108B2 (ja) * 1975-02-07 1984-07-03 株式会社日立製作所 半導体制御整流装置

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3360696A (en) * 1965-05-14 1967-12-26 Rca Corp Five-layer symmetrical semiconductor switch
US3428874A (en) * 1965-05-14 1969-02-18 Licentia Gmbh Controllable semiconductor rectifier unit
US3462620A (en) * 1967-07-18 1969-08-19 Int Rectifier Corp Axial bias gate for controlled rectifiers
US3526815A (en) * 1966-07-07 1970-09-01 Asea Ab Controllable semi-conductor devices comprising main and auxiliary thyristors having all except one emitter-layer in common
US3543105A (en) * 1967-06-30 1970-11-24 Asea Ab Switching means comprising a thyristor with controlled and bias electrodes
US3566211A (en) * 1966-10-25 1971-02-23 Asea Ab Thyristor-type semiconductor device with auxiliary starting electrodes
US3670217A (en) * 1967-03-16 1972-06-13 Asea Ab Thyristor with a control device and having several control electrodes
US3725753A (en) * 1969-06-11 1973-04-03 Westinghouse Brake & Signal Inverse gate semiconductor controlled rectifier
US3836994A (en) * 1969-05-01 1974-09-17 Gen Electric Thyristor overvoltage protective element
US3914783A (en) * 1971-10-01 1975-10-21 Hitachi Ltd Multi-layer semiconductor device
US3943548A (en) * 1973-02-14 1976-03-09 Hitachi, Ltd. Semiconductor controlled rectifier

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3360696A (en) * 1965-05-14 1967-12-26 Rca Corp Five-layer symmetrical semiconductor switch
US3428874A (en) * 1965-05-14 1969-02-18 Licentia Gmbh Controllable semiconductor rectifier unit
US3526815A (en) * 1966-07-07 1970-09-01 Asea Ab Controllable semi-conductor devices comprising main and auxiliary thyristors having all except one emitter-layer in common
US3566211A (en) * 1966-10-25 1971-02-23 Asea Ab Thyristor-type semiconductor device with auxiliary starting electrodes
US3670217A (en) * 1967-03-16 1972-06-13 Asea Ab Thyristor with a control device and having several control electrodes
US3543105A (en) * 1967-06-30 1970-11-24 Asea Ab Switching means comprising a thyristor with controlled and bias electrodes
US3462620A (en) * 1967-07-18 1969-08-19 Int Rectifier Corp Axial bias gate for controlled rectifiers
US3836994A (en) * 1969-05-01 1974-09-17 Gen Electric Thyristor overvoltage protective element
US3725753A (en) * 1969-06-11 1973-04-03 Westinghouse Brake & Signal Inverse gate semiconductor controlled rectifier
US3914783A (en) * 1971-10-01 1975-10-21 Hitachi Ltd Multi-layer semiconductor device
US3943548A (en) * 1973-02-14 1976-03-09 Hitachi, Ltd. Semiconductor controlled rectifier

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4210924A (en) * 1977-09-14 1980-07-01 Hitachi, Ltd. Semiconductor controlled rectifier with configured cathode to eliminate hot-spots
US4414559A (en) * 1978-03-31 1983-11-08 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor thyristor device with laterally displaced auxiliary and main cathode regions
EP0046578A3 (en) * 1980-08-22 1983-06-22 Tokyo Shibaura Denki Kabushiki Kaisha Power thyristor

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JPS49131387A (enrdf_load_html_response) 1974-12-17

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