US3885994A - Bipolar transistor construction method - Google Patents

Bipolar transistor construction method Download PDF

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US3885994A
US3885994A US363995A US36399573A US3885994A US 3885994 A US3885994 A US 3885994A US 363995 A US363995 A US 363995A US 36399573 A US36399573 A US 36399573A US 3885994 A US3885994 A US 3885994A
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mask
region
rectangular opening
collector
conductivity type
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Ralph W Miller
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Raytheon Co
TRW LSI Products Inc
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TRW Inc
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Priority to CA192,642A priority patent/CA1000873A/en
Priority to NL7404302.A priority patent/NL162247C/xx
Priority to DE2419816A priority patent/DE2419816A1/de
Priority to JP5799674A priority patent/JPS5517494B2/ja
Priority to FR7418076A priority patent/FR2231112B1/fr
Priority to GB2339574A priority patent/GB1443836A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/10—ROM devices comprising bipolar components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/043—Dual dielectric
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/145—Shaped junctions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/151—Simultaneous diffusion

Definitions

  • ABSTRACT A layer of silicon nitride deposited on a semiconductive substrate is etched to form an opening that de- [52] mall's; 145/187 357/9 fines the outer boundaries of a diffused transistor.
  • the III. C.- H01! suicon nitride y serves as a permanen fixed diffu [58] Fleld Search 317/235; sion mask.
  • the first diffusion is performed through the permanent mask opening. Thereafter, portions of the [56] References Cned permanent mask opening are masked by depositing UNITED S A PATENTS layers of silicon dioxide therein and subsequent diffu- 3.479.237 11/1969 Bergh et a1.
  • This invention relates to LSI circuit construction of bipolar transistors, and more particularly to a method of fabricating such transistors which results in greatly reduced size.
  • bipolar transistors are fabricated by a process which involves several steps of selective impurity diffusion into a semiconductive body or substrate. This process is sometimes called a triple diffusion process because three separate diffusion steps are carried out to form the collector, base, and emitter regions, one within the other.
  • a separate masking operation is performed for each of the several diffusions.
  • the masking operation is performed by a photolithographic process that involves growing a masking oxide layer on the semiconductive substrate, coating the oxide layer with a photoresist, exposing the photoresist to light through a masking pattern, developing the photoresist pattern, and etching the oxide layer through the photoresist pattern until the semiconductor surface is bare.
  • the oxide acts as a diffusion barrier and the diffusion regions are thereby defined when the wafer is subjected to a diffusant.
  • the primary factor limiting the reduction of the size of a triple diffused transistor is the registration tolerance of the photolithographic process.
  • the fabrication of a triple diffused bipolar transistor can be thought of in a simplified form as analogous to the fabrication of three nested bath tubs referred to as collector, base. and emitter in descending size.
  • the collector is the largest region and is diffused into the substrate.
  • the base is intermediate in size and is diffused into the collector region.
  • the emitter is the smallest region and is diffused into the base region.
  • An important design rule for a transistor is that the surfaces of the diffused regions or tubs must not touch one another. This requires that in the vertical dimension, the emitter diffusion layer is shallower than the base diffusion layer and the base diffusion layer is shallower than the collector diffusion layer. In the horizon tal dimensions, it requires that the difference in size between adjacent regions or tubs be sufficient to assure that the tolerance with which they are placed within one another does not cause their edges to touch. This tolerance is the factor which limits the reduction of the size of triple diffused transistors.
  • a process of selfalignment of the three diffused regions of a bipolar transistor is provided by establishing a single tolerance region for all three diffusion layers rather than individual tolerance regions between the adjacent diffusion layers.
  • the single tolerance region so established defines an annular region where deposition is prohibited.
  • a silicon nitride layer deposited in a semiconductive substrate is provided in annular form with a single opening that defines the outer boundaries of the first diffusion region.
  • the silicon nitride layer serves as a permanent mask for all three diffusions.
  • For the first diffusion it serves as the sole mask within the transistor region.
  • For the second diffusion a portion of the opening in the silicon nitride layer is covered by a layer of silicon dioxide and the two layers comprising silicon nitride and silicon dioxide form a composite mask for the second diffusion.
  • a second silicon dioxide layer is formed to cover a different portion of the opening in the silicon nitride layer. The composite mask formed by the silicon nitride layer and the new silicon dioxide layer defines the region for the third diffusion.
  • FIG. 1 is a top plan view ofa portion of an LSI circuit incorporating an array of bipolar transistors of elongated extent;
  • FIG. 2 is a sectional view taken along line 22 of FIG. 1'
  • FIG. 3 is a sectional view taken along line 3-3 of FIG. 1;
  • FIG. 4l2 are sectional views illustrating the step by step fabrication of the LS1 structure of FIGS. I3;
  • FIG. 13 is a top plan view of a portion of an LSI circuit incorporating an array of bipolar transistors of square extent;
  • FIG. 14 is a sectional view taken along line 14I4 of FIG. 13;
  • FIG. 15 is a sectional view taken along line 15-15 of FIG. 13;
  • FIGS. 16-25 are sectional views illustrating the step by step fabrication of the LSI structure of FIGS. l3l5.
  • FIGS. l3 there is shown a portion of an L8] circuit incorporating an array of bipolar tran sistors fabricated according to the method of the invention.
  • the transistors are illustrated as being of the NPN type. although it is understood that the method of the invention is applicable as well to fabricating transistors of the PNP type.
  • Each of the transistors in the top plan view of FIG. I is shown as being encompassed within a large elongated outer rectangle 10. Two of which are shown in full and four others being shown only partiaily. Lying concentrically within each large rectangle 10 is a smaller elongated inner rectangle 12.
  • the annular area 14 between the two rectangles l and 12 repre sents a tolerance region within which must lie the open ings of masking structures for the several diffusions of the transistors.
  • Each annular area 14 represents the boundary of a permanent masking structure over which is superim posed other individual masking structures which serve to mask different portions of the area bounded by the inner rectangle 12.
  • the entire area within the inner rectangle 12 defines the region of the semiconductor or substrate that is exposed to the first impurity diffusion. whereas different portions of that rectangular area that are subsequently left unmasked serve to define the regions for the diffusions occurring after the first diffusion.
  • the annular area 14 is formed by selective deposition of silicon nitride, and portions ofthe area within the inner rectangle 12 are masked by selectively forming silicon dioxide thereon.
  • the width of the inner rectangle 12 is identified as having a dimension and the length thereof is divided into nine equal parts, each with a length equal to the dimension S.
  • the large rectangle is spaced from the smaller rectangle 12 by the dimension S. All of the large rectangles 10 are spaced from each other longitudinally and laterally by the same distance equal to the dimension S.
  • the dimension S represents the smallest dimension practical for registration tolerances, which according to the present state of the art is 0.1 mil. The significance of the dimension S will become clearer as the description of the fabrication of the transistor structure proceeds.
  • the L8] bi polar transistor array includes a substrate 16 or body of semiconductive material, in this case P type silicon.
  • the substrate 16 contains a multiplicity of transistors 17 that are formed by diffusing various impurities in different regions of the substrate.
  • collector regions 18 are formed by diffusing an N type impurity within the substrate 16. This is accomplished by forming a permanent mask 20 of silicon nitride in the regions represented by the an nular areas 14 and then superimposing a second mask of silicon dioxide over the permanent mask 20 and portions of the substrate 16, leaving only a rectangular opening concentrically between the rectangles 10 and 12.
  • this first rectangular opening is represented by a horizontal line between points 1 and 5, a vertical line between points 5 and 6, a horizontal line between points 6 and 1S, and a vertical line between points and 1.
  • base regions 22 are formed by diffusing a P type impurity within the collector re gion 18. This is accomplished by superimposing a mask of silicon dioxide over the permanent mask and portions of the substrate 16, leaving a rectangular opening between points 2, 5, 6, 9 and leaving exposed all of the substrate regions between the large rectangles 10.
  • the rectangular opening is represented by a horizontal line between points 2 and 5. a vertical line between points 5 and 6. a horizontal line between points 6 and 9, and a vertical line between points 9 and 2. in addition to forming the P type collector regions 22, this P type diffusion forms P type isolation regions 24 surrounding each of the transistors 17.
  • an N type impurity diffusion is performed to form an N type emitter region 26 within the base region 22 and an N+ type collector contact region 28 within the collector region 18.
  • This diffusion is accomplished by superimposing a mask of silicon dioxide over the permanent mask 20 and portions of the substrate 16, leaving a rectangular opening between points 3, 4, 7, 8 and another rectangular opening between points 1, 11, 13, 15.
  • One rectangular opening is represented, for example, by a horizontal line between points 3 and 4, a vertical line between points 4 and 7, a horizontal line between points 7 and 8, and a vertical line between points 8 and 3.
  • ohmic metallic contacts are made to the collector, emitter and base regions respectively.
  • a collector contact 30 is made to the collector region 18 by depositing metal on the collector contact region 28;
  • an emitter contact 32 is made to the emitter region 26 by depositing metal on the emitter region 26;
  • a base contact 34 is made to the base region 22 by depositing metal on the base region 22.
  • the ohmic metallic contacts to the semiconductor, collector, emitter, and base regions are made by superimposing a silicon di0xide contact mask over the permanent mask 20 and over all semiconductor surface regions.
  • the square surface areas 36, 38, 40 exposing portions of the collector contact region 28, emitter region 26 and base region 22 respectively, are formed by regions left open in both the permanent mask 20 and the silicon dioxide contact mask.
  • the silicon dioxide mask is indicated by the ref erence numeral 42 in FIGS. 2 and 3. in FIG. 1, the surface areas 36, 38, 40 are also labeled C, E, B. respectively, to indicate where contacts are made to the collector. emitter, and base
  • a spacing S is provided to form the diffused isolation region 24. Another spacing S is provided to space the isolation region 24 from the collector contact region 28, and yet another spacing S is provided to form the collector contact region 28. A spacing S is provided to space the collector contact region 28 from the base region 22, and another spacing S spaces the base region 22 from the emitter region 26. Finally, a spacing S is provided to space the emitter contact 32 from the edge of the emitter region 26 and another spacing S is provided to form the emitter contact 32. A spacing of 8/2 is provided between the innermost edge of the permanent mask 20 and the innermost edge of the silicon dioxide mask 42 to allow a tolerance region for misregistration of the masks.
  • a space S is provided to form the emitter contact 32, another space S is provided to space the isolation region 24 from the base region 22, and another space S is provided to form the isolation region 24.
  • the isolation regions 24 and the collector regions 18 are allowed to overlap without any adverse effects.
  • FIGS. 4-12 for a step by step description of the process of fabricating the transistor 17 according to the invention.
  • a substrate 16 of silicon that is doped with a P type impurity, such as boron there is formed a permanent mask of silicon nitride, as shown in FIG. 4.
  • the mask 20 is preferably formed by a photolithographic technique well known in the semiconductor art.
  • a thin layer of silicon dioxide of about 400 to 500 Angstroms thick is first formed on the semiconductive surface, and then a continuous layer of silicon nitride is formed on the silicon dioxide layer.
  • the silicon dioxide layer is needed to stabilize the silicon semiconductive surface electrically, for if the silicon nitride is laid down directly on the silicon substrate, it would tend to exchange charge with the silicon.
  • the silicon nitride layer is formed by reacting silicon tetrachloride (SiCl with ammonia (NH to form silicon nitride (Si N Hydrochloric acid gas is given off as a byproduct.
  • a layer of silicon nitride is formed that is about 3,000 angstroms thick.
  • the layer of silicon nitride is covered with 500 A of silicon dioxide which in turn is covered by photo-resist.
  • the photoresist is patterned and then used as a mask to etch the silicon dioxide.
  • the silicon dioxide is then used as a mask to etch the silicon nitride using hot phosphoric acid.
  • the thin silicon dioxide layer that is left exposed is then etched away with buffered hydrofluoric acid.
  • the substrate 16 and permanent mask 20 are coated with a continuous layer 42 of silicon dioxide.
  • the silicon dioxide layer 42 may be thermally grown by heating the substrate 16 in oxygen satu rated with water vapor.
  • the substrate 16 may be heated at 900C for about 1 hour. It should be noted that the silicon dioxide layer that forms on the silicon nitride layer is only a small fraction of the thickness of oxide layer that is formed on the bare silicon.
  • portions of the silicon dioxide layer 42 are removed from the regions of the substrate 16 where diffusions are to occur to form the collector regions.
  • the sili con dioxide layer 42 is left standing in regions where no diffusions are to occur.
  • the state of the process shown in FIG. 6 corresponds to the formation in FIG. 1 of a silicon dioxide mask superimposed on the permanent mask 20, with the edges of the silicon dioxide mask forming a rectangular opening running between points 1, 5, 6, l5.
  • Buffered hydrofluoric acid is used to etch the silicon dioxide layer 42.
  • the silicon nitride layer is left intact during this etching operation because it is selectively inert in the hydrofluoric acid etchant,
  • FIG, 6 also illustrates the next step which is to diffuse an N type impurity into the P type substrate 16, shown as a P- region, to form the collector regions 18 which define the extent of each transistor 17.
  • the collector regions l8 may be formed, for example. either by thermally diffusing arsenic into the semiconductor sub strate 16 or by implanting phosphorous ions into the substrate and thereafter thermally distributing the im' purity atoms.
  • the ion implantation process has certain advantages in that the concentration of impurities is more uniform over the region and more controllable.
  • FIG. 8 corresponds to the formation in FIG. I of a silicon dioxide mask over portions of the substrate 16 and within the inner rectangle 12, leaving a rectangular opening be tween points 2, S, 6, 9 and leaving exposed all of the regions between the large rectangles 10 that are not cow ered by the permanent mask.
  • the next step in the process is to convert a portion of the N type collector regions 18 into the P type base regions 22, and also to form the P type isolation regions 24 within the P- region of the substrate 16 so that the isolation regions 24 surround the transistors 17. This is done by thermally diffusing a P type impurity such as boron.
  • FIG. 10 illustrates the formation in FIG. I of a silicon dioxide mask over the permanent mask 20 and portions of the substrate 16, leaving a rectangular opening be tween points 3, 4, 7, 8, and another rectangular opening between points 1, ll, l3, 15.
  • the next step of the process is also shown in FIG. 10 and that is the diffusion of an N type impurity, such as arsenic or phosphorus, to form the emitter regions 26 within the P type base regions 22 and also the N+ collector contact regions 28 within the collector regions 18.
  • an N type impurity such as arsenic or phosphorus
  • the next step in the process is to cover the substrate 16 with another silicon dioxide layer 42, as shown in FIG. 11. Portions of the silicon dioxide layer 42 are then removed to define the regions where ohmic contacts will be made to the collector, base, and emitter by depositing metal thereon.
  • FIG. 12 which is similar to FIG. 2, holes are formed in the silicon dioxide layer 42 over the N+ collector contact region 28, over the emitter region 26 and over the base region 22. In these holes are deposited metallic contacts which are identified as collector contact 30, emitter contact 32, and base contact 34. The metallic contacts may extend over the silicon dioxide layer 42 in the form of strips or bands to form various desired interconnection paths.
  • the resistivity of the substrate is 3 ohmcentimeters corresponding to a concentration of boron impurity atoms of 2 X 10 per cubic centimeters (cm
  • the N type region 18 has a depth of its junction with the P type zone of the substrate 16 from the surfaces of the substrate 16 of 4.2 X It) cm.
  • the sheet resistance of the N type region 18 is 88 ohms per square with a surface concentration of 1.8 X 10" impurity atoms per cm,
  • the sheet resistance of the P type region 22 and P region 24 is I16 ohms per square and the depth of the junctions from the surface is L9 X l cm.
  • the surface concentration is 1.5 X 10 boron atoms per cm.
  • the sheet resistance of the N type region 26 and N+ type region 28 is 4.2 ohms per square. The producibility is improved when the permanent work is not used to form the edge of the metallic contact. This leaves a larger space between the junction and the metal, thereby permitting greater anomalies of diffusion of the metal into the silicon.
  • the parasitic collector resistance can be reduced by moving the collector contact from the end opposite the base contact to the side of the transistor.
  • the depth of the junctions from the surfaces is l.4 X l0 cm and the concentration of impurity atoms per cm is l.5 X 10
  • the P isolation regions 24 are needed to isolate the transistors from each other. If the P isolation regions 24 were omitted, the lightly doped P regions where they are omitted normally contain a thin surface layer of N type conductivity that causes conducting channels to form between the transistors. The P isolation regions 24 prevent these conducting channels from forming.
  • nitride is preferred as the material for the permanent mask 20
  • other materials that are relatively inert in the etchant used for the silicon dioxide.
  • Such other materials may include zirconium dioxide (ZrO or aluminum oxide (A1 0
  • ZrO zirconium dioxide
  • Al oxide aluminum oxide
  • FIGS. 13-25 A structure with both of the above modifications and its fabrication process will now be described with reference to FIGS. 13-25. For simplicity, only one transistor 48 is shown and the formation of the isolation regions will only be referred to generally and not in detail.
  • a permanent mask 50 of silicon nitride is formed on a P type semiconductor substrate 52.
  • the permanent mask 50 is annular and generally square overall, but has two openings 54 and 56 instead of one, much in the fashion of a figure eight. One of the openings 56 is wider than the other opening 54.
  • a continuous layer 58 of silicon dioxide is then etched away in regions to prepare the substrate for the first diffusion, as shown in FIG. 18. For this diffusion, both openings 54 and 56 in the permanent mask 50 are left uncovered, and an N type diffusion is performed so that the two regions beneath the openings 54 and 56 merge into a single N type collector region 60.
  • the substrate 52 and permanent mask is again coated with a silicon dioxide layer 58 as shown in FIG. 19, and the silicon dioxide layer 58 is etched once again preparatory to the second diffusion.
  • the second diffusion is P type to form a base region 62 beneath the larger opening 56 while masking the smaller opening 54. During this same diffusion, it is preferred to form the P isolation regions 64 surrounding the transistor 48.
  • the next steps are to grow another silicon dioxide layer 58 as shown in FIG. 2], and then etch the layer 58 preparatory to the third diffusion as shown in FIG. 22.
  • the third diffusion is N type and forms the N type emitter region 66 within a half portion of the P type base region 62 by masking one half of the large opening 56, as shown more clearly in FIGS. 13 and 15.
  • the third diffusion also forms the N+ type collector contact region 68 through the unmasked smaller opening 54.
  • FIGS. 23 through 25 illustrate the location and formation of the metallic contacts for the elements of the transistor 48. This procedure involves forming another silicon dioxide layer 58, etching the layer 58 to form holes registered with the collector, base, and emitter regions, and depositing metallic contacts in those holes.
  • FIG. 25 shows a collector contact 70, an emitter contact 72, and a passivating layer 74 of silicon dioxide.
  • the base contact which is not shown, is deposited in the region labeled B in FIG. 23.
  • the regions labeled C and E indicate the location of the collector contact and emitter contact 72.
  • a method of fabricating a bipolar transistor in integrated circuit form by a triple deposition process comprising:
  • G introducing thirdly an impurity of said second conductivity type into the unmasked area portions of said collector and base regions to form a collector contact region within said collector region and 9 an emitter region within said base region, respectively.
  • said first masking material is silicon nitride and said second masking material is silicon dioxide.
  • a method of fabricating a bipolar transistor in integrated circuit form by a triple deposition process comprising:
  • said permanent mask is formed by depositing and etching a layer of silicon nitride on said semiconductor substrate.

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  • General Physics & Mathematics (AREA)
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US363995A 1973-05-25 1973-05-25 Bipolar transistor construction method Expired - Lifetime US3885994A (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
US363995A US3885994A (en) 1973-05-25 1973-05-25 Bipolar transistor construction method
CA192,642A CA1000873A (en) 1973-05-25 1974-02-15 Bipolar transistor construction method
NL7404302.A NL162247C (nl) 1973-05-25 1974-03-29 Werkwijze voor het vervaardigen van een bipolaire transistor voor een geintegreerde halfgeleider- schakeling.
DE2419816A DE2419816A1 (de) 1973-05-25 1974-04-24 Verfahren zur herstellung bipolarer transistoren
JP5799674A JPS5517494B2 (enExample) 1973-05-25 1974-05-24
FR7418076A FR2231112B1 (enExample) 1973-05-25 1974-05-24
GB2339574A GB1443836A (en) 1973-05-25 1974-05-24 Bipolar transistor construction method

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US363995A US3885994A (en) 1973-05-25 1973-05-25 Bipolar transistor construction method

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JP (1) JPS5517494B2 (enExample)
CA (1) CA1000873A (enExample)
DE (1) DE2419816A1 (enExample)
FR (1) FR2231112B1 (enExample)
NL (1) NL162247C (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4567644A (en) * 1982-12-20 1986-02-04 Signetics Corporation Method of making triple diffused ISL structure

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US4276543A (en) * 1979-03-19 1981-06-30 Trw Inc. Monolithic triple diffusion analog to digital converter
JPS5624970A (en) * 1979-08-07 1981-03-10 Nec Corp Manufacture of semiconductor device
DE3379563D1 (en) * 1982-12-20 1989-05-11 Philips Nv Integrated circuit and method

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US3660735A (en) * 1969-09-10 1972-05-02 Sprague Electric Co Complementary metal insulator silicon transistor pairs
US3698966A (en) * 1970-02-26 1972-10-17 North American Rockwell Processes using a masking layer for producing field effect devices having oxide isolation
US3771218A (en) * 1972-07-13 1973-11-13 Ibm Process for fabricating passivated transistors
US3783047A (en) * 1971-03-17 1974-01-01 Philips Corp Method of manufacturing a semiconductor device and semiconductor device manufactured by using such a method

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US3660735A (en) * 1969-09-10 1972-05-02 Sprague Electric Co Complementary metal insulator silicon transistor pairs
US3698966A (en) * 1970-02-26 1972-10-17 North American Rockwell Processes using a masking layer for producing field effect devices having oxide isolation
US3783047A (en) * 1971-03-17 1974-01-01 Philips Corp Method of manufacturing a semiconductor device and semiconductor device manufactured by using such a method
US3771218A (en) * 1972-07-13 1973-11-13 Ibm Process for fabricating passivated transistors

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Also Published As

Publication number Publication date
JPS5517494B2 (enExample) 1980-05-12
FR2231112B1 (enExample) 1979-02-16
FR2231112A1 (enExample) 1974-12-20
NL162247C (nl) 1980-04-15
NL162247B (nl) 1979-11-15
JPS5022581A (enExample) 1975-03-11
CA1000873A (en) 1976-11-30
NL7404302A (enExample) 1974-11-27
DE2419816A1 (de) 1974-12-05

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