US3801851A - Plasma display panel - Google Patents

Plasma display panel Download PDF

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Publication number
US3801851A
US3801851A US00298530A US3801851DA US3801851A US 3801851 A US3801851 A US 3801851A US 00298530 A US00298530 A US 00298530A US 3801851D A US3801851D A US 3801851DA US 3801851 A US3801851 A US 3801851A
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United States
Prior art keywords
electrodes
main electrodes
plasma display
voltage
main
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Expired - Lifetime
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US00298530A
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English (en)
Inventor
S Andoh
T Urade
T Hirose
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Fujitsu Ltd
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Fujitsu Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J11/00—Gas-filled discharge tubes with alternating current induction of the discharge, e.g. alternating current plasma display panels [AC-PDP]; Gas-filled discharge tubes without any main electrode inside the vessel; Gas-filled discharge tubes with at least one main electrode outside the vessel

Definitions

  • ABSTRACT A plasma display panel in which two transparent base plates are assembled together to define a discharge gas space therebetween. On each transparent base plate, a plurality of strip-like main electrodes are provided and a dielectric layer is formed to cover them and, further, third electrodes are each provided between adjacent ones of the main electrodes.
  • the two transparent base plates are assembled together in opposing relation to each other in such a manner that their main electrodes and third electrodes are disposed substantially perpendicuar to each other in the form of a matrix.
  • a discharge spot is produced at their intersecting point to provide a display.
  • the discharge spot becomes enlarged or reduced or extends in a certain direction according to the polarity of a voltage impressed between the third electrodes of both transparent base plates and to the selection of the third electrodes to be supplied with the voltage.
  • the discharge spot can be shifted in either direction of the row and column of the matrix.
  • PATENIEDAPR 21974 (801,851 sum 5 0F 6 FIG. 10
  • This invention relates to a plasma display panel which is provided with main electrodes causing a plasma discharge and electrodes for controlling the electric field of the plasma discharge.
  • a glass plate having formed therein apertures serving as discharge cells is interposed between glass base plates having electrodes, a mixed gas composed of Ne and N is sealed in the cells and an AC voltage is impressed to the electrodes to cause plasma discharge in the discharge cells when the impressed voltage exceeds a discharge voltage, thereby to provide a display.
  • the plasma display panels have a memory function due to wall charge. Even if the glass plate having the apertures and serving as the discharge cells is left out to provide a continuous discharge space, only a matrix display can be provided if a voltage is also impressed a little to unselected intersecting points resulting in lowered resolution of the display.
  • a self shift panel of the type in which kindling radiation is effected to spread electric field to adjacent cells and then firing radiation is achieved by impression of a sustain voltage is defective in that when it is controlled, coupling of adjacent cells is likely to be insufficient to cause erroneous shift.
  • a plasma display panel in which dielectric layers are formed on main electrodes and disposed opposite to each other with a discharge gas space therebetween and third electrodes are provided to control electric field between the main electrodes and in which electric field of plasma discharge is controlled by the third electrodes to enlarge, reduce or extend a discharge spot in a certain direction.
  • the third electrodes are provided in dielectric layers and in which electric field of the plasma discharge can be controlled by an extremely low voltage applied thereto.
  • a further feature of this invention is to provide a plasma display panel in which the third electrodes are covered with insulating layers to prevent damage to the third electrodes by direct bombardment of ions thereon, thereby to provide for lengthened service life of the plasma display panel.
  • the plasma display panel is provided with the third electrodes and the main electrodes simultaneously formed in the same plane, thereby to simplify the manufacturing process of the display panel and lengthen the service life thereof.
  • one of the third electrodes is replaced with the main electrode, thereby to simplify the manufacturing process of the display panel and hence lower the manufacturing cost thereof.
  • the plasma display panel includes a plurality of third electrodes disposed between the main electrodes or the third electrodes adjacent to the main electrodes of the one side, thereby to control electric field of plasma discharge more in various ways.
  • FIG. 1 is a fragmentary cross-sectional view of one example of this invention
  • FIG. 2 and 3 are fragmentary, cross-sectional views showing arrangements of third electrodes of the one side in other examples of this invention, respectively;
  • FIGS. 4 and 5 are schematic diagrams, for explaining the operation of the third electrode, respectively.
  • FIG. 6 is a series of voltage waveform diagrams, for explaining this invention.
  • FIG. 7 is a schematic diagram illustrating one example of a matrix electrode construction in a plasma display panel of this invention.
  • FIG. 8A is a schematic diagram, for explaining generation of a discharge spot
  • FIG. 8B is a time chart of a voltage impressed to electrodes for generating the discharge spot shown in FIG. 8A;
  • FIG. 9A is a schematic diagram, for explaining generation of a discharge spot being controlled.
  • FIG. 9B is a time chart of a voltage impressed to the electrodes for generating the discharge spot depicted in FIG. 9A;
  • FIG. 10 is a schematic diagram showing another example of the matrix electrode construction of FIG. 7.
  • FIG. 11 is a circuit diagram illustrating one example of a circuit for driving the plasma diaplay panel of this invention.
  • FIG. 1 there is illustrated in section one example of this invention.
  • Reference numeral 1 indicates glass base plates
  • numeral 2 refers to main electrodes
  • numeral 3 identifies dielectric layers
  • numeral 4 indicates a discharge gas space
  • numeral 5 refers to third electrodes.
  • the main electrodes 2 are arranged in the form of a matrix and plasma discharge is pro-' Jerusalem at selected intersecting points of the main electrodes 2 to cause radiation.
  • the third electrodes 5 are shown to be exposed in the discharge gas space 4 but they may be covered with dielectric layers 6' as depicted in FIG. 2 or may be formed in the same plane as the main electrodes 2" as shown in FIG. 3.
  • each third electrode 5 is shown to be disposed midway between adjacent main electrodes 5 but it may be located near either of the electrodes 5 or a plurality of third electrodes 5, may be provided between adjacent electrodes 5. It is also possible to use the third electrodes of the one side as the main electrodes 2.
  • the third electrodes 5 are used while being held at the same polarity as the main electrodes 2 or opposite in polarity thereto or grounded. Where the third electrodes 5 are of the same polarity as the main electrodes 2, an electric field provided by the main electrode 2 spreads to widen a radiation area as depicted in FIG. 4. Namely, an electric field E1 of the main electrode 2 and an electric field E2 of the third electrodes 5 are in the same direction, so that plasma discharge spreads as indicated by the dotted lines.
  • the electric field E1 of the main electrode 2 is opposite in direction to the electric field E2 of the third electrodes 5, and hence is narrow as if focused and the plasma discharge is also narrow in area to limit the radiation area, thus providing a display with high resolution.
  • the third electrodes 5 are grounded, an intermediate operation between the above-described operations is carried out.
  • the area of the electric field E1 of the main electrode 2 can also be controlled by a voltage impressed to the third electrodes 5.
  • FIG. 6 shows the relationships between a voltage V impressed to the main electrodes 2 and voltages V and V impressed to the third electrodes 5, in which the voltage V shows the case of the main and third electrodes being of the same polarity and the voltage V the case of the both electrodes being opposite in polarity to each other.
  • the relationship in magnitude between the voltages V V and V can be selected as desired and their relationships in phase and frequency can also be selected different from one another.
  • FIG. 7 illustrates one example of the matrix electrode arrangement used in the plasma display panel of this invention. This electrode arrangement is of particular utility when employed in graphic display.
  • electrodes xal, xfl, xbl, xj2, xcl, xf3, xa2, and write electrodes W1, W2, W3, Wn are provided on the first base plate, while electrodes yal, yfl, ybl, yf2, ycl, yj3, ya2, are provided on the other or second base plate.
  • Buses XA, XB, XC and XF have connected thereto the main electrodes xal, x112, xbl, xb2, xcl, x02, and the third electrodes xfl, xf2, respectively. While, buses YA, YB, YC and YF have similarly connected thereto the main electrodes yal, ya2, ybl, yb2, ycl, yc2, and the third electrodes yfl, yj2, respectively.
  • the aforesaid discharge spot is shifted to the intersecting point of the main electrodes ybl and xal.
  • the voltage previously impressed to the main electrode yal is cut off after impression of the voltage to the main electrode ybl.
  • the discharge spot is generated at a desired position to provide a display by selective combinations of the main electrodes yal, ybl, and those xal, xbl, and the write electrodes W] to Wn.
  • FIGS. 8A and 9A each show one part of the matrix electrode arrangement of FIG. 7 for convenience of explanation and in the figures each electrode group is shown for each bus.
  • FIG. 9A shows exactly the same electrode arrangement as that depicted in FIG. 8A.
  • voltages are applied to the electrodes in such a manner as shown in FIG. 9B.
  • the pulse voltage +Vl is impressed between the buses XB and YB alternately.
  • pulse voltages +V2 and -V3 are applied to the buses XF and YF respectively or that the bus YF is held at zero volt, the discharge spot lengthens in the direction of the bus YB and shortens in the direction of the bus XB for the same reasons as those described previously in connection with FIGS. 4 and 5, as indicated by a broken line L0 in FIG. 9A.
  • VF a firing voltage
  • FIG. 10 illustrates a matrix electrode arrangement suitable for character display by self shift, which electrode arrangement is employed in the plasma display panel described hereinbelow in connection with FIG. 11.
  • electrodes on the side X are divided into electrode groups associated with the buses XA, XB, XC and XF and those associated with the buses Xa, Xb, Xc and Xf and write electrodes W1, W2, W3, Wn correspond to the electrode groups associated with the buses XA, XB, XC and XF as shown.
  • the matrix electrode arrangement depicted in FIG. is effective for two-dimensional shift.
  • FIG. 11 illustrates one example of a drive circuit for the plasma display panel employing the matrix electrode arrangement described above in connection with FIG. 10.
  • reference numeral 100 indicates a key board
  • numeral 101 refers to a diode matrix circuit
  • numerals 102 and 103 identify R'S flip-flop circuits
  • numeral 104 indicate an oscillator
  • numeral 105 refers to a frequency divider circuit
  • numerals 106 to 117 identify AND gate circuits
  • numerals 118 to 120 represent ring counters
  • numeral 121 refers to a flip-flop circuit
  • numerals 121a and 121b indicate AND gate circuits
  • numeral 122 refers to a gate circuit
  • numeral 123 represents a IO-stage counter
  • numeral 124 represents a plasma display panel
  • reference characters XF, XA, XB, XC, YF, YA, YB and YC designate the aforesaid buses and W1 to W7 designate the aforementioned write
  • Anoutput of the oscillator 104 is frequency divided by the frequency divider circuit 105 to l/n.
  • the RS flip-flop circuit 102 is set by the start signal.
  • the AND gate circuit 106 When supplied with an output of the RS flip-flop circuit 102, the AND gate circuit 106 derives therefrom an output frequency divided by the frequency divider circuit 105, which output is applied to the three-stage ring counter 119.
  • Outputs of the respective stages of the three-stage ring counter 119 are fed to the buses XA, X8 and XC through the AND gate circuits 113, 114 and 115 respectively.
  • the ring counter 118 is supplied with the output of the final stage of the ring counter 119 and an output of the diode matrix circuit 101 which is supplied with a character selecting signal from the key board 100 is sequentially applied to the gate circuit 122 by the output of each stage of the aforementioned ring counter 118 and a write voltage is impressed to one of the write electrodes W1 to W7 which is selected by the diode matrix circuit 122.
  • the voltage V1 is sequentially supplied by the output of the ring counter 119 to the buses XA, XB and XC, for example, in the manner ofa three-phase voltage.
  • the bus XF is supplied with the voltage V2 through the AND gate circuit 117.
  • the bus YF is supplied with the voltage V3 through the AND gate circuit 112.
  • the flipflop circuit 102 Upon completion of writing one character, the flipflop circuit 102 is reset by the output of the final stage of the ring counter 118 to stop the ring counter 119.
  • the flip-flop circuit 103 is reset and the output of the the frequency divider is applied to the ring counter from the AND gate circuit 107.
  • An output of the ring counter 120 is applied to the buses YA, YB and YC and the manner of this application is exactly the same as the aforesaid one for the buses XA, XB and XC and the voltage V] is sequentially impressed to the buses.
  • the bus YF is supplied with the voltage V2 through the AND gate circuit 111 and the bus XF is supplied with the voltage V3 through the AND gate circuit 116.
  • the buses YA, YB and YC are sequentially supplied with the voltage V1 and the discharge spot extends in a direction perpendicular to that L0 depicted in FIG. 9A, that is, becomes longer in a vertical direction and it is shifted upwardly in the figure.
  • the voltage impressed to the buses YA, YB, YC and YF is displaced apart in phase from that impressed to the buses XA, XB, XC and XF by a circuit including the flip-flop circuit 121 and the AND gate circuits 121a and l21b.
  • the output of the final stage of the ring counter 120 is counted by the lO-stage counter 123 and the flipflop circuit 103 is reset by its output to stop the line shift.
  • the reason for the use of the lO-stage counter 123 is to provide a space for three dots between lines in the case of forming one character with 5 X 7 dots.
  • the flip-flop circuits 102 and 103 are both in their reset condition, so that the AND gate circuits 111, 112, 116 and 117 are all closed and no voltage is applied to the buses XF and YF.
  • the present invention makes it possible that the liminous spot is enlarged or the self shift operation is facilitated by forming the electric field by the third electrode in the same direction as that by the main electrode, and that the luminous spot is narrowed to provide a display with high resolution by forming the both electric fields in reverse directions.
  • the degree of enlargement and reduction of the sopt can readily be controlled by the shape, the arrangement and the number of the third electrode and a voltage impressed thereto.
  • a plasma display system comprising:
  • a plasma display device including first and second base plates disposed opposite to each other for defining a discharge gas region therebetween, first and second sets of main electrodes disposed respectively upon said first and second base plates whereby said first and second sets of main electrodes intersect each other;
  • discharge energizing means for impressing a voltage between selected main electrodes of said first and second sets whereby an electrical discharge is established at the intersecting points of said selected main electrodes
  • auxiliary energizing means for applying a control voltage to said auxiliary electrodes to control the size and configuration of the electrical discharge established between said selected main electrodes of said first and second sets.
  • auxiliary electrodes comprise a first set thereof and are disposed between adjacent main electrodes of said first set, and there is further included a second set of auxiliary electrodes disposed between the adjacent main electrodes of said second set.
  • a plasma display system wherein said first-mentioned and said second sets of auxiliary electrodes are each covered with a dielectric layer.
  • auxiliary electrodes for controlling electric fields established between said main electrodes are formed in substantially the same plane as said first set of electrodes and are covered with a dielectric layer.
  • auxiliary electrodes for controlling electric fields established between said main electrodes are formed in substantially the same plane as said second set of electrodes and are covered with a dielectric layer.
  • auxiliary electrodes are formed between adjacent ones of said main electrodes formed on the same base plate.
  • each of said auxiliary electrodes is located between adjacent main electrodes formed on a base plate, and is disposed closer to one of said adjacent main electrodes than the other of said adjacent main electrodes.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Gas-Filled Discharge Tubes (AREA)
  • Transforming Electric Information Into Light Information (AREA)
US00298530A 1971-10-18 1972-10-18 Plasma display panel Expired - Lifetime US3801851A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP46082300A JPS5248765B2 (ko) 1971-10-18 1971-10-18

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US00298530A Expired - Lifetime US3801851A (en) 1971-10-18 1972-10-18 Plasma display panel

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US (1) US3801851A (ko)
JP (1) JPS5248765B2 (ko)
DE (1) DE2250821C3 (ko)
GB (1) GB1411804A (ko)
NL (1) NL175957C (ko)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4147960A (en) * 1976-12-06 1979-04-03 Fujitsu Limited Plasma display panel including shift channels and method of operating same
FR2511530A1 (fr) * 1981-08-17 1983-02-18 Sony Corp Dispositif d'affichage a decharge
US4703225A (en) * 1984-12-13 1987-10-27 Gold Star Co., Ltd. Plasma display device
US5723946A (en) * 1994-10-11 1998-03-03 Samsung Display Devices Co., Ltd. Plane optical source device
US6177762B1 (en) * 1997-10-23 2001-01-23 Sharp Kabushiki Kaisha Plasma display panel having mixed gases to counteract sputtering effects
EP1077467A1 (en) * 1999-08-16 2001-02-21 Sony Corporation Flat plasma discharge display device
US6411031B1 (en) * 1998-01-12 2002-06-25 Lg Electronics Inc. Discharge electrodes for a color plasma display panel capable of lowering a discharge voltage
US6603266B1 (en) * 1999-03-01 2003-08-05 Lg Electronics Inc. Flat-panel display
US6680573B1 (en) * 1999-07-26 2004-01-20 Lg Electronics Inc. Plasma display panel with improved illuminance
US20050253515A1 (en) * 2004-05-13 2005-11-17 Jae-Ik Kwon Plasma display panel
US9130327B2 (en) 2013-06-18 2015-09-08 Trinity, Llc Power assembly for display

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS579183B2 (ko) * 1974-03-05 1982-02-19
JPS5760522Y2 (ko) * 1977-04-08 1982-12-23
US4454449A (en) * 1980-06-30 1984-06-12 Ncr Corporation Protected electrodes for plasma panels
WO1982000220A1 (en) * 1980-06-30 1982-01-21 Ncr Co Electrodes for gaseous discharge devices
JPH0119319Y2 (ko) * 1981-01-21 1989-06-05
US7701578B1 (en) * 2003-09-12 2010-04-20 Herring Cyrus M Planar micro-discharge gas detector

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3336499A (en) * 1966-04-29 1967-08-15 Hughes Aircraft Co Display device with plasma discharge propagating delay line read-in
US3499167A (en) * 1967-11-24 1970-03-03 Owens Illinois Inc Gas discharge display memory device and method of operating
US3513327A (en) * 1968-01-19 1970-05-19 Owens Illinois Inc Low impedance pulse generator
US3562737A (en) * 1967-12-19 1971-02-09 Schjeldahl Co G T Electro-optical device
US3614511A (en) * 1967-11-24 1971-10-19 Owens Illinois Inc Gas discharge display memory device
US3716742A (en) * 1970-03-03 1973-02-13 Fujitsu Ltd Display device utilization gas discharge

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3336499A (en) * 1966-04-29 1967-08-15 Hughes Aircraft Co Display device with plasma discharge propagating delay line read-in
US3499167A (en) * 1967-11-24 1970-03-03 Owens Illinois Inc Gas discharge display memory device and method of operating
US3614511A (en) * 1967-11-24 1971-10-19 Owens Illinois Inc Gas discharge display memory device
US3562737A (en) * 1967-12-19 1971-02-09 Schjeldahl Co G T Electro-optical device
US3513327A (en) * 1968-01-19 1970-05-19 Owens Illinois Inc Low impedance pulse generator
US3716742A (en) * 1970-03-03 1973-02-13 Fujitsu Ltd Display device utilization gas discharge

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4147960A (en) * 1976-12-06 1979-04-03 Fujitsu Limited Plasma display panel including shift channels and method of operating same
FR2511530A1 (fr) * 1981-08-17 1983-02-18 Sony Corp Dispositif d'affichage a decharge
US4703225A (en) * 1984-12-13 1987-10-27 Gold Star Co., Ltd. Plasma display device
US5723946A (en) * 1994-10-11 1998-03-03 Samsung Display Devices Co., Ltd. Plane optical source device
US6177762B1 (en) * 1997-10-23 2001-01-23 Sharp Kabushiki Kaisha Plasma display panel having mixed gases to counteract sputtering effects
US6411031B1 (en) * 1998-01-12 2002-06-25 Lg Electronics Inc. Discharge electrodes for a color plasma display panel capable of lowering a discharge voltage
US6603266B1 (en) * 1999-03-01 2003-08-05 Lg Electronics Inc. Flat-panel display
US6680573B1 (en) * 1999-07-26 2004-01-20 Lg Electronics Inc. Plasma display panel with improved illuminance
US20040113554A1 (en) * 1999-07-26 2004-06-17 Kim Jae Sung Plasma display panel
US7071622B2 (en) 1999-07-26 2006-07-04 Lg Electronics Inc. Plasma display panel
US20080054807A1 (en) * 1999-07-26 2008-03-06 Lg Electronics Inc. Plasma display panel
US7352129B2 (en) 1999-07-26 2008-04-01 Lg Electronics Inc. Plasma display panel
US6512499B1 (en) 1999-08-16 2003-01-28 Sony Corporation Flat plasma discharge display device
EP1077467A1 (en) * 1999-08-16 2001-02-21 Sony Corporation Flat plasma discharge display device
US20050253515A1 (en) * 2004-05-13 2005-11-17 Jae-Ik Kwon Plasma display panel
US7315124B2 (en) * 2004-05-13 2008-01-01 Samsung Sdi Co., Ltd. Plasma display panel
US9130327B2 (en) 2013-06-18 2015-09-08 Trinity, Llc Power assembly for display

Also Published As

Publication number Publication date
DE2250821C3 (de) 1979-01-18
JPS5248765B2 (ko) 1977-12-12
NL7214112A (ko) 1973-04-24
JPS4847764A (ko) 1973-07-06
NL175957B (nl) 1984-08-16
DE2250821A1 (de) 1973-05-10
DE2250821B2 (de) 1978-05-24
GB1411804A (en) 1975-10-29
NL175957C (nl) 1985-01-16

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