US3784983A - Information handling system - Google Patents

Information handling system Download PDF

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US3784983A
US3784983A US27971052A US3784983A US 3784983 A US3784983 A US 3784983A US 27971052 A US27971052 A US 27971052A US 3784983 A US3784983 A US 3784983A
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storage
data
information
control
sequence
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J Eckert
H Welsh
J Weiner
R Shaw
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Sperry Corp
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Sperry Rand Corp
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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10Program control for peripheral devices
    • G06F13/12Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit

Abstract

1. In an information handling system wherein information is represented by electrical impulse trains having the same number of impulse positions in each train, each train representing an item of information and containing impulses which are present and absent in and from said positions in a coded arrangement which varies with the item of information represented by each train, an information transfer network, means to supply impulse trains to the input to said transfer network, and checking means coupled to said transfer network, said checking means including a first counter means indicating the count of the individual trains supplied to said network, a second counter means responsive to the indIvidual impulses contained within the trains supplied to said network, and means for periodically indicating when said first and second counter means do or do not tally.

Description

United States Patent 1 1 1 1 3,784,983

Eckert, Jr. et al. 1 1 Jan. 8, 1974 1 INFORMATION HANDLING SYSTEM 2,552,629 5/1951 Hamming et a1. 177 353 [75] Inventors: John Presper Eckert, Jr., Gladwyne; James R. Wemer, Philadelphia, both 2 539 043 U195] Vemeaux 35 of a; Robert Show. Brooklyn, 2,641,696 1/1953 Woolard 235/61 NY; Herbert Frazer Welsh, 2,539,623 l/l951 Heising 235/92 Philadelphia, Pa. 2,570,716 /1951 Rochester. /155 2,609,143 9/1952 Stihitz 235/61 [73] Assigneec Sperry Rand Corp., New York,

NY. FOREIGN PATENTS OR APPLICATIONS 964,113 1/1950 France 1, 235/92 [22] 1952 975,941 10/1950 France 235/92 121] P19917951 OTHER PUBLICATIONS 24 Digit Parallel Computer With Magnetic Drum [521 US. Cl 340/1725, 235/153, 235/616 Memory," 1949 [51] Int. Cl. G061 15/00 Proc. of a Symposium of Large Scale Digital Calcu- [58] Field of Search 340/1725, 347; lating Machinery," 1948 235/157, 61.6, 61.7, 153 "Proc. of the Natl Electronics Cont." Mar 17, 1948 The EDSAC Mathematical Tables and Other Aids to 1 1 Rel'el'fllctls Cited Communication (MT/AC)" 1950 UNITED STATES PATENTS A Functional Description of the EdVac, Nov. 1, 2,528,101 10/1950 Williams 235/61 1949 2 533 53 1 195 wm 23 How an Electronic Brain Works" Radio Electric 2,589,465 3/1952 Weiner i i 235/61 Magaz. July, 51 .1 12/1952 Van Duurefl /2 -1 The Binac, Proceedings of the I R.E,.1an. 1952 29357052 4/1953 Bloch 4 235/61 Computing Instruments and Machines" by D. R. 2,639,859 5/1953 Serel1,.... 235/61 Hartree 2,659,072 11/1953 Coales 235/6] 2.6.71.6 1 3/1954 vibbard 235,6] Hlgh Speed Computing Devices McGraw-H1ll Book 2,672,283 3/1954 Havens 1 235 61 728-50 2 095 2 955 stibitzm 235/6] Proc. of the Inst. of Elec. Engrs." Feb, 1951 2,726,038 12/1955 Ergen 1 235/61 Mathematical Tables and Other Aids to Communica- 2,652,196 9/1953 Sterling 235/61 [1011" 4, 1950 2,735,005 2/1956 Steele 235/92 21737342 3/1956 235/6' Primary Examiner-Paul .1. Henon 52:21:31: ttorney-Charles c. English and William Grobman 2,810,516 10/1957 Toothill e! 111... .1 235/157 2,313,238 3 1943 HOICOmb 178/52 EXEMPLARY CLAIM 5 3/1944 Kolmfi 5/ I. In an information handling system wherein informa- 23358970 11/1953 tion is represented by electrical impulse trains having 2,682,574 6/1954 Canfora 178/50 the same number of impulse positions in each train g g 'g each train representing an item of information and 9/1952 235/6] containing impulses which are present and absent in 2'6l5l27 0/1952 Edwards H 235,6] and from said positions in a coded arrangement which 2,750,532 6 1956 Samuel 235/61 varies with the item of information represented y 2,617,704 11 1952 Mallina 235/61 h train. n information transfer network. means to 2,657,856 11/1953 Edwards 235/ supply impulse trains to the input to said transfer net- .75 9/1956 wright I 0/ work, and checking means coupled to said transfer 21418928 4/1947 Gemme|m- 178/531 network, said checking means including a first counter 2'544l26 3/1951 Baldwin 235,6 means indicating the count of the individual trains 2,777,635 1/1957 Tootlll et a1. 2351157 pp to Said network a Second counter means 6,558,447 6/1951 MacSar1ey.... 235/92 r 2.604262 7/1952 Phelps n 235,61 sponsive to the mdividual impulses contained w1th1n 2,7962; 6,1957 Tomi" at n 235" the trams supplied to said network, and means for pe- 2,623,115 1211952 Woods-Hill 235/61 riodically indicating when Said first and Second 2,623,171 12/1952 w00dS-Hi11 11 235 61 counter means o or do not tally. 2,652,554 9/ I 953 Williams et a1 i 235f k 2.671,607 3/ 1954 Williams et a1 235/172 43 Claims, 303 Drawing Figures PATENTEUJAN 8:914 3.784.983 SHEEI OIUF 263 IN V EN TOR! J. PRESPER ECKERT, JR

JAMES R. WEINER ROBERT F SHAW H. FRAZER WELSH ATTORN=Y PATENIEDJIIII 8 I914 SIIEEI MANUAL GDNTRDL CONTROL BUSSES r r i SUPERVISORY TO ALL UN'TS CONTROL READ BUS TO AND FROM ALL TAPE N D S G3I L TRANSDUCERS 1 FROM ALL UNITS A h I WRITE I CONTROL I B L MAIN MEMORY I-- (MM) MEMORY I I SWITCH I I I IIDDD WORDS) I y I I HSDZM HSBIM I |NPUT- I FONTROL SIGNALS OUTPUT I I6 INPUTVOUTPUT I CONTROL I CONTROL 8 I I I I SYNCHRONIZERS I I I I A I I l i y l I L w INPUT I OUTPUT SYNCHRONIZER SYNCHRONIZER I I I n I I I re I60 WDRDSI I I I I60 WDRDSI I I I V V V SIGNALS TO coNTRoL HIGH cIRcuITS ODD EVEN HSBII CHECKER AMEL I EIER HSBZO (DEC) (HSBA) CC CR (I WORD) (I WDRDI I FIG. 2A FIG. 2B

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PATENTEDJMI M14 3,784,983 SHEET DMJF 263 IN VEN TORS J. PRESPER ECKERT, JR.

JAMES R. WEINER ROBERT F. SHAW H. FRAZER WELSH BY M WA ATTORNEY RESET PULSE FIG. 92

ADOEND s 2 sun AUGENO 11 'EN TORS J. PRESPER ECKERT, JR, 8 JAMES R. WEINER A CARRY ROBERT F. SHAW IG. BY "6801111 1! Tomb H. FRAZER WELSH PATENTEDJAI 819M 3784.983

SHEEI 079? 263 MANUAL SET INI'ENTORS J. PRESPER ECKERT, JR. JAMES R. WEINER ROBERT F. SHAW H. FRAZER WELSH av y ATTORNEY PATENIEDJAN 8W4 3,784,983

saw user 263 GOES GBEG

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sum 09 a; 263

1N1 'EN TORS J PRESPER ECKERT, JR.

JAMES R. WEINER ROBERT F. SHAW H. FRAZER WELSH ATTORNLY MTEHTEH JAN 8 W SHEEY 10 OF 263 Shae -n NO m Fan 1N1 'EN TORS PATENTEU I 31974 3. 784,983

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WORD l FIG. 14 l 1] INPUT A INVENTORS FIG. JV PRESPER ECKERT, JR.

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ATTORNEY PATENTEDJAI 8 i974 SHEET 1% OF 263 OUT FIGIESA 1 N VEN T ORS IATENTEUJAH 8 IBM SHEET 16 OF 263 IT I 000 col FIG.2I

PMENTEDJA! 8:974 3.784.983

c; O U W WA i c: C Q 19 A G. vra E E 8 a I I; T I l 1N1 'EAN'TORS J. PRESPER ECKERT, JR.

JAMES R. WEINER ROBERT F. SHAW H. FRAZER WELSH ATTORN Y iM ENIED- 8W 3,784,993

SHEI 180? 263 J. PRESPER ECKERT, JR.

JAMES R. wemsa ROBERT F. SHAW H FRAZER WELSH BY 25km; L 3561 .1(

ATTORN Y

Claims (43)

1. In an information handling system wherein information is represented by electrical impulse trains having the same number of impulse positions in each train, each train representing an item of information and containing impulses which are present and absent in and from said positions in a coded arrangement which varies with the item of information represented by each train an information transfer network, means to supply impulse trains to the input to said transfer network, and checking means coupled to said transfer network, said checking means including a first counter means indicating the count of the individual trains supplied to sAid network, a second counter means responsive to the individual impulses contained within the trains supplied to said network, and means for periodically indicating when said first and second counter means do or do not tally.
2. An information handling system as set forth in claim 1 wherein said indicating means indicates a tally when said number of impulses which are present in each train is an odd integer.
3. An information handling system as set forth in claim 1 wherein said indicating means indicates a tally when the total number of impulses which are present in a plurality of trains is an even integer.
4. An information handling system as set forth in claim 1 wherein checking means is rendered inoperative when said indicating means indicates a tally.
5. An information handling system as set forth in claim 1 wherein said checking means is rendered operative when said indicating means indicates a tally.
6. In combination, a reentrant circulating storage means for storing a plurality of electrical impulse trains in series disposition in time, each train representing an item of information and containing impulses which are present and absent in and from said positions in a coded arrangement which varies with the item of information represented by each train, checking means comprising a first counter means indicating the count of the individual trains applied to said checking means, a second counter means responsive to the individual impulses contained within the trains applied to said checking means, means for periodically indicating when said first and second counter means do not tally, and means for passing the contents of said storage means through said checking means.
7. The combination defined in claim 6 further including means for periodically altering the circulation loop of said storage means to include said checking means.
8. The combination defined in claim 7 wherein the period of time between adjacent alterations is greater than the time of circulation in said storage means.
9. A data processing system in which data in the form of coded signal groups is processed by electronic equipment in accordance with prescribed instructions in the same form, said system comprising input devices for storing large amounts of data to be processed and instructions, electronic apparatus for processing data in the form of coded groups of signals, an internal memory for storing instructions and data to be processed, said internal memory being connected to said electronic apparatus for supplying data to said apparatus, a first control unit receiving coded instructions from said internal memory and utilizing said coded instructions to control the operation of said data processing system, transfer means for selectively transferring data to be processed and instructions from said input devices to said internal memory, said transfer means including buffer storage means for accumulating signal groups as they are transferred from said input devices and for retaining a plurality of the accumulated signal groups so transferred preliminary to transfer to said internal memory while said electronic apparatus is processing other pluralities of signal groups earlier stored in said internal memory and a second control unit for controlling the transfer of data and instructions from said input devices to said buffer storage means during the time that data from said memory is being processed by said apparatus.
10. A data processing system in which data represented by coded groups of signals are processed in accordance with instructions represented by groups of signals, said system comprising means for processing data in the form of signal groups in accordance with prescribed instructions, an internal memory of limited capacity, said internal memory storing groups of signals which represent data to be processed and instructions, first means for selectively connecting said internal memory to said data processing means for transferring signal groups representing dAta to be processed from said memory to said data processing means, first control means connected to said internal memory for receiving therefrom signal groups representative of instructions and to said data processing means for controlling the operation of said data processing means in accordance with said instructions, input equipment for storing signal groups representative of data to be processed and instructions in numbers virtually without limit, means for transferring signal groups from said input equipment to said internal memory, including buffer storage means connected between said input equipment and said internal memory for receiving individual signal groups from said input equipment and for accumulating a plurality of signal groups transferred from said input equipment for later transfer to said internal memory, and second control means operable upon an initial stimulation of said first control means to control the transfer of signal groups from said input equipment to said buffer storage means at the same time said first control means is controlling the operation of said data processing means in the processing of signal groups stored in said internal memory.
11. A data processing system comprising input equipment for storing data to be processed; data processing apparatus including manipulation and utilization means for processing data, memory means for temporarily storing both data to be processed received from said input equipment and the results of data processing, means for connecting said memory means to said manipulation and utilization means for transferring thereto data to be processed and for receiving therefrom the results of such processing, said first control means for controlling the operation of said manipulation and utilization means and the transfer of data and results between said memory and said manipulation and utilization means; output equipment for receiving from said memory results of data processing and for storing such results; buffer storage means connected between said memory and said input and output equipment for storing data being transferred between said memory and said input and output equipment, said buffer means transferring data to and from said memory and to and from said input and output equipment; and second control means operable under the initial stimulation of said first control means for controlling the operation of said buffer storage means and said input and output equipment while said first control means is controlling the operation of said data processing apparatus.
12. The data processing system defined in claim 10 further including means for terminating the transfer of data from said input equipment to said buffer storage means when a preselected number of input signal groups have been transferred.
13. The data processing system defined in claim 10 wherein said means for transferring signal groups from said input equipment to said internal memory includes means for transferring the contents of said buffer storage means to said memory means, said last named means being under the control of said first control means.
14. The data processing system defined in claim 11 further including means for transferring data between said buffer storage means and said memory means under the control of said first control means.
15. The data processing system defined in claim 11 wherein said second control means includes means for terminating the transfer of data from said buffer storage means to said output equipment when a preselected amount of data has been transferred.
16. An electronic data processing system comprising manipulation and utilization means for processing data in the form of groups of serially arranged electric pulse positions, all groups comprising the same number of positions, each group representing a character by the presence and absence of pulses in prescribed combinations, a memory for supplying data to be processed to said manipulation and utilization means and temporarily storing said daTa in words of a prescribed length, means for checking individual groups, said checking means including a first counter means responsive to the individual pulses contained within a group, second counter means responsive to each group of positions, means for periodically indicating when said first and second counters do and do not tally and means for periodically presenting the entire contents of said memory to said checking means for checking each group thereof.
17. An electronic data processing system comprising manipulation and utilization means for processing data in the form of series of individual characters arranged in words of a fixed length, each character being represented by a group of electric pulse positions, pulses being present in or absent from individual positions in prescribed combinations to represent information, a memory for temporarily storing a plurality of words and for transferring such words to said manipulation and utilization means for processing, means for checking individual groups of pulses for conformity to a specified condition, said checking means including a first counter means responsive to the individual pulses in the pulse positions representing a character, a second counter means indicating the count of individual characters, means for periodically indicating when said first and second counter means do not tally, and means for periodically presenting the entire contents of said memory to said checking means to determine the conformance of each group contained therein to said condition.
18. In a data handling system, a first storage device, a second storage device, a tape unit, means for driving said tape unit, means for transferring information between said first storage device and said tape unit, means for initiating the operation of said tape driving means including means for delaying the operation of said information transfer means for a period after the initiation of the operation of said tape driving means to allow said tape unit to attain its operating speed and means for transferring information between said storage devices during said period of delay.
19. In a data handling system, a first storage device, a second storage device, means for transferring data between said storage devices, a tape unit, means for transferring data between said first storage device and said tape unit, means for driving said tape unit, means for simultaneously initiating the operation of said first mentioned data transfer means and said tape driving means, means for delaying the operation of said second mentioned data transfer means for a period after the initiation of the operation of said tape driving means to allow said tape unit to attain its operating speed.
20. In a data handling system, a source of data, a storage device, means for transferring data from said source to said storage device, a write tape unit, means for transferring data from said storage device to said write tape unit, means for driving said write tape unit, means for simultaneously initiating the operation of said first data transfer means and said type driving means and means for delaying the operation of said second mentioned data transfer means for a period after the initiation of the operation of said tape driving means to allow said tape unit to attain its operating speed, during which period the data transfer from said source to said storage device is completed.
21. In a data handling system, a first storage device having information stored therein, a second storage device, a tape unit, means for driving said tape unit, means for transferring information from said tape unit to said first storage unit, means for initiating the operation of said tape driving means including means for delaying the operation of said information transfer means for a period after the initiation of the operation of said tape driving means to allow said tape unit to attain its operating speed and means for transferring information from said first storage device to said second storage devIce during said period of delay.
22. In a data handling system, a first storage device having information stored therein, a second storage device, means for transferring information from said first storage device to said second storage device, a read tape unit having information stored therein, means for transferring information from said read tape unit to said first storage device, means for driving said read tape unit, means for simultaneously initiating the operation of said first information transfer means and said tape driving means and means for delaying the operation of said second mentioned information transfer means for a period after the initiation of the operation of said tape driving means to allow said read tape unit to attain its operating speed, during which period the information transfer from said first storage device to said second storage device is completed.
23. In combination, a record medium having data representations recorded thereon, reading means, means energized to feed said record medium past said reading means at a certain speed, means conditioning said reading means to read data representations from said record medium as it is fed, a storage device having data representations stored therein, a data processing device, means controlling transfer of data representations from said record medium to said storage device and from said storage device to said data processing device, said last named means including means to first energize said feed means, means rendering said conditioning means inoperative for a fixed period after said feed means is first energized until said record medium is being fed at said certain speed, means reading data representations from said storage device to said processing device during said fixed period and means transferring data representations from said reading means to said storage device after said fixed period.
24. In combination, a record medium having data representations recorded thereon, reading means, means capable of being energized to feed said record medium past said reading means at a certain speed, means conditioning said reading means to read said data representations from said record medium as it is fed, a storage device having data representations stored therein, a data processing device, means controlling transfer of data representations from said record medium to said storage device and from said storage device to said data processing device, said last named means including means to initiate transfer of data from said storage device to the processing device, means first energizing said feed means during the transfer of data from said storage device to the processing device, means rendering said conditioning means inoperative for a fixed period after said feed means is first energized, and means transferring data representations from said reading means to said storage device after said fixed period.
25. In a data handling system, a storage unit having a plurality of storage registers for storing a file of information, a write tape unit, means for transferring a first file of information from said storage unit to said write tape unit, a read tape unit, means for transferring a second file of information from said read tape unit to said storage unit, and means for controlling said transferring means to operate concurrently so that the first file of information is transferred from said storage unit to said write tape unit while the second file of information is concurrently transferred from said read tape unit to said storage unit.
26. In combination with a central processing unit which operates in accordance with a program of instructions, a storage unit having a plurality of storage registers for storing information, a write tape unit, means for transferring information from said storage unit to said write tape unit, a read tape unit, means for transferring information from said read tape unit to said storage unit and means operable under control of said central processing unit in accordance with the progRam of instructions to control said transferring means to operate concurrently while said central processing unit is processing data.
27. An electronic digital computer comprising main digital stores, supplementary digital stores, a main instruction control having a plurality of instruction outputs, a plurality of gates connected to the instruction outputs and to locations in the main digital stores for controlling transfers to and from the said locations, a supplementary instruction control connected to the supplementary digital stores and for controlling transfers between the main digital stores and the supplementary digital stores, at least one further gate connected to a first instruction output, to a second instruction output and to the supplementary instruction control to control the application of the second instruction output to the supplementary instruction control in accordance with the signal applied to said further gate from said first instruction output.
28. An electronic digital computer comprising main digital stores, supplementary digital stores, a main instruction control having a plurality of instruction outputs including a first set of instruction outputs and a second set of instruction outputs, a plurality of gates connected to at least some of the instruction outputs and to locations in the main digital store for controlling transfers between locations in the main digital store, a supplementary instruction control connected to the supplementary digital stores and for controlling transfers between the main digital stores and the supplementary digital stores, and a set of gates, each connected separately to each of the first set of instruction outputs, all connected collectively to at least one instruction output of the second set of instruction outputs and each connected to the supplementary instruction control to control the application of the first set of instruction outputs thereto.
29. An information handling system comprising, a digital data processor section, an input-output device, said input-output device having writing circuits for recording digital data on a record member and reading circuits for reading digital data from a record member, a read synchronizer for coupling the read circuits of said input-output device to said data processor section, a write synchronizer for coupling said data processor section to the write circuits of said input-output device, a control circuit coupled to said data processor section for sequencing said processor through a routine and for selectively generating certain input-output control signals, an input-output control circuit responsive to a first one of said input-output control signals to energize said input-output device and responsive to predetermined others of said input-output control signals to actuate a selected one of said synchronizers, means for indicating the amount of data transferred between said input-output device and said data processor section and for generating a release signal when a predetermined quantum of data has been transferred, and an interlock circuit included in the input-output control circuit responsive to said input-output control signals and said release signal for inhibiting both the further energization of said input-output device and the reactuation of the selected synchronizer until after the generation of the release signal.
30. An information handling system comprising, a digital data processor section, an input-output device adapted to handle a record member on which coded information can be recorded, a signal translation network coupling said input-output device to said data processor section, said network being operative to feed coded information signals read by said input-output device into said data processor section or for feeding coded information signals into said input-output device from said data processor section, a first control circuit means included in said data processor section for controlling the operation of said data processor section and For generating certain input-output control signals, a second control circuit means coupled to said input-output device for controlling the operations of said device in response to the receipt of certain input-output control signals, means coupling the input-output control signals generated by said first control circuit means to said second control circuit means, settable control elements in said second control circuit means for storing certain input-output control signals generated by said first control means, and means in said second control circuit means responsive to the initiation of an input-output operation by said input-output device for terminating the generation of said certain input-output control signals by said first control circuit means.
31. In an electronic digital information processing system, apparatus for processing information according to a program of commands designating a sequence of operations to be performed by said apparatus, storage means storing items of information and said program of commands coupled to said apparatus, said storage means containing a first sequence of commands in first consecutive addresses, said first sequence representing commands for carrying out a first operation, and a second sequence of commands in second consecutive addresses, said second sequence representing commands for carrying out a second operation, an address counter the count of which represents the address in said storage means of the next command to be used, said address counter being coupled to said storage means to cause the command in the address designated thereby to be applied to said apparatus, said apparatus including a first storage register for receiving and storing a result from the execution of some of said operations, and a second storage register for receiving and storing a result from the execution of other of said operations, and first control means connected to said registers and to said apparatus for comparing the contents of said first and second registers and for modifying the contents of said address counter when the value of the information in said first register is greater than the value of the information in said second register, the contents of the address counter being modified from a count representing an address in said first sequence of addresses to the first address in said second sequence of addresses whereby the control of said apparatus is effectively transferred from said sequence to said second sequence.
32. In an electronic digital information processing system, apparatus for processing information according to a program of commands designating a sequence of operations to be performed by said apparatus, storage means storing items of information and said program of commands coupled to said apparatus, said storage means containing a first sequence of commands in first consecutive addresses, said first sequence representing commands for carrying out a first operation, and a second sequence of commands in second consecutive addresses, said second sequence representing commands for carrying out a second operation, an address counter the count of which represents the address in said storage means of the next command to be used, said address counter being coupled to said storage means to cause the command in the address designated thereby to be applied to said apparatus, said apparatus including a first storage register for receiving and storing a result from the execution of some of said operations, and a second storage register for receiving and storing a result from the execution of other of said operations, and control means connected to said registers and to said apparatus for comparing the contents of said first and second registers and for modifying the contents of said address counter when the value of the information in said first register is equal to the value of the information in said second register, the contents of the address counter being modified from a count representing an address in said first sequence oF addresses to the first address in said second sequence of addresses whereby the control of said apparatus is effectively transferred from said first sequence to said second sequence.
33. In an electronic digital information processing system, apparatus for processing information according to a program of commands designating a sequence of operations to be performed by said apparatus, storage means storing items of information and said program of commands coupled to said apparatus, said storage means containing a first sequence of commands in first consecutive addresses, said first sequence representing commands for carrying out a first operation, and a second sequence of commands in second consecutive addresses, said second sequence representing commands for carrying out a second operation, an address counter the count of which represents the address in said storage means of the next command to be used, said address counter being coupled to said storage means to cause the command in the address designated thereby to be applied to said apparatus, said apparatus including a first storage register for receiving and storing a result from the execution of some of said operations, and a second storage register for receiving and storing a result from the execution of other of said operations, and control means connected to said registers and to said apparatus for comparing the contents of said first and second registers and for modifying the contents of said address counter when the value of the information in said first register bears a predetermined relation to the value of the information in said second register, the contents of the address counter being modified from a count representing an address in said first sequence of addresses to the first address in said second sequence of addresses whereby the control of said apparatus is effectively transferred from said first sequence to said second sequence.
34. In an electronic digital information processing system, apparatus for processing information according to a program of commands designating a sequence of operations to be performed by said apparatus, items of information to be processed and individual commands to said system comprising groups of signals, storage means storing items of information and said program of commands coupled to said apparatus, and automatic control means coupled to said storage means and responsive to a first portion of the signals in a group representative of a command for controlling the operation of said processing apparatus, said automatic control means further including a first means for modifying the sequence of commands whenever any of a plurality of preselected signal patterns appears in a second portion of the signals comprising a command, said automatic means including a device for detecting any of the preselected signal patterns in the second portion of the command and for rendering said first means operative.
35. In an electronic digital information processing system, apparatus for processing information according to a program of commands designating a sequence of operations to be performed by said apparatus, items of information to be processed and individual commands to said system comprising groups of signals, means storing items of information and said program of commands coupled to said apparatus, and automatic control means responsive to a first portion of the signals in a group representative of a command for controlling the operation of said processing apparatus, said automatic control means further including comparison apparatus receiving the signals in a second portion of the group representing said command, a register storing values corresponding to any of a plurality of signal patterns in the second portion of a command coupled to said comparison apparatus, means responsive to a plurality of different signal patterns in said first portion of a command to render said comparison apparatus operable, said comparison apparatus responsive when operable to produce an ouTput upon the detection of a predetermined relationship between a value in said register and the pattern of signals in said second portion of the group of signals representing said command to automatically modify said sequence of operations.
36. The system set forth in claim 35 further defined in that said register comprises a plurality of manually operated switches wherein each switch when operated represents a different value.
37. In an electronic digital processing system, apparatus for processing information according to a program of commands designating a sequence of operations to be performed by said apparatus, items of information to be processed and individual commands to said system comprising groups of signals, storage means comprising a plurality of addresses at which signal groups may be stored, said storage means containing a first sequence of signal groups in first consecutive addresses, said first sequence representing commands for carrying out a first operation, and a second sequence of signal groups in second consecutive addresses, said second sequence representing commands for carrying out a second operation, automatic control means coupled to said storage means and responsive to a first portion of the signals in a group representative of a command for controlling the operation of said processing apparatus, an address counter the count of which represents the address in said storage means of the next command to be used, said address counter being coupled to said storage means to cause the individual command in the address designated thereby to be applied to said apparatus, said apparatus including a first storage register for receiving and storing a group of signals which result from the execution of some of said operations, and a second storage register system for receiving and storing a group of signals which result from the execution of other of said operations, the group of signals in said first and second registers being representative of information, first control means connected to said registers and to said system and responsive to certain predetermined commands for comparing the contents of said first and second registers and for modifying the contents of said address counter when the value of the information in said first register bears a predetermined relationship to the value of the information in said second register, the contents of the address counter being modified from a count representing an address in said first sequence of addresses to the first address in said second sequence of addresses whereby the control of said apparatus is effectively transferred from said first sequence to said second sequence and wherein said automatic control means further includes apparatus responsive to prescribed patterns of signals in a second portion of the signals in the group representing said predetermined commands to automatically halt the operation of said system after the comparison of the contents of said registers has taken place and before the control of said apparatus is transferred.
38. In an electronic digital processing system, apparatus for processing information according to a program of commands designating a sequence of operations to be performed by said apparatus, items of information to be processed and individual commands to said system comprising groups of signals, storage means comprising a plurality of addresses at which signal groups may be stored, said storage means containing a first sequence of signal groups in first consecutive addresses, said first sequence representing commands for carrying out a first operation, and a second sequence of signal groups in second consecutive addresses, said second sequence representing commands for carrying out a second operation, automatic control means coupled to said storage means and responsive to a first portion of the signals in a group representative of a command for controlling the operation of said processing apparatus, an address counter the count of which represents the adDress in said storage means of the next command to be used, said address counter being coupled to said storage means to cause the individual command in the address designated thereby to be applied to said apparatus, said apparatus including a first storage register for receiving and storing a group of signals which result from the execution of some of said operations, and a second storage register system for receiving and storing a group of signals which result from the execution of other of said operations, the group of signals in said first and second registers being representative of information, first control means connected to said registers and to said system responsive to certain predetermined commands for comparing the contents of said first and second registers and for modifying the contents of said address counter when the value of the information in said first register bears a predetermined relationship to the value of the information in said second register, the contents of the address counter being modified from a count representing an address in said first sequence of addresses to the first address in said second sequence of addresses whereby the control of said apparatus is effectively transferred from said first sequence to said second sequence and wherein said automatic control means further includes comparison apparatus receiving the signals in a second portion of the signals in the group representing said predetermined commands, a third register storing values coupled to said comparison apparatus, said comparison apparatus responsive to produce an output upon the detection of a predetermined relationship between the value in said register and the pattern of signals in said second portion of the group of the signals representing said predetermined commands, to automatically halt the operations of said system after the comparison of the contents of said registers has taken place and before the control of said apparatus is transferred.
39. The system set forth in claim 38 further defined in that said third register comprises a plurality of manually operated switches, wherein each switch when operated represents a different value.
40. In a stored program digital computer comprising a memory for storing instruction and data digits, an arithmetic unit, a control unit and at least one register for storing instruction digits thereby enabling said control unit to furnish control signals to said arithmetic unit, the improvement which comprises a plurality of presettable means each capable of being readily turned off and on and each representing a different digit when turned on, said means being associated with said register and effective to produce an output signal in response to the presence of any one of a number of predetermined digits in an instruction when turned on and to ignore any one of said number of predetermined digits which might be present in an instruction when turned off, and means responsive to an output signal from said presettable means to modify the operation of said computer.
41. In a stored program digital computer comprising a memory for storing instruction and data digits, an arithmetic unit for performing operations on said data in response to instruction digits, an instruction register, a control unit for developing control signals in response to instructions stored in said instruction register and at least one sequencing means for controlling the sequence of instructions extracted from said memory, the improvement which comprises a plurality of presettable means each capable of being readily turned on and off and each representing a different digit when turned on, said means being effective to produce an output signal in response to the presence of any one of a number of predetermined digits in an instruction when turned on and to ignore any of said number of predetermined digits which might be present in an instruction when turned off, and means associated with said presettable means and said sequencing means effective to determine fuRther sequencing of instructions in accordance with a digit so detected.
42. The system defined in claim 9 wherein said second control unit comprises means for choosing and causing one of said input devices to transmit data to said buffer storage means.
43. The system defined in claim 9 wherein said second control unit is coupled to receive at least a portion of an instruction from said internal memory and comprises means for choosing and causing one of said input devices to transmit data to said buffer storage means in response to at least a portion of an instruction.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4030074A (en) * 1974-06-03 1977-06-14 Centro Studi E Laboratori Telecomunicazioni System for checking two data processors operating in parallel
US6158857A (en) * 1999-04-29 2000-12-12 Hewlett-Packard Company Internal drum communication using a capacitor
US10252736B2 (en) * 2015-11-25 2019-04-09 Coordem Transport Tech. Co., Ltd. Method and system for controlling grade of automation of train operation

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2950465A (en) * 1954-03-22 1960-08-23 Ibm Electronic data processing machine
US3245039A (en) * 1954-03-22 1966-04-05 Ibm Electronic data processing machine
US2974866A (en) * 1954-03-30 1961-03-14 Ibm Electronic data processing machine
NL198494A (en) * 1954-07-01
US2936118A (en) * 1954-09-27 1960-05-10 Marchant Res Inc Electronic digital computers
US3015442A (en) * 1954-12-24 1962-01-02 Ibm Electronic multipliers
US3118055A (en) * 1954-12-28 1964-01-14 Rca Corp Electronic digital information handling system with character recognition for controlling information flow
NL203878A (en) * 1955-01-24
US3050717A (en) * 1955-03-04 1962-08-21 Burroughs Corp Computer shift control circuits
US3053449A (en) * 1955-03-04 1962-09-11 Burroughs Corp Electronic computer system
US2982472A (en) * 1955-05-02 1961-05-02 Harry D Huskey Binary digital computer with magnetic drum storage
US3274376A (en) * 1955-05-18 1966-09-20 Bendix Corp Digital differential analyzer in conjunction with a general purpose computer
NL209391A (en) * 1955-08-01
BE550148A (en) * 1955-08-11 1900-01-01
US2957626A (en) * 1955-11-21 1960-10-25 Ibm High-speed electronic calculator
US3313925A (en) * 1956-05-11 1967-04-11 Gen Precision Inc Digital differential analyzer
US3012722A (en) * 1956-08-31 1961-12-12 Minneanolis Honeywell Regulato Checking circutiry for data processing apparatus
US3029412A (en) * 1956-09-20 1962-04-10 Ibm Data input-output control mechanism
US2979260A (en) * 1956-09-21 1961-04-11 Ibm Data transfer system
US3170142A (en) * 1956-09-26 1965-02-16 Ibm Data processing machine
US3037700A (en) * 1956-11-29 1962-06-05 Ibm Indexing registers for calculators
US3201762A (en) * 1957-01-25 1965-08-17 Honeywell Inc Electrical data processing apparatus
US2937810A (en) * 1957-06-28 1960-05-24 Bell Telephone Labor Inc Digital computer circuit
US3019976A (en) * 1957-12-26 1962-02-06 Ibm Data processing system including an indicating register
US3037193A (en) * 1958-02-28 1962-05-29 Honeywell Regulator Co Electrical apparatus for processing digital data
US3157867A (en) * 1958-07-18 1964-11-17 Ncr Co Tape handling apparatus
BE582071A (en) * 1958-08-29 1900-01-01
FR1210183A (en) * 1958-09-05 1960-03-07 Improvements to series-type arithmetic machines
US3062438A (en) * 1958-12-30 1962-11-06 Ibm Data storage and transfer apparatus
US3074636A (en) * 1958-12-31 1963-01-22 Texas Instruments Inc Digital computer with simultaneous internal data transfer
US3022006A (en) * 1959-01-26 1962-02-20 Burroughs Corp Floating-point computer
US3105143A (en) * 1959-06-30 1963-09-24 Research Corp Selective comparison apparatus for a digital computer
US3166668A (en) * 1960-03-24 1965-01-19 Ibm Computer program system
US3222650A (en) * 1960-12-30 1965-12-07 Ibm Interpretation machine
NL279116A (en) * 1961-05-31
US3277448A (en) * 1961-12-06 1966-10-04 Scm Corp Data processing mechanisms
US3231867A (en) * 1962-03-02 1966-01-25 Gen Dynamics Corp Dynamic data storage circuit
US3252149A (en) * 1963-03-28 1966-05-17 Digitronics Corp Data processing system

Citations (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2313238A (en) * 1933-04-13 1943-03-09 Western Union Telegraph Co Multichannel telegraph system
US2344885A (en) * 1938-10-21 1944-03-21 Int Standard Electric Corp Electrical calculating equipment
US2418928A (en) * 1944-11-04 1947-04-15 Teletype Corp Telegraph system and apparatus for selective single or double channel operation
FR964113A (en) * 1950-08-07
US2528101A (en) * 1947-07-29 1950-10-31 Bell Telephone Labor Inc Telephone system
US2538636A (en) * 1947-12-31 1951-01-16 Bell Telephone Labor Inc Digital computer
US2539043A (en) * 1943-02-22 1951-01-23 Cie Ind Des Machines Automatiq Number comparing device
US2539623A (en) * 1947-02-12 1951-01-30 Bell Telephone Labor Inc Communication system
US2544126A (en) * 1947-03-25 1951-03-06 Powers Samas Account Mach Ltd Calculating machine
FR975941A (en) * 1948-09-22 1951-03-12 Electronique & Automatisme Sa Pulse counters
US2552629A (en) * 1950-01-11 1951-05-15 Bell Telephone Labor Inc Error-detecting and correcting system
US2558447A (en) * 1948-12-30 1951-06-26 Rca Corp High-speed frequency divider
US2570716A (en) * 1948-11-27 1951-10-09 Sylvania Electric Prod Signal transmission network
US2589465A (en) * 1949-10-22 1952-03-18 Eckert Mauchly Comp Corp Monitoring system
US2604262A (en) * 1949-01-19 1952-07-22 Ibm Multiplying and dividing means
US2609143A (en) * 1948-06-24 1952-09-02 George R Stibitz Electronic computer for addition and subtraction
US2611813A (en) * 1948-05-26 1952-09-23 Technitrol Engineering Company Magnetic data storage system
US2615127A (en) * 1949-09-17 1952-10-21 Gen Electric Electronic comparator device
US2617704A (en) * 1947-07-15 1952-11-11 Bell Telephone Labor Inc Recording system
US2622148A (en) * 1948-03-15 1952-12-16 Nederlanden Staat Error detector for telegraph printer codes
US2623171A (en) * 1949-03-24 1952-12-23 Ibm Electronic divider
US2623115A (en) * 1949-03-24 1952-12-23 Ibm Electronic multiplier
US2624507A (en) * 1945-09-27 1953-01-06 Ibm Electronic calculating machine
US2625328A (en) * 1946-12-17 1953-01-13 Bell Telephone Labor Inc Automatic code translating system
US2634052A (en) * 1949-04-27 1953-04-07 Raytheon Mfg Co Diagnostic information monitoring system
US2639859A (en) * 1950-11-29 1953-05-26 Rca Corp Transitory memory circuits
US2641696A (en) * 1950-01-18 1953-06-09 Gen Electric Binary numbers comparator
US2652196A (en) * 1949-05-20 1953-09-15 Remington Rand Inc Wire recording storage mechanism for bookkeeping machines
US2652554A (en) * 1949-03-01 1953-09-15 Nat Res Dev Magnetic storage system for electronic binary digital computers
US2657856A (en) * 1949-11-15 1953-11-03 Gen Electric Number converter
US2658670A (en) * 1949-08-31 1953-11-10 Rca Corp Rate determining device
US2659072A (en) * 1949-01-13 1953-11-10 John F Coales Data transmission system for digital calculating machines or the like
US2671611A (en) * 1946-12-17 1954-03-09 Bell Telephone Labor Inc Control circuit for calculating machines
US2671607A (en) * 1948-10-13 1954-03-09 Nat Res Dev Electronic digital computing apparatus
US2672283A (en) * 1948-09-03 1954-03-16 Ibm Electronic multiplier
US2682574A (en) * 1952-03-29 1954-06-29 Rca Corp Electronic diplex transmitting distributor
US2686632A (en) * 1950-01-04 1954-08-17 Nat Res Dev Digital computer
US2701095A (en) * 1949-02-12 1955-02-01 George R Stibitz Electronic computer for division
US2726038A (en) * 1948-05-18 1955-12-06 William K Ergen Electronic digital computers
US2735005A (en) * 1956-02-14 Add-subtract counter
US2737342A (en) * 1948-08-04 1956-03-06 Teleregister Corp Rotary magnetic data storage system
US2749037A (en) * 1950-04-21 1956-06-05 George R Stibitz Electronic computer for multiplication
US2750532A (en) * 1948-06-03 1956-06-12 Ibm Cathode-ray devices, particularly for electronic computers
US2757864A (en) * 1950-08-30 1956-08-07 Nat Res Dev Information translating apparatus
US2764750A (en) * 1949-12-02 1956-09-25 Int Standard Electric Corp Arrangements for extracting information from electrical storage circuits
US2767908A (en) * 1950-08-18 1956-10-23 Nat Res Dev Electronic digital computing machines
US2777635A (en) * 1949-08-17 1957-01-15 Nat Res Dev Electronic digital computing machines
US2796218A (en) * 1949-06-22 1957-06-18 Nat Res Dev Electronic computing devices with subsidiary storage
US2810516A (en) * 1949-06-03 1957-10-22 Nat Res Dev Electronic digital computing devices

Patent Citations (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR964113A (en) * 1950-08-07
US2735005A (en) * 1956-02-14 Add-subtract counter
US2313238A (en) * 1933-04-13 1943-03-09 Western Union Telegraph Co Multichannel telegraph system
US2344885A (en) * 1938-10-21 1944-03-21 Int Standard Electric Corp Electrical calculating equipment
US2539043A (en) * 1943-02-22 1951-01-23 Cie Ind Des Machines Automatiq Number comparing device
US2418928A (en) * 1944-11-04 1947-04-15 Teletype Corp Telegraph system and apparatus for selective single or double channel operation
US2624507A (en) * 1945-09-27 1953-01-06 Ibm Electronic calculating machine
US2671611A (en) * 1946-12-17 1954-03-09 Bell Telephone Labor Inc Control circuit for calculating machines
US2625328A (en) * 1946-12-17 1953-01-13 Bell Telephone Labor Inc Automatic code translating system
US2539623A (en) * 1947-02-12 1951-01-30 Bell Telephone Labor Inc Communication system
US2544126A (en) * 1947-03-25 1951-03-06 Powers Samas Account Mach Ltd Calculating machine
US2617704A (en) * 1947-07-15 1952-11-11 Bell Telephone Labor Inc Recording system
US2528101A (en) * 1947-07-29 1950-10-31 Bell Telephone Labor Inc Telephone system
US2538636A (en) * 1947-12-31 1951-01-16 Bell Telephone Labor Inc Digital computer
US2622148A (en) * 1948-03-15 1952-12-16 Nederlanden Staat Error detector for telegraph printer codes
US2726038A (en) * 1948-05-18 1955-12-06 William K Ergen Electronic digital computers
US2611813A (en) * 1948-05-26 1952-09-23 Technitrol Engineering Company Magnetic data storage system
US2750532A (en) * 1948-06-03 1956-06-12 Ibm Cathode-ray devices, particularly for electronic computers
US2609143A (en) * 1948-06-24 1952-09-02 George R Stibitz Electronic computer for addition and subtraction
US2737342A (en) * 1948-08-04 1956-03-06 Teleregister Corp Rotary magnetic data storage system
US2672283A (en) * 1948-09-03 1954-03-16 Ibm Electronic multiplier
FR975941A (en) * 1948-09-22 1951-03-12 Electronique & Automatisme Sa Pulse counters
US2671607A (en) * 1948-10-13 1954-03-09 Nat Res Dev Electronic digital computing apparatus
US2570716A (en) * 1948-11-27 1951-10-09 Sylvania Electric Prod Signal transmission network
US2558447A (en) * 1948-12-30 1951-06-26 Rca Corp High-speed frequency divider
US2659072A (en) * 1949-01-13 1953-11-10 John F Coales Data transmission system for digital calculating machines or the like
US2604262A (en) * 1949-01-19 1952-07-22 Ibm Multiplying and dividing means
US2701095A (en) * 1949-02-12 1955-02-01 George R Stibitz Electronic computer for division
US2652554A (en) * 1949-03-01 1953-09-15 Nat Res Dev Magnetic storage system for electronic binary digital computers
US2623171A (en) * 1949-03-24 1952-12-23 Ibm Electronic divider
US2623115A (en) * 1949-03-24 1952-12-23 Ibm Electronic multiplier
US2634052A (en) * 1949-04-27 1953-04-07 Raytheon Mfg Co Diagnostic information monitoring system
US2652196A (en) * 1949-05-20 1953-09-15 Remington Rand Inc Wire recording storage mechanism for bookkeeping machines
US2810516A (en) * 1949-06-03 1957-10-22 Nat Res Dev Electronic digital computing devices
US2796218A (en) * 1949-06-22 1957-06-18 Nat Res Dev Electronic computing devices with subsidiary storage
US2777635A (en) * 1949-08-17 1957-01-15 Nat Res Dev Electronic digital computing machines
US2658670A (en) * 1949-08-31 1953-11-10 Rca Corp Rate determining device
US2615127A (en) * 1949-09-17 1952-10-21 Gen Electric Electronic comparator device
US2589465A (en) * 1949-10-22 1952-03-18 Eckert Mauchly Comp Corp Monitoring system
US2657856A (en) * 1949-11-15 1953-11-03 Gen Electric Number converter
US2764750A (en) * 1949-12-02 1956-09-25 Int Standard Electric Corp Arrangements for extracting information from electrical storage circuits
US2686632A (en) * 1950-01-04 1954-08-17 Nat Res Dev Digital computer
US2552629A (en) * 1950-01-11 1951-05-15 Bell Telephone Labor Inc Error-detecting and correcting system
US2641696A (en) * 1950-01-18 1953-06-09 Gen Electric Binary numbers comparator
US2749037A (en) * 1950-04-21 1956-06-05 George R Stibitz Electronic computer for multiplication
US2767908A (en) * 1950-08-18 1956-10-23 Nat Res Dev Electronic digital computing machines
US2757864A (en) * 1950-08-30 1956-08-07 Nat Res Dev Information translating apparatus
US2639859A (en) * 1950-11-29 1953-05-26 Rca Corp Transitory memory circuits
US2682574A (en) * 1952-03-29 1954-06-29 Rca Corp Electronic diplex transmitting distributor

Non-Patent Citations (11)

* Cited by examiner, † Cited by third party
Title
24 Digit Parallel Computer With Magnetic Drum Memory, 1949 *
A Functional Description of the Ed Vac, Nov. 1, 1949 *
Computing Instruments and Machines by D. R. Hartree 8 15 49 *
High Speed Computing Devices McGraw Hill Book Co. 7 28 50 *
How an Electronic Brain Works Radio Electric Magaz. July, 51 *
Mathematical Tables and Other Aids to Communication 4, 1950 *
Proc. of a Symposium of Large Scale Digital Calculating Machinery, 1948 *
Proc. of the Inst. of Elec. Engrs. Feb. 1951 *
Proc. of the Nat l Electronics Conf. Mar. 17, 1948 *
The Binac, Proceedings of the I.R.E. Jan. 1952 *
The EDSAC Mathematical Tables and Other Aids to Communication (MTAC) 1950 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4030074A (en) * 1974-06-03 1977-06-14 Centro Studi E Laboratori Telecomunicazioni System for checking two data processors operating in parallel
US6158857A (en) * 1999-04-29 2000-12-12 Hewlett-Packard Company Internal drum communication using a capacitor
US10252736B2 (en) * 2015-11-25 2019-04-09 Coordem Transport Tech. Co., Ltd. Method and system for controlling grade of automation of train operation

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