GB1003923A - Digital computing system - Google Patents
Digital computing systemInfo
- Publication number
- GB1003923A GB1003923A GB10005/62A GB1000562A GB1003923A GB 1003923 A GB1003923 A GB 1003923A GB 10005/62 A GB10005/62 A GB 10005/62A GB 1000562 A GB1000562 A GB 1000562A GB 1003923 A GB1003923 A GB 1003923A
- Authority
- GB
- United Kingdom
- Prior art keywords
- instruction
- memory
- digits
- control
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000006870 function Effects 0.000 abstract 5
- 239000011159 matrix material Substances 0.000 abstract 4
- 230000004044 response Effects 0.000 abstract 3
- 239000013256 coordination polymer Substances 0.000 abstract 1
- 230000001419 dependent effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 abstract 1
- 238000000605 extraction Methods 0.000 abstract 1
- 239000003607 modifier Substances 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Complex Calculations (AREA)
- Hardware Redundancy (AREA)
Abstract
1,003,923. Electronic digital computers' SPERRY RAND CORPORATION. March 15' 1962 [March 24, 1961], No. 10005/62. Headings G4A and G4C. An electronic computing system comprises a plurality of computers, a common memory, a plurality of input-output units for feeding data to and receiving data from the memory, and an input-output processor effective to control by a programme the exchange of data between the memory and the several input-output units in accordance with predetermined priorities for the input-output units. General arrangement, Fig. 1.-The system described comprises digital computers 1-10, 1-11, an input-output section 1-12 which may comprise high-speed, medium speed and low speed I/O devices, such as magnetic drums, magnetic tape and printers respectively; an input-output processor comprising a central processor 1-14 generally similar to the computers 1-10, 1-11 but adapted to control the exchange of data between the I/O apparatus and a magnetic core matrix memory 1-15 common to all the elements of the system, the I/O processor also comprising a dispatcher 1-13 which includes I/O device priority circuits, conventional I/O buffer stores and address modifying circuits arranged to control the extraction of data and placing of data in sequential locations in the memory. The various components are arranged to address the memory 1-15 on a multiplex basis, the system operation being divided for this purpose into minor cycles of eight ¢ Ás time slots t0-t7, the computer 1-10 for instance addressing the memory only in time slots t0, t5. The memory is divided into 39 memory units, each unit comprising a core matrix such as is disclosed in Specification 769,384, and if a given unit is being addressed it is one minor cycle before it can be addressed again. Each memory unit includes a component priority circuit arranged to give priority to the various components in the order: (1) Dispatcher 1-13, (2) Central processor 1-14, (3) Computers 1-10, 1-11. Codes employed.-The system employs two codes: an " L " code in the central processor, and an " M " code in the memory. In the " M " code shown in Fig. 6, the decimal digits 0-9 are represented in a 5-bit " biquinary " type code of which bit 5 is a combined parity check and odd/even indicator. Bit 4 is a weighted bit, 0 for 0-4 and 1 for 5-9, and bits 1-3 are non-weighted but their components for digits 0-4 are the same as those for 5-9. The " L " code is another similar 5-bit code. An instruction word is of the form IINNNNNMMMMM (12 digits) where digits II represent a function and the digits N, M represent two respective memory addresses, the N digits also being capable of identifying particular I/O devices. System memory.-The memory, Fig. 2, comprises 39 3-dimensional matrix core units arranged in 10 cabinets and has a capacity of 97,500 words. To select a given storage address, the address digits are decoded in a memory address decoder (Figs. 4A-B, 8, not shown) to provide (1) a unit select signal on one of 39 unit select lines to select a particular memory unit and (2) X and Y address signals to select the word in the particular unit. The address digits are obtained either from the N or M digits of an instruction or from the address modifier circuits of the dispatcher 1-13 or from the control counter of the central processor 1-14 or from the control circuits of the computers 1-10, 1-11. In the operation of the memory both for reading and for writing, the memory goes through a read-write cycle, whereby the data contained in an address location interrogated is cleared or read out and new data or the old data is entered into the location. The memory control and priority circuits (Figs. 9A-C, not shown) include for each unit an interlock flip-flop adapted to prevent access to that unit when it is busy. Also included for each unit are interlock flipflops to control the access priorities of the inputoutput equipment and the central processor, the former having the greater priority. Central processor, Figs. 10, 10B.-This is a general-purpose stored-programme computer arranged to control the operation of the inputoutput devices and the dispatcher. The processor can perform various types of instruction: " book-keeping orders," " summary orders," " input-output instructions." A summary order is one delivered by a computer to the central processor where it is tested using the bookkeeping orders. In response to these tests, control is transferred to a particular sequence of central processor instructions. However, a sequence of instructions may be left and later rejoined at the same point. The central processor comprises various control and timing circuits, an arithmetic unit 10-41, instruction registers IR1, IR2 and temporary storage registers RP1, RP2. The " book-keeping orders " include " skip " (i.e. proceed to next instruction), " shift," " add," " subtract," conditional and unconditional transfer of control and various data transfer instructions for transferring data between the memory and the registers RP-1, RP-2. A high speed read bus HSB-R is adapted to carry information read from the memory 1-15, Fig. 1, either to the 1-word instruction register IR2, 10-11 via gates 10-10 if the information read out is an instruction, or to registers RP-1 or RP-2 if the information represents an operand, via gates 10-25 or 10-24 respectively. An instruction entered into the register IR2 is subsequently transferred to the register IB1, where the flipflops which register the two instruction function digits II are connected to an instruction decoder 10-17 (Figs. 12, 12A, not shown) comprising a gating matrix which produces a signal on a single output line, the particular line effective being also dependent on the output of a programme counter 10-19 (Fig. 16, not shown) adapted to cause to be generated various function table signals for instructions requiring a plurality of steps. The decoder 10-17 is connected to an instruction encoder 10-18 which produces a different set of output function table signals FT for each input from the instruction encoder 10-17, the FT signals being employed to control the various operations in the processor, dispatcher and drum and tape units. The " M " and " N " digits of the instruction in the register IR1 are transmitted in turn via " or " gates 3-31 to the memory address decoder 10-64, the " N " digits being also capable of addressing other items of equipment over connections not shown. The control counter 10-35 serves to address the memory for instructions to be executed by the central processor, and is normally stepped in response to a signal from the instruction cycle control 10-22, but in operations requiring a transfer of control, the normal sequence may be altered by transferring the " M " digits of the instruction in the register IR2 to the control counter 10-35 via gates 10-37. The contents of the control counter 10-35 can be transferred to the memory, if this is required, via gates 10-36. Thus, in a " return jump " instruction, the " M " digits sorted in the register IR1 are transferred to the control counter 10-35, the 5-digits contents of which are stored in the address designated by the " N " digits of the instruction. The remaining seven most significant digits are derived from a register 10-38 which stores the digits 0500000, the " 05 " function digits of the instruction thus formed, denoting the unconditional transfer instruction. Data paths.-The data read from the memory in response to an instruction in the register IR1 is transferred via the bus HSB-R either to register RP1 or to register RP2 from which data may be transferred back to the memory, or, via gates 10-47, 10-48, 10-65 to the addercomparator 10-41. The adder-comparator 10-41 (Figs. 18-25, not shown) produces sum or difference signals and also, on lines FC, EQ during a comparison operation signals indicating that the content of RP1 is greater than that of RP2 or that the contents are equal, respectively. These signals cause recomplementing of the result if this is required. The arithmetic control circuits 10-42 (Fig. 27, not shown) are also supplied with the content of the registers RP1, RP2 and produce a CP signal applied to the adder-comparator 10-41 and adapted to control addition or subtraction according to the signs of the contents of the registers RP1, RP2. Performance of instructions.-The instruction cycle control circuit 10-22 (Fig. 11, not shown) causes the performance of instructions in three steps: (1) the memory is addressed and the selected instruction stored in the register IR2, (2) the instruction is read into the register IR1, (3) the control counter 10-35 is stepped. The first instruction is selected by the control counter 10-35. Subsequently, the " M " and "N" portions of an instruction are given priority over the control counter in addressing the memory. The operation of the various components in the central processor is described in detail in the Specification, with reference to Figs. 11-28 (not shown). Book-keeping instructions.-The following thirteen central processor instructions are described in detail in the Specification, with reference to timing diagrams, Figs. 87-94 (not shown):- (i), (ii). The " 15 " and " 12 " instructions are effective to transfer data from the memory location specified by the " N " digits of the instruction to one of the registers RP1, RP2. (iii), (iv). The " 13 " and " 16 " instructions are effective to transfer the contents of the registers RP1 or RP2 to the memory location specified by the " N " digits of the instruction. (v). In the unconditional transfer instruction, " 05," the five " M " digits thereof are transferred to the control counter 10-35 and designate the address of the next instruction. (vi). In the return jump instruction, " 14," which has the form 14 NNNNNMMMMM, the five " M " digits are transferred to the control counter 10-35 and the contents of the c
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US98148A US3247488A (en) | 1961-03-24 | 1961-03-24 | Digital computing system |
DES78672A DE1190704B (en) | 1961-03-24 | 1962-03-26 | Computer system |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1003923A true GB1003923A (en) | 1965-09-08 |
Family
ID=25996819
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB10005/62A Expired GB1003923A (en) | 1961-03-24 | 1962-03-15 | Digital computing system |
Country Status (7)
Country | Link |
---|---|
US (1) | US3247488A (en) |
CH (1) | CH412410A (en) |
DE (1) | DE1190704B (en) |
FR (1) | FR1331378A (en) |
GB (1) | GB1003923A (en) |
NL (1) | NL276308A (en) |
SE (1) | SE303623B (en) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3323109A (en) * | 1963-12-30 | 1967-05-30 | North American Aviation Inc | Multiple computer-multiple memory system |
US3350689A (en) * | 1964-02-10 | 1967-10-31 | North American Aviation Inc | Multiple computer system |
US3346851A (en) * | 1964-07-08 | 1967-10-10 | Control Data Corp | Simultaneous multiprocessing computer system |
US3426330A (en) * | 1966-02-14 | 1969-02-04 | Burroughs Corp | Central data processor |
US3416139A (en) * | 1966-02-14 | 1968-12-10 | Burroughs Corp | Interface control module for modular computer system and plural peripheral devices |
US3432813A (en) * | 1966-04-19 | 1969-03-11 | Ibm | Apparatus for control of a plurality of peripheral devices |
US3462741A (en) * | 1966-07-25 | 1969-08-19 | Ibm | Automatic control of peripheral processors |
US3421150A (en) * | 1966-08-26 | 1969-01-07 | Sperry Rand Corp | Multiprocessor interrupt directory |
US3480914A (en) * | 1967-01-03 | 1969-11-25 | Ibm | Control mechanism for a multi-processor computing system |
US3430201A (en) * | 1967-06-16 | 1969-02-25 | Cutler Hammer Inc | Extending pulse rate multiplication capability of system that includes general purpose computer and hardwired pulse rate multiplier of limited capacity |
US3521238A (en) * | 1967-07-13 | 1970-07-21 | Honeywell Inc | Multi-processor computing apparatus |
US3533073A (en) * | 1967-09-12 | 1970-10-06 | Automatic Elect Lab | Digital control and memory arrangement,particularly for a communication switching system |
US3702462A (en) * | 1967-10-26 | 1972-11-07 | Delaware Sds Inc | Computer input-output system |
US3569943A (en) * | 1969-04-02 | 1971-03-09 | Ibm | Variable speed line adapter |
US4156907A (en) * | 1977-03-02 | 1979-05-29 | Burroughs Corporation | Data communications subsystem |
US5010476A (en) * | 1986-06-20 | 1991-04-23 | International Business Machines Corporation | Time multiplexed system for tightly coupling pipelined processors to separate shared instruction and data storage units |
EP0312764A3 (en) * | 1987-10-19 | 1991-04-10 | International Business Machines Corporation | A data processor having multiple execution units for processing plural classes of instructions in parallel |
JP4587756B2 (en) * | 2004-09-21 | 2010-11-24 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit device |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2840705A (en) * | 1954-11-26 | 1958-06-24 | Monroe Calculating Machine | Sequential selection means |
US3201762A (en) * | 1957-01-25 | 1965-08-17 | Honeywell Inc | Electrical data processing apparatus |
US3048333A (en) * | 1957-12-26 | 1962-08-07 | Ibm | Fast multiply apparatus in an electronic digital computer |
US3117306A (en) * | 1958-02-17 | 1964-01-07 | Ibm | Multiplex computer inquiry stations |
US3029414A (en) * | 1958-08-11 | 1962-04-10 | Honeywell Regulator Co | Information handling apparatus |
US3061192A (en) * | 1958-08-18 | 1962-10-30 | Sylvania Electric Prod | Data processing system |
-
0
- NL NL276308D patent/NL276308A/xx unknown
-
1961
- 1961-03-24 US US98148A patent/US3247488A/en not_active Expired - Lifetime
-
1962
- 1962-03-15 GB GB10005/62A patent/GB1003923A/en not_active Expired
- 1962-03-22 FR FR891885A patent/FR1331378A/en not_active Expired
- 1962-03-22 SE SE3220/62A patent/SE303623B/xx unknown
- 1962-03-23 CH CH346162A patent/CH412410A/en unknown
- 1962-03-26 DE DES78672A patent/DE1190704B/en active Pending
Also Published As
Publication number | Publication date |
---|---|
FR1331378A (en) | 1963-07-05 |
SE303623B (en) | 1968-09-02 |
DE1190704B (en) | 1965-04-08 |
CH412410A (en) | 1966-04-30 |
NL276308A (en) | |
US3247488A (en) | 1966-04-19 |
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