DE1190704B - Computer system - Google Patents

Description

FEDERAL REPUBLIC OF GERMANY GERMAN MfWOk PATENT OFFICE

EDITORIAL

Int. CL:

G06f

-ν-4Λ "

German class: 42 m-14

Number: 1190 704 * S

File number: S 78672IX c / 42 m

Filing date: March 26, 1962

Opening day: April 8, 1965

The aim of the invention is to use known computing systems which carry out internal data transfers and perform the arithmetic operations at high speeds with the aim of improving their To expand the scope for action. According to the invention provides in a computing system with a Memory with several addressable word storage locations in which at least one computer is used for the purpose of exchanging information communicates with the memory and several different input and output devices are provided that can exchange information with the memory, a monitoring control center independent of the individual computers specific instructions for the information exchange with the memory for the various input and output devices. This monitoring control center is direct to the memory as well as to a computer via a signal device connected, which can be set by the computer after this has transferred a keyword into a given memory location, and which from time to time by the control center is checked, which takes effect on a setting state of the signaling device, to get an instruction and word data from memory as they are there in successive Addresses were accommodated by the computer. The invention enables the traffic relationships of a shared memory and the To regulate input and output devices independently of the computers, so that they can be and dispensing operations are not affected. The supervisory control center according to the invention is also capable of the traffic relations between the common memory and the individual To regulate computers. In this case, a time-shifted traffic option can preferably be used for each the computer pass, d. that is, each of the computers and the input and output system can periodically for short, but different periods of time associated with the shared memory for each unit so that the facilities work together according to a time division multiplex system.

The invention makes it possible to use a new and effective priority system, on the one hand for regulating the priority of the connections between the memory and the computers and the input and output system and on the other hand to regulate the priority of the connections between the individual input and output devices and the memory.

The interconnection of several computers with a computer system

Applicant:

Sperry Rand Corporation, New York, N.Y.

(V. St. A.)

Representative:

Dipl.-Ing. E. Weintraud, patent attorney,

Frankfurt / M., Mainzer Landstr. 136-142

Named as inventor:
Herbert Frazer Welsh, Philadelphia, Pa .;
John Presper Eckert, Jr., Gladwyne, Pa .;
William F. Schmitt, Wayne, Pa. (V. St. A.)

a common memory in a computing system according to the invention allows that of the input devices introduced information into the memory and from the output devices Information can be taken out of the memory without going into the individual Computers running program needs to be interrupted.

The invention also enables a common input-output control system for monitoring the activity of all input and output devices, thereby increasing the training the individual input-output synchronization devices is simplified and the computer of the System are only burdened to a small extent.

According to the invention, it is possible with particular advantage that one of the computers controls the input and output apparatus of the system depending on control commands from another computer.

Some embodiments of the invention are shown in the drawings.

Further details of the present invention will become apparent from the following description in conjunction visible with the drawings. It shows

F i g. 1 is a simplified block diagram illustrating the organizational structure in accordance with the present Invention represents

F i g. Figure 2 is a simplified block diagram of the general one used in accordance with the invention Memory,

Fig. 3 is a diagram from which the OR circuits routed input signals for the storage

509 533/373

cheradressen decryption device can be seen are,

4, 4A and 4B show the logical connection the unit selection part of the memory address decryption device,

F i g. Figure 5 shows the format of the central processing facility according to the present invention used command word,

F i g. 6 is a tabular representation of a five digit used in accordance with the present invention Binary codes,

Fig. 6A those used in the present invention Symbols for the AND circuits,

Fig. 7 shows the structure of the invention Words used by others,

8 shows the logical link for the selection of the; c-y coordinates in the memory,

Figures 9, 9A, 9B and 9C illustrate the logical network the storage control unit including the priority circuits for the storage,

10 and 10B show a block diagram of the central processing system,

Figure 10A is a more detailed block diagram of a Command register I in FIG. 10,

11 is a detailed block diagram of the control unit for the command period in FIG. 10,

Fig. HA and HB diagrams from which the Timing for the various signals in the control circuits for the command period in FIG. 11 can be seen

12 is a detailed block diagram of the instruction decryption and encoder in Fig. 10,

Figure 12A is a detailed diagram of a portion the command decryption and coding device in FIG. 12,

F i g. 13 and 13 A part of the command register I, which is used as a counter,

14A is a block diagram of one of the registers (RP1) of the central processing system,

14B is a block diagram of a further register (RP 2) of the central processing system,

14C shows a detailed view of the individual memory elements for the memory in FIG 14A and 14B with the corresponding control elements,

14D is a simplified block diagram of a used in the circuits in Figs. 14A and 14B Shift register,

14E is a time chart showing the Timing of the signal pulses shifted by the shift register in Fig. 14D,

F i g. 15 the block diagram of the clock generator, dei the clock pulses for the modules of the entire system delivers,

16 shows the program counter of the central processing system,

17 shows a bistable flip-flop circuit which responds to the sign or the value of the sign position of a machine word stored in the register RP1 or RP 2 of the central processing system,

18 shows a first input circuit for the Adding comparison unit of the central processing system,

19 shows a second input circuit for the adding and comparing unit of the central processing system,

F i g. 20 the circuit for bridging the adder,

F i g. 21 a part of the adder including the device for forming the complement to one of the operands,

F i g. 22 the circuit arrangement for introduction the parity bit for the adder,

23 and 23A the comparison work of the central Processing system as well as the input circuit of the result circuits,

24 the adder which controls the input circuit of the result circuits,

25 shows the result circuit arrangement,

F i g. 26 the carry network for the adder and the signal generator for the complement signal,

F i g. 27 the bistable complement circuit,

F i g. 28 the network for generating the jump signals (CT),

28A shows the chain of AND and OR circuits for performing the main test or the 99 loop tests for the input and output synchronization devices,

28B is a simplified flow diagram of the program control loop;

F i g. 29 is a block diagram of the distributor;

F i g. 30 the logical connection of the priority circuits for the synchronization device 1,

31 shows the logical connection of the priority circuits for the synchronizer 2,

Fig. 32 the logical connection of the address and buffer controls for the synchronizing device 1,

F i g. 33 the logical combination of the addresses ^ and buffer controls for the synchronizing device 2,

Fig. 34 the logical connection of the address and buffer controls for the synchronizing device 3,

F i g. 35 is a diagram of the address register;

Fig. 36 is a logic diagram of the address transfer control,

37 shows the logical connection of the address change control and their connection to the address change facility,

F i g. 38 shows the logical arrangement of the signal control for address inhibition and for reading the memory,

39 is a diagram of the input buffer registers;

Fig. 40 is a diagram of the output buffer registers;

F i g. 41 is a diagram showing the timing of the various signals in the distributor,

Fig.42 is a simplified block diagram of the inventive magnetic head control for a the magnetic drums,

F i g. 43 is an illustration of the drum information tapes;

F i g. 44 a schematic view of the control unit assigned to the magnetic head control in FIG. 42,

F i g. 45 and 46 are a schematic view of one of the drum read synchronizers;

F i g. 47 a simplified representation of the circuits for switching the magnetic heads for the drums,

5 6

F i g. 48, 49 and 50 a schematic representation (Ä input) opposite and with this on

the synchronizer for writing on the same side of the block.

the drum, usually requires a bistable toggle switch

51 to 54 are a simplified flowchart for setting or resetting a time which of the program for the magnetic head control on the 5 corresponds to a pulse length. So receives the tilting

Drums, a setting input signal during a circuit

F i g. 55 to 58 is a simplified pulse length flowchart, it becomes its setting output

of a characteristic drum reading program, generated during the next pulse duration. Will

59 to 71 are a schematic view of the flip-flop, for example, set by the clock pulse magnetic tape synchronization device, io t ₂ , so the output signal appears on

F i g. 72 and 73 a schematic view of a setting output only at time t _z . typical magnetic tape recorder, _,. . ,. _,. ,

74 to 86 show a simplified flow chart of the organizational structure of the system

of a typical program for writing to tape, FIG. 1 shows a greatly simplified block slide diagram. 87 is a timing diagram from which the commands 15 grams, from which the present invention for transmitting and reading data is clearly based on the main works and their connection, fertilize can be seen. As the figure F i g. 88 a timing diagram showing the commands, the invention can consist of the following modules for transferring and writing data: a first and a second digital light are, 20 computers 1-10 and 1-11 with stored Pro-Fig. 89A and 89B timing diagrams, from which grams, an input and output part 1-12 with a sequence of the shift can be seen, number of input and output devices for ver-F i g. 90 is a time diagram showing a first indistinguishable working speed and the assigned jump command, assigned to synchronizing devices, a one-fig. 91 is a time diagram showing a second 25 and output distributor 1-13 for control and co-ordinate jump command, determining the operation of the input and output part. and subtraction commands can be seen. The central processing system alone already represents FIG. 93 is a timing diagram showing the two clubs, complete digital computers with stored equal commands that cause a jump, 30 program that controls the operation of the in and out. 94 a time diagram from which the dispensing part 1-12 can be seen both directly from the control unit of the acceptance command from the central processing system and indirectly from FIGS. 95A, 95B and 95C a block diagram monitors via the distributor. All of these works of one of the arithmetic units that receive their information in the overall system are used by a common storage unit 1-15, which is connected to the two arithmetic units. 96 a block diagram of the command keys 1-10 and 1-11, the central processing and coding device for the computer system 1-14 as well as with the input and output parts and 1-12 via the distributor 1-13 with the help of the main F i g. 97 is a block diagram connecting a portion of the "read" and "write" lead function control circuits 95 through 148 in FIGS. 95C 40 1-16 and 1-17. All works are shown, in particular the arithmetic unit cycle as well as the sensors 1-18 synchronized by the clock pulse generator or the clock control elements 96 to 214 in FIG. 96. This known per se; In the description of the drawings, a clock generator 1-18 generates a two-part number system every 4 microseconds, whereby the pulse of half a microsecond length on the number to the left of the hyphen denotes the number of the 45 of each of the eight connected lines after a drawing, while the number right other. These pulses, which are referred to in the drawing as the relevant component in the drawing clock pulses T ₀ to T ₇ , are the indicates. For example, B. the two-part number supplied to different plants in the system to 1-2 on drawing 1, component 2; 3-4 refers to ensuring synchronized operation. Drawing 3, component 4, etc. 50 Before FIG. 1 is described in detail, it should be noted that the symbols used below indicate that the information flow paths are indicated by a crescent moon with a drawn in by thick black lines, while the point is an AND circuit. An OR circuit rend the control paths appear as thinner lines, is also represented by a crescent, but with these control paths in reality a or a drawn plus sign. 55 can comprise several signal lines. Blocking or NO circuits are like AND- For the control of the electronic computer is shown in circuits, except that the blocking inputs are primarily responsible for the central processing system 1-14 at their connection points on the relevant Sym-. This plant works with the verbol having small circles. Bistable flip-flops 1-13 together to form a continuous gene or so-called flip-flops are represented by the 60 or almost continuous data flow between the abbreviation FF ; a setting or return input and output part 1-12 and the storage unit control output signal always occurs to ensure a bistable 1-15. The central processing toggle switch on when this has been set or back system receives rudimentary input and output commands. The setting output signal comes from one of the arithmetic units 1-10 or 1-11, analyzing the setting input (^ input) and interprets these instructions and then issues specific commands that are at the same level as these the relevant single page of the block. The reset output and output devices. The central processing signal occurs, however, at the the reset input processing system also monitors the operation of the

various input and output devices, determines their current status, saves this information and, if necessary, issues commands for further operation. For this purpose, each arithmetic unit contains a bistable announcement flip-flop (DFF); however, only one of these flip-flops is shown at 1-11A in FIG. This announcement toggle switch is always switched to its setting state by the associated arithmetic unit 1-11 when the arithmetic unit has a group of input and output commands ready for further processing. The announcement flip-flop is repeatedly scanned by the central processing system 1-14 via the gate circuit 1-185. If an output signal appears at this gate circuit as a result of the setting of the bistable announcement flip-flop, the central processing system searches for a predetermined memory location in which the arithmetic unit has stored the addressed memory locations of a number of input and output commands. The announcement toggle switch (DFF) is then switched to its reset state by the central processing system via line 1-11C. The central processing system then begins to process the input and output commands in sequence.

Although all plants used a common memory, the simultaneous operation of the various works with the help of a new and extremely effective multiple system, which is described in detail further below. The memory itself is preferably a Memory with any access, with an access time of 4 microseconds. In other words, the time between a call from one of the factories to the store and the receipt of the desired information from memory takes 4 microseconds. This time is called "small cycle" designated. The flow of information to and from the memory takes place in words of 60 bits each Length. These 60 information units are divided into five bits per digit, each word being made up consists of twelve digits. The transfer of the 60 information units of a word to and from memory takes place in parallel in the period in which one of the eight pulses of half a microsecond Length is generated by the clock 1-18.

Each of the two arithmetic units 1-10 and 1-11 represents a self-contained electronic digital computer, which includes the following components known in the art: a control counter for taking commands from the memory in a certain order, a static register for recording the commands taken from the memory, decoding and coding function tables for generating function signals depending on the instructions stored in the static register, as well as a program counter that is controlled by the information contained in the static register to automatically perform a series of operations on the computer to have carried out. In addition, each arithmetic unit can contain suitable arithmetic circuits which are fed both with the data taken from the memory and with the data of a number of internal buffers. The choice of whether this data is to be taken from the memory or the intermediate memory naturally depends on the instruction stored in the static register. Furthermore, each arithmetic unit contains a clock control which essentially monitors the cycle of the arithmetic operations and the order in which the individual arithmetic operations are carried out. For example, the clock device has the task of setting the control unit of the computer so that the computer first calls up a command from the memory, then accepts this command, then takes the required operands again from the memory and finally executes the command that has been removed. Once the command has been carried out, the clock circuit naturally starts the cycle of the arithmetic operations again. In general, the timing device causes the computation processes to run as a function of two processes: One process occurs when the computer has almost carried out a specific command. The signal that arises at this point in time is generally referred to as the "end pulse" (Ep) . The other process on which the execution of the computation depends is the notification that the memory circuits are free. The signal generated at this point is called the »memory free signal« (MNB). The two computers are generally completely independent of one another and only have one common memory.

The input and output processing device (IOP) shown in the drawing consists of two main units: the central processing system 1-14 and the distributor 1-13. The central processing system can be regarded as a complete computer which is able to process the information taken from the memory and which contains circuits which are similar to the circuits described in connection with the arithmetic unit. The main task of the central processing system, however, is to control the input and output devices that deliver the information to the memory or receive it from it. When controlling these input and output devices, the central processing system must perform numerous known arithmetic operations, e.g. B. Adding, subtracting, comparing, etc. The control or function table signals generated by the central processing system not only control the control unit and the computing circuits of the central processing system, but are also the distributor 1-13 and the input and output parts 1-12 at the same time in order to directly control the input and output devices, such as tape devices, storage drums, printing devices, etc. in this way. For this purpose, the central processing system takes instructions and data from the memory essentially in the same way as the arithmetic units.

The distributor contains three separate devices: the input and output buffers, the priority circuits for the input and output devices and the address changing circuitry. the Input and output buffers connect the

6g input and output devices with the memory 1-15 via the read and write main lines 1-16 and 1-17. The buffers have the task, known per se, in particular, which is carried out by an input

and output device at a certain speed incoming information with a forward other speed to the memory. The buffers received from a certain input and output devices the information units belonging to an information word one after the other and then feed the entire word to the memory in parallel.

Conversely, an information word is fed in parallel from the memory to the buffers (60 information units), which they then transfer to the input and output devices assigned to them in Forward series. Each input and output device is controlled by suitable synchronizing devices controlled, each synchronizer having its own group of input and output buffers assigned. These synchronizers represent the connection by means of one input and output device (tape device, magnetic drum, etc.) to a buffer connected. For example, the high-speed synchronization device controls the flow of information between the quick input and output devices (magnetic drum) and the input and output devices assigned to them and output buffer. The medium-speed synchronizer monitors the transmission of information between the medium-speed input and output devices and their input and Output buffers and the slow synchronizer ultimately controls the flow of information between the low-speed input and output devices (High-speed printing devices, etc.) and the intermediate storage devices assigned to these input and output devices.

The priority circuits shown in the distributor determine which synchronization device has access to get memory 1-15. Hold z. B. the magnetic drum and the magnetic tape information ready for the memory, the priority circuit determines which of the two devices comes first Should have access to the memory. The priority circuits are arranged so that the device which forwards the information fastest takes precedence over all other devices receives.

Note that the block that the various synchronizers and Input and output devices on the drawing reproduces, is a simplified representation. In practice, several quick synchronizers can be provided, which upon receipt a number of magnetic drums in each case from corresponding instructions from the central processing system can control. Several medium-speed synchronizers can also be used in practice be provided, each controlling a number of magnetic tape devices. The priority circuits not only decide on the basis of the speed with which the information is transmitted which device is given preferential access to the memory, but they can also be arbitrary determine which synchronizer of the same speed class has priority over the other synchronizers of the same class.

As a final device, the switch 1-13 includes the address change circuitry. These circuits generally work like a tax meter; so they initiate the extraction of words successive storage locations in the memory to these words to the input and output devices such as magnetic tapes, magnetic drums and the like. In the same way, these circuits cause that the information words coming from the input and output devices in series in stored in the memory. In normal

ίο Operation is the one for the removal or for the storage starting address provided by information by the address changing circuitry provided by the central processing facility. As mentioned earlier, it is the memory shown in Fig. 1 to a memory with any access. Each of the initially Works described is designed so that it can control the memory and give it information can feed. The data from and

ao is transferred to memory via the read and write main lines 1-16 and 1-17, while the Address for this information via a group specially designated as "address lines" is coupled by lines 20 to the memory.

The various plants can have access to the storage facility during the various predetermined time intervals of the small period of the plant. This is done by connecting the address lines 1-20 from the respective plants to the memory 15 via the individual gate circuits 1-10 E, 1-11E, 1-13 E and 1-14 £. For example, the first arithmetic unit controls the memory via gate 1-10 E at times t ₀ and t ₅ ; the second arithmetic unit performs this control via the gate 1-11E at times t _x and t _t , the central processing system 1-14 at time t ₇ via gate 1-14 E and the distributor 1-13 at times t ₂ and t ₆ via gate 1-13E. As soon as one of the arithmetic units, the central processing system or the distributor sends a request to the memory, the memory circuits generate a memory-free signal (MNB) to indicate that access to the memory is free. This memory-free signal arrives via the corresponding gate 10F, UF, 13 F or 14 F to the plant from which the request to the memory was made, since the memory-free line through the gates 1OF, UF, 13F and 14 F is only switched on when the clock signal is present at the relevant gate. The first arithmetic unit receives the memory-free signal only at times t ₂ and t _v, the second arithmetic unit only at times t ₃ and t ₆ , the distributor only at times t _i and i ₀ and the central processing system only at Time t _v The address circuits including the address lines 20 and the memory-free circuits with their lines 21 are subject to a delay which corresponds to the length of a pulse; so if the first arithmetic unit at time t ₀

directs a request to the memory, it receives the memory-free pulse at time t ₂ . The gate 1-10 F connected to the memory-free line of the first arithmetic unit is the only gate that is open at this time; the memory-free pulse is thus only fed to this first arithmetic unit, where it causes the clock control assigned to the computer to control the sequence of operations of the arithmetic unit. Has a similar effect

5tt9 538/373

the memory free signal when it works the other is fed.

As will be described in detail further below, the memory contains a number (39) of memory units, each of which has a memory capacity of 2500 words. In a preferred embodiment of such a memory, each memory unit consists of an arrangement of memory matrices known per se. Each memory unit contains 65 levels, with one level each being provided for the individual information units of a word, which consists of a core matrix 50 × 50. If a certain memory unit is activated, a small period (eight pulse lengths or 4 microseconds) elapses before this unit can be activated again. Controls e.g. If, for example, the first arithmetic unit sends a certain storage unit at time t _{t of} a certain small period, the same storage unit can neither be controlled by this arithmetic unit nor by another unit of the system during the following eight pulse lengths or 4 microseconds. In contrast, different storage units can be reached during successive time intervals in the same short period. In the case just described, a second movement that controls the same memory unit at the same point in time would not receive a memory-free signal. The absence of this memory-free signal would indicate to this second work that the activated memory unit is not free.

The memory circuits contain a factory priority circuit for each memory unit, the regulates the sequence of connection to this memory unit. The priority circuit is set up in such a way that that it connects the individual plants of the system to the memory in the following order: Distributor, central processing system, first and second arithmetic unit. The priority circuit works basically as follows: Does the distributor control a certain storage unit and is this unit not free, the process in which this memory unit is involved is first ended is. After completion of this process, however, due to the priority switching, initially neither an arithmetic unit nor the central processing system get access to the memory. Much more the distributor has priority and can now control this storage unit. On the other hand, the Storage unit 1 just queried by the first arithmetic unit and at the same time from the distributor and controlled by the central processing plant, the distributor receives access to the next plant Storage unit 1, even if the first arithmetic unit and the central processing system continue to control the storage unit 1 try.

Storage and decryption facility
for the memory addresses

After the description of the general structure of the system that has just been made, this will now be first main work, the memory and the decryption device for the memory addresses described. Before describing the memory, however, it is useful to make a few considerations about the commands used by the central processing plant as well as that used in the present plant To employ encryption procedures. In this connection, reference is made to FIG. 5 and 6 referenced, the structure of a command word for the central processing system as well as the numerical and digital coding techniques used in the present memory, respectively. The one shown here Code was chosen arbitrarily, of course, and can be used at various points in the overall system converted to any other code by suitable code conversion devices will. Like F i g. 6 shows, some form of biquinary code is used in memory, where a decimal digit is expressed by five information units or bits. The fifth Bit has the double task of a check bit and an even-odd display. Is the The fifth information unit is a "1", which indicates that the relevant decimal number is odd, while a "0" in the fifth place of the coded digit corresponds to an even decimal digit indicates. In addition, the »1« appearing in the fifth position is used as a check bit by inserting the Total number of all ones contained in a coded decimal digit due to this check bit odd is made. In this way, any test method known per se can be used to to check the individual coded decimal digits whether they contain one bit too many or too little. The fourth Bit is the only unit of information in the coded decimal digit that is evaluated. Occurs at this If you put a "1" on, this means that the decimal value of the coded digit is 5 or greater. the first three bits form the quinary part of the code and are corresponding to that shown in the figure Format chosen arbitrarily. However, the quinary part of the code is in the range of decimals 5 symmetrical insofar as the quinary part of the decimals 5 of the decimals 0 and, analogously, the quinary Part of the decimals 1 corresponds to the decimals 6, and so on.

As FIG. 5 shows, a command word consists of twelve decimal digits of five information units each. The eleventh and twelfth digits are particularly important here, as they are the actual command formation and thus control the operation to be performed. The digits from the sixth to to the tenth decimal place - in the drawing with iV - can be used, among other things, to identify the address of a memory location. The N digits are also used to denote certain input and output devices and select synchronizers which are involved in an input and output operation, i. H. in the Input of information about the memory or when outputting information about the input and output device, are to be used. Similarly, the decimal digits shown as M digits in the drawing are used 1 to 5 of the command word to identify a second memory address.

F i g. 2 shows a simplified diagram from which the general structure of the memory can be seen. As can be seen from this figure, the memory has a capacity of 97,500 words. These words are accommodated in 39 memory units of the same size, with each memory unit 2500 words which are stored in cores in the half-current process known per se. The type of winding the kernels are also already known. The following wires run through each core: an X-wire

13 14

"or row wire, a Y-wire or column wire, N-digits of the command word. CC ₂₅ corresponds to a Z-wire or locking wire and finally a 25th bit of the control counter of the central processing read rotates. The memory arrangement consists of system, and SMS ₂₅ corresponds to the 25th bit of the address 60 level, namely one level for each information register in the distribution circuits can also about the latch chain einjede column 50 includes memory cores. a memory are fed, these addresses are g in F i. 3 designated unit corresponds with a capacity of 2500 words C ^ _25th the digits therefore the portion of a container 60 levels with 50 columns for each drawing, such as P ₂₅ , etc., denote the 50 cores.10 position of a bit belonging to the five digits in

As shown in FIG. 2 includes the memory address signal. In other words: the information

cheinheit 1 correspond to the storage locations 00000 to 02499. tion units P ₂₅ to P _{21 inclusive}

The memory unit 2 accordingly includes the fifth digit or D _{5 of} the address signal. P ₂₀

Storage locations 02500 to 04999 etc. All 39 storage locations up to P ₁₆ correspond to the fourth digit or D _{4 of} the storage locations are housed in ten cabinets. 15 address, P ₁₅ to P ₁₁ correspond to the third digit

With the exception of the last cabinet, in each or D ₃ , P ₁₀ to P ₆ correspond to the second digit

Cabinet accommodates four storage units. The or D ₃ , and P ₅ to P ₁ finally correspond to

Storage locations are thus distributed over the barrier, first digit or D _{1 of} the address. In other words

that cabinet no. 0 the first 10,000 words, cabinet th: The digit D ₁ is the ones place, D _{2 is} the tens

No. 1 stores the next 10,000 words, etc. 20 digits, D ₃ the hundreds digit, D ₄ the thousands digit

can. The last cupboard contains only three memory and D ₅ the ten thousand digit of the address,

units and thus the storage locations for the words in the inset from FIG. 4 corresponding

The order from 90000 to 97499th order in Figures 4A and 4B shows a logical one

Since a total of 97500 words in the memory circuit for the part of the memory address de-

can be brought, is a key device for the control 25, which allows the selection of the storage

a five-digit decimal number for each memory location. Before describing this

(25 information units) required. As is still the case, it seems appropriate to begin with the circuit

Described below, the five digit designation can be used here and in other drawings

far from this number either from the M or from the appearing signals. The entrance

N digits of a command word of the address signals of the gate circuits are overlined

Change circuits in the distributor (SMS), from or not overlined designations.

Tax counter (CC) of the central processing. B. in Fig. 6A, the gate circuit 6-1 a

plant or from the tail unit of one of the two AND circuits, whose input signals from a

Arithmetic units are derived. P3c signal (Px overlined ) and a Py signal

In order to now select a certain memory location (Py not overlined) exist. The gate circuit len, the address digits of a word in the is opened when both input signals have the level prescribed by the memories as described below; this is the case when the Px signal is a binary "0" and that is the case. This decryption process is used to make Signal Py represent a binary "1". In other words, at first a memory unit selection signal pushes a 4 °: If the signal Px is not present, then the signal Tx to be connected to the 39 memory unit selection lines is present, and vice versa. From a logical point of view, the gate circuit 6-1 of the gate circuit 6-2 selects and, secondly, X and Y address signals which represent a NO circuit, in which the input is to be provided, in order to thus be within the relevant output signal Px acts as a lock. In this case, the memory unit will receive access to a specific word 45 the gate circuit 6-2 if Py = I and memory location. The memory addresses - Px = O. If an AND gate circuit decryption device is used at this point, thus consisting of two, the input signal Tx can be divided with the help of: the part for selecting the memory unit of a conversion device from the Px line (FIGS. 4A and 4B) and the part for the XY- Selection to be derived. So z. B. the address shown in Fig. 4A (Fig. 8). Both parts of the memory 50 assume that the input signal P 24 received for the gate circuits 4-41 is derived from the input signal P _{24 which is} seen by one of the above-described processing devices, which are connected to the line devices connected to the decryption device. P ₂₄ in Fig. 3 is connected. To simplify the device with the aid of the chain of the description shown in Fig. 3, such conversion buffers are switched on. 55 facilities, however, not shown. Rather, as shown in FIG. 3, the corresponding indexes of the gate circuits are drawn as in FIG. 6 with 6-1 or formation units from one of the above-described 6-2, with correspondingly swept over devices by assigned buffer or not swept over designations fed to the one ^u , z. B. by the buffer 3-31, input signals are used to identify them in order to provide the corresponding P bits that are used to describe the selection of a word from when selecting the memory location to be controlled in a memory unit in a specific memory. In particular, the intermediate cabinet now receives the 25th bit from each train as the input signal in FIGS. 4A, 4B and 2 storage memories 3-31. For this selection it is first of all the devices mentioned above; the intermediate required to check the value of the digit D _{5 of} the address memory 3-32 receives the 24th bit 65 signal as an input signal. If the value of the decimal D ₅ = 0, etc. The origin of these signals is as follows, this means that one of the first four denotes memories: M ₂₅ corresponds to the 25th bit of the M-digit units 1 to 4 of cabinet 0 in which the words of the command word. N ₂₅ corresponds to the 25th bit of which 00000-09999 is saved and is controlled.

If, on the other hand, the value of the decimal D ₅ = 1, then this means that the four memory sectors 5 to 8 of cabinet 1 are activated, which are used to store the words 10000-19999, etc. Ten D ₅ gate circuits 4-41 are required for this test α to 4-41 / provided, but only three of them are shown in the drawing, namely 4-41 α, 4-41 b and 4-41 /. Input signals are present at each gate circuit, which means that the value of D _{5 is} checked. In the case of the gate circuit 4-41 α, which checks whether D ₅ = O, the input signals consist of P ^ ₁ , P ^ ₃ , P ₂₂ and P _n . To simplify matters, check bit P _{25 is} not used for D _5. From the code arrangement in FIG. 6 it can be seen that this combination of input signals results in the code combination 0010, which corresponds to the decimal zero. In a similar way, the gate circuits 4-41 b to 4-41 / check the input signals whether they _{contain the information D 5} = I to D ₅ = 9.

With the exception of the gate circuit 4-41 /, the output signal of each D ₅ gate circuit 4 ~ 41a, 4-41 & etc. forms the one input signal of a further group of four memory unit selection gate circuits, which in the first stage with 4-42 α, 4- 52 α, 4-62 α and 4-72 α are designated. The output signal of the D ₅ = 9-gate circuit 4-41 / forms the one input signal of a group of three storage unit selection gate circuits 4-42 /, 4-52 / and 4-62 /, since the last cabinet, as is well known, only contains three storage units. In each of these groups, the other input signal for the gate circuits 4-42 α to 4-42 / is derived from the buffered output signals of the three gate circuits 4-43, 4-44 and 4-45, whereby these check whether D ₄ = O , D ₄ = I or D ₄ = 2, while D _{3 is} less than 5. The gate circuit 4-42 α thus checks whether D ₅ = 0, D ₄ = 0 or 1 or D ₄ = 2, while D _{3 is} less than 5. If this condition applies, memory unit 1 is selected because the address sought must correspond to a number that is less than 02500. In a similar way, the gate circuit 4-426 checks whether D ₅ = I, D ₄ = O or 1 or D ₄ = 2, while D _{3 is} less than 5. If this condition applies, then the memory unit 5 is selected, since the address sought must be between 10000 and 12499. From the above description follows that dieSpeichereinheits-selection gate 4-42 to 4-42 c / in the same manner by selecting the first storage unit of each cabinet.

For this purpose, the gates 4-43, 4-44 and 4-45 receive input signals from the following Meanings:

gate
circuit Input signals meaning 4-43
4-44
4-45 Κ »Κ» Pw ? Ϋ́
P>P>P> P
ρ ρ P ~ Z, P, P D ₄ = O
D ₄ = I.
D ₄ = 2 and D ₃
less than 5

It can be seen from the table above that the gate circuit 4-45, which _{checks the signal P 14} ^, ie the fourth bit of D ₃ , also checks whether D _{3 is} less than 5 and D ₄ = 2.

The second input signal for every second memory unit selection gate circuit 4-52 α to 4-52 / is derived from the buffered output signals of the three gate circuits 4-47, 4-48 and 4-49, which check whether D ₄ = 2 and D ₃ is greater than 5, D ₄ = 3, or D ₄ = 4. The memory unit selection gate circuit 4-52 α therefore checks whether D ₅ = 0, D ₄ = 2 and D _{3 is} greater than 5 or D ₄ = 3 or 4. If this is the case, the address lines 02500 to 04999 and thus the memory unit 2 are selected. From the description above, it is clear in what way the remaining circuits operate in order to select a particular memory unit 1-39.

The remainder of the memory address decryption device will now be described in connection with FIG. 8 described. This part is the part to select the XY address. Since the 60 levels of a storage unit are completely the same, each level contains a square matrix of 50-50 = 2500 storage cores. Each level also contains 50 vertical wires, each wire going through all the cores of a column, and 50 horizontal wires, each of which goes through the 50 cores of a row. The corresponding vertical and horizontal wires of the 60 levels are connected to one another in series, so that there are 50 X-wires and 50 Y-wires for a storage unit. Each X-wire thus crosses any Y-wire 60 times at a core of each plane. A pair of XY wires is used to select a specific row of 60 cores that contain one of the 2500 words of the memory unit. Since there are also 50 X- and 50 Y-wires, each X-wire can be identified with a two-digit number, which - generally represented as JC ₂ X ₁ - expresses a number in the series 00 to 49. Analogously, each Y-wire can be controlled by a number in the series 00 to 49, _{generally designated V 2} V _1. The coded digits D ₁ and D ₂ now contain the numbers X ₂ X ₁ and the digits D ₃ and D ₄ V ₂ V ₁ . From the above illustration it can be seen that the value of X _{1 can be} between 0 and 9. For this reason, with the exception of the check bit, all bits of the digit D ₁ to represent part X _{1 of} the in FIG. 8 can be used to select a line. The part jc ₂ , however, only changes

between 0 and 4, so that therefore only the quinary part P ₆ to P _{8 of} the number is required to represent the part x _{2 of} the address. In the same way, the part V _{1 of} the address changes from 0 to 9 and therefore requires four information units to represent these digits. While the quadratic part of V _{1 is formed} from the quinary part of D ₃ and comprises the information units P ₁₁ , P ₁₂ and P ₁₃ , the fourth bit of V ₁ results from the coincidence of the check _{bit P 5 of} the digit D ₁ with the fourth bit P ₉ from D ₂ . So is z. B.

in the gate circuits 8-1, 8-2 there is coincidence between P ₆ and P ^ or between P ₆ and P ₉ , and the output signals of these gate circuits are combined by intermediate storage in order to form _{the fourth bit of V 1.} This allows adjacent addresses in memory to be shifted between two lines. So if z. If, for example, adjacent addresses in the memory are called up by the arithmetic operation of an arithmetic unit, these calls are distributed over two line output

6g control amplifier instead of a line level amplifier, whereby the duty cycle and thus the load on the line level amplifiers is decreased.

Like X _{2, the} number y ₂ for designating the address line can only have a value between 0 and 4 and therefore requires a maximum of three bits to represent it. These three information units are derived from the binary bits of D ₄ and the binary bit of D _{3 of} the address number. The criterion for forming the digit y ₂ is that each word in a memory unit physically occupies the same position as the same word in any other memory unit, except that the address numbers differ from one unit to another by 2500. For example, the address 00001 of unit 1 occupies the same position as address 02501 in unit 2, etc. Each memory unit is divided into five partial memories of 500 words each; This means that each partial memory in the entire memory can be identified uniformly by the values 0 to 4 of the number y ₂ . In other words: addresses that are among the first 500 words of a memory unit can be given the designation y ₂ = 0; those in the next 500 words, i.e. in the second partial memory, are given the designation y ₂ = 1 etc. In this way, the value of y _{2 can be} determined by checking the bit P _{14 of} the hundreds D ₃ and the quinary bits P ₁₆ , P ₁₇ and P _{18 of} the thousand digit D _{4 of} the address signal can be determined according to the following scheme:

D ₄ D ₃ Test gates PlB) Pill PlS Pn according to FIG. 8 0 0 less than 5 8-3 1 0 same or greater than 5 8-5 2 1 less than 5 8-7 3 1 same or greater than 5 8-9 4th 2 less than 5 8-11 0 2 same or greater than 5 8-4 1 3 less than 5 8-6 2 3 same or greater than 5 8-8 3 4th less than 5 8-10 4th 4th same or greater than 5 8-12

Address numbers D ₂ D ₁ Fig. 7 r-wire Tuesday Tuesday 0 0 JP wire 00 5 0 0 0 o · 00 00 2 5 0 1 00 05 0 0 0 2 01 00 0 0 5 1 02 01 0 1 0 1 01 48 ίο 2 3 9 8th 01 48 2 3 48

The above table is repeated for each 500-word sub-memory if the value D _{4 is} between 5 and 9. The gates 8-3 to 8-12 are arranged so that they can check the various conditions according to the table above. The output signals of a gate circuit pair 8-3 and 8-4, 8-5 and 8-6, 8-7 and 8-8, 8-9 and 8-10 as well as 8-11 and 8-12 are stored in the corresponding OR Circuits 8-13, 8-14, 8-15, 8-16 and 8-17 are combined and fed to an encryption matrix 8-18, 8-19 and 8-20 in order to assign the corresponding digit y ₂ for final selection in the memory unit form.

How the Y-X part of the address works in the memory address decryption device will now be described in connection with FIG. 7 and 8 as well as in connection with the table below:

As the table shows, in the case of the address 0000, the two digits 00 are in places D ₁ and D ₂

simply converted to 00 for the values x ₂ and Jc ₁ . This is also shown in FIG. 8. Since there is a "0" _{at position D 3 , V 1} = 0 after conversion. Likewise, the digit 0 at position D _{4 is converted} to y ₂ = 0. The storage location for the address 0000 is thus the upper left corner of the matrix shown in FIG. At address 2500, the digits 00 in places D ₁ , D _{2 are converted} into 00 for X ₂ Jt ₁ . Since there is a “5” _{at D 3} , there is a “0” _{for V 1.} Since the digits D ₄ and D _{3 represent} a "2" and a "5", respectively, the conversion results in y ₂ = 0. This memory location is accordingly located in the upper left corner of the second memory unit. If the address is 0001, D ₁ = I is converted to JC ₁ = I and D ₂ = O to JC ₂ = O. D ₂ = O and D ₁ = I, on the other hand, become V ₁ = S, since the input signals P ₅ and PjJ applied to the gate circuit 8-2 generate a signal level on the fourth line of V ₁ . This bit and the bit of P ₁₂ (D ₃ = O) together result in the code combination 1010 on the four lines vj, which corresponds to the decimal number 5. The digit D ₄ = O is converted by the gate circuit 8-3, the OR circuits 8-13 and 8-19 into the binary code combination 010 on the three lines y ₂ , which is the decimal

digit 0 corresponds to the code used in the memory. The address 0001 is thus shifted from the address 0000 by five lines and one column. In the case of address 0002, the number 2 in the number position D ₁ in Jc ₁ - 2 and the number D ₂ = O in

Jt ₂ = O converted. D ₃ = O becomes V ₁ = O, and D ₄ = O together with D ₃ = O pass through the gate circuit 8-3 and the OR circuits 8-13 and 8-19 to become y ₂ = 0. The address or memory location 0002 is therefore in the same row as 0000, but shifted by two columns. In the case of the address 0154 described next, the "1" in the digit position D ₁ (D ₁ = I) is converted to Jc ₁ = I and the digit D ₂ = 5 to Jt ₂ = O. D ₃ = I together with D ₂ = 5 results

Vi = I, while the "0" in the digit position D ₄ together with the "1" in the digit position D ₃ passes through the gate circuit 8-3 and the OR circuits 8-13 and 8-19 and as V ₂ = O appears. In the example of address 2301, the number 1 is in the

Digit position D _{1 is converted} to JC ₁ = I, while the "0" in digit position D ₂ becomes JC ₂ = O. The number 3 of the number position D ₃ becomes "3" in the quinary part of V ₁ ; however, the fourth bit of V ₁ is also present, since the gate circuit 8-2 is opened by the joint action of the signals P ₅ , ψ ~ _α . The four bits of V ₁ are thus converted to an "8". The number 2 in the number position 4 together with D ₃ = 3 runs through the gate circuit 8-11

509 538/373

19 20

as well as the OR circuits 8-17 and 8-18 and the signal associated with seven x ^ lines (FIG. 8). _{In a similar way, y 2} appears at the input of each line, whereby y _{2 appears} as "4". In order to describe a last example of the seven F-address input gate circuits 9-5, the input signal corresponding to _{one of the seven V 2} V ₁ -LeItUn addresses 2398 corresponds to the number 8 in the number position D _{1 in 5} (Fig. 8) and that converted in the above-described X ₁ = 8; the number 9 in the numbered manner from the memory address decryption D ₂ becomes X ₂ = 4. The number 3 in the numbering device is derived. Each input position D ₃ is addressed with the assistance of the gate circuit 9-4, 9-5 also receives an 8-1 in V ₁ = 8. The number 2 in the number lock signal, which is labeled MCKA . This position D _{4 of} the address as well as the number 3 in the io signal is passed through the gate circuit 8-11 intermediate lock toggle circuit 9-13 or the Zwis as well as the OR circuits 8-17 and 8-18 _{by the output signal of the memory digit position D 3} to become syny ₂ = 4 shenlock flip-flops 9-14 and 9-15. 'chronising device or the central processing like F i g. 2 shows, the seven lines are generated during the occupancy period of the storage unit X ^ c ₁ and the seven lines V ₂ V ₁ to all storage unit 1. The Z and Y address signals are connected in parallel. The signal combination is temporarily 9-5 to the seven Z-address flip-flops 9-2 and stored and further evaluated on these lines via the corresponding gate circuits 9-4, in order to convert the seven Y-address flip-flops 9- 3 so selected pairs of Z and Y wires to mark. led that these flip-flops in accordance

_ ■, ^{,,,, ao} mung with the code combination that the signals on

Storage unit and priority circuits represent _{the χ} _ _and y address lines in their

9A, 9B and 9C show the details of the setting state to be tilted. The bistable Ares tail unit that belongs to any control unit of the sen flip-flops 9-2 and 9-3 store the total memory. In particular, this ZY address temporarily shows the tail unit and the storage priority period during a small figure. The output signals of these X- and Y-flops are circuits for the memory unit 1 of the cabinet 0. the X- and Y-Adressenentschlüs Similar circuits are supplied for any other selungsmatrizen 9-17 and 9-18. This de-storage unit is provided. 9A, 9B and 9C coding matrices can be arranged from conventional are in such a way as they consist of the secondary image in and per se known diodes. Your Funk-F i g. 9 can be seen. 3 ° tion is based on the

The memory matrix with its 60 levels and th coded input signals in the illustrated 2500 cores is symbolically selected in FIG. 9A with 9-1 as a way of selecting one of its 50 output lines. Cube shown. Like most memories that work on these output lines each one of the basis of the coincidence of half-currents, 50 Z-switches 9-19 and 50 Γ-switches 9-20, which also allows this memory only a destructive 35 on its part with the 50 Z-wires and the 50 Γ-wire reading out the stored information. In beds that are pulled through the storage cores, drift passes through this storage are therefore connected without regard. The read and write currents on whether it is the read or write operation sources 9-23 and 9-71 are determined by the 50 Z- and, a read and write cycle in which the 50 Y switches 9-19 and 9, respectively 9-20 switched on in order to read the information contained in the addressed memory location 4 ° the selected IF wires of the memory during mation as a result of an interrogation first of all, the read and write period is read with power. Depending on whether it is about reading.

or write process, then the old one arrives. Each storage unit is also in the tail unit

or the new information is assigned to a separate clock 9-21 in the circulation process, which the time-

the storage location. 45 borrowed progress of the storage process monitored.

To control the memory, the memory This per se known clock generated in chereinheiten-selection lines, which extend at the top of the receipt of a request signal from one of the edge of the figure, selectively for the time of a memory-driving works, such. B. excited the central pulse duration, as already described processing system, the synchronization devices. The one selection line, which is assigned to the controlled 50 or the arithmetic logic unit, pulses from one storage unit each, in this case ben microsecond length one after the other at seven, i.e. the selection line 1, is connected to seven Z address taps MT ₁ to MT ₁ .

Input gates and seven Γ address on-These clock pulses of half a microsecond

Aisle gate circuits coupled, the symbolic length appear one after the other at the taps MT ₁

each represented by a gate circuit (9-4 and 9-5) 55 to MT ₇ at intervals of half a micro-

are. The same selection line is also open with the second, whereby the clock pulse at the tap

the inputs of a read gate circuit 9-1, a function MT ₁ ¹ Iz microseconds after receiving the memory

Memory intermediate lock gate circuit 9-7, a synch unit selection signal arrives. This memory

chronisier- intermediate lock gate circuit 9-8, a unit selection signal is timed together with

Intermediate lock gate circuit for the central processing 60 of the main clock assigned to the calling plant

processing system (9-9), a pair of arithmetic unit intermediate signals (t ₀ to t ₇ , FIG. 1) are generated. The at the tap

Schensperr gate circuits 9-10 and 9-11 for interfering output signals are then

writing of information blocks as well as a return to the rest of the control unit of the memory,

Stell gate circuit 9-12 for writing to the timing of the storage process

Blocks coupled. Monitor all of these gates 65.

are shown in the drawing. At each of them- In normal operation, the storage unit takes

ben Z-address input gate circuits 9-4 indicate that a "write-in" process is to be carried out.

also seems to be the input signal that one of the is to carry out a "read" process

21 * 22

A "read" signal PYMR is free from the requesting plant and the operation is generated in the requesting plant, which can now take place together with the storage unit plant. The setting, selection signal of the read input gate circuit 9-6 is fed to the memory intermediate blocking toggle circuit P-IS. The output of this Torschal- is via the OR circuit 9-40 generates the signal is the set input of a bistable read 5 MCKA tung, supplied so that the gates 9-4, flip-flop 9-22, which, by the storage 9-5 9-6 and 9-7 locked and the gate circuits cher clock pulse MT _{7 are opened} again in their reset 9-8, 9-9, 9-41 and 9-42. The walkout is upset. This flip-flop 9-22 are input signals of the gate circuits 9-6 and 9-7, that is to say, remain for a short period of time in the computer, and are set as a start signal to the clock in their setting state. The memory encoder 9-21 is switched on. A pulse length later, the unit selection signal, which the read flip-flop in ie at the storage time MT ₁ , is flipped over at its setting state, is timed to the tapping MT _{1 of} the clock 9-21 occurring input signal of the clock 9-21 Clock pulse supplied to the reading current source 9-23 to initiate the timing of the storage process, which turns it on and conducts the reading current. 15 flows through the pair of ZY switches, which flows from the

The sequence of the individual operations of the control unit assigned to the flip-flops 9-2 and 9-3 is selected according to the address. The read current flowing through the selected using an example, in the case of the th XY lines, has the effect that it is assumed that all cores located at the intersection points in the _; are processing plant a "reading" -request to the storage za 0 state controlled. The kernels, which are directed to the cup. As FIG. 1 shows, the read lines are already in state 0, generate an address on their central processing system with a weak or even controls read lines, the signal required for this being no output signal, while those in state 1 are time t ₇ of the main clock cycle is generated. The cores located during the read current flow a signal consists of the memory unit selection generate a strong output signal. The individual read signal and the XY address signal. Since the transmission of the memory address signals are provided for the lines in each case to 60 read gate circuits 9-24. These gate circuits, which have a delay from a pulse setting output signal of the bistable multivibrator due to the lines, meet the memory unit selection signal 9-22 were prepared, are actually stroboscopic _{at the memory time and the XF address signal only at 30 point MT 3} sampled, with the time t _{0 of} the small period in the memory. Among those gate circuits at whose inputs "Assumption that the memory unit 1 is activated" generate output signals while it is supposed to be and is not occupied (no MCKA signal, those with "zeros" appearing at their inputs) are triggered by this address signal which are tet do not generate an output signal. The gate circuits 9-4 and 9-5 open, so that the 35 output signals of the 60 read gate circuits 9-24 who XY address signals on the address lines X ₂ X ₁ correspond to the setting input of the corresponding 60 Um- and y "y _{1 of} the memory address decryption prefetch flip-flops 9-25, whose direction of adjustment appear and the bistable X and output signals are supplied to the corresponding 60 read-out Y address flip-flops in correspondence with flip-flops 9-26. These last with the activated address in their settings for the lower gate circuits will overturn at the time of saving. At the same time, the bistable MT _{6 is} stroboscopically scanned in that the tap read toggle circuit 9-22 is connected by the memory unit MT _{6 of} the clock generator 9-21 with this gate circuit selection signal set via the gate circuit 9-6. The output signals of these 60 gate and the read command from the control of the circuits are generated with the output signals of the memory performing plant. The memory 45-like gate circuits of other gate circuits in the intermediate memory latch flip-flop 9-13 are connected by the storage unit selection signal located in the cabinet together via the gate switch and set to the read main line at the point in time 9-7. The memory unit selection MT ₇ coupled, the amplifier circuit signal is also a memory-free gate 9-28 for the read main line a delay of device (MNB) 9-31 via an OR circuit 9-30 50 adheres to a pulse length. The information is fed in such a way that all storage unit selections are then received as a result of the signals inherent in the read current paths for this storage cabinet. The Tor- den delay the interrogating plant with a circuit 9-31 receives four blocking input signals, and a delay of one pulse length is supplied. In response to a signal from four of the gate circuits in this way, the inquiring plant receives the Infor-9-41 similar gate circuits. Each of the storage units located in a storage cabinet for the exactly eight pulse lengths in 55 mation after the call, which corresponds to a small period,
th intended gate circuit 9-41 receives as input After reading out from the controlled

input signals their own MCKA and memory input storage location, the information must be regenerated. The gate circuit 9-31 is only the. This is done in that the reset output of the gate circuit 9-41 is blocked when the MC1L4 signal of the memory unit 1 is present. When 60 Z gate circuits 9-70 are supplied, the present example assumes, however, also the input signal of a Z control gene that this signal does not occur. The memory circuit 9-29 received in order to control the excitation of the winding unit selection signal therefore runs through the lungs of the corresponding Z level in the memory gate circuit 9-31 and generates the memory free unit 9-1. The regeneration of the out-signal MNB. This signal is then fed to the factory read information occurs during the write that sent the query to the memory, period of the "read-write" cycle. This indicates that the memory input in question is the read current at time MT ₁

23 * 24

turned off by the clock 9-21 and the read line so that it turned on test switch write current (not shown). At the same time, the lines are offered for comparison purposes. Control circuits Z can be closed at time MT _4. Since, as already mentioned before, the and open at the time MT _7. During the storage units during a given small write operation, the current flows through the period requests from one or both arithmetic units. Synchronizing devices can get, it was necessary to change direction, except for the cores, these means are provided in order to prevent an occupied by the current flowing in the Z-winding from storage unit for these works or devices. Because only the cores of the write io to temporarily block. The current for this purpose remains unaffected, the Z-windings of which are provided in the circuit comprising the storage sequence of the reset output signals of the 60 circulating intermediate blocking flip-flop circuit 9-13. If these intermediate flip-flops are excited, all the other blocking flip-flops are returned to their setting state 1 in the memory unit selection line by the excitation of the cores during the writing process. This process switches the state and in this state the information originally stored in the memory remains regenerated. At the time MT ₇ are set up. By means of the clock, the intermediate then through the clock 9-21 the bistable toggle lock-toggle circuit at the time MT ₇ then switched circuits 9-2, 9-3, 9-22, 9-13 and 9-26 into the reset state upset.
Reset status switched to prepare the memory for the next call after the intermediate memory lock has been set. Flop 9-13 passes through their set-off The following example is now assumed input signal an OR circuit 9-40 to the Sidaß the memory is free and generate an "Enrollment" flashbulbs gnal MCKA. This signal is used to indicate the gear to be carried out. As can be seen from the Xy address input gates 9-4 and 9-5 below, the input 25 is supplied as a blocking signal so that the address tilt write operation is essentially the same as that of the circuits 9-2 and 9-3 Read operation not previously described for eight pulses. As with reading let be adjusted. The signal MCKA is also assumed here as well, that the memory unit 1 is to be controlled in Speig at the gate circuits 9-41 and 9-42. The memory unit selector free circuit as a pass signal connected to signal 1 thus passes through together with the XY- 3 »tet. The gate circuit 9-41, the gate circuits 9-4 and 9-5 with the selection address signal. The line 1 of the relevant memory unit connected address signal is in the address memory toggle, is stored in this way eight pulses long upstream circuits 9-2 and 9-3 and prepared by the so that a subsequent memory unit-off decryption device 9 -17 and 9-18 deselect signal, through which this memory unit codes in order to control an XY- 35 of this time period from the 50 switch pairs, the gate switch pairs 9-19 and 9-20 and thus the ones with the tang 9- 41 runs through and the gate circuit 9-31 connected as a memory unit XY lines is supplied to the blocking input, in order to select the. Since in the present case it is not a matter of preventing the generation of a memory-free signal or a read process, the gate circuit 9-6, but the gate circuit 9-7, is not opened, which means that the three blocking inputs directly above the gate circuit 9-6 9-41 come from gate switches, which are similar to the gate through the intermediate memory blocking circuit in their circuit 9-41 and which are switched to the three setting states and the signal MCKA is supplied to other memory units of this cabinet. These tax units are included for a small period. Each of these signals blocks the gates 9-4, 9-5, 9-6 and gate circuits receive their own MCKA and 9-7 to allow further interrogation of these memory unit selection signals.
that is to be prevented during eight pulse lengths. In addition to the processes just described, the memory unit selection signal is also activated by the signal MCKA, so that the synchro-OR circuit 9-30 and the gate circuit 9-31 nisier-Zwischenblock-Torschaltang9-8 and the intermediate circuits to the memory Free signal MNB to generate lock gate circuit 9-9 of the central processing. At the beginning of the operation, the storage system will be made conductive. These two cores, as before, when the read current is switched on. Since the read toggle switch 9-22 but not synchronizing intermediate lock toggle switch 9-14 and has been set, the 60 read gate switches of the intermediate lock toggle circuit 9-15 of the central gene 9-24 remain closed, so that the output of the Processing plant. The purpose of the information appearing on these switching arrangement read lines is to ensure that the order in which the individual running toggle switches are not received. Instead of the works to regulate the memory unit when this sen appears at the time MT ₅ which was found "occupied" in the memory. The information to be written receives on the write line synchronization devices of the input and output and passes through the circulating flip-flops 9-25 devices in front of the central processing system under the influence of the gate circuit 9-32 and 60 access to the memory. Is to the memory unit of the 60 write-in gate circuits 9-33. In the time no request has been made, MT ₅ to MT ₇ will receive the access to the tumble-switching arithmetic unit. This process is described below with the aid of an example under the action of the write current source 9-71, which is assumed that the memory be-Z control circuits 9-29 and the gate circuits 65 are set, with this state is then stored by a signal 9-70. When the MCKA is opened, it is indicated, and that during this read-out gate circuits 9-26, this new set status appears for one of the synchronizing devices information at the time MT _7, i.e. also on that of the input and output devices in the

25 26

ordered time intervals t ₃ or t _7, a request is made if it is suppressed. As in the case above, through

aimed at the storage unit. By this request, the absence of the signal MCELA das

the memory unit selection line 1 is generated in the memory free signal. At the same time, the

Time intervals i ₃ or t ₇ coupled. The address signals occurring on the XF lines

tion 9-8 is opened because at their inputs 5 are stored in the flip-flops 9-2 and 9-3,

the memory unit selection signal passed through the output of the gates 9-6

Signal MCKA and the corresponding clock or 9-7, the clock is also switched on, depending

pulse t ₃ or t _{7 of} the main clock generator are present. according to whether it is a reading or a

The output signal of the gate circuit 9-8 acts as a write command.

the synchronizing intermediate locking flip-flop circuit io. In the following example, it is assumed that 9-14 is switched to its setting state. The fact that the control output signal of this flip-flop circuit is during a "busy" period is fed to both a synchronization device, a blocking circuit 9-50 of the MCO-OR circuit and a central processing system, this device 9-40 tries to control a fictitious MCKA signal memory unit. In this case to generate. At the end of the small period, in which 15 first the synchronization device access the memory unit was occupied, the memory to the memory and then the central processing intermediate blocking toggle circuit by the clock signal processing system, provided that the synchro MT ₁ in the reset state upset. The signal nizereinrichtungen no further inquiries to the MCKA is still pending, however, since the syn memory takes place. The chronizing intermediate locking toggle circuit is set by both queries, and no further queries to the memory and 9-15 are set. In this case it will be registered by that. In the next time interval t _s or t ₇ block / flip-flop 9-14 assigned to the synchronizing setting output signal of the synchronizing intermediate signaling device, the gate circuit 9-51 is then blocked by the synchronizing device , while, on the other hand, the signal MCKA via the device second call to the storage unit. This gate circuit 9-50 is generated. Assuming that the gate is blocked by the clock pulse t _s or i _7, the next request from the central processing circuit 9-50 is blocked so that the signal MCKA is processed, the gate has ended immediately in this time interval. circuit 9-51 supplied clock signal t ₀ no We-As a result, the memory-free signal MiVB via kung on the signal MCKA, since it is chronisier-intermediate locking toggle circuit through the Syndie gate circuit 9-31 and the OR circuit 9-30 30 9-14 will be generated and the new will be saved. In other words, if the synchro addresses are in the XY address flip-flops nisier-interlock flip-flop circuit 9-14 in their take place via the gate circuits 9-4 and 9-5. The setting state, the processing system receives a memory unit selection signal passes the gate - no access to the memory. If, on the other hand, the circuit 9-7 takes place, whereby the next interrogation is set by the synchronizing device, flip-flop circuit 9-13 and the clock, access to the memory is released and the 9-21 is switched on. At the time MT _{1 of} this intermediate blocking toggle circuits 9-14 and 9-15 who store cycle, the synchronization intermediate is reset.

lock-toggle switch reset; the signal as in FIG. 9 shows, a device MCKA is also provided, however, as a result of the setting state of FIG. 40, by means of which the memory unit can be excluded from further memory latching toggle circuit 9-13 from a write operation. This is made possible by the circuitry MCKB shown in the lower part of FIG In this case, essentially the same flip-flops that control these gate circuits are output as in the case of a request by the synchronizers 9-62 and 9-63 for the writing of information devices. In this case, the memory blocks will belong. If, however, a specific memory unit selection signal contains commands specific to the unit _{at time i 0 which are not erased memory.} Since the signal should be present at the same time, a circuit 9-9 generated by the processing system MCKA and the main clock pulse t _{0 will be applied} to the gate- generated circuitry 9-9 occurring in the command register IR 1, and this generates an output error 21 or 22 for this purpose used to set one of the toggle circuits 9-62 or 9-63 set to the one-signal, whereby the intermediate blocking toggle switch write of information blocks provided 9-15 of the central processing system. By will. The setting output signal of this intermediate the setting of these flip-flops are the blocking-flip-flop is opened via a lock gate circuit 55 gate circuits 9-60 and 9-61, on whose other 9-51 the OR circuit 9-40 is fed to their inputs the CCT-1 clock pulse or which in turn generate a fictitious signal MCKA. Apply to the Ci7-2 clock pulse, so that after the end of the "busy" time, the intermediate memory position of these flip-flops is a signal MCKB blocking flip-flop is generated by the clock pulse MT ₇ in each of the arithmetic unit concerned reset. Because the intermediate blocking circuit of the zen- 60 assigned clock interval of the memory. This Sitralen processing system has been set, however, signal MCKB the memory intermediate lock toggle keeps the signal MCKA. If there is then no connection 9-7 via the gate circuit 9-7 ^ 4 as a blocking question by a synchronization device, the signal is supplied, this gate circuit being prepared by the central processing system for its next write signal CU of the arithmetic unit, at time t ₀ call made to the memory 65 to prevent the intermediate memory lock access to it. At this point in time the signal is generated and the clock generator 9-21 is interrupted during an output signal of the gate circuit 9-51 a pulse writing process of the arithmetic units 1 or 2, whereby the signal MCKA is switched into line. The MCKB signal is also used as a

27 28

Pass signal is coupled to the gate circuit 9-42 in the memory-free circuit of a specific memory gate circuit 9-42 comprising 2500 words, to generate the extra-unity. This signal is coupled to the memory unit selection signal and a circuit 9-10, which receives the function write signal CU from the arithmetic unit. This table signal FT 721 becomes conductive and the write- in signal CU is always generated when a write command for writing information blocks is issued by the arithmetic unit. The toggle switch 9-62 in its setting state toggle the output signal of the gate circuit 9-42 is the gate. The instruction 22 has the format 22 NNNNN xxxxx supplied to circuit 9-31 to prevent the generation of the and generates the same function table signals as memory-free signals during the arithmetic unit of the instruction 21, except that it instead of the function table assigned time interval. For the io lensignals FT721, the function table signal FT122 generates three other storage units located in the cabinet. The function table signal FT 722 generated are three more similar to the gate circuit 9-42 together with that from the digit part NNNNN of the gate circuit, the memory unit selection signal received in each case its own command, a memory unit selection signal and its own Si signal from the gate circuit 9 -11 to receive the input MCKB and the gate circuit 9-31 each write 15 information blocks because a blocking signal is provided, as set directly from the toggle switch. The command 23 becomes the three blocking signals shown for the gate circuit 9-42 . Resetting of the flip-flops 9-62 and 9-63 can be seen. The MCKB signal is also used and has the format 23 NNNNN xxxxx. This Jf-Y address input gates 9-4 and instruction produces the same function table signals 9-5 through the inhibit gate circuit 9-80 as the inhibit input 20 as instruction 21, except that it is supplied in place of the function. This gate circuit 9-80 is blocked by a table signal FT 721 the function table signal on the read line occurring read command. FT723 generated. The function table signal FT723, apart from the time span in which the generated together with the NNNNN computer carries out a read operation and the memory unit selection circuit 9-80 derived from the command 23 is blocked, the signals 25 are a signal from the gate circuit 9-12, whereby MCKB the address gate circuits as blocking inputs both flip-flops 9-62 and 9-63 reset gears fed to prevent them from being in the.

• Y-Y address flip-flops 9-2 and 9-3 in the description above and below

Address is saved. Should from the arithmetic logic unit, an X contained in the command format means a

on the other hand, information from the memory - 30 unused digit. When transferring information

read, this can be done as follows: information from and to the memory also results

The read line is energized, and the gate circuit when this information is transmitted via the

9-80 is blocked so that the gates 9-4 read and write lines a delay of one

and 9-5 become conductive. The read address is the pulse length.
Flip-flops 9-2 and 9-3 and the clock 35
encoder started via gate circuit 9-6. That

The memory-free signal is sent via the OR circuit of the central processing system
9-30 and the gate circuit 9-31 generates under the

Assumption that the memory unit was not occupied As already mentioned at the beginning, one of the

and the lock signal from the gate circuit 9-42 not 40 major works of the electronic computer from the

was generated. central processing plant and the distributor

Once the storage unit is once from a standing input and output processing system. If the write process has been excluded, information can only be written into the central processing system, a general-purpose computer with a stored program , the operations of all storage unit is canceled. If the above input and output device failure occurs, the gate circuit 9-12 becomes conductive, and to control the conditions and to coordinate the operations of the distributor for writing information blocks and the synchronization devices, see flip-flops 9-62 and 9 -63 become 50 The central processing system has its own command, which is typical for a general-purpose computer and is returned by the memory unit selection signal, whereby the signal MCKB is canceled. reportoire assigned so that the facility at least

The setting and resetting of the toggle switch can execute the following commands:
The general procedure for 9-62 and 9-63 is as follows

yourself: To set the toggle switch 9-62, 55 ^ add *

a command 21 with the ''

Format 21 NNNN xxxxx. This command generates at 2nd subtract;
its storage in

the command register IR1 a number of function ³ · withdraw;

table signals of the encryption device 60 4 shifting
10-18. Specifically, this command 21 generates the following

Working table signals: FT700, FT600, FT721 5. Equality and size checking for conditional

and FT709. The effect of this function table jump;

signals will be described in detail later. _{6 unconditional} jump command and
The function table 65 generated at time t ₇

signal FT 700 forwards the digit part NNNNN of the transmission 7. Transmission of data from and to the central

failure of the address encryption device to, central processing system and from and to

thereby a memory unit selection signal for main memory.

These instructions, referred to below as "accounting commands", are sent to the central processing system the possibility of receiving a basic command coming from the main arithmetic unit, interpreting it and then the operations the input and output device on the basis of a stored program in accordance with the Basic command to control one after the other. As a rule, the input and output device should be controlled by a basic command to perform an operation. However, this operation cannot can be carried out in a single operation by e.g. B. the central processing plant only executes an instruction. So although the basic commands are usually in the form of the computer word they cannot be executed directly, but must first be carried out by the central processing plant be evaluated. This evaluation is carried out with the help of the accounting commands. The accounting orders are also used to modify the commands currently stored and the status of the various To monitor input and output devices. It also runs the central processing facility also issue a series of commands called "input and output instructions" will. Some of these input and output instructions check the status of an input and output device and cause this device to initiate an operation in response to such a test or move on to their next task. Initiate other input and output instructions on the other hand, a selected input and output device directly to carry out a specific one Task. These last-mentioned input and output commands usually occur after they have been carried out of the instructions, the execution of which had to be checked.

The control of the input and output devices and the devices assigned to them by the central Processing plant is carried out according to a predetermined system, with the higher speed working input and output devices more frequently queried and to carry out operations according to the input and output commands coming from the central processing system than the input and output devices operating at a lower speed. In particular, the central processing system monitors the activity of all synchronizing devices, of the distributor as well as all input and output devices by changing the individual devices monitors and controls in a certain order. To ensure the smooth running of one of several to ensure the operation to be performed by various input and output devices, e.g. a priority control can be provided in the program of the central processing system. This priority control will be explained in detail later in connection with the "99 loop" instructions of the central processing plant described.

In order to be able to completely carry out an input and output operation in accordance with a basic command, a number of consecutive commands of the processing system must be carried out. Some commands in this command sequence belong to the accounting commands, while others in turn belong to the group of input and output commands. Normally, the central processing system is supplied with a basic command from the arithmetic unit. The system then evaluates this command by checking it several times with the help of the accounting commands, whereupon the control is then transferred to a specific command sequence of the central processing system in accordance with these checks. As a rule, however, such a sequence of commands cannot be carried out in an uninterrupted sequence. The central processing system must therefore be designed so that it can exit a certain input and output program assigned to a certain part of the input and output devices at any point for the purpose of executing other instructions and switch on again at the same point at a later point in time. The central processing system is shown as a block diagram in FIG. 10, while FIGS. 11 to 29 essentially show the details of the various components in FIG. Will now Subsequently, the central processing unit in relation to the abovementioned figures, _r be written, to be showing how the individual accounting instructions are executed and in what way the central processing system is affected by the input and output commands over the other levels of the computer. When the input and output commands are received by the central processing system, a number of control signals are generated which are transmitted to the various parts of the input and output devices as well as to the synchronization devices and the distributor. ; ^; Before describing the various in FIG. The components shown in FIG. 10 first list the accounting commands that are executed by the central processing system. In order to better understand the functions of the individual components, these accounting commands are already listed here.

Accounting orders

Command format MMMMM Short name description // NNNNN XXXXX 00 XXXXX MMMMM Skip Go to the next command. 05 XXXXX Jump or? 7 command Save the five M-digits of the command "05" in the
Tax counter 10-35 um. The next command will be the one through
these five M-digits marked memory location ent
took.

31

Accounting commands (continued)

Command format

Short name Description

07 NNXXX XXXXX

10 NNNNN XXXXX

11 NNNNN XXXXX

12 NNNNN XXXXX

13 NNNNN XXXXX

14 NNNNN MMMMM

15 NNNNN XXXXX

16 NNNNN XXXXX 18 NNNNN MMMMM

19 NNNNN MMMMM

shift

algebraic addition

algebraic subtraction

File transfer File transfer

unconditional return command

File transfer File transfer

Parity check for conditional jump

Conditional jump size check

20 NNNNN XXXXX

Removal Shift the contents of the register RP-I (a word consisting of twelve digits) by nn places to the right. The entire word contained in the register, including its sign, is shifted so that the content of the lowest nn digits becomes the content of the most significant nn digits.

Add the content of the memory location identified by the five digits to the content of the register RP-I and store the result in the register RP-I.

Subtract the content of the memory location identified by the five digits in the IV from the content of register RP-I and store the result in register .RP-I.

Relocate the contents of the memory location identified by the five JV digits in the register RP-2 .

Save the contents of the register RP-2 in the memory location identified by the five digits in the iv.

Save the five M-digits of the command "14" in the Tax counter 10-35 um. The next command is taken from the memory location identified by these five M digits. The contents of the control counter (i.e., five digits in control counter 10-35) that resulted in the extraction of this command from the memory, plus two is identified in the by the five digits of the command "14" Storage location saved.

Save the content of the memory location identified by the five digits in the register RP-I .

Save the contents of the register RP-I in the memory location identified by the five digits in the IV.

Save the content of the memory location identified by the five digits in the register RP-2 and compare the content of the register RP-I with that of the register RP-2. If RP-I = RP-2, re- store the five M-digits of the instruction in the control counter 10-35; the next command is taken from the memory location identified by the M digits. If RP-I is not equal to RP-2 , the next instruction is taken from the memory location identified by the digits in the control counter 10-35.

Save the content of the memory location identified by the five digits in the register RP-2 and compare the content of the register RP-I with that of the register RP-2. If RP-I is greater than RP-2 , transfer the five M digits of the command to control counter 10-35. The next instruction is taken from a memory location which is identified by the M digits. If RP-I is equal to or less than RP-2 , the next instruction is taken from the memory location indicated by the digits in the control counter.

Transfer the content of the memory location identified by the five digits to RP-I in the manner corresponding to the content of the register RP-2.

In general, the commands are denoted by digits, which correspond to the two "/" digits or the abbreviation. So z. B. the move command can also be referred to as command »07«. Those marked by the letter "X" Digits of a command mean that these digits are digits that cannot be deciphered. The device shown in FIG. 10 and the other associated figures can command a wide variety of commands Perform Art. On the other hand, only those are shown in the part of the description that now follows Discussed accounting commands that actually operate the input and output devices required are.

As FIG. 10 shows, the data or commands to be processed are fed to the central processing system from the memory (FIGS. 9A, 9B and 9C) via the read lines HSB-R shown in the lower part of FIG. These read lines are shown in FIG. 10 shown by a single line, in reality, however, represent a cable harness consisting of 60 lines on which the digits of the machine word are transmitted from the memory to the central processing system. As already mentioned, this information (data or commands) is available to the central processing system at time t ₇ on the read line HSB-R .

To display the information to be processed by the central processing system, the the following L-code is used:

4th bit 2 1 sign 5 0 3 0 0 1 0 0 0 1–1 0 0 0 0 1 1 1 1 0 0 1 1 2 0 0 1 1 0 3 1 1 1 0 0 4th 0 1 0 0 1 5 1 1 0 1 1 6th 0 1 0 1 1 7th 1 1 1 1 0 8th 0 0 1 1 0 9 0 0 0 0 0 (-) minus 1 0 (+) Plus

In contrast, the following M code is used to represent the information to be processed by the memory used:

4th bit 2 1 sign 5 O 3 1 O O O O 1 T-I O 1 O O O 1 1 O O O O 1 2 1 O 1 O O 3 O 1 1 1 O 4th 1 T-I O 1 1 5 O 1 O O 1 6th 1 1 O O 1 7th O 1 1 O O 8th 1 O 1 O O 9 1 O O 1 O (-) minus O O (+) Plus

The illustration shows that the second and fifth bits of the L code are each the complement of the second and fifth bits of the M code. In order for the processing plants to meet the requirements of Memory can also process incoming information (transmitted in M code), a conversion device must be used are provided, by means of which the M-coded information signals on their way to the central processing system in L-coded information signals being transformed. Similarly, the L-coded information signals must be their way to memory are converted into M-coded signals. For the sake of simplicity, there is one Conversion devices have been omitted, which are normally located in the read line and only the complements to the second and fifth bits transmitted on this read line of the information digits would form.

As can be seen from the drawings, the read line HSB-R is via the 60 gate circuits 10-24 and 10-25 with two one-word registers RP-I or RP-2 and via 60 gate circuits 10-10 with one

ίο One word command register 10-11 IR-2 connected. Commands from the memory are transferred to the command register IR-2 via the 60 gate circuits 10-10, while data coming from the memory are passed via the gate circuits 10-24 and 10-25 to the register RP-I or RP-2 . The data or command information coming from the memory is fed to the inputs of the gate circuits 10-10, 10-23 and 10-24. However, as will be described further below, the gates 10-24 and 10-25 are controlled by the function table signals FT 707 and FT 705, respectively. These signals only open the gate circuits mentioned last when data coming from the memory are to be fed to the relevant registers. The function table signals prevent commands from being transferred to the registers. The gate circuits 10-10 are connected to the main lines via a delay device 10-21 operating with a delay of one pulse length, so that the command information appearing on the read lines at time t ₇ is present at the inputs of the gate circuits 10-10 at time t _0. The gate circuits 10-10 are turned on by the clock signal i ₀ and the signal appearing on the output line 10-22 d of the command circulation control unit. A signal appears on the line 10-22 d only when a command is to be fed to the central processing system. The 60 gate circuits 10-10 are each connected at their outputs to one of 60 associated bistable flip-flops which belong to the command register IR-2. The 60 bistable flip-flops in the command register IR-2 receive the twelve digits of a command via the gate circuits 10-10 at time t ₀ and generate

at time t _t an output signal which corresponds to the stored command. As already mentioned, the twelve digits of a command consist of the two / digits, the five N digits and the five M digits. The two / digits represent the command part of an instruction, while the two groups of the five M and five iV digits denote, among other things, the memory location in which an operand to be processed by the arithmetic unit of the central processing system is located or in which data from are to be stored in the central processing plant. The five M-digits (25 information units stored in the instruction register IR-2 ) are supplied via 25 gate circuits 10-12 «25 bistable flip-flops of another command register IR-I , which comprises 60 flip-flops and stores twelve digits, in which the same five M-digits des Command can be saved. The two / digits and the five iV digits in the command register IR-2 are fed via 35 gate circuits 10-12 to the inputs of 35 bistable flip-flops in the command register IR-I , in which these numbers of the command are stored. Since each instruction digit consists of five information units

509 538/373

exists, ten bistable flip-flops are required to store the two / digits, while on the other hand, 25 flip-flops are required to store the five ΛΓ digits. The gate circuits 10-12 and 10-12 α are prepared by the clock signal t ₅ or ί _β . In contrast, the gate circuit 10-12 α is blocked by a signal PCT generated by the command circulation control unit 10-22. As will be described further below, this signal PCr is generated when a jump is to take place outside of the normal sequence. In addition, the gate circuit 10-12 is prepared by the signal N and the gate circuit 10-12 «by the signal N delayed by one pulse length. This signal N is also generated by the command circulation control unit 10-22 and indicates that a normal process, such as. B. the command currently stored in the command register 712-1, comes to an end and that the next command contained in the command register IR-2 is to be forwarded to the command register IR-I . If the signal N occurs, the command in the command register IR-2 is relocated to the register IR-I. The signal N , not shown, is used to clear the toggle switch of the command register IR-I so that the command contained in the command register IR-2 can be re-stored.

The ten as well as the 25 flip-flops in the command register IR-I, in which the two / digits or the five iV digits are stored, receive them at time t _s , so that the information is available at time t _e . The 25 flip-flops in the command register //? - !, in which the five M digits are stored, receive them at time t _e , so that the information there is at time i _? is available. The reason why the two parts of the command stored in the command register IR-2 are fed to the command register IR-I at different times can be seen from the description of the conditional jump command.

The ten flip-flops in the command register IR-I, in which the two / digits are stored, have their outputs coupled to the command decryption device 10-17. The command decoder 10-17 is essentially a matrix of gates which receive a number of signals corresponding to the / digits and, under the influence of these signals, energize a single output line. So z. B. for the individual in the last ten flip-flops of the command register IR-I stored signal combinations each energizes a different output line of the command decryption device 10-17. The gate circuits of this command decryption device 10-17 are also coupled with their inputs to the output of the program counter 19, whereby the output line selected by the command decryption device is changed even if the content of the command register IR-I remains unchanged. So z. For example, by a certain combination of command number of the command register IR-I plurality of gate circuits in the instruction decoding means to be prepared, while the program counter in its handoff another, prepared by the present in the instruction register IR I / Numeric gate circuit for transmitting a signal other initiated on one of the assigned output lines of the command decryption device 10-17.

The program counter 10-19 is also used to generate various function table signals used for commands that require multiple operations to perform. Program counter are already known in the art. They are generally designed so that they always then be forwarded when a new part of a

ίο given command is to be executed. The program counter 10-19, which in connection with FIG. 16 is controlled by the function table signals generated by the command encryption device 10-18, the memory-free signal MNB, the recomplement signal PRCP of the command circulation control unit 10-12 and the clock signals of the clock generator 10-23 . When a switch-off signal is generated by the command circulation control unit 10-22, all gate circuits of the command decryption device 10-17 are blocked. This shutdown signal is intended to prevent the command stored in the command register IR1 from causing the generation of function table signals during certain operations of the central processing system. As will be described further below, the switch-off signal is generated in particular during the transfer of control and during certain sections of the arithmetic operations (renewed formation of the complement).

The command decryption device 10-17 is connected to the command encryption device 10-18 for the purpose of controlling the command encryption device 10-18. This command encryption device generates a number of different function table signals for each input signal received from the command decryption device 10-17. The command encryption device 10-18 consists of an array of OR circuits. Some outputs of the command scrambler 10-18 are connected to gates which receive clock signals from the clock, while other outputs of the command scrambler are connected to delay devices. As will be described in connection with the detailed drawings of the decryption and encryption devices 10-17 and 10-18, the function table signals (FIGS. 12 and 12A) can either be present during the entire time in which an instruction is in the instruction register IR -I is stored, or during a certain setting of the program counter 10-19 or during a certain time segment of a small period.

The output signals generated by the encryption device 10-18 are referred to as function table signals and in this capacity are represented in all of the drawings by a circle with a number contained therein. These function table signals are connected to the various parts of the input and output processing equipment, the synchronizing device and the distributor, as well as the magnetic drums and tape devices, etc., in order to operate these devices according to the instructions in the command register //? -! to control the command digits. The five M digits contained in the first 25 of the 60 bistable flip-flops in the command register IR-I are assigned to the one shown in FIG. 3 input of the OR circuit 3-31 shown in detail via the 25 AND circuits 10-14 selectively supplied.

The AND circuits 10-14 are controlled by the clock signal t ₇ and the function table signal FT 701 generated by the command encryption device 10-18. This function table signal FT701 is generated by the command encryption device 10-18 whenever a command contained in the command register IR-I indicates that the M-digits also stored in the command register IR-I drive the memory either for the purpose of extracting an operand or a specific one Look for a memory location in order to store information from the central processing system there. The M digits in the command register IR-I pass through the AND circuits 10-14 at the time t ₇ and are thus supplied to the address decryption device already described via the OR circuits 3-31 at the time t _7. The five iV digits stored in the next 25 flip-flops of the instruction register / jR-1 are fed to the address decryption device via the 25 AND circuits 10-15 and OR circuits 3-31. These AND circuits 10-15 are controlled by the clock signal t ₇ and the function table signal FT 700. The function table signal FT 700 is always generated by the command encryption device 10-18 when the memory is to be controlled by the IV digits of the same command on the basis of the command digits in the command register IR-I.

In addition, certain IV digits are fed from the command register IR-2 to the other registers and decryption devices. The 2V digits can therefore not only be used to control the memory, but also to control other devices in the input and output processing system.

Fig. 10A shows the section of the command register IR-I in which the five iV digits, ie the digits 6 to 10 of a command word, are stored. In the case of the command register IR-2, this section is represented by 25 bistable trigger circuits // 26 to ff 50, the sixth digit of a command word being stored in trigger circuits ff 26 to ff 30, the seventh digit in trigger circuits $ 31 to $ 35, etc. . The output lines of these flip-flops # 26 to FF SO are labeled PR-26 to PR 50.

The sixth and seventh digits of the command word located in the command register IR-I are used for certain input and output commands to identify the tape device to be confirmed, the tape synchronizing device to be selected or the magnetic drum to be used. The output lines PR-26 to Pi? -30 assigned to the flip-flops # 26 to # 30 are individually connected to five gate circuits 10.4-25. The inputs of these five gate circuits are also connected to one another for the purpose of receiving the function table signal FT 809. When the function table signal FT 809 is generated by the encryption device 10-18, the content of the flip-flops # 26 to # 30 (ie the sixth command digit) is re-stored via the gate circuits 10.4-25. The outputs of the gate circuits 10.4-25 are coupled to the input of the B register 10 / 1-27. This B register consists of five flip-flops, each of which can store one information unit of the information contained in flip-flops # 26 to # 30 of the instruction register IR-I. The outputs of the individual flip-flops of the B register 10.4-27 are connected to the decryption device 10 ^ 4-20, which generates a single output signal for one of the ten different digits stored in the B register. In other words: for each of the ten digits possibly located in the B register 10.4-27, the decryption device 10A-29

ίο generates an output signal on the output lines Γ0 to T 9 assigned to it, this output signal corresponding to the digit stored in the B register 10.4-27.

Similarly, the flip-flops # 31 to # 35 containing the seventh instruction digit are connected to the input of the A register 10 / 4-28 via the gates 10 ^ 4-26 controlled by the function table signal FT 809. The outputs of the A register are coupled to the input of the decryption device 10 / 4-30, which operates similarly to the decryption device 10.4-29, the decryption device 10.4-30 entering for each digit in the A register 10 / 4-28 single output signal SO to S9 is generated.

The output lines SO, S1 and 52 of the decryption device 10 / 4-30 and the output lines TO to Γ9 are connected to the input of the decryption device 10 / 1-34. The digits stored in A register 10.4-28 and in B register 10.4-27 together form a two-digit number, with the digit in A register 10.4-28 being the higher value. As a result of the aforementioned connections between the decryption device 10.4-30 and the decryption device 10 ^ 4-34, only the values between 0 and 29 are displayed by the latter. In practice, even fewer output lines are provided for the decryption device 10.4-34. These output lines, labeled PD1 to PD 24, are used to represent the various digits 1 to 24, which are stored in the A and B registers 10 / 1-28 and 10.4-27, respectively. In this context it should also be mentioned that the function table signal FT 809, by which the gate circuits 10 / 1-25 and 10.4-26 are controlled, is used simultaneously to clear the A and B registers 10 ^ 4-28 and 10 ^ 4- 27 can be used.

The flip-flops // 36 to // 40 of the command register IR-I, which store the eighth command digit, are coupled directly to the input of the decryption device 10 / 1-31. The decryption device 10 / 1-31 also generates a single output signal for each digit stored in the flip-flops // 36 to // 40, which among other things designates the magnetic drum synchronization device which is to be used for a specific operation.

The information stored in the flip-flops // 26 to // 35 can only be fed to the A and B registers 10 / 1-28 or 10 / 1-27 via the gate circuits 10 / 1-25 or 10Α-2Ί when the function table signal FT 809 is generated, ie a specific command causes this relocation. The direct connection of the flip-flops // 36 to // 40 to the decryption device 10 / 1-31 also results in the eighth digit of each command from the decryption device 10 / 1-31 in the command register IR-I

is decoded and a corresponding signal is generated on the output lines PSO to PS. 9 In this way, 10 Λ-28 or 10 / 1-27 digits can be stored in the A and ß registers which do not belong to the information currently contained in the flip-flops // 26 to // 35, provided that the Gate circuits 10,4-25 and 10 / 4-26 were previously opened by another command. The output signal of the decryption device 10 , 4-31, on the other hand, always represents the eighth command digit currently in the command register IR-I.

The flip-flops // 41 to // 45 and the flip-flops // 46 to // 50 of the command register IR-I, which store the ninth and tenth digits of the command, are directly connected to the shift decryption device 10, 4-32 . This shift-decryption device 10 / 1-32 is in turn connected to the arithmetic control unit 10-42 to be described later and the counting gate circuits 10 / 1-33 . The outputs of the counting gate circuits 10, 4-33 are fed back to the inputs of the flip-flops // 41 to // 45. These counting gates are controlled by the output signal of the AND circuit 10, 4-34, the input of which is controlled by the function table signal FT 615 and the shift signal from the arithmetic control unit 10-42 .

Like F i g. 10 shows, in addition to the signals from the two sections of the command register IR-I, which store the M and JV digits of a command, the address decryption device described earlier also receives signals from three other devices via the OR circuits 3- 31, namely a five-digit address from one or both arithmetic units, from the distributor (FIG. 37) and from the control counter 10-35 shown in FIG. The distributor and the arithmetic unit will be described later in detail, but it can already be seen from the drawing that the distributor controls the memory via the common address decryption device, so that information between the memory and the various input and output devices can be exchanged. It can also be seen from the drawing that the arithmetic unit also controls the memory via the common address decryption device, so that it can receive operands and commands from the memory and, conversely, store results obtained there by arithmetic operations.

The control counter 10-35 of the central processing system (FIG. 10) is used to query the memory for commands to be executed by the central processing system. The control counter 10-35, shown only as a block, can consist of a storage register and an adder, which increases the content of the storage register by one each time a signal is present from another device. The control counter 10-35 stores a five-digit number which can be fed to the common address decryption device via 25 AND circuits 10-36 and 25 OR circuits 3-31. The AND circuits 10-36 forward the output signal of the control counter at the time t ₇ on receipt of a clock signal generated by the clock generator and in the absence of a function table signal FT 600 from the command encryption device 10-18. The function table signal FT 600 is always generated when a command in the command register IR-I requires the use of the memory. If the central processing system controls the memory for the purpose of an operand designated by a command from the command register IR-I , the AND circuits 10-36 are blocked so that the output signal of the control counter cannot control the memory. When a signal is present from the command circulation control unit 10-22, the control counter 10-35 is incremented, ie its content is increased by one in each case. In general, the control counter is always switched on by the command circulation control unit 10-22 when the central processing system has successfully activated the memory due to a previous command.

The control counter 10-35 takes commands for the central processing system from the successive addresses in the memory. This withdrawal takes place in accordance with the number stored in the tax meter. If the counter z. If, for example, set to store a "1" at the beginning, the first command to be taken is taken from memory location 1, the second command from memory location 2, and so on. Normally, this successive command extraction is retained. In the course of certain operations of the input and output processing system (e.g. during the execution of a transfer of control command), however, it is sometimes useful to change this normal sequence when a certain event occurs. In such a case, the M-digits of the command are then transferred from the command register IR-2 to the control counter 10-35. The commands are then taken from new memory locations which correspond to the new number stored in the control counter 10-35. Adding one to the new number increases the content of the control counter (the new number corresponds to the value of the M digits).

It can be seen from the drawing that the outputs of the flip-flops // 1 to // 25 of the command register IR-I, which store the M digits of a command, are connected to the input of the control counter 10-35 via 25 AND circuits 10-37 are. The other input of the AND circuits is controlled by the signal PCT from the command circulation controller 10-22, which is fed to the AND circuits via the OR circuit 10-60. The signal PCT is generated by the command circulation control unit 10-22 when the sequence in which the commands are taken, which is determined by the content of the control counter 10-35, is to be interrupted. The OR circuit 10-16 is also connected at its input to the output of the AND circuit 10-61, which _{receives a signal f 0} from the clock generator and also a function table signal FT 613 which was generated during an unconditional detonate command to be described. The content of the first 25 flip-flops of the instruction register / Ä-1, which represents the M digits of an instruction, can thus be fed to the control counter 10-35 via the AND circuits 10-37 either during the execution of the instruction through which the function table signal FT 613 was generated, or when the output signal PCT of the command circulation control unit 10-22 is present.

The output signal of the control counter 10-35 is generally supplied to the address decryption device via the AND circuits 10-36 in order to drive the memory. Sometimes, however, the output signal of the control counter is also sent to the memory in order to be stored there. This latter case occurs when the content of the control counter 10-35 is to be stored in the memory for certain reasons. It can be seen from the drawing that the output of the control counter is connected to an input of 25 AND circuits 10-39, the outputs of which are coupled to the write lines HSB-W. The AND circuits 10-39 are also _{controlled by the clock pulse i 4} generated by the clock generator 10-23 and by a function table signal FT 708. This function table signal FT 708 is generated by the command encryption device 10-18 when a return command is stored in the command register IR-I . This return command, which is described in detail further below, causes the M-digits in the command register IR-X to be re -stored in the control counter 10-35, with the content of the control counter as part of a new command in the N-digit memory location marked remote from the command is stored. The five digits, which are re-stored in the memory by the control counter via the AND circuits 10-39, form the five least significant digits of a command. The remaining seven most significant digits of the instruction to be stored in the memory are taken from a register 10-38 in which the seven digits 0500000 are stored. This register is also connected to the write lines via 35 AND circuits 10-40 _{, which are controlled by the same two signals, the clock signal i 4} and the function table signal FT 708, which also control the AND circuits 10-39 at the same time. If the function table signal FT 708 is generated at the time i ₄ on the basis of a command in the command register IR-I , the digits 0500000 and the content of the control counter (five digits) are coupled to the write lines in order to be written into the memory. As will be described in connection with the return command, the iV digits of this command located in the command register IR-I designate the memory location in which the command composed of the digits 0500000 and the five digits of the control counter is to be stored. The digits 05 from register 10-38 form the most significant digits of the command and thus designate a specific command to be carried out. Command "05" is an unconditional jump command that changes the contents of the memory so that it corresponds to the five lowest digits of command 05.

After the path that a command travels when it occurs on the write lines at time t _{7 has been} described, the path for the data will now be briefly described that also occur on the lines at time t ₇ - but during a different short period.

For this purpose, it is assumed that the command contained in the command register IR-I has activated a specific location in the memory, identified by the M or IV digits of this command, for the purpose of processing data. The data taken from this memory location appear on the read lines at time t ₇ and are fed to the inputs of AND circuits 10-24, 10-25 and 10-20. However, the data cannot pass through the AND circuit 10-10 and from there into the command register IR-2 , since the command circulation control unit 10-22 does not generate a pass signal for this data. In contrast, the command contained in the command register IR-I , which has activated the memory, causes the command encryption device 10-18 to generate the function table signal FT 705 or FT 707, which is fed to the AND circuits 10-25 or 10-24 will. Depending on the type of instruction that caused the removal of data from the memory, either the function table signal FT 705 or FT 707 is generated, whereby either the AND circuits 10-25 or 10-24 are opened and the information appearing on the line forward onto. The AND circuits 10-25 and 10-24 have their outputs at the inputs of the registers RP-I and RP-2, which store the 60 information units. As will be described later in connection with FIGS. 14A, 14B and 14C, the information units appearing on the read lines HSB-R are all supplied to the registers in parallel. The contents of the registers RP-I and RP-2 can also be stored back into the memory in parallel via the AND circuits 10-45 and 10-46. In addition to the content of the register RP-I, which is fed to the AND circuits 10-45, these are controlled by the function table signal FT 703 _{occurring at the time i 4} , while the AND circuits 10-46 are controlled by the signal FT 703 that also occurs at the time t _t Function table signal FT 710 must be prepared. If the content of the register RP-I is to be stored in the memory again, the function table signal FT 703 is generated, while if the content of the register RP-2 is stored again in the memory, the function table signal FT 710 is generated. Both registers can be connected to one another so that the contents of the register RP-I can be transferred to the register RP-2 . This restoring process is controlled by the AND circuits 10-49, which in turn are opened by the function table signal FT 606.

The content of the register RP-I can be fed to the adder-comparison unit 10-41 via the AND circuits 10-47 and 10-48, which are controlled by the function table signal FT 504 or FT 508 generated by the encryption device 10-18. The content of the register RP-2 , on the other hand, can be fed to the adder-comparison unit via the AND circuits 10-65, which are controlled by the signal shifting the content of the register RP-2. If an addition or subtraction is to be carried out on the basis of the command contained in the command register IR-I , the content of the two registers RP-I and RP-2 is sent to the adding-comparator 10-41 via the AND circuits 10-47 and 10, respectively -65 fed. The result can then be stored back into the register RP-I via the line 10-41 α and the AND circuits 10-53. As can be seen from the drawing, the AND circuit 10-53 is controlled by the function table signal FT 500, the respective

509 538/373

43 44

is then generated as soon as an instruction requires that Hch in correspondence with the result of an arithmetic operation in the instruction register in which the instruction contained in IR-I operation carried out soden registers RP-I and RP-2 contained digits, depending on which sign who are involved in the process, are to be stored in the register RP-I , registers RP-I and RP-2 stored digit values. Like F i g. 10 also shows, will have 5, the computer control unit generates or does not generate the sign of the element signal in the registers RP-I and RP-2. Show the digits contained in the arithmetic logic unit 10-42, for example, the radio sent to the arithmetic unit control unit via the lines 10-62 and 10-63. In the case of table signals, it indicates that an add instruction is carried out by executing one in detail below and that the arithmetic control unit 10-42 has written a further complement formation for those in registers RP-I and RP-2 , the contents of register RP- I determine the AND-switch digit values with different signs 10-48, while the zeros above the AND- places, the complement signal CP is generated. Circuits 10-66 are used. This AND and the adder comparison unit 10-41 fed. Circuits 10-66 are controlled by the function If the control unit detects that the table signal FT 508 is subtracted. 15 the number of digits in registers RP-I and RP-2

In addition to those coupled to the line 10-41 α have the same signs, then likewise

Sum or difference signals are generated by the Ad- the complement signal CP. Because of this

dier-comparison unit 10-41 nor the final carry complement signal becomes the adding-comparison unit

signal FC and a signal EQ are generated. The signal 10-41 causes the complement to the operand

FC is generated on the basis of an instruction at which 20 to form that which it receives from register RP-2 , and

the content of the register RP-I with that of the register before the two numerical values from the re-

RP-2 is to be compared. This signal shows when RP-I and RP-2 are added together. To the

Such a comparison suggests that the content of the re-skilled person should be clear that by the formation

register RP-I larger than the content of the register of the complement to one of two

üuP-2 is. The absence of the FC 25 signal adding operands to the difference between the

is effected when the two operands in the registers sen and not their sum

RP-I and RP-2 contained numerical values is shifted.

The arithmetic control unit 10-42 also generates the or if, after the subtraction has been made, the storage or shift signals that have both digit values with the same sign are fed to the registers RP-I and RP-2 . The absence of this signal FC The content of these shift signals means that the result obtained from the two registers has to be processed further from one register to the, in particular that the grain has to be re-stored or the addition / comparison supplement has to be created for this purpose. plant 10-41 or only within a

The signal EQ is re-stored by the comparison device 35 and the same register. The that of the adder comparison unit 10-41 generates. The signal supplied to the two arithmetic control unit 10-42 by the digitization decryption device 10.4-32 (FIG. Values are not only processed arithmetically, but 10A) is also compared with one another during the execution. If, when a relocation command is received, it is indicated that the comparison found that both digit values 4 ° in the register RP-I or RP-2 operand are equal to one another, a signal EQ is generated in order to determine the value indicated by the in the command register IR-I If the amount determined further below in connection with the hold command is shifted, the comparator is described. These signals has been made.

FC and EQ are fed to the arithmetic control unit 10-42. The operations of the central processing system, which thereupon a conditional jump signal 45, run after a certain cycle, both of which and a complement signal generated. Both signals taken from the successive memory signals, conditional jump signal and recomplement points in the memory and executed are sent to the command circulation control unit 10-22. The command cycle is passed to the central processing system to cause the system to consist of the control operations, the command 50 located in the command register IR-I , in order to keep one there from the memory if necessary, until the complement to the The command has just been called off and this command has been created again for the purpose of calculating the result. lead to the command registers. The loading

In addition, the arithmetic control unit 10-42 has the task of erroneous circulation control unit 10-22

yet another signal is generated to perform the complement- this command cycle. With all of them

signal. From the drawing it can be seen that there are 55 commands from the command circulation control unit

Arithmetic controller information from registers 10-22 to perform the following three basic operations

RP-I and RP-2 are fed. As will lead later:

is described, the computer control unit the ". _. ,, _.

Sign of the in registers RP-I and RP-2 ^L Activate the memory and store the

stored digit values via lines 10-62 60 command queried m a buffer

and 10-63 supplied. The computer control unit itself register IR-2;

is also controlled, by a · ² to end the previous command and initiating

this time in the command register IR-I stored the new command by Umspeichem the

th command. The new command from the buffer register due to this in the command register

IR-I contained command from the encryption 6 ₅ IR-2 in the main command register IR-2 and

device 10-18 generated function table signal 3.

So also control the arithmetic control unit 10-42. In speaking of the address of the following command

Depending on a reference to the momentary adjust.

As will become apparent from the description, the above-mentioned control processes overlap for the commands in time. In addition, common control flip-flops are used for these control operations and logic circuits are provided. During operation, the commands are taken from the memory (Fig. 9 A, 9 B and 9 C) in accordance with the content of the taxpayer 10-35 in turn taken. The 25 information units that correspond to the digits stored in the tax meter, are the address decryption device 10-64 via 25 AND circuits 10-36 and OR circuits 3-31 supplied.

The digits sent to the address decryption device 10-64 by the control counter select the memory location from which the first command, marked "/", is to be taken. The AND circuits 10-36 are controlled by a signal from the instruction circulation control unit 10-22 which - as will be described later - is generated when a new instruction is to be stored in the instruction register IR-2. This signal generated by the command circulation control unit is fed to the AND circuits 10-36 at time t _{7 for} a short period. The AND circuits 10-36 are blocked by the function table signal FT 600, which is generated by all commands in which data is to be queried from the memory or written into it. It can be seen from the drawing that the AND circuits 10-14 and 10-15, with the aid of which the M or iV digits of a command can control the memory for the purpose of extracting data, are also opened at time t ₇ . The memory addresses controlled by the M and JV digits therefore have priority over the addresses controlled by the taxpayer. The content of the control counter 10-35 can therefore be coupled to the address lines of the memory optionally via the AND circuits 10-36 and OR circuits 3-31 at time t _{7 during the first short period.} A memory-free signal MNB generated by the memory, which indicates the successful activation of the memory by the control counter, is fed to the command circulation control unit 10-22, whereby the incremental signal for the control counter 10-35 is generated by this control unit. This incremental signal increments the control counter 10-35 by one at the point in time ^ of the second short period. From the description of the memory it follows that the content of the memory, ie the first command that was triggered by the control counter, appears on the read line HSB-R at time t _{7 of} the next, ie the second short period. At the same point in time t _{7 of} the second short period, the content of the control counter 10-35 increased by one can control the memory for the purpose of interrogating the second command / + 1 via the AND circuits 10-36. This second command then appears on the read lines HSB-R at time t _{7 of the third short period.} The 60 information units of the first command are fed from the read lines HSB-R via 60 lines of the pulse delay device 10-21 to the inputs of 60 AND circuits 10-10. In the third short period, the AND circuits 10-10 are opened by a clock pulse t ₀ and an output pulse of the command circulation control unit 10-22 appearing on the line 10-22. This latter signal indicates that an instruction is awaiting from memory. The first command "/" is therefore stored in the 60 flip-flops in the command register IR-2 via the AND circuit 10-10. The 35 flip-flops, in which the seven most significant digits of the command, i.e. the two / digits and the five iV digits are located, are individually connected to 35 gate circuits 10-12, which are triggered by the signal JV of the command circulation control unit 10 -22 and become conductive by a clock signal t _5. The five M-digits, on the other hand, are coupled to the inputs of the 25 AND circuits 10-12 ", which are opened by the clock signal t _e and the signal JV delayed by one pulse length. The signal JV indicates that there is an instruction in the instruction register IR-2 and that the currently executed instruction, ie the instruction contained in the instruction register IR-X , has ended within a short period. The signal JV therefore causes the command from the command register IR-2 to be re-stored in the command register IR-X. This re-storage is ended at time t _{7 of} the third short period.

The previously called up command / + 1 is known to be stored at the same time, ie at time i ₀ , of the fourth short period under the influence of the command circulation control unit 10-22 as the command / described above.

In the fourth short period, the first command / is in the command register IR-X and can be carried out. At the same time, the second command is in command register IR-2 and is waiting to be re-stored in command register IR-X.

The two / digits of the first command are fed to the command decryption device 10-17. In this way, the command encryption device 10-18 is energized via one of the output lines of the command decryption device 10-17 and in turn generates the function table signals required to carry out the command. Let us assume first that the command included in the instruction register IR-X requires an operand, the memory location labeled is located in the memory at the M digits by this command that the operand to the instruction register IR-X and then secondly so marked for Adder-comparator 10-41 is to be transported for processing and that, thirdly, the time required to execute this instruction takes more than a short period and a number of different operations.

The M digits, which designate the memory location in which the operand is located, pass through the AND circuits 10-14 at time t ₇ , since the function table signal FT 701 from the command encryption device 10-18 on the basis of the / digits of the command stored in the command register IR-X is generated. The same command also causes the generation of the function table signal FT 600, which inter alia blocks the AND circuits 10-36 so that the output signal of the control counter 10-35 cannot reach the address decryption device and from there to the memory. Will the memory by the M-digits. of the commands contained in the command register IR-X are successfully controlled (Figs. 3, 8 and 9), the memory-free signal MJVJ5 is generated by the memory, which, among other things, continues the program counter 10-19.

switches. This program counter 10-19 causes a new output line to be energized by the command decryption device 10-17 and the command encryption device 10-18 thereby to generate further or new function table signals. These additionally generated function table signals also include the function table signal FT705, which is fed to the 25 AND circuits 10-25 which connect the read lines HSB-R to the register RP-I . Depending on the type of instruction in the instruction register IR-I , further function table signals are generated in order to control the clock generator 10-23, the registers RP-I and RP-2, the adder-comparison unit 10-41, the arithmetic control unit 10-42 and the instruction circulation unit. Control unit 10-22 to control. In the last phase of a command to be carried out, a function table signal EP is generated by the command encryption device 10-18 under the influence of the program counter 10-19 and the command register IR-I and at the same time the function table signal FT 600 is switched off. This function table signal EP is fed to the command circulation control unit 10-22 and causes this unit to generate the signal JV. The program counter 10-19 is cleared by the signal JV. At the same time, as a result of this signal, the next command contained in the command register IR-2 is relocated to the command register IR-X. Since the function table signal FT 600 is no longer switched on, the control counter 10-35 can now query the memory for the third command.

For a better understanding of the mode of operation of the central processing system, reference is now made to the Detailed drawings of the in F i g. 10 works illustrated are referred to. The first work is below the command circulation control unit 10-22 described, which essentially the timing of the individual Operations of the computer under the influence of other devices in the central processing plant controls generated signals.

Command circulation control unit

FIG. 11 shows, in the form of a block diagram, the instruction circulation control unit 22. As in this figure As can be seen, the command circulation control unit consists essentially of the four flip-flops 10-4, 11-3, 11-2 and 11-1, which show the timing of the operations for the central processing plant steer. These flip-flops are the same type of bistable devices that are already used previously described.

In the normal course of operation, a signal fed to the setting input of the bistable multivibrator 11-4 indicates that the control counter 10-25 has successfully scanned a command and that this command appears on the read lines approximately a short period thereafter. The flip-flop 11-4 is toggled into its set state by a signal from the OR circuit 11-23. This OR circuit 11-23 is connected at its inputs to the AND circuits 11-21 and 11-22. The AND circuit 11-22 is made conductive by the memory-free signal (i ₂ ) and by the setting output signal of the flip-flop circuit 11-2, which is fed to the AND circuit via the OR circuit 11-16. The AND circuit 11-22 can also be disabled by the function table signal FT 600, which - as already mentioned - is generated by all instructions which require access to the memory. The flip-flop 11-2 generates a set output when a currently executing command (ie, the command stored in the command register IR-I ) expires within a short period. The memory-free signal (i ₂ ) is generated when the memory is free and a clock signal t _{x is} coupled to the AND circuit 11-42. The output of the AND circuit 11-42 is with

ίο a pulse delay device 11-43 connected, which works with a delay of one pulse length. The memory-free signal MNB (i ₂ ) is generated by this pulse delay device at time i _2. The AND circuit 11-21 controlling the flip-flop 11-4 receives the function table signal FT 613 and the memory-free signal MNB (t ₂ ) at its input. The function table signal FT 613 is generated by the unconditional jump and return commands, which cause control to be transferred to other devices, so that the normal course of the individual arithmetic operations is interrupted.

The flip-flop 11-4 is reset by an output of the OR circuit 11-33. At the inputs of this OR circuit are the clock signal i ₀ , the signal RCP generated by the circuit in FIG. 26 and that of the circuit in FIG. 28 generated signal PCTA . The signal RCP is generated at time t _s (pt 13) and indicates

that a renewed correction of the result obtained by an addition or subtraction is necessary. The signal PCTA is generated at time t _e (pt 14) and indicates that a command transfer has to take place as a result of an operation or a check of the input and output device.

The setting output of the flip-flop 11-4 is connected to the AND circuits 10-10 (FIG. 10) and to one input of the AND circuit 11-25, which also receives the clock signal t _{0 at its other input.} As already described in connection with FIG. 10, the AND circuits 10-10 are opened by the command circulation control unit 10-22, in particular by the toggle circuit 11-4, so that commands can pass from the memory into the command register IR-2 . The setting output of the flip-flop circuit 11-4 is also connected to one input of the AND circuit 11-39, the output signal of which advances the control counter 10-35.

In the short period following the setting of the flip-flop 11-4, a signal from the AND circuit 11-25 is fed _{to the setting input of the flip-flop 11-3 at time i 0.} As a result of this signal supplied by the AND circuit 11-25, the flip-flop circuit 11-3 generates an adjustment output signal at the time t _t , which is supplied to the AND circuit 11-29. The setting of the flip-flop 11-3 indicates that the required command, which generated the memory-free signal MJVi3, whereby the flip-flop 11-4 was set, is now in the command register IR-2 . The AND circuit 11-29 also receives two further pass signals, the clock signal t _s and the setting output signal of the flip-flop II-2. The AND circuit 11-29 is blocked by the signal RCP. The output signal JV of the AND circuit 11-29 is the AND circuit 10-12 as well as the input of a pulse delay

10-12 b supplied, which works with a delay of a pulse length and whose output is connected to an input of the AND circuit 10-12 α. If the AND circuit 11-29 generates a signal on the basis of the output signals of the flip-flops 11-3 and 11-2, this indicates that there is an instruction in the instruction register IU-2 and that the instruction currently being executed, ie that in the instruction register IR-I stored command, is about to end. Since the AND circuit 11-29 is connected to the AND circuits 10-12 and 10-12 «, an output signal from this AND circuit causes the command in the command register IR-2 to be transferred to the command register IR- I is relocated.

The reset input of the flip-flop circuit 11-3 is connected to the output of the OR circuit 11-28, at the inputs of which the signal N generated by the AND circuit 11-29 and the signal of the AND circuit 11-27 are present. If the function table signal FT 613 generated by the unconditional transport and return commands and the clock signal I ₁ generated by the clock generator (FIG. 15) are present at the inputs of the gate circuit 11-27, an output signal is generated by this AND circuit. If a command contained in the command register IR-2 is re -stored in the command register IR-I , the toggle circuit 11-3 is reset and thus indicates that there is no more command in the command register IR-2. The reset output of the flip-flop 11-3 is connected to the inputs of the AND circuits 11-39 and 11-40, which in turn are connected at their outputs to the OR circuit 11-38. At the inputs of the AND circuit 11-39 are not only the reset output signal of the flip-flop 11-3 and the setting output signal of the flip-flop 11-4, but also the clock signal ί ₆ as a forward signal. The gate circuit 11-39 can also be blocked by the signal PCTA. If the toggle circuit 11-4 is in its setting state and the toggle _{circuit 11-3 is in its reset state, an output signal is generated by the gate circuit 11-39 at the time i 6} , which is sent to the control counter 10-35 via the OR circuit 11- 38 is supplied to switch this further. At the inputs of the AND circuit 11-40, in addition to the reset output signal of the flip-flop circuit 11-3, the clock signal I ₁ (memory free signal MNB) and the function table signal FT 617 generated for all unconditional return commands are also present. The output signal generated by the gate circuit 11-40 is fed to the control counter 10-35 via the OR circuit 11-38 in order to increment the counter.

The reset output of the flip-flop 11-3 is also connected to an input of the gate circuits 11-17 and 11-22 via the OR circuits 11-16. The AND circuit 11-17 receives the pass signal t _e from the clock. In addition, this AND circuit can be blocked by a signal PCTA. The output of the AND circuit 11-17 is connected to a pulse delay device 11-18, which operates with a delay of one pulse length and at time t ₇ generates an output signal which is sent to the input of the gate circuits 10-36 (FIG. 10). is fed. As is known, the control counter 10-35 is connected to the address decryption device 10-64 through these gate circuits 10-36. As shown in FIGS. 10 and 11, the control counter 10-35 can drive the memory at time t ₇ , provided, first, that the flip-flop 11-3 is in its reset state, indicating that there are currently no instructions in the instruction register IR-2 is that, secondly, there is no instruction in the instruction register IR-I which requires access to the memory, ie

ίο that the function table signal FT 600 is not present and, thirdly, that the AND circuit 11-17 is not blocked by the signal PCTA , ie that no jump takes place.

As is known, an output signal from the gate circuit 11-22 turns the flip-flop 11-4 into its set state. The memory-free signal MNB (t ₂ ) and the function table signal FT 600, which acts as a blocking signal, are present at the inputs of this gate circuit. The flip-flop 11-4 is thus set via the AND circuit 11-22 when the above conditions apply and the memory-free signal MNB (t ₂ ) is present, indicating that an instruction has been taken from the memory.

If the flip-flop 11-2 is in its set state, this indicates that the command currently in the command register IR-I will expire within a short period. The setting input of this flip-flop 11-2 is at the output of the OR circuit 11-36. Of the five inputs of the OR circuit 11-36, four are connected to the output of the AND circuits 11-31, 11-32, 11-34 and 11-35, while the fifth input of this OR circuit 1-36 has the Signal PCTA , which is generated by the circuit shown in FIG. 28, is coupled.

These four AND circuits, hereinafter referred to as "end pulse AND circuits", are controlled by signals from the command cipher 10-18 generated during the final phase of an command. _{The clock signal ί 7} and the function table signal FT 614 are present at the inputs of the end pulse AND circuit 11-34. This function table signal FT 614 is generated for all commands that only require a short period of time to be executed. The final pulse AND circuit 11-34 can e.g. B. used in conjunction with commands that check the status of the individual input and output devices as well as individual accounting commands.

The memory-free signal MNB (t ₂ ) and the function table signal F Γ709 of the command encryption device 10-18 are present at the inputs of the end pulse AND circuit 11-35. This final pulse AND circuit is used in connection with a write operation in which information from the registers RP-I, RP-2 or from the control counter 10-35 (FIG. 10) is to be written into the memory. It can be seen from the drawing that the final pulse AND circuit 11-35 is controlled by a signal which is derived from the memory-free signal MNB (t ₂ ) . The writing process can therefore only begin when the memory for the information to be written is available.

The function table signal PT 615, the

509 538/373

Clock signal t ₇ as well as the signal PSR 3 X generated by the displacement decryption device 10-32 associated with a portion of the instruction register IR-I which stores the ninth and tenth instruction digits. The generation of the PSR3X signal is discussed in connection with FIG. 13 A described in detail. For the moment it is sufficient to know that when the signal PSR3X was generated, the information of the register RP-I or RP-2 to be relocated on the basis of the instruction contained in the command register IR-I has been almost completely relocated. The final pulse AND circuit 11-31 is only used in connection with the shift or relocation command to be described later.

At the inputs of the end pulse AND circuit 11-32 are the clock signal t ₅ , the function table signal FT 610, the signal N generated by the AND circuit 11-29 and that of the in FIG. AND circuit 26-10 shown in FIG. 26 generates signal RCP . The last two signals mentioned are used to block the final pulse AND circuit 11-32, while the first two signals open this AND circuit when switched on at the same time and thus cause it to generate an output signal. The final pulse and circuit 11-32 is used in conjunction with the accounting instructions (add, subtract, compare, etc.) to be performed by the central processing facility. Several time intervals are required to execute these commands. The function table signal FT 610 is therefore only generated after the last time interval required for such a command. The program counter 10-19, which is used when executing these commands, therefore has the task of not causing the generation of the function table signal controlling the end pulse AND circuit 11-32 until the last phase of the command has been executed.

The setting output of the bistable flip-flop 11-2 is connected directly to one input of the AND circuits 11-29 and 11-14 and to one input of the AND circuits 11-17 and 11-22 via the OR circuit 11-16 . The effect of an output signal that is fed from the OR circuit 11-16 via the AND circuits 11-17 and the delay device 11-18 to the control counter 10-35, as well as the effect that this also has via the AND circuit A 11 -22 routed signal to the flip-flop 11-4 have already been described. The digits in the control counter 10-35 can control the memory, firstly when the command currently in the command register IR-I is executed within a short period, ie when the toggle switch 11-2 is set, secondly when the command contained in the command register IR-I Command does not require access to the memory, so the function table signal FT 600 is not present, and if, thirdly, the AND circuit 11-17 is not blocked by the signal PCTA. It also follows from this that the flip-flop 11-4 is toggled into its setting state via the AND circuit 11-22 when the flip-flop 11-2 is set. In addition, the result is that the memory-free signal MNB (i ₂ ) is present at the input of the AND circuit 11-12, whereas the function table signal FT 600 is not present.

In addition to the one input of the AND circuit 11-14, which is connected to the output of the flip-flop 11-2, this AND circuit also contains three further inputs to which the clock signal t ₅ and the blocking signals N or RCP are present. The blocking signal RCP is generated by the arithmetic control unit 10-42 shown in FIG. 26 and indicates that a result which has just been calculated in the adder-comparison unit still has to be corrected. The signal N

ίο is known to be present at the input of the AND circuit 11-29 when there is an instruction in the instruction register IR-2 and the instruction currently contained in the instruction register IR-I is executed within a short period.

The flip-flop 11-2 is reset by the signals N or RCP, which are fed to the inputs of the OR circuit 11-37, which is connected at its output to the reset input of the flip-flop 11-2.

The toggle circuit 11-1, also known as the switch-off toggle circuit, is set by the output signal of the AND circuit 11-13, which in turn receives the following input signal: the signal PCT, the output signal of the OR circuit 11-14 and

as the output of the AND circuit 11-15.

As already mentioned, the adjustment output signal the shutdown toggle 11-1 all gates in the command decryption device 10-17 blocked.

The PCT signal is generated when a command to transfer control occurs (while commands 05, 14, 18 or 19 are being executed). This signal sets the flip-flop 11-1 so that an instruction cannot be executed until the new instruction identified by the iV digits of the transport instruction has been re-stored in the instruction register IR-I for the purpose of its execution.
In the normal process, after the command contained in the command register IR-I has been executed, a new command is transferred from the command register IR-2 to the command register / jR-1. However, if no new command can be stored in the command register IR-I because the command register IR-2 has received no command at all, the switch-off toggle must be set to prevent the old command contained in the command register IR-I from still run once.
The shutdown toggle is set by the output of the AND circuit 11-14 through the OR circuit 11-13 at time / ₀ when the toggle 11-2 indicates that the instruction currently in the instruction register IR1 has ended within a short period goes, and when the flip-flop 11-3 indicates that there is no command in the command register IR-2 (that is, the signal N is not present). If, on the other hand, the result has to be corrected again, the switch-off signal must not be generated, since otherwise the command contained in the command register IR-I would be terminated too early. For this purpose, the signal RCP is connected to the AND circuit 11-14, whereby this is blocked and the command contained in the command register IR-I can control the computer control unit during any correction that may be required.

Through the AND circuit 11-15, the inputs of which are connected to the switch 11-44 and the output of the AND circuit 11-29 (signal N) ,

the flip-flop 11-1 is set via the OR circuit 11-13. Should the computer be switched off synchronously the off switch 11-44 is closed and thereby prepares the AND circuit 11-15 before. Then occurs at the output of the AND circuit 11-29 due to the setting of the toggle switch 11-2 the signal JV on, the switch-off toggle switch can be set, since in this An order has just ended at the moment.

The shutdown toggle is reset by an output of the OR circuit 11-11. At the inputs of this OR circuit 11-11 are the signal JV and the output signal of the switch 11-45, which is passed through the one-pulse generator 11-10. This one-pulse generator 11-10 is controlled by a clock signal t ₅ , so that when the switch 11-45 is closed, a single pulse is switched on to the OR circuit 11-11 at time t ₅ . The on / off switch is used to initiate the arithmetic operations synchronously if a command is already stored in the command register IR-I. The switch-off toggle circuit 11-1 is reset by the signal JV supplied to the OR circuit 11-11 if it was in the set state as a result of the generation of the signal PCT or an output signal of the AND circuit 11-14.

Figures HA and HB are timing charts showing the signals generated by the devices shown in Figure 11 during various short periods. A total of eleven short periods are shown, the first two short periods showing the signals that occur when the computer is switched on. The next four short periods indicate the state in which the memory is occupied when the central processing system triggers it for a command. The seventh and eighth short periods indicate the state in which an instruction contained in the instruction register IR-I requires the removal of an operand from the memory and takes precedence over the removal of the next instruction, which is identified by the digits contained in the control counter 10-35 is. The ninth and tenth short periods show the timing of an unconditional handover of control. On the left-hand side of Fig. HA the signals are listed which are stored by the various registers, as well as the signals which are generated by the devices of the central processing plant. So is z. For example, the top line in FIGS. HA and HB is labeled "Command register IR-2 contains", the waveform next to it representing the content of the command register IR-2 . The second and third lines show the content of the command register IR-I and the content of the control counter 10-35. In the first short period, the command register IR-I thus contains the first command to be executed (/); the instruction register IR-2 contains the second instruction to be executed (/ + 1), and the control counter 10-35 contains the memory address of the third instruction (/ + 2), this memory address being indicated in brackets in line 3 of FIG. 11A. The fourth line indicates the point in time when the content of the control counter 10-35 can be fed to the address decryption device via the AND circuits 10-36 in order to drive the memory on the basis of an instruction. The fifth line shows the time at which this address appears on the address line leading to the memory. Lines 6 and 7 indicate the cycle times t at which the memory-free signals MNB and MNB (t ₂ ) are generated as a result of successful activation of the memory for the purpose of removing an operand or command.

Lines 8 and 9 indicate the time at which a command is transported via the gate circuits 10-10 to the command register IR-2 or at what time data (an operand) is transferred to the register RP-I (or RP-2) the AND circuits 10-25 (or 10-24) are stored.

Lines 10, 11, 13 and 16 show the times at which the flip-flops 11-4, 11-3, 11-2 or 11-1 generate an adjustment output signal. In this connection it should be mentioned that the setting output signal of the flip-flops one pulse length after the setting input signal has been switched on is produced. In the twelfth line of FIGS. HA and HB, the times are shown at which the end pulses are generated by the instruction currently in the instruction register / R-I. The AND circuit (AND circuits 11-32, 11-31, 11-34 or 11-35) that the relevant End pulse generated is indicated in the timing diagram next to the end pulse. For example the end pulse occurring in the first short period is generated by the AND circuit 11-34.

Line 14 indicates at what point in time the signal JV from the AND circuit 11-29 as a function is generated from the state of the flip-flops 11-3 and 11-2. Line 15 indicates to at what point in time the control counter 10-35 switched on will, d. H. at what point in time its content is increased by one.

As the timing diagram shows, the command register IR-I contains the first command / to be carried out in the first short period. In the same short period, the command register IR-2 contains the second command / + 1, and the control counter 10-35 contains the address of the third command / + 1, i.e. the numerical value 00003. These devices are set to the state just described by (not shown) switches connected to the facilities. In addition, toggle switch 11-3 is manually set to indicate that there is an instruction in instruction register IR-2 . It is also assumed that only a short period is required to execute the command / now contained in the command register IR-I and that this command does not require the removal of an operand from the memory. As line 4 of the timing diagram in Fig. HA shows, the control counter 10-35 can control the memory via the AND circuits 10-36 at the time ^ of the first short period. The addressed address, which is shown as memory location 00003 or 3, appears on the address lines at time t ₀ . Assuming that the memory location containing the M address is not occupied, the memory-free signal MNB appears at time t _{t (line 6).} This signal is fed to the delay device 11-43 via the AND circuit 11-42, so that the memory-free signal MNB (t ₂ ) (line 7) is generated. This memory-free signal MJVB (t ₂ ) is fed to the setting input of the flip-flop circuit 11-4 via the AND circuit 11-22. This AND-scarf

55 56

As is known, device 11-22 is opened when the command contained in the command register command register IR-I at point t _{0 of} the second period does not store any access IR-2 . It should be noted that at the time the memory is requested (the function table signal point t _{0 of} this second short period, the setting FT 600 is not present) and if either no output signal from the flip-flop 11-4 is still pending, the command is contained in the command register IR-2 (flip-flop 5 and known to open the AND circuits 10-10 , circuit 11-3 reset) or if the op- At times t _s and ί _{β of} the second command period briefly contained in the command register IR-I , the command / + 1 from the command register is almost finished (toggle switch 11-2 set). IR-2 relocated to the command register IR-I. The wave process generated by the flip-flop 11-4 is brought about by the signal N ; the form is shown in line 10. The input 10-12 generated by the io at the time t _s and the AND circuit flip-flop 11-4 at the time i ₃ is supplied. This AND circuit 10-12 control output signal is opposite to that via which is opened by this signal iV, while the AND circuit 11-22 at the setting input of this AND circuit 12 a by the pending memory-free signal by a pulse delayed signal N is opened at time i ₆ , where- MNB (i ₂ ) delayed by one pulse length. 15 through the contents of the instruction register IR-2 into the loading-sub, assuming that the error register IR-I can be reloaded for execution. While the command register IR-I contains the command / only rend of the second short period so that a short period is required, the command / + 1, the command register influence of the function table signal FT 614 becomes ster / 7? -2 under the error register IR-I the third command 7 + 2 and the control time t _{7 of} the first short period an end pulse 20 counter 10-35, which is shown at the time i _{6 of} the second short via the gate circuit 11-34 . This end period was switched on, the address of the four-pulse is shown in the timing diagram in line 12. th command 7 + 3 (memory location 00004). Is assumed, the output signal of the end pulse AND circuit that in the instruction register IR-I befind- 11-34 is supplied to the set input of flip-flop Liehe command within a short period carried 11-2 supplied, then the time t _0, a 25 can be carried out, then during this two-setting output signal is generated, which is shown in line 13 for the short period essentially the same processes. The flip-flop 11-3 was set by hand at the beginning instead of, as is known, previously in connection with the first, so that it was described as a one-short period. Attention should be paid to the generated output signal. Since both toggle, however, that the operations in this second circuits 11-3 and 11-2 setting output signals 30 run automatically for a short period. In other words, the AND circuit 11-29 produces a signal N at the time t _B located in the fourth memory location. This state is command 7 + 3 is represented by the control counter 10-35 in the timing diagram in line 14. automatically retrieved at time t ₇ , while after the flip-flops 11-3 and 11-4 to the time counter, the 35 point i ₀ in its setting or reset state be-memory location for the purpose of removing a If the command is successful, i.e. does not have to be set manually, this counter must now be set, as required in the case of the first short period. In other words, the Indian was.

The stop of the counter must be increased by one, so in the third short period the control contains that it now contains the address of the next command 40 counter 10-35, the memory address for the command 7 + 4. For this purpose, the (memory address 00005) is used at time i _6. The command register 77Ϊ-1 setting output of the flip-flop 11-4 contains the third command 7 + 2 and the command the AND circuit 11-39 and the OR circuit register IR-2 contains the fourth command 7 + 3. To 11-38 the input of the control counter 10-35 drawing illustration of another phase of the arithmetic leads to advance this. As line 15 shows, 45 cycle it is assumed that the memory location containing the command 7 + 4 changes the control counter 10-35 under the influence at the time of this signal, its output signal at time t ₆ controlled by the control counter 10-35 occupied the second short period . is, so that the memory-free signals MNB (J ₁ ) The flip-flop 11-4 will not be generated by a clock and MNB (t ₂ ). Reset in the timing pulse t ₀ , which is fed to it via the OR 5 ° grams are the places in the third and fourth circuits 11-33. The flip-flop short period at which these signals 11-3 would normally occur at the time t _s due to the signal N are shown hatched. Since in the advanced case, the memory-free signal MiVS (i ₂ ) circuit is not generated at the reset input of this toggle case via the OR circuit 11-28, the toggle is applied to the setting input. Finally, the flip-flop 11-2 55 circuit 11-4 is also not reset at the time by the signal N , which is sent to the point t ₂ or point A in line 10 of the third control input of this circuit via the OR switch - short period on. In contrast, the flip-flop device 11-37 is coupled. 11-3 at time t ₀ , since the flip-flop 11-4 still occurs the setting output signal of the previously called command 7 + 2 on the reading line 60 from the previous operation of the second short period and at time t _{7 of the second short period} is generated at the inputs of the AND period, which is applied to the third circuits 10-10 via the delay device short period up to time t _x. This signal can be used to feed gen 10-21 . Line 8 in the timing diagram, the AND circuit 11-25, the clock signal t ₀ further designates the point in time at which a command is passed, as a result of which the toggle circuit 11-3 is supplied to the set command register / 7? -2. In detail 65 becomes. This process indicates that the following commands 7 + 3 are stored in the command register 772-2 during the second short period: The command 7+ contained in the third memory or that the command register IR-2 contains a command 2 is received at the time. The end pulse shown in line 12 is

57 58

generated in the third short penode, since it assumes. In the fifth short period the command / + 3 has been passed, that the command / + 2 stored in the command register IR-I ent- in both registers IR-2 and IR-I is still held within a short period during the control counters 10-35 which is carried out. Contains memory address for command 7 + 4. In the fourth short period, the old one remains. Instruction 5 ser short period, however, it is assumed that the den / + 3 still in the instruction register IR-2, since the memory location containing instruction 7 + 4 has become free, instruction 7 + 4 could not be called up. That is. This fact is caused by the generation of the command register IR-2 so does not contain any new loading memory-free signals MNB (^ ₁ ) and MNB (£,), although the command 7 + 3 for the purpose of execution in shows the lines 6 and 7 of the fifth brief the instruction register IR-I has been relocated. io period are shown. Under the influence of the storage free signal MNB (* ₂ ) contained during the fourth short period, the toggle command registers 77? -1 and IR-2 generate the same circuit 11-4 at time £ _{3 of} the fifth short error 7 +3, while the control counter 10-35 continues to be a setting output signal. This signal precedes memory address 00005, which is shown in line 10 of the timing diagram. The address of the command 7 + 4 corresponds. 15 failed 7 + 4, however, still can not via the AND Also for the fourth short period, it is assumed circuits 10-10 to the instruction register IR-2 transdaß the memory address is assigned 0QQQ5 and therefore ported because the Indas contained in the storage memory-free -Signal MNB is not generated. formation only a short period after the success. This state is indicated by the activation of the memory in lines 6 and 7 on the reading lines. Also occurs in the fourth 20 lines. Due to the set output short period, the flip-flop 11-4 is not set to the signal of the flip-flop 11-4 generates the toggle normal time, that is, at time A t . circuit 11-3 at time t _{t of} the next, ie as just mentioned, the command 7 + 4 of the sixth short period becomes a setting signal. In the AND circuit 10-10 during the fourth short fifth short period, no end pulse is generated, the period is not supplied since the memory location containing the command 7 + 4 during the third short sequence the activation of the switch-off signal of the breakover period could not be activated. The circuit 11-1 can not generate any function table signals either, as indicated by the hatched block. End pulse AND circuits 11-34, line 8 shown. The flop 11-3 generates 11-35, 11-31 and 11-32, which does not require initial adjustment 3 ° end pulse function table signals to produce a fourth thus in the short term, are input signal at time t _v since no new command thus locked . The flip-flop 11-2, which was stored in the command register IR-2 by. The one end pulse of the last-mentioned tIND switch state can be seen from the timing diagram in line 11, which is controlled, ie during the fifth point 7? Not set during the fourth short-short period. This state is caused by the period shown in this time segment by line 13 of the time diagram. Also the guided command 7 + 3 the generation of an end pulse signal N is again ses in the fifth short period at the time L via the AND circuit 11-34. not generated because neither the flip-flop 11-3 nor. With this end pulse, the flip-flop the flip-flop 11-2 generates a setting output signal 11-2 for generating a setting signal at the time to open the AND circuit 11-29, point t _{0 of} the fourth short period caused. 40 Since the signal N is not generated in this short period, make sure that the incrementing signal that became the counter remains the switch-off toggle circuit of the control counter 10-35 does not advance in its setting state, so that even in the six is generated at the normal time point f _e since the th short period is not set to function bar signals of the flip-flop 11-4 . That will be generated. As line 15 of the timing diagram shows, sometimes at the time i ₅ at the output of AND 45, on the other hand, in the sixth short period the continuation 11-29 occurring signal N is generated in the switching signal, so that the count of the fourth short period is also not generated , since the control counter 10-35 is increased by one, so that the flip-flop 11-3 in its reset state of the control counter is now the memory address for, whereby one of the pass signals for the command 7 + 5, ie the address 00006, contains. AND circuit 11-29 is not generated. This incremental signal is also generated because the Kippser state is represented by the hatched block 11-4 in the previous short period, which was switched to the setting state at the point in the time diagram and which finds itself which normally the signal N occurs. Flip-flop 11-3 remains in the reset state, so that the signal N is absent and the AND circuit therefore cannot block a signal 11-14 from the AND circuit 11-39 and, in addition, the 55 can be generated that the input of the control flip-flop circuit Hl is not set, the counter can be fed to the OR circuit 11-38 AND circuit 11-14 to the setting input of the flip-flop can be.

circuit 11-1 a clock signal t ₅ via the OR. At time t _{7 of} the sixth short period, circuit 11-13 can supply, whereby from the time of control counter 10-35 the new memory location is sent to the switch-off signal via t _{9 of the fifth short period} Activate AND circuit 10-36 , since the radio is generated. As has already been described above, the control table signal FT 600 due to the connection, this disconnection signal is not applied to the command decryption of the disconnection signal. As supplied by the timing device 10-17 and causing the diagram to show, the command indicated by the control counter can be successfully addressed to all commands identified by this decryption device, normally generated signals are suppressed so that the memory-free signals are generated. The toggle encryption device 10-18 does not apply any signals 11-4 and 11-3 - as already described - to the, so that at the outputs of the command reason of these memory-free signals. ben —- set. As is well known, in the fourth

59 60

and fifth short period, the signal Λ 'is not generated, processing devices 10-17 and 10-18 are generated so that the flip-flop 11-2 in the fifth and can. During this short period, the toggle six short period remains in its setting state interconnection 11-4 by the memory-free signal. The AND circuit 11-29 is therefore not set to the MNB (i ₂ ), since the AND circuit _{opens time / 6} and generates the signal N, the 5 11-22 despite the new one at time t ₂ from, among other things, the Shutdown toggle switch in their command encryption device 10-18 generated reset state and thus their on-function table signals remains blocked. This advance output signal at point in time _{6 of} the seventh gear will be terminated later in connection with FIG. 12, short period. Also described in more detail at time ί _β of FIGS. 12A and 12B. Several of the seventh short period, the increment signal generated by io of the encryption device 10-18 of the AND circuit 11-39 is generated, whereby the in-function table signals are increased by one via delay stop of the control counter 10-35 , so that they also then so that this control counter now has the address available if the command / + 6 already contains new data. The above-described command decryption device 10-17 and the and in the instruction register IR-2 is given command encryption device 15 10-18 fed worzu times t ₅ and _ί β are the AND formwork to. At time t ₀ , the memory location in the sixth lines 10-12 and 10-12 α in the command register IR-I is stored and re-stored by the control counter. At the beginning of the seventh short 10-35 so located during the sixth short period sampled period, the command 7 + 4 (ie the command / + 5 coupled to the read lines and fifth command) in the command register IR-I and may N & N 20 the command register IR-2 can be executed more via the AND circuits. 10-10 fed. By this process, the flip-flop circuit 11-3 is set for a better illustration, indicating that the command / + 4 access to the memory requires that a new command be entered in the command register IR-2 and the address of a in its M digits Operan is stored. One containing ground by this command, the transport to the register RP-I 25 witnessed function table signals is the signal is such an operation means that is firstly FT 610. By this function table signal FT 610 is a command, the access to the SpeI - The end pulse AND circuit 11-32 is controlled, rather requested and therefore takes precedence over the control of the memory for the purpose of removing one of the flip-flops 11-2 at the point in time t _s which causes a signal to be sent to the setting input, which commands another command, and Secondly, for the purpose of starting this flip-flop with the generation of an introduction of this command, the output signal for more than a short period begins at time t _e. Because is needed. The reason why such an output signal of this flip-flop 11-2 cannot be executed within a short period, that is to say up to time t ₆ at the AND circuit, lies in the fact that in the first 11-29 not is present, no signal N is generated during the seventh stage of the execution of this instruction of the memory 35 short period. During the short period to be controlled for the purpose of removing the operand, the function table signal den must and that in the second stage of the execution FT 600 is no longer available, and the storage, ie a short period afterwards, the operand address 00007, which command 1 +6 can be fed to the central processing plant. Controlled by the control counter 10-35 in the manner described above in accordance with the first execution phase 40 (ie the toggle switch of the command / + 4 can be set during the seventh 11-4 ). During the eighth short period, including the function table short period, the content of the two command signals FT 600 and PT701 remains generated. Due to the radio register IR-I and IR-2, however, unchanged, since by tion table signal FT 600 , the AND circuit is blocked from the absence of the signal iV at the end of 10-36 , so that the content of the control counter 45 for the seventh short period is the content of the Command register 10-35 cannot control the memory. Through the IR-2 the AND circuits 10-12 and 10-12 α not function table signal FT 701 , the AND can go through. Under the influence of the memory circuits 10-14 open, so that the command-free signal MNB (t ₂ ) , the flip-flop 11-4 register IR-I is set over this five M-digits stored during the eighth short period. As AND circuits for memory address decisions 50 Fig. 118 shows, the flip- flop circuit 11-3 in the processing device 10-64 remains in its setting state, in which during the previous short period in this way the operand was stored was switched, as rather to be found. This state is not generated in the seven during the seventh short period, the signal N th short period in lines 4A and 5 of the time, whereby the flip-flop 11-3 is shown in the diagram. As the timing diagram shows, 55 would otherwise have been reset. Since the M-digits of the command for newspapers 11-3 and 11-2 at time t _s the eighth point t _7, the AND circuits 10-14 are set and appear brief periods, now appears on the address lines leading to the memory again the signal N at time t _5, this again at time t ₀ . Is the through the five lowest short period. In addition, the function -valued digit of the memory error identified in the command register IR-I is generated in the table signal FT '705 in the second stage of this lower command (M digits). By this function table signal set free, the AND circuits 10-25 are opened at time t _{t of} the seventh, so that the memory-free signal MNB is shown for a short period. the operand called up by the command / + 4 in the seventh short-This state is now set to the time in line 6 of the timing diagram. By the memory-free signal MNB (t _t ) 65 point t ₇ in the register jRP-1 according to the Bewird the program counter 10-19 is incremented if 7 + 4 can be stored incorrectly. Because a new group of function table signals is generated in the command decryption and encryption signal JV at the time i _{5 of} the eighth short period, the command 7 + 5 from the command register

61 62

IR-2 relocated to the command register IR-I , circuit 11-3 is set and thus generates a setting switch-off 11-4 of the control counter in the eighth output signal at the time t _t assigned to it due to the setting state of the tilting the influence of an instruction 7 + 6 called up to it at the short time period is stored in the register Punkti ₀ from the AND circuit 11-25 supplied IR-2 at the time ίο (whereby ^ 5 signal. This AND circuit 11-25 was through this generates an output signal at time i _x ). the setting output of the multivibrator 11-4 In the ninth short period, assume that it is open. The command / + 5 circuit 11-3 contained in the command register IR-I with the reset input of the Kippder via the OR circuit 11-28 represents an unconditional jump command. Bekannt- · Thematic AND circuit 11-27 on the other hand received at lent allows this command that the by-Diem para- io its inputs a clock signal t, and _t marked tionstabellensignalJTölS a radio of the unconditional branch instruction. A signal can therefore be sent to the flip-flop circuit by means of this AND switch. Two short periods are required for the execution of the unconditional · 11-3 coupled, which defers this jump command. and a reset output at time i _2. However, 15 is generated during the second short period. The final pulse AND circuit 11-34 does not generate any function table signals. The function table signal FT 614 opened, described in detail later, is not caused by the jump command, which is also caused by the unconditional jump command. For the present case, therefore, at time t ₇ , the AND circuit only transmits that part of the jump command, 11-34 therefore a signal to the setting input that is connected to the arithmetic operations, 20 toggle circuit 11-2, which is then followed at the time Dots ₀ ones shown, an adjusting output signal time sequence by in Fig. 11. This set switching elements is controlled. In the first state, this unconditional jump command generates the period in the time diagram in the ninth short stage. Since the flip-flop 11-3 to the function table signals FT613, Fr701 and FT600. Time i _{2 was} reset, the AND remains. The function table signal FT 600 closes 25 circuits 11-29 at time i _5. The AND circuits 10-36 are blocked again, so that signal N cannot be generated. The AND contents of the control counter 10-35 are not coupled to the circuit 11-14 at the time t ₅ through address lines of the memory. The function table signal FT 701 opens the clock signal t ₅ and the absence of the AND ^L circuits 10-14, so that the M-digits 30 signal N is opened so that the switch-off toggle switch of the command can drive the memory. This device 11-1 at time i _{6 of} the tenth short-period state is shown in lines 4 A and 5 of the time diagram with the generation of an output signal begins, graph. If the memory location identified by the M-digits of the command, as shown in line 15 of the timing diagram, is also free at this time, the incremental signal at time i _{6 of} the tenth time is generated during the ninth 35 short period, since the flip-flop 11-4 short period the two memory-free signals MNB are still in the setting state and are generated (lines 6 and 7). The memory free signal AND circuit 11-39 therefore has an output signal er MNB {t. _z ) is fed to the AND circuit 11-21, which shows that the device 11-38 is also fed to the control counter via the OR circuit whose other input is at the same time. This signal causes the function table signal FT 613 to be applied. This AND 40 increases the content of the control counter by one, so circuit 11-21 therefore generates an output signal that, from time i _7, stores a value which corresponds to the value M + 1 at the setting input of flip-flop 11-4 . At the time i _q which is supplied via the OR circuit 11-23. tenth short period through the M digits, the function table signal FT 613 is the same 7 + 5 marked the command and coupled α while also to the AND circuit 10-61, 45 ninth short period retrieved content of Speisomit the time ίο generates a signal , which is coupled via chers to the read lines and via the OR circuit 10-60 to the input of the AND circuits 10-10 to the command register AND circuits 10-37. This transports IR-I . Since the signal N does not generate the M-digits can of is in the instruction register IR-I, also the old contents of the instruction register stored command is used to control counter 10-35 trans- 50 7R-2 not in the instruction register IR-I is restored, be ported The sixth command 7 + 5 is therefore changed in the command so that it unregisters the value of the M digits IR-I. During the tenth short period there is talk. but generates the shutdown signal while other-

The function / function table signal FT613 not only generated the table signals via the OR circuit 10-60 "on the AND side under the influence of the signal PCT currently supplied in the command circuit 10-37 or the command located in register 7R-1 The control counter, in the task of opening these AND circuits, but now the memory address M + 1 also needs to find the control counter 10-35 at the same time, controls the memory for the purpose of clearing would accept the next command. If the computer system is increasing at this time. In other words: If one point is the memory location that contains this address, the one AND upstream of a register is free, then the memory-free signals MNB (J ₁ ) The circuit opens, also causes the Rau and MNB (i ₂ ) to be generated at the same time. In this tenth abbreviation of the relevant register

During the ninth short period, the time t _{3 can} again generate a command 7 + 6 called up beforehand by the AND circuits 6g control signal, while the flip-flop 11-3 runs through the 10-10 and at the time i ₀ starts generating of a setting signal at time t _x, command register 772-2, which starts at the start. The flip-flop 11-2 remains in this short time ^ an output signal generated. The breakover period is set because the signal N during the

63 64

ninth short period was not generated and store the command digit that an output on flip-flop H-2 could therefore not reset. the lines PGOO to PG 09 of the decisions - At the time i _{5 of} the tenth short period, processing device 10-17 b is generated, which generates a signal N stored in the flip-flops 51 to 55 in the manner described above, whereby the switch-off flip-flop 11-1 corresponds to 5 digits. Is thus located in the Kippzurückgestellt and is in the instruction register IR-Z circuits 51 to 55 to a decimal "0", command so produced contained the purpose of executing in loading the decryption means 10-17 b Ausfehlsregister an IR-X is dumped. Since also the output signal on the line PGOO. If this flip-flop 11-4 has been set, if the flip-flop circuit can contain a decimal "1", the command contained in the transmitter address M + 1 is now energized, and if they contain one more the AND circuits 10-10 go through and decimal »9«, the output line PG 09 is energized into the command excitation during the eleventh short period. The decryption device 10-17 ft will be stored in pstsxIR-2 . likewise controlled by a switch-off signal and _,., ._ ....,, ,, ,, .., accordingly generates no signals when command decryption and encryption * ^ _XJJ ^ switch-off toggle circuit 11-1 in their setting device is in the state. The output lines PG 10 to Fig. 12 and 12 A show a detailed block PG19 of the decryption device 10-17 a as well as diagrarani of the linkage of the ten toggle switches - the output lines PGOO to PG 09 of the Entgen of the command register IR-I, in which the / - Digits coding device 10-17 b are stored with the one command. Further show ao gear to another decryption device these figures the command Entscblüsselungsvorrich- connected c 12-17. The three decryption devices 10-17 and the command encryptions 12-17 α, 12-176 and 12-17 c provide the device 10-18. As EntschlüsselungsvorrichsichtUch command shown in the drawings ER- Fig. 10, the two f-Ziffem be a sawn tion 10-17. Also, the Entschlüsselungseinrichfehls in the flip-flops 51 to 60 of the command as tang 12-17 C consists of a number of gate switching registers IR-X stored, whereby the twelfth digit gen, at whose inputs not only the output (i.e. do the most significant / digit) in the toggle switch lines PG10 to PG 19 and PGOO to PG 09, lines 56 to 60 and the eleventh digit (ie the but also the output lines PPCX to the least significant / digit) ta the flip-flops 51 PPC4 of the program counter 10-14 (FIG. 10) to 55 are stored. The output lines 30 are located. If one assumes for a moment that the flip-flops 56 to 60 are with PV 56 the decryption device 12-17 c not with to. PV6Q and the output lines of the toggle The output lines of the program counter 10-14 circuits 51 to 55 are connected with PV 51 to PV 55, the decryption network The output lines PF56 to PF60 are device 100 different output signals erroit of the decryption device2-17a connected. 35 testify that at their inputs there are two ten inputs, which represent a part of the input lines shown in FIG. 10 (PG10 to PG 19 and PGOO to command decryption device 10-17, PG 09). Due to the additional coupling, this BntscWüsselungseinrichtung consists of one of the signals PPCl to PPC 4 of the program counter number of AND circuits, each of which is blocked by the number of possible gate switches in the switch-off signal of the toggle switch 11-1 of the decryption device 12-17 c so increased, the and each to another in the tilt that this device 400 different signals circuits of the command register IR-X stored can be generated. In practice, of course, Zjfferowert are appealing. The decryption so many lines are not required. For the impairment Z-17a, signals are sent via the tendering of the mode of operation of the decryption channel lines. PF56 PF60 supplied to that of a 45 device C 12-17 Assume that all Torin 56 to 60 of the command this means a signal from the circuits Proregisters IJR-I correspond to the flip-flops stored digit. Received gram counter and that the program counter Under the influence of these signals, the Ent- first generates a signal on the output line PPC X locking device direction 12-17 α on one of the outputs. A signal for each of the output lines PG10 to PG19 in the flip-flops 51 to 60. Corresponding digit pairs contained in the command register IR-X speak e.g. B. the digits of 12-17 c stored in the toggle rods 56 to 60 by the decryption device of the command register IR-X become one of a hundred possible output line undecimal "0", so the decryption gene excites, on the assumption that that the device energizes the output line PG 10. The program counter speaks a signal on the output line that is generated in the aforementioned flip-flops and the digit stored by the decryption device, on the other hand, with a decimal "1", so that another output line without any change becomes the decider in the flip-flops 51 to 60 of the command device 12-17 α is excited, and if digits in register IR-X are excited, these flip-flops are set to a decimal "9", so the decoding device can change an output 60 by verifying the contents of the program counter. In other words: If the program signal is switched on on line PG 19. All AND circuit counters are switched on, so that instead of on the length of this decryption device, line PPCl on line PPC 2 is now blocked by a switch-off signal, so that a signal appears from this , and remains of the content of the tilting device, no signals can be generated, circuits 51 to 60 unchanged, as is the Kippschaltang 11-1 (Fig. 11) c in 65 decryption means 12-17 is a new Ausihrena EüJStettzustand of the weno, output line selected . The output lines cause the toggle switches in a similar manner. This decryption device 12-17c is connected to Sl Ife 55 of the command register IR-X, which designates the eleventh PLQ to PLN and is at the input

i 190 704

65 66

of the encryption device 12-18 α which, since several of the command-Ver time intervals shown in FIG. 10 are required for the execution of the command "15". For the moment it represents a keying device. It is sufficient for the locks to know that a certain line processing device 12-18 « consists of a number PL under the influence of the OR circuits in the flip-flops, so that each signal line PLO 5 51 to 60 of the command register IR-I is statically entered PLN is connected to the input of one of these OR-stored commands in accordance with the circuits. If a signal appears on the content of the program counter (FIG. 16) selected line PLO, the ver. This selected line controls the encryption device 12-18 α, optionally several encryption devices 12-18 α, which generate signals on the output lines. io then a number of function table signals

As FIG. 12 shows, the locks that are assigned to the selected line PL and the processing device 12-18 α are also the read signal PYMR . Since the command "15" discussed here generates the Enter. This read signal PYMR is always required to take data from the memory and must be generated when the read signal PYMR is also generated in the flip-flops 51 to 6ö. Some of the commands stored in the command register IR-I receive from the encryption device 12-18 ' that data are of course to be read out from the memory (FIGS. 9A, 9B and 9C). The scrambling system c generated directly supplied to the switching elements of the central Verarbeitungsselungseinrichtung 12-18 a portion of the plant. One such function function table signals that table signals from the Einrichtun- can, however, use b to control the use of this gen electronic computer 20 encryptor 12-18 werwerden. The holding control that the clock generator (F i g. 15) ER- clock signals 12-18 "function table signals generated by the encryption device. The function table signals generated by the encryption device not only directly on the individual devices of the 12-18 α remain in the computer, but are also switched on to another device for as long as the decryption-encryption device 12-18 b is supplied to the devices 12-17 " and 12- 17 δ of which there is a number of gate circuits, whose command contained in the error register IR-I is also controlled by inputs with clock signals from the clock. The gate circuit to which this function table generator (Fig. 15) is present. So while the generated in the signals, is controlled during this time by the flip-flops 51 to 60 of the command register IR-I program counter. The digits stored by the lock can be present for the duration of a function table 12-18 & generated for several short periods, lens signals, however, only remain switched on during the interval of the encryption device in which the gate circuit, the function table signals generated 12-18 b only One of these signals is generated, opened by the clock generator, or several pulse times are available, depending on- For each stored in the command register IR-I

Which clock signals are sent to the gate circuits are passed by the encryption devices which generate the relevant functions 12-18 ” and 12-18 & function table signals. The encryption generated, the device 12-18 b assigned to the relevant command generates the function tables.

signals through which the individual devices of the In Fig. 12A is at least one of the

central processing system as well as the distributor 40 switching elements of the decryption devices and the synchronizing devices are controlled 12-17 ", 12-17 & and 12-17 c as well as the encryption, processing devices 12-18 α and 12-18 & shown. To better illustrate the mode of operation From the drawing it can be seen that the decryption and encryption device decryption device 12-17 " consists of a number of devices 10-17 or 10-18 Command in the command register IR-I fed in output lines of the flip-flops 56 to 60 is chert. In the present case it is assumed that the command register IR-I is present. Specifically, the command “15” has been generated, which means that the decryption device 12-Πα consists of data from the at least ten AND circuits identified by the iV digits of the command, each of which has a designated memory location in the register i? P1 50 of the ten possible digits that can be transferred to. In the flip-flops 56 of the five flip-flops 56 to 60 stored to 60 of the command register IR-I will therefore be those of the. In FIG. 12A, the AND circuit represents signals corresponding to number 1 and in the toggle 12 A-Ylal one of the AND circuits, from circuits 51 to 55 of the command register, the signals corresponding to those of the decryption device 12-17 « number 5 are stored . Under 55 stands. This AND circuit 12-17al generates a signal on the influence of this in the flip-flops 51 to the output line PGIl when the signals stored in 60 are from the decoder of the twelfth digit position of the command register IR-I selungseinrichtung 12-17 « and 12- 17 b The digit stored at the outset corresponds to a »1«. The signals generated on the lines PGIl and PG 05. of the flip-flops 56 to 60 of the command register One of the gate circuits of the L-coded form is supplied to the AND circuit 12yl-17al in devices by these output signals of the decryption 60 IR-I. So if in the toggle decryption device 12-17 c for generating circuit 56 causes a binary "1" and in the toggle of a signal on one of the lines PLO to PLN circuits 57 to 60 causes binary zeros to be stored. As will be explained in detail in connection with, the one represented by these signals corresponds to the command “15”; at this 65 value, a decimal “1”, which is also used by the AND switching process of the program counter (Fig. 16). processing is forwarded in the form of a signal. The det. Of the various lines PL AND circuit have at different times excited advertising circuits of the decoding device 12-17 12 A -17 "1 and the other AND-lines"

67 68

also receive a blocking signal in the form of the OR circuit 12A-ISaI are the output

the switch-off flip-flop 11-1 generated lines PL 143, PL 131 and PL 161 of the

output signal. Encryption facility 12-17 c . How further

The AND circuit 12-17öl represents one of ten will be described below, can be dar-AND circuits INTR to this, from which the decryption is 5 gene signals b during the third stage of a Belungseinrichtung 12-17. This AND signal error "14" and during the first stage of the prayer generates a signal on the PG 05 line if "13" and "16" are missing. During these stages the in the flip-flops 51 to 55 of the command of the commands "13", "14" and "16" will correspond to the binary digits stored by the register JR-I of a decentralized processing system "5". io mation written into memory. The reading

The output lines PGIl and PG 05 are signal PYMR 1 is therefore suppressed at at least one of the AND circuits of the Ent- at these times. This signal is therefore available to the ZeitscUüsselungseinrichtung 12-17 c. As Fig. 12 A point i _{7 available} , when the control counter shows 10-35, these two lines are connected to the one that controls the memory because of a command. When the AND circuits 12A-YIcI and 15 have passed, the one currently in the command register IR-I arrives at 12A-YIcI at which the executed command is not the removal of an opera input line PPCl or PPC2 of the program from the memory or the control counter (FIG. 16) can be present. In this way, the memory is not activated, so the read signal is generated by the AND circuit 12 A -17el only during PYMR1 at time i ₇ . The first stage of the command "15" and the AND switch have no effect in this case, tl2 / 4-17c2 only during the second stage, since it opens with the memory unit selection signal. The output lines of the AND switch - (Fig. 4A, 4B and 4C) must be forwarded, genes 12A-YIcI and 12A-YIc2 are labeled PL151, which is only generated for controlling the memory, or PL 152, respectively. As is well known, the memory will control the signals occurring on this output during the first lines . Command register JR-I located command controlled.

As already mentioned above, if this control is successful, the decryption device 12-17c generates a number of memory-free signals MNB, which - like output lines PLO to PLN. Each of these lines is described - the program counter of PPC lines controls the encryption device 30 to PPC 2 , whereupon from the AND 12-1Sa as this in connection with the circuit 12A-Ylc2 a signal is missing on the line » 15 ”will now be described. In the first PL 152 is generated and the second stage of the BeStufe of the command »15« generates the AND circuit error »15« begins.

12A-YIcI on line PL151 an output signal as shown in Fig. 12A on the line. This signal is fed directly to the encryption 35 PL 152 function table signals FT 610 device 12-18 α , which is then generated directly and FT 620. These function table signals via the OR circuit 12 / 4-18a5 and the register JR-I working with the command "15" in the command of a delay of one pulse length remains and the program counter in the delay device 12 / 4-18a8 the function - remains set in the second stage (ie as long as the table signal FT 600 is generated. The program counter on line 40 generates the output signal PPC 2 ). PL 151 occurring signal is also fed to a further signal at the inputs of the AND circuits 12.4-18 bl teren OR circuit 12 / 4-18a6 of the locking device and 12 / 4-18 & 2, the signals pil3 processing device 12-18 α , which in turn are coupled to a and pi 14 of the clock (Fig. 15). Output signal to the AND circuit 12 / 4-1863 The AND circuit 12A-ISbI thus generates while the encryption device 12-18 b outputs. This 45 rend of the second stage of the command "15" an OFF AND circuit 12A-IS b 3 also receives from the output signal at time pi 13 and the AND clock a clock signal i ₆ and therefore transmits an output signal to circuit 12 A-IS b 2 at this point in time, a signal is sent to those with a verpunkt pi 14.

delay of a pulse working delay The output signals of the AND circuits

device 12A-20, which in turn controls the radio 50 12 / 4-1851 and 12 / 4-18 b 2 , a delay

tion table signal FT700 generated. approximately device 12-19 or 12-20 supplied, the

As Fig. 10 shows, by the functional part, the function table FT 704 signals or signal table FT, 600 is prevented that the control FT 705 pi at time points or 15 pt erzeuzähler 10-35 gen memory due to a further treatment 14 Controls the task and purpose of this function table error. On the other hand, the function signals FT 610, FT 620, FT704 and FT708 become table signal FT700 to write the five digits of the presently stored in the command register / RI later in connection with the command "15".

Command through the AND circuits 10-15 in order from Fig. 12A it can be seen that the OR

to drive the memory at time i _7. Even circuits 12 A -18 al and 12 / 4-18a6 still further

if at time i ₇ the read signal PYMR1 will have 60 tere inputs, not shown in detail,

at the output of the AND circuit 12 A-ISb 4, the function table signals shown in FIG. 12A

testifies. At the inputs of the AND circuit are not only used to generate the command »15«,

12 / 4-18 b 4 are the clock signal i ₇ and an off but often also to generate other commands

output signal of the OR circuit 12A-ISaI that uses. The other inputs of the OR switch

this AND circuit blocks. So if the OR lines 12 A -18 al etc. therefore represent the lines

Circuit does not generate a signal, the PL of the decryption device 12 A-YIc represents,

AND circuit 12 A -18 b 4 a read signal PYMR 1 on which the function shown in Fig. 12A

generated at time i _7. At the inputs of the table signals while executing others

69 70

Commands can be generated. The flip-flops 41 to 45 of the command mode of all commands between "10" and "20" registers IR-I are generated at their setting inputs of each function table signal FT 600. The Weil ver-OR circuit 12 / 4-18 a5 with the output of an OR circuit would be bound in this. In this way, the trigger circuits trap with the lines PL of the decryption 5 45, 44, 43, 42 and 41 are connected to the outputs of the device 12 A -17 c , which during the OR circuits 13-11, 13-12, 13-13, 13-14 or execution of one of the commands between "10" and 13-15. These OR circuits 13-11 "20" are energized. to 13-15 are at their one entrance with the

The signals ι ο 13-4 or 13-5 occurring on the output lines PL of the decryption outputs of the AND circuits 13-1, 13-2, 13-3, selungseinrichtung 12 A-Vl c . At one input, the AND circuits 13-1 to 13-5 do not need to be routed to this input via further circuits, but rather are used to control a voltage of the AND circuit 11-29 (FIG. 11), such as z. B. the delay signal N on. In addition, this AND circuit device 12A-I is used, which in turn generates a radio with the outputs of the trigger circuits of the bet table signal. The error registers IR-2 (FIG. 10) connected in this way, in which the function table signals generated remain stored as long as the information units 41 to 45, ie the ninth, switched on, as the code generating these signals of an instruction will; the Ausfehl in the instruction register IR-I is saved and gears of these flip-flops are bezeichder with PR Progannmzähler not comparable net, so that the change of its count on lines 41 to PR PR 45th The function table signal generated in this way is shifted 20 occurring signals, the ninth digit of one, however, by one pulse length. Since the command stored in the error register IR-2 represents the command generating the function table signal is known - while the command on lines PR 46 to PR 50 between the time intervals t ₅ and r _{6 is} stored in the tenth digit of this command register IR-I, will therefore be wrong. The flip-flops 46 to 50 of the function table signal via the delay 25 command register IR-I are connected to their setting input device 12 a-1 between the time intervals i ₆ with the output of the AND circuits, and i ₇ coupled. at their inputs the signal N as well as the output

In this way, the function table signal output signals PR of the flip-flops of the command from the AND circuit 12 A -17 c will be present in connection with register IR-2 , which generates the tenth digit of a with the delay device 12 A-I. The 30 stored commands correspond. Thus, the one generating the function table signal FT 600 via setting inputs of flip-flops 46 to 49 directly, the delay device 12A-18a8 adjusts the just-described arrangement, the output of the AND circuits 13-6 to example. 13-9 connected, in turn, the signals PR 46 bis In this case, the AND circuit Pi? 49 of the flip-flops 46 to 49 of the instruction 12A-YIc receive the signals PGM and PGN from the ent registers IR-2 . The setting input of the coding devices 12-17 α or 12-176 so-flip-flop 50 of the command register IR-I is fed like the output signal PPCL from the program counter via the OR circuit 13-16 with the ler, whereby this circuit on the Lei - Output of AND circuit 13-10 connected, tingPLX generates an output signal. The 40 PR 50 of the flip-flop circuit 50 of the command register delay device 12 AI is controlled by the signal occurring in turn, the signal JV and the signal on the line PLX , which now receives IR-2.

in turn, the delayed function table signal FT results from the description of FIGS

generated. This function table signal is located, that shifted in time upon generation of the signal N through a pulse length, but takes so AND circuit 11-29, the bits of the ninth digit long as the erzeu- the signals PGM and PGN 45 a in the instruction register IR 2 command stored in the command register IR-I is in the flip-flops 41 to 45 of the command (and the signals PGM and PGN thus to the register IR-I via the AND circuits 13-1 to AND circuit 12 A - remain coupled 17 c) and 13-5 and 13-11 is set to PPCL to 13-15 of the program counter, the OR circuits. can be saved. The tenth digit is

13 and 13A show a detailed view 50 of the flip-flops 46 to 50 of the command of the ten flip-flops 41 to 50 of the command register IR-I via the AND circuits 13-6 to register IR-I (FIG. 10). These flip-flops 13-10 are supplied.

store the ninth and tenth digits of a load on the reset inputs of the flip-flop circuits

missing, the flip-flops 41 to 45 the 41 to 45 of the command register IR-I are the ninth and the flip-flops 46 to 50 are the 55 gears of the OR circuits 13-17 to 13-21 . Save the tenth digit of a command. As Fig. 13 shows all the OR circuits 13-17 to receive 13-21, each flip-flop, the signal generates two output at its one input each N. signals which are denoted by PV and TV. This results from the description of the flip-flop circuits, signals are mutually exclusive, that is, when the signal N is generated and when it is not present, only one signal is generated at a time. The toggle switch z. B. a signal PV, so storage flip-flops 41 to 45 of the command register IR-I chert a one; if, on the other hand, it generates a signal for these flip-flops to return to their reset state TV, it saves a "0". A toggle at the setting input, ie generate a signal TV, output one of the flip-flops 41 to 50 is applied. B. generates the signal N and occurs on that of the signal causes the generation of a signal PV; 65 line PR 45 no signal, the toggle and a signal present at the reset input of one of these toggle switch circuits 45 of the command register IR-I leads to the generation of a signal and thereby generates the signal PF35, since the Si signal FF. signal to the reset input of this flip-flop

is supplied through the OR circuit 13-21. If, on the other hand, a signal occurs on line PR 45 at the time the signal JV is switched on, the toggle circuit 45 of the command register IR-I is switched to the setting state and thereby generates a signal PV 45. The signal JV is also sent to the reset inputs of all Flip-flops coupled that store the tenth digit of an instruction (flip-flops 46 to 50 of the command register IR-I). The signal JV is coupled via the OR circuits 13-23, 13-24 and 13-25 to the reset inputs of the flip-flops 46, 47 and 50, while in the case of the flip-flops 48 and 49 it is connected directly to their reset inputs.

Each OR circuit 13-11 to 13-15 also contains a further input to which a signal is present, by means of which the flip-flops 41 to 45 of the command register IR-I are set. Thus, at the input of the OR circuit, the output line of the AND circuit 13-27 is present, to whose three inputs the following signals are coupled: the function table signal of the command encryption device 10-18, which is generated by the flip-flop circuit 14C-27 (FIG. 14C ) generated displacement signals PRAH and the signal PF35, which is generated at the reset output of the flip-flop 45 of the command register IR-I . The OR circuits 13-12 and 13-15 have their one input connected directly to the output lines PSVOO and PSV 49, respectively, of the matrix shown in FIG. 13A, while the OR circuits 13-13 and 13-14 both to the output line PSVOS are connected to the same matrix. As will be described in more detail below, this matrix 13-31 is controlled by the output signals of the flip-flops 41 to 45 of the command register IR-I . As already mentioned before, all flip-flops 41 to 50 of the command register IR-I are connected at their reset inputs to the output of the AND circuit 11-29, which generates the signal JV. The reset input of the flip-flop circuit 41 of the command register IR-I , however, is also supplied with the signal PSV 16 of the matrix 13-31 via the OR circuit 13-17. The flip-flop 42 receives the signal PSV Π via the OR circuit 13-18, the flip-flop 43 the signal PSV 38 via the OR circuit 13-19, the flip-flop 44 the signal PSF 05 via the OR circuit 13-20 and the Flip circuit 45 the signal of the AND circuit 13-40 through the OR circuit 13-21. This AND circuit 13-40 is in turn controlled by the shift signal PRAH and the function table signal FT 615. In addition to the JV signal, the output signal of the AND circuit 13-22 is fed to the reset input of the toggle circuit 46 of the command register IR-I , which in turn receives the PV 47 signal from the toggle circuit 47 and the PSFOO signal from the matrix 13-31. Flip circuits 47 and 50 of instruction register / jR-1 are reset by signal PSFOO passed through OR circuits 13-24 and 13-25, respectively. Finally, the flip-flop 50 is connected at its setting input to the output of the AND circuit 13-26 via the OR circuit 13-16. The output signal PF5Ö of the flip-flop 50 and the signal PSFOO of the matrix 13-31 are present at the inputs of this AND circuit 13-26.

In the case of the in FIG. 13 a is a known matrix consisting of the gate circuits 13-32 to 13-38, the inputs of which are arranged on the left-hand side of the figure. The following signals generated by the flip-flops 41 to 44 of the command register IR-I are present at these inputs: PF4I, PF41, PF32, PF42, PF33, PF43, PVM and PF44. The matrix also receives the PRAH displacement signal

ίο toggle circuit 14C-27 (Fig. 14C) and the function table signal FT 615. Each vertical represents a gate circuit, and each point on a vertical indicates a connection with the horizontal input lines. So lie z. B. at the inputs of the AND circuit 13-32 generating the signal PSFOO the following signals: PVM, PF43, PF3Z, PF4T, F7615 and PRAH. From the drawing it can be seen that with the exception of the AND circuit 13-33 all AND circuits

ao of this matrix can be controlled by the displacement signal PRAH and the function table signal FT 615.

The AND circuits 13-28, 13-29 and 13-30 eras shown on the right-hand side in FIG. 13A generate the signals PSR 3 X, PSFIl and PSROO. These three signals indicate that the number stored in the flip-flops 41 to 50 of the instruction register IR-I is a) less than 3, b) equal to 1 and c) equal to 0, respectively. As can be seen from the drawing, the outputs PF33 ", PVM, PF47i and PF47 of the flip-flops 43, 44, 46 and 47 of the command register IR-I are present at the inputs of the AND circuit 13-28. At the inputs of the AND 13-29 are circuit the output signal PSR 3 X of the aND circuit 13-28 and the output signal of the aND circuit 16 PSV 13-35 of the matrix at 13-31. in contrast, the aND circuit 13-30 receives the function table FT signal 615 , the output signal PSR 0 of the AND circuit 13-33 of the matrix 13-31 and the signal PSR3X of the AND circuit 13-28.

The L code already mentioned elsewhere shows that both the signal PSFOO generated by the AND circuit 13-32 and the signal PSR 0 generated by the AND circuit 13-33 indicate that the signal generated in the flip-flops 41 up to 45 stored value corresponds to a »0«. The generation of the signal PSV 05 means that the value stored in the aforementioned flip-flops is equal to 0 or 5, while the signals PSF 16, PSF 27, PSV 38 and PSV 49 indicate that the value 1 or 6, 2 or 7, 3 or 8 or 4 or 9, respectively.

As is known, the two most significant digits of the JV address of an instruction are stored in the flip-flops 41 to 50 of the instruction register IR-I. This JV address is used to control a memory location in which an operand is located. This control takes place on the basis of a corresponding command. With certain commands, in particular with the shift command 07, these two digits are used to identify the number of shifts that are required for a value stored in the command register / RI. After each shift, the number in flip-flops 41 to 50 must be reduced by one. During this operation, the number has decreased to 3 or less, which is indicated by the signal PSR3X or PSFIl or

73 74

PSRQO is displayed, a signal must also be added. Should then subsequently be generated in addition to the result so that other control devices, which have yet to be described, come into operation with a further arithmetic value to be added. To be added, the result becomes the first for this purpose, the output lines of the summands and this further third arithmetic value trigger circuits 41 to 50 of the command register IR-I 5 become the second summand. Although with this operation again three values were added together to the different inputs of this tilting, circuits were fed back and control the matrix, the arithmetic unit always only processes two 13-31, which in turn processes the inputs of these toggle arithmetic values at once,
controls. The exercise signal PRAH to be processed by the adder / comparison unit is therefore always changed when a shift is generated in the present computer system. As an example, let calculation quantities temporarily be in the form shown in FIG. It is assumed that registers RP-I and RP-2 are stored in the flip-flops 41, the number 14 is located up to 50, the flip-flops subsequently to the adding-comparator 10-41 genes 41 to 45 the number 4 and the flip-flops to be transported. As just mentioned, 46 to 50 store the number 1. From these toggles, the result obtained with an addition takes the following signals: very often takes the place of the first summand, when PV42, PV43, PV45 and PV 46 as well as PVH, yet another calculation variable is added PVM, PV41, PVM, PVW and PVSO. That should lie. In the present computer system, therefore, the function table signal FT 615 and the various other circuits are provided so that the training signal PRAH is on, the signal PSV 49 is generated from the AND circuit input information of the adding / comparing unit 10-41 of the matrix 13-31 generated. again the register RP-I supplied and there to 13-15 This signal is the purpose of a further operation is stored the set input of flip-flop 41 can be zugelei- via the OR circuit.

tet, which is now the signal PV 41 instead of the signal below, the mode of operation of the PV4T is now generated. In addition, a signal is also transmitted from the AND 25 registers RP-I and RP-2 in conjunction with circuit 13-40, since FIGS. 14A, 14B and 14C have been described. Fig. 14A shows that both the shift signal shows details of the circuits and logic PRAH and the function table signal FT 615 link of the intermediate register ÜP-1. How linked are. The flip-flop 45, which has already been mentioned elsewhere, consists of a reset and instead of the signal PF45 generates the machine word made up of twelve digits, with signal PF35 in each case. The AND circuits which make up the one digit of five bits including a toggle switch 46 to 50 of the command register IR-I ity test bits. The two buffers control are not opened; the contents of these RP-1 and RP-2 therefore each have five shift flip-flops remaining 00001. In contrast, advertising registers, which are each represented as an information channel by the flip-flops 41 to 45, now 35. Each shift register comprises the following signals generated: PF35, PV4 ~ 4, PV43, twelve stages, each of which can store an information unit PV 42 and PV 41. A comparison of these signals can also be saved. If the information shows the L code that the value 00111 of the decimal 3 in the same steps stored in these toggle switching units, which are stored in the five registers in gen, is considered as a whole, then speaks. The content of the flip-flops 41 to 50 40, these information units correspond to one digit, has therefore been reduced from the decimal value 14 to 13. with a check bit. In other words, they will

The principle of changing the value of a number registers stored in information units that are stored within the five speech flip-flops 41 to 50 in the twelve stages, as so-called countdown AND circuits (considered as a whole, the four information modes 13- 3, 13-20, 13-7 etc.) as well as the AND 45 units in channels 1 to 4 to use the digits and the circuits of matrix 13-31, the check bit is already known to the fifth information unit in channel 5, so that further details are omitted. The shift registers are common to the various values that are switched on in the toggle switch so that the five information items can be stored. Output lines signals occur in parallel, which should be noted, however, that the circuit arrangement shown in FIGS. 13 and 50 corresponds to the five information units, which represent the number and 13 A, only when one represents the check bit.
Downcounting is permitted if the number stored in the toggle In detail channel 1 or the circuits 41 to 50 of the command register IR-I shift register 14 ^ 4-13 of the intermediate memory is not greater than 24. Described in this RP-1. As FIG. 14A shows, the operator of these shift registers 14.4-13 contains twelve levels. Each direction has its limits. If necessary, additional AND circuits can be used for these twelve stages of the shift register. individual stages will still be in conjunction with

60 Fig. 14C described in more detail. GeRegister At this point, RP-I and RP 2, the central processing ^nu 8t ^{it to} know that the information Veranlaee the shift registers 14A-13 either through the AND

Circuit arrangement 14 / 4-14 in series or across

Arithmetic units, such as that in connection with the input lines A \ 4A- \ 2A \ to 14A-IAl

Fig. 10 described adding-comparison unit, lead 65 can be supplied in parallel. The

ren generally arithmetic operations with at least information from the shift register 14A-13

two operands. So z. B. with one on the lines B 14ΑΊ2Β1 to 14A-IBl

Addition of the first summand to the second can be taken in parallel. At the intermediate

75 76

memory via the lines A parallel supplied schenspeicher RP-I . The function table signal FT 501 is sent to the second input line and taken in parallel via the lines B . B. a memory, 5 shift registers of the buffer RP-I are supplied or that are hidden, tries to produce. The function table signal to then be sent to another data handling input FT 501 , among other things, from the shift direction. As is also generated in the individual command »07« and described for the AND circuit, it is also possible to only route parts 14Λ-28 via line 14 / 4-30. To save or hide the information. io third and last input line to the AND switch The shifting or forwarding of the information 14 / 1-28 is the line IAA- ¹ Sl, which is a mation in the shift registers in a loop connection or a circular path between series and parallel . The information is then fed to the output of the shift register, adding and comparing unit (FIG. 10). From 14 / 4-13 and its input, so that FIG. 14A it can be seen that the information which is transported onward from the shift register by the shift register 14 / 4-13 in series is returned to its input via the train information signals AND circuits 14 / 4-14 can be performed. The line 14 / 4-32 is with is forwards. Similar AND circuit arrangements are connected to the output line 14 / 4-31, whereby channels 2, 3, 4 and 5 are provided which form the loop for returning the information with 14 / 4-15, 14 / 4-16, 14 / 4- 17 or 14 / 4-18 are 20 signals to the shift register is closed. are drawn. The AND circuit arrangement The output signals of the two AND circuits 14 / 4-14 contain an AND circuit 14 / 4-19, the 14 / 4-19 and 14 / 4-28 of the OR circuit have four input lines. Supplied on line 14 / 4-33. The mode of operation of the OR 14 / 4-20 , the information signals of the adder circuit 14 / 4-33 in connection with the twelfth comparison unit to the shift register will be explained in more detail with reference to FIG. 14C. On the second input line of the AND wrote.

Circuit 14 / 4-19 becomes the function table signal The AND circuit shown in Fig. 14A

FT 500 is transmitted, which shows if it is present, arrangement 14 / 4-14 is also for blocks 14 / 4-15,

that the command provides a reading from the adders 14 / 4-16, 14 / 4-17 and 14 / 4-18. Since the

Comparison unit in the buffer RP-I. 30 Mode of operation for all channels or shift

is enough. The AND registers on the third input line are the same, the description of the channel applies.

Circuit 14 Λ -19 is the signal PRAH , the nals 1 or the first shift register

is transmitted over the line 14 / 4-22. As for the other four channels or displacement

will be described in detail, this signal represents register.

PRAH represents a shift signal which is fed to the 35 In FIG. 14A, the connection 14 / 4-34 shift registers of the buffer memory RP-I is also shown, which is fed as “Hold and Shift”. This shift signal is referred to as "signals". The output lines that couple each shift register stage to this port 14 / 4-34 are shown as one line for the sake of simplicity, which actually carry information within the shift registers. On the fourth and last 40 it consists of at least two lines. The input line of the AND circuit 14 / 4-19 is the generator for the hold and shift the clock signals ptl to pi 13 of the processing signals is a device that is applied. As will be described in more detail, two different signals are generated, as will be described in Verdelt for these signals pi to be clock signals, linked to FIG. 14C,
In the present case by a total of twelve 45. In addition, each line A (FIG. 14A) contains clock signals pi 2 to pi 13. These twelve clock signals connect the connection G for a second input path, and serve to completely transfer the shift register, ie the connection 14 A-UG1 to switch on for the line so that the 14 A-II Al. In addition, information is also connected to the output lines on the lines B - a connection for a second output path is pre-coupled when the clock signals pt1 to pi 13 50 are seen, ie in this case the connection is terminated. 14 A-HHl for the line 14 A -12Bl. About these

If information signals from the adding lines 14 A -12 Gl and 14/4 11 Hl can be linked to the line 14 / 4-20 in the comparison unit 10-41 with other devices in the arithmetic unit, then these signals are system optionally information is fed into the shifting exercise registers 14 / 4-13 in series, namely 55 registers written in or read out of them at the times when the radio is activated at the same time.

table signal FT 500, the shift signal Fig. 14B is a block diagram of the shift

PRAH and the clock signals pt 1 to pt 13 are present. Exercise register arrangement of the buffer memory RP-I.

It can also be seen from FIG. 14A that an arrangement essentially corresponds to that provided in the second AND circuit 14 / 4-28 , over 60 of FIG. 14A. Fig. 14B shows the information in the shift shift register 145-13, which can be stored from a total of registers 14 / 4-13. There are twelve stages, each of which has an input of this AND circuit is the AND line A and an output line B. Circuit 10-51, which due to its more detailed each of the input lines A 14 B-11 A1 is designated 14 / 4-28 through illustration. At 65 14B-IAl , three input-like gate circuits are connected to one of the gate circuits 14 ß-12 Cl of the AND circuit 14 / 4-28. The output lines to: On the first line 14 / 4-29, lines B 14 B-II Bl to 14 BI Bl represent the shift signal PRAH for the intermediate output lines of AND circuits,

which are similar to the AND circuit IA B-12 Dl. The input AND circuit 145-12C1 and the output AND circuit 145-12D1 are shown in Figure 14B to show the function table signals associated with all of the input and output AND circuits of the RP-2 shift registers are fed.

As can be seen from Fig. 14B, the AND circuit 14 5-12 Cl has two inputs. The first input is connected to the reading line HSB-R . Information signals are coupled to the AND circuit 14 B-12 Cl on this read line HSB-R when information units are fed to the twelfth stage of the shift register 1 of the buffer RP-2. The function table signal FT 707 is present at the second input of the AND circuit 14 5-12 Cl. As will be described later, when this function table signal is coupled to the AND circuit 145-12Cl, data from a specific data source, such as e.g. B. the memory (Fig. 2), into the buffer RP-2, in this case into the stage 12, read. The mode of operation of the output signal of the AND circuit 14 5-14 Cl can still be seen from the description of FIG. 14C.

The AND circuit 14 5-12 Dl has an output line which is connected to the write line HSB-W . One input of the AND circuit 145-12D1 is connected to the output line 14B-12B1 of the twelfth stage, on which information signals are transmitted when data is read from the shift register. The function table signal FT 710 is present at the other input of the AND circuit 14, B-12 Dl. This function table signal is then coupled to the AND circuit when data are to be read from the buffer memory RP-2 and transported to the memory (FIG. 2).

The input and output AND circuits for the individual stages of the shift register 145-13 are not shown since they represent the FIG. AND circuits 14B 5-12 Cl and 14 5-12 Dl are similar. The input lines A are each connected to an AND circuit C, while the output lines B are each connected to an AND circuit D. In addition, the function table signal FT 707 is applied to each AND circuit C , while the function table signal FT 710 can be coupled to each AND circuit D.

From the drawing it can be seen that the shift register of an AND circuit arrangement 145-16 is controlled. This AND circuit arrangement 145-16 corresponds essentially to that AND circuitry in Fig. 14A. The shift registers 2, 3, 4 and 5 are also provided with such an AND circuit arrangement, which is labeled 145-17, 145-18, 145-19 and 145-20, respectively.

The AND circuit arrangement for the shift register 145-16 differs somewhat from the AND circuit arrangement for the shift registers of the buffer memory RP-I, since only one such circuit arrangement is provided for the shift register 145-16 compared to two such arrangements for the shift registers of the buffer memory RP- I. In the case of the buffer RP-2 , the information transported by the shift register can then be fed back to the input of the buffer via the AND circuit 145-23 and the corresponding other AND circuits in the case of the other shift registers. The AND circuit 145-21 transfers the information which is transferred from the buffer RP-I to the buffer RP-2 . As shown in Fig. 14B, AND circuit 145-21 has two inputs. The shift signal PRAH is coupled to the first input of this AND circuit and is generated when the information contained in the first buffer memory RP-I is to be transported further. The second input of this AND circuit is connected to the output line of the corresponding shift register of the buffer memory RP-I . When a shift signal PRAH and an information signal from the first shift register of the first buffer memory RP-I are switched on at the same time, information signals are transported to the shift register 145-13 via the AND circuit 145-21 and the OR circuit 145-22.

The AND circuit arrangement 145-16 also includes the AND circuit 145-23. This AND circuit 145-23 has two inputs: The signal PRBH can be coupled to the first input, which signal has already been referred to previously as the shift signal for the shift register of the second buffer memory RP-2 . The second input line to the AND circuit 145-23 represents the circulating connection to the first shift register of the buffer memory RP-2 , as a result of which the information signals can be fed back to this shift register. If the shift signal PRBH and at the same time the information signals coming from the buffer RP-2 are coupled to the inputs of the AND circuit 145-23, then these information signals are fed to the OR circuit 145-22 via the AND circuit 145-23. The transmission of the information signals via the OR circuit 145-22 is described in connection with FIG. 14 C.

The channels or shift registers 2, 3, 4 and 5 of the intermediate memory RP-2 essentially correspond to the channel or shift register 1 of the intermediate memory RP-2, which has already been described. In addition, the overall arrangement of these shift registers corresponds to the arrangement of the shift registers of the buffer memory RP-I. In addition, in contrast to the first buffer RP-I, locking signals can be fed to the second buffer RP-2 for the purpose of transmission to the shift register of the first buffer RP-I. It can be seen from the drawing that each output line 5 of the fifth shift register of the buffer memory RP-2 has a further conduction path, from which it can be seen that the output signals occurring on this line have a further task. This second conduction path is indicated in the drawing for lines 5 of stage 12. As shown in FIG. 14B, the output signals appearing on the output lines 5 of the stage 12 are transmitted via the line

14 5-12 B 5 fed to the two AND circuits 145-25 and 14 £ -26. A signal appearing on the output line 5 of the stage 12 acts on the AND circuit 145-26 as a blocking signal and on the AND circuit 145-25 as a pass signal. In addition, the function table signal FT 509 is fed to these two AND circuits 145-25 and 145-26. From Fig. 14B it can be seen that with the simultaneous coupling of the signal 5 of the twelfth stage via the secondary line and the function table signal FT 509, the AND circuit 145-25 is opened and thus emits an output signal to the line 14 5-12 £ 5. This output signal is described below in connection with FIG. 14C. 14B it can also be seen that in the absence of a signal on the line 145-1255 of the twelfth stage, the AND circuit 145-26 is not blocked, so that when the function table signal FT 509 is coupled, this AND circuit is opened and an output signal is generated to line 14 5-12 F 5 delivers. The function of this signal appearing on line 14 5-12 F 5 is also described in connection with FIG. 14C.

Each line B 145-1255 to 145-155 is connected to two AND circuits similar to AND circuits 145-25 and 145-26. The AND circuits 145-27 and 145-28 are shown as an example of this connection, at the inputs of which the signal 145-155 and the function table signal FT 509 are present.

Fig. 14C will now be described. This figure shows a block diagram of a shift register, specifically the shift register of the buffer memory RJP-I, designated by channel 1. Since each shift register of the two buffers RP-I and RP-2 consists of a total of twelve stages, it is sufficient to understand the mode of operation of these shift registers if only channel 1, ie shift register 1, is written to. Fig. 14C shows three stages of the shift register, namely stages 12, 11 and 1. The AND circuitry which controls the shift register 1 in Fig. 14C has already been described in connection with Fig. 14A. This AND circuit arrangement is provided with the same reference symbols as in the preceding description.

Each stage of the shift register includes pulse shaping circuitry which operates with a delay of one pulse length. When coupling a corresponding signal to the pulse shaping circuit via an OR circuit, such as. B. the OR circuit 14 Λ-33, the pulse shaping circuit generates an output signal that is delayed from its input signal by a clock pulse length. The output of the pulse shaping circuit 14C-13 is applied to the AND circuit 14C-15 via line 14C-14. If the output of the pulse shaping circuit 14C-13 is coupled to the AND circuit 14C-15 at the same time as the output of the AND circuit 14C-16 , the signal of the pulse shaping circuit is coupled through the AND circuit 14C-15 returned to the OR circuit 14 Λ-33.

During this process, the OR circuit 14., 4-33 is supplied with a signal which is transmitted via the Pulse shaping circuit runs and one clock pulse length later to the OR circuit again is coupled. This output signal from the pulse shaping circuit remains on all the time, as it is via the circulation circuit, consisting of line 14 C-14, AND circuit 14 C-15 and OR circuit 14 ^ 4-33, is continuously fed to the pulse shaping circuit, thereby converting it into holds its setting state.

ίο To make the circulation signal effective, the AND circuit 14 C-15 must be opened by the output signal of the AND circuit 14 C-16. A hold signal can be connected to the inputs of the AND circuit 14 C-16 via line 14C-17 and a blocking signal can be connected via line 14 5-12 F 5. The generation of the signal 14 5-12 F 5 has already been discussed in connection with FIG. 14B. Should the information located in the twelfth stage of the shift register through

ao return of the output signal of the pulse shaping circuit 14C-13 remain stored, the AND circuit 14C-16 is opened by the hold signal coupled to the line 14C-17, so that the twelfth stage of the shift register is not cleared. If, on the other hand, the digit representing the sign is odd, the function table signal FT 509 is coupled to the AND circuit 145-26 (FIG. 14B), as a result of which a signal is generated on the line 14 5-12 F 5 which the AND circuit 14 C-16 blocks. The output signal of the pulse-shaping circuit or pulse-shaping element 14C-13 can therefore not pass through the AND circuit 14C-15. The pulse shaping element therefore returns to its reset state, ie the twelfth stage of the shift register is cleared. The generation of the hold signal will be described in detail later. For the moment it is sufficient to know that the stop signal will be generated at a suitable time by a command pulse.

Assume that a unit of information has been stored in the twelfth stage and is now to be transported from the twelfth to the eleventh stage. At this point, i. H.

when the information is to be transported to the next stage, the displacement signal PRAH is generated on line 14C-18. This shift signal PRAH is supplied to the following AND circuits of the individual stages: AND circuit 14A-28 of the twelfth stage, AND circuit 14 C-19 of the eleventh stage and the similar AND circuits of the other stages, such as. B. the AND circuit 14 C-20, which represents the AND circuits of stages 10 to 1 in the present case.

With the above assumption, the output of the twelfth stage becomes the same timing as the shift signal is coupled to AND circuit 14 C-19. This AND circuit generates thereby an output on line 14C-21 which is fed to OR circuit 14C-22. The OR circuit 14C-22 corresponds in its structure to the OR circuit 14Λ-33. If you have any concerns of a signal at one of its inputs is generated by the pulse shaping element 14C-23 assigned to it an output signal. This output signal is delayed by one pulse length and is transmitted over the line 14 C-24 and the AND circuit 14 C-25 are fed back to the OR circuit 14C-22. The Ver-

81 82

The information is now shifted from one level to the start by means of the AND circuit, which always takes place in the same prescribed 14C-12D1 that is connected to the twelfth level, until line 14 / 1-31 is an output described. It is assumed that the signal is coupled that corresponds to the information unit 5 originally stored in the twelfth stage, an information signal located in the twelfth stage, and thus corresponds to an output signal on the line. This line represents the output line 14 A-12Bi is generated, whereby the AND signal of the last pulse-shaping element is. The processing 14 C-II Dl is prepared. In addition, the shifting process is the same for all registers of the two function table signals FT 703 to the AND switch buffers jRP-1 and RP-2. device 14 C-12 Dl coupled, which indicated

If, when a shift signal is generated, it becomes io that the content of the five shift registers is to be masked out with simultaneous excitation of the other input. The AND circuit lines to the AND circuits IAAAS and 1AC-12D1 is thus opened in this way and 14 / 1-28 of the twelfth stage generates an information signal on the line 14 C-26 an information either from the adding-comparator via the line signal. This information signal is coupled to the reading 14 ^ 4-20 or from the first stage of the line HSB-W 14B-15 and rather fed to the storage shift register 1 of the buffer RP-I.

Passed over the line 14 / 1-32, so the- So far, the storage of information

This signal to the OR circuit 14 / 1-33, which then - in series via the AND circuits 14 / 4-19 and sends a signal to the pulse shaping element 14C-13 14 / 4-28 and in parallel via the AND, that during the next clock pulse time a 20 circuits 14 C-12 Cl as well as the fading out of Output signal generated. Information about the AND circuit 14C-12D1

Discussed in addition to the transmission of the information signals. In addition, provisions have been made to move from into the shift registers via the AND switch information within the individual shift stages 14 / 1-19 and 14A-28 , and also to retain information in order to avoid the 60 information signals of a word described in a relevant register. This tes about the AND circuits 14 C-12 Cl to the description was only made in connection with 14 CI Cl and the corresponding other of the twelfth stage, but also applies to the other 48 input AND circuits C of the other four stages of the both buffers RP-I and RP-2. To be able to store shift registers in parallel, the generation of the. As can be seen from the drawing, the 30 hold and shift signals for the intermediate AND circuit 14 C-12 Cl has three inputs. Discussed on the memory RP-I , which is mainly from one input, the function table signal of the hold and shift toggle circuit FT 705 is present, which indicates that In-14C-27 are being generated by the memory. The hold and shift information is read into the shift register. The second input of the AND switch 35 hold signal under the influence of the output signal device 14 C-12 Cl is connected to the read line HSB-R to the OR circuit 14 C-28 and a shift circuit on which the data on the memory is read out. Training signal under the influence of the output signal senen information signals are transmitted. At the AND circuit 14 C-29. The hold signal is fed to the third input of the AND circuit 14C-12 Cl of the AND circuit 14C-41, which can also be coupled to the locking signal 145-12 Zs 5 at the same time and also has a locking input to which the one already has has been previously described. The function table signal FT 704 coupled werses blocking signal 14 B-12 E 5 is used to block the can. This function table signal FT 704 AND circuit 14 C-12Cl and which is not shown is generated by a command in which information provided AND circuits 14C-12C2, 14C-12C3 are read into the buffer RP-I or the -14- 12 C 4 and 14 C-12 C 5, if the intermediate storage is to be cleared at the time. Due to the coupling of the function table signal to the function table signal FT 704, the hold FT 509 is blocked in the fifth digit position in the intermediate signal, so that the toggle circuits of the memory RP-2 are a "1". The functional buffer RP-I will be cleared. The same table signal FT 509 is generated in the case of a removal task of a blocking signal takes over with the intermediate command (command "20") and indicates that the function table signal memory information is sent from the 50 schenspeicher RP-2 to the buffer RP-I FT 706, in which case the The eviction signal is supplied to circuit 14C-40 via the AND of the buffer RP-2 in accordance with a system determined by the content for the buffer RP-2. Transport is from Fig. 14C. So step z. B. on the line it can be seen that the OR circuit 14 C-28 14ZJ-12E5 does not have any blocking signals and is 55 has five inputs. At the first input is the time of the coupling of the information signals signal N , at the second input the output to the read line is the function table signal signal of the AND circuit 14 C-30, at the third input FT 705, these information signals become the output signal of the AND -Circuit via the AND circuits C14 C-12 Cl to 14 C-31, at the fourth input the signal PSR 00 and 14 CI Cl via the lines A1AA-12A1 to 60 at the fifth input the signal PSV 11.
14 / 4-1 Al the assigned OR circuits, As already in connection with the on and off

such as, for example, the OR circuit 14, 4-33. processing system (Fig. 10). In addition to the direct and parallel storage, the signal N is generated when an instruction of information in the shift register has come to an end and information from the instruction has the entire content on five shift registers 65 register IR-2 buffer RP-I transferred to the command register IR-I via 60 AND switches. This signal N is fed to the flip-flop circuit D (for example the AND circuits 14C-12 Dl 14C-27 in order to keep them in their hold state up to 14 CI Di) . This upstream connection, which ensures that the

Information located in the shift register is not transported further until a new command has been stored in the command register IR-I.

The output signal of the AND circuit 14C-30 also causes the flip-flop circuit 14C-27 to be switched to its hold state. The AND circuit 14C-30 is controlled by the following signals: the function table signal FT 501, which indicates that the information contained in the buffer RP-I is fed back to its input, the function table signal FT 615, the AND circuit 14C-30 so blocks for a long time until the shift operation is completed, as well as the clock signal pill, which switches the flip-flop 14 C-27 to its hold state after the shift operation has ended. The AND circuit 14 C-30 has the task that when the information circulates again, the toggle circuit 14C-27 is not switched to its hold state when the function table signal FT 615 is coupled until the shifting process has ended.

The output signal of the AND circuit 14C-31 also causes the flip-flop to be switched 14 C-27 after the move is complete. In this case the switchover takes place however, under the influence of the clock signal pi 13 instead.

The signals PSR 00 and PSVIL are generated by the countdown AND circuits already described in connection with FIGS. 13 and 13A. The signal PSR 00 indicates that the shifting process has ended, and the signal PSVIl means that a single shift still has to take place.

When an output signal from the AND circuit 14 C-29 is present, the flip-flop circuit 14 C-27 is switched to its shifted state. The AND circuit 14 C-29 has four input lines. It is blocked either by the PSR 00 or the PSV 11 signal. Both signals ensure that the flip-flop circuit 14 C-27 is not switched to the shift state by interference signals after the shifting process has ended. If the signals PSR 00 and PSV 11 are not present, the function table signal FT 602 generated by a shift command 07 switches the flip-flop 14 C-27 to the shift state at time pi 15.

The shift and hold signals of the latch i? P-2 are primarily generated by the flip-flop 14C-32. The flip-flop circuit 14C-32 is switched to the shift state by the output signal of the AND circuit 14C-33, while it is switched to the hold state by the clock signal pt U. At the inputs of the AND circuit 14C-33 are the clock signal p / 15 and the function table signal FT 510, which has the same task as the function table signal FT 602 just described. The operation of the flip-flop circuit 14C-32 and its control result from the description the flip-flop 14 C-27.

14C also shows an AND circuit arrangement 10-47 to which the AND circuits 14C-35 and 14C-36 belong. During an add or subtract command, the function table signal FT 504 is generated and information is supplied to the adding / comparing unit 10-41. Similarly, when the complement is formed again, the function table signal FT 508 is generated in order to supply information to the adding / comparing unit 10-41.

The purpose and function of these signals can be seen from the description of the adder-comparator. At this point it should only be mentioned that the AND circuits 14C-35 and 14C-36 do the job have, the information shifted out of the intermediate memory i? P-l to the adder-comparison unit 10-41 feed.

The scrolling process will now be discussed in connection with Figures 14D and 14E.

FIG. 14D shows, in simplified form, four stages of the buffer memory RP-I shown in FIG. 14C. As has already been mentioned repeatedly, the pulse shaping elements such. B. the pulse shaping element 14C-13, a pulse is supplied during a first time t , whereupon this pulse shaping element generates an output signal during the next time t. 14D shows four such pulse shaping elements or delay devices 14 DU, 14D-12, 14D-13 and 14D-14.

Assume that a hold signal labeled A is coupled to lines 14D-15, 14D-16, 14D-17 and 14D-18. The timing relationship of the hold signal A to the other signals is shown in Fig. 14E. If a pulse B is fed to input line 14 D-19 at time ^, then a pulse time (currently) a pulse C appears on line 14 D-20. Since the hold signal A is present at one input of the AND circuit 14D-21 and the signal C is fed to the other input at the time t _s via the line 14D-20, this AND circuit thus generates a signal D on the line 14 D- 22nd The arrows beginning at 14D-23 in Figure 14E graphically show the progress of this operation.

The signal is on line 14D-20 until the end of time i ₀ . It can be seen from FIG. 14E that a displacement signal E is generated at time t ₀ and, on the other hand, the hold signal A comes to an end at the same time. With the termination of the hold signal A , the signal D also comes to an end, since the AND circuit 14D-21 is no longer open. The pulse D, which occurred at the time i ₇ , appears at the time t ₀ as the pulse C. The pulse C becomes the pulse F at the time t ₀ , since the AND circuit 14 D-24 is based on the displacement signal supplied at the time t ₀ E is opened. The pulse F passes through the pulse delay device 14D-12 and becomes the pulse G at time ij.

Since the AND circuit 14 D-25 is not open due to the absence of the hold signal A at the time t _t , the signal H is only very weak and can be disregarded here. The signal B was thus stored in the delay device 14 DU during the four pulse times t _s , i ₆ , t ₇ and t ₀ and was then shifted in order to appear as signal G at time t _t. As the graph in FIG. 14E shows, the shifting process is continued until the shifting signal E is terminated at the beginning of time i _3. At the end of the displacement signal E , the pulse B appears as the pulse M of the pulse delay device 14D-14.

Clock

provide set signals pt. In addition to the input to which the signal i6 is coupled, the AND circuit 15-17 has two further inputs. A signal from the main clock generator is connected to one of these two additional inputs 5 for the purpose of synchronizing the pulses ptl to pt 14. The function table signal FT 601 can appear at the third input of the AND circuit 15-17. By connecting this function table signal,

F i g. 15 shows a detailed block diagram of FIG
10-23 in Fig. 10. the
present data processing system works with
eight main clock pulses i0 to ti and sixteen secondary clock pulses pt 0 to pt 15.
in which the clock pulses iObis ti are generated
in the description of the system with »small« - or

“Short period” denotes, whereby the AND circuit is blocked for the implementation, so that the signal t6 for the individual operations does not indicate “small” or “short periods” in the second signal delay device 15-16. How can be fed. It should be noted that the Im shows the designation "pi" (clock for the processing pulse ti at the same time as the pulse pi7 processing system), the clock pulses "pi" will occur in. The function table signal FT 601 has the connection to the arithmetic unit of the central processing unit, which is used by the second signal delay processing system. 15 shows a device 15-16 generated pulses pi one after the other main clock generator 15-11, in which one of the eight further pulses pi is to be added. Sixteen crystal-controlled oscillator is involved, which requires the successive pulses to be the speed of the periodically recurring clock when pulses are determined from one of the buffers RP-I . These time or clock pulses generated by the main clock generator 20 and RP-2 information for the adding-comparison tool can be transported to all 10-41 (FIG. 10). That parts of the system are fed in order to form sixteen successive intervals in this process and to regenerate damaged pulses. pulse pt are required, the pulses that have been derived from numerous devices written in the adder-comparison unit 10-41 are damaged in that their amplitudes become visible. As long as no Funktionstabellentude damped, its rise and fall time verän- signal FT is turned on 601, passes through the Imdert be, etc. These pulses must therefore re- pulse 1 6, the AND circuit 15-17 and the OR are generated. Such a regeneration can be accomplished in circuit 15-18 in order to generate the pulses pi 7 in various ways. So will initiate up to pi 14, which is connected to the eight Signalanzapz. B. at some points of the present arithmetic 3 ° fung the delay device 15-16 generates a main clock pulse to an AND circuit. If, on the other hand, the function table end pulse is fed during the second or coupled to the subsequent short period to be regenerated, this AND signal FT 601 coupled to the AND circuit 15-20 then generates a suitable pulse. pelt, then the signal pt 14 is synchronized via the AND switch 15-20 to the delay device 15-21 from the main clock generator 15-21 and coupled in time at certain intervals, which generates eight signal taps using a reference value . As the clock pulses gen pt to 15 pt 6 are generated, from Fig. 15 it can be seen the master clock starts the same time, the AND circuit 15-17 is locked, sensorless its activity when coupling a start signal so that the next time t6 pt 14 signal that 4 ° generated by a start signal source 15-12 cannot be transmitted. Instead it will. In addition to the main clock signal pt 6 , the start signal is sent to OR 15-11 via line 15-22 and a signal delay device
15-14 supplied via the OR circuit 15-13,
wherein the signal delay device has eight signal taps. In the drawing, the 45
Signal generator for the signals i and pt shown as a delay device. However, it can also
another device such. B. a ring counter, a
Decade counters, etc. are provided, the special signals using a start signal as 50, two more time references can be generated to the AND circuit 15-20. tere input signals can be coupled. The start signal is fed to the signal delay in the second input of this AND circuit device 15-14, which provides eight precise signals t, clock signal from the main clock generator via line i0 to i7. The pulse ti is fed to the AND 15-23 in order to feed the pulse ptl4 in a similar circuit 15-15, where it is synchronized or regenerated by a precise clock pulse from the master clock 15-11 is pre-generated or reset in time at the AND circuits 15-15 and 15-17. Was taken on this. The third input of the AND mode ensures that the signals t are always synchronous. Circuit 15-20 is known to function with the pulses of the main clock generator. The table signal FTöOl is supplied. If the additionally synchronized signal i7 of the AND circuit 15-15 60 borrowed eight clock pulses pt 15 to pt 6 is not required, the generation of the pulses t causes the second so the function table signal FT 601 is also short period. The other i-pulses are then not coupled into; the clock signal pi 14 is thus generated in the same way as the i-pulses of the first short period not added to the signal delay device 15-21. directs. At this point it should be mentioned that the signal i6 is sent to the delay device 15-16 consisting of eight signal taps 65 signal pt 15 - if it is generated - synchronous fungen with the clock signal i7 occurs via the AND circuit 15-17 and In summary, it can be stated that circuit 15-18 is coupled to generate a total of eight main clock signals at exactly eight times

Circuit 15-18 is coupled so as to provide sixteen pulses pt as long as the function table signal FT 601 is on.

The last signal pt 14 of the signal delay device 15-16 is fed to the third signal delay device 15-21 via the AND circuit 15-20 in order to initiate the generation of the eight pulses pi 15, pi0 to pi 6. In addition to the clock signal pt 14

correspond to a short period. In addition, eight clock signals pi 7 to pt 14 are provided as well as a further eight clock signals pi 15 to pt 6, which can be added one after the other to the first-mentioned eight clock pulses pt in order in this way to provide a period of sixteen clock pulses pi. The clock pulses / and pi are generated by three signal delay devices controlled by a main clock generator, the main clock generator synchronizing the clock signals at the respective input circuits of the three delay devices. The generation of the clock signals pt is controlled by the function table signal FT 601, which on the one hand prevents a clock pulse i6 from generating the clock pulses pt in the delay device 15-16 and on the other hand the generation of a

Caused clock signal pt in the signal delay device 15-21.

If the function table signal FT 601 is not generated, the clock signals of the delay device 15-14 have the following temporal relationship to the clock signals of the delay device 15-16: The clock pulse ti is generated at the same time as the clock pulse ptl, while the clock pulses iO, il, i3, t4 and i6 are generated at the same time

ίο are like the pulses pt 8, pt 10, pt 11, pt 12, pt 13 or pt 14. If the function table signal FT 601 is generated, the time correspondence of the signals t and pt can be taken from the table below. It should be noted that the FunktionstabellensignalFT601 a short period occurs at time 1. 6

i70123456701234567 pt 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

16 shows a more detailed view of the program counter in FIG. 10. As can be seen from FIGS. 10 and 12, the program counter controls the instruction decoder 10-17. The command decryption device 10-17 is a matrix consisting of AND circuits, the inputs of which are controlled by the digits stored in the flip-flops 51 to 60 of the command register IR-I and the output signals PPC Ibis PPC 4 of the program counter 10-19 will. The program counter cooperates with the flip-flops 51 to 60 of the instruction register IR-I in order to successively provide output signals to the instruction decryption device 10-17. Assuming that the command digits in the flip-flops 51 to 60 remain unchanged, the command decryption device energizes a new output line PLO to PLN (FIG. 12) whenever the output signal of the program counter is changed. The program counter is used for all instructions that require more than a short period to execute. So z. B. in the case of a command (command 14) which requires the storage of data in a register of the central processing system, the following operations must be carried out: First, the command would have to go to the location in the memory that is indicated by the iV digits of the command. In the following short period the data in the selected memory location would be available and new function table signals would have to be generated in order to carry out the second stage of the instruction, namely, the data in the register RP-I (FIGS. 10, 14A and 14C ) to be saved.

The program counter 10-19 generates four output signals, which are designated with PPCl, PPC 2, PPC 3 and PPC 4. These output signals are provided by the matrix 16-26, which consists of the four AND circuits 16-22, 16-23, 16-24 and 16-25. The inputs of these four AND circuits are connected to the outputs of the four flip-flops 16-18, 16-19, 16-20 and 16-21 . The output signals of these four trigger circuits are coupled to the inputs of the AND circuits 16-22 to 16-25 as follows:

1. The reset output signals of the flip-flops are at the inputs of the AND circuit 16-22 16-21, 16-20 and 16-19 as well as the setting output of the flip-flop circuit 16-18 at.

2. The reset output signals of the flip-flops are at the inputs of the AND circuit 16-23 16-21 and 16-20 as well as the setting output signals of the flip-flops 16-19 and 16-18 at.

3. The reset output signals of the flip-flops are at the inputs of the AND circuit 16-24 16-21 and 16-18 as well as the setting output signal of the flip-flop circuit 16-20.

4. The reset output signals 16-20, 16-19 are at the inputs of the AND circuit 16-25 and 16-18 and the setting output of the flip-flop 16-21.

All of the flip-flops 16-18 to 16-21 are controlled by the signal N generated by the AND circuit 11-29 (FIG. 11). So the output of the AND circuit 11-29 is directly connected to the reset input of the flip-flop 16-21 and to the setting input of the flip-flop 16-18, while it is connected to the reset inputs of the flip-flops 16-19 and 16-20 via the OR circuits 16-12 or 16-14 is connected.

The output of the OR circuit 16-11 is applied to the reset input of the flip-flop circuit 16-18, at the inputs of which the signal RCP generated by the AND circuit 26-10 (FIG. 26) and the signal RCP generated by the AND circuit 16- 15 generated signal PPCS 3 are coupled. The signal PPCS 3 is generated when the program counter is to be incremented so that it generates the signal PPC 3 at the output of the AND circuit 16-24. The signal RCP is generated by the AND circuit 26-10 if the complement is to be formed again for a result generated by the adder-comparison unit 10-41 (FIG. 10). This AND circuit 26-10 forms part of the arithmetic control unit 10-42.

The setting input of the flip-flop circuit 16-19 is that generated by the AND circuit 16-16

Signal PPCS 2 switched on. Normally, this signal causes the program counter 10-19 to generate the signal PPC 2 at the output of the AND circuit 16-23. By connecting the signal N or the signal PPCS 3 to the reset input of the flip-flop 16-19, the latter is switched to the reset state. Both signals are fed to this flip-flop via the OR circuit 16-12.

The output signal of the OR circuit 16-13 is applied to the setting input of the flip-flop circuit 16-20, at whose inputs the signal PPCS 2 generated by the AND circuit 16-15 and the signal PPCS 2 X generated by the AND circuit 16-17 are coupled. As will be described in more detail in connection with the data transfer commands (e.g. commands "15" and "12"), the signal PPC 2 X always sets the flip-flop 16-20 when the flip-flops 16-18 to 16- 21 generate signals that are not deciphered by the AND circuits of matrix 16-26. In addition to resetting the flip-flop circuit 16-20 by the signal N , this circuit is also reset by the signal RCP conducted via the OR circuit 16-14. The signal RCP is also _{fed to the setting input a5 of} the flip-flop circuit 16-21.

The function table signal FT 612 and the clock signal pt13 generated by the clock generator (FIG. 15) are present at the inputs of the AND circuit 16-15 which generates the signal PPCS 3. As already mentioned above, this signal generated by the AND circuit 16-15 causes the program counter 10-19 to generate the signal PPC 3 at the output of the AND circuit 16-24. If the program counter is to be switched from PPC 2 to PPC 3 , one of the AND circuits of the decryption device 12-17c (FIG. 12) must be opened by the signal PPC 2 in order to energize one of the lines PLO to PLN , which then for their part, in addition to other OR circuits, must control the OR circuit which generates the function table signal FT 612.

The clock signal i0 of the clock generator (FIG. 15) and the function table signal FT 620 of the encryption device 10-18 (FIGS. 10 and 12) are present at the inputs of the AND circuit 16-17 which generates the signal PPCS 2 X. The function table signal FT 620 is generated when the program counter 10-19 generates the signal PPC 2 and no further signals are to be generated by the program counter. The signal PPC 2 opens an AND circuit in the decryption device 12-17 C, the output signal of which, in addition to other OR circuits of the encryption device 12-18, controls that OR circuit of this device which generates the function table signal FT 620 for commands in which the PPC 2 signal should be switched off without coupling the program counter to another output line.

The AND circuit 16-16 generates the signal PPCS 2, which is coupled to the setting input of the flip-flop circuit 16-19 in order to cause the program counter to generate the signal PPC 2 at the output of the AND circuit 16-23. At the inputs of this AND circuit are located on three Durchlaßsignale and an inhibiting signal, and that the function table signal FT 600, the signal MNB, the clock signal ti from the clock and the on line PL 143 of the decryption device 12-17 c occurring inhibit signal. Signals that are coupled to line PL 143 are generated by a return command (command "14") when the program counter generates a PPC 3 signal. The reason why the AND circuit 16-16 is blocked by a signal appearing on the line PL 143 will be described in connection with the command "14".

During operation, the signal N generated by the AND circuit 11-29 is coupled to the inputs of the flip-flops 16-18 to 16-21 at the time t _s. By connecting the signal N to these flip-flops, the corresponding combination of setting and reset signals is generated at the time t _e , as a result of which the AND circuit 16-22 can generate the signal PPC 1. As is known, the signal N is always generated when a new command is to be transferred from the command register IR-2 to the command register IR-I for the purpose of execution, so that the program counter for each command is reset or cleared at the beginning of the execution of the command, to generate the signal PPC 1. To generate the signal PPC 1. The signal PPCl is fed to all AND circuits of the decryption device 12-17c (FIG. 12) which are required for the execution of the first stage of an instruction stored in the flip-flops 51 to 60 of the instruction register IR-I. It should be noted that the AND circuits of the decryption device 12 to 17 c do not need to be opened by commands to their implementation, only one step is required. These AND circuits are controlled by any output signal from the program counter. The program counter is incremented by the signal PPCS 2, ie it terminates the signal PPCl and instead generates a signal PPC 2. The signal PPCS 2 is applied to the setting input of the flip-flop 16-19. The program counter is then incremented again by the signal PPCS 3, which is fed to the setting input of the flip-flop circuit 16-20 via the OR circuit 16-13 and the reset input of the flip-flop circuit 16-19 via the OR circuit 16-12, to the program counter to cause the generation of the signal PPC 3.

The signal PPC 2 causes the command decryption device 10-17 to generate the function table signals FT 705 and PT 707 during the second command stage, as a result of which information can be stored in the command register IR-I or IR-2 from the memory. The signal PPC 3 causes the command decryption device 10-17 to generate function table signals during the third stage of a multi-stage command, by means of which the adder-comparison unit comes into operation. Finally, the program counter 10-15 is optionally switched from PPC 3 to PPC 4 by the signal RCP , which the reset inputs of the trigger circuits 16-20 and 16-18 via the OR circuits 16-14 or 16-11 and the setting input of the trigger circuit 16-21 is supplied if the complement has to be formed again for a result generated by the addition-comparison unit. This process will be described in detail later.

27 shows a further part of the arithmetic control unit 10-42. The circuit arrangement shown in this figure generates in accordance

509 538/373

with the signs of the operands in the registers RP-I and RP-2 as well as the signals CPE, CPL, UFE and CPE in accordance with the operation identified by the instruction in the instruction register / i? -l. The signals CPE and CPL are generated during an addition if the summands to be added have different signs. The same signals are also generated with a subtraction, with the same sign of the operands. The signals CPL and CPE are generated in the case of addition when the signs are equal, and in the case of subtraction when the signs are not equal. Either the signals UFE or the CP E or the signals CPE and CPL are generated.

The signal CPL is generated at the reset output of the »5 complement flip-flop 27-10 and the signal CPL is generated at the setting output of the same flip-flop. The signal CPE, which is generated at the same time as the signal CPL , appears at the output of the OR circuit 27-19, one input of which is applied to the setting output of the complement flip-flop 27-10. The signal CPE is periodic To membered 27-20 produced by inversion of the signal by d CPE as. The signals CPE and CTE are mutually exclusive. The output signals of the AND circuits 27-18 and 27-12 are also present at the inputs of the OR circuit ^a 5 27-19.

The complement flip-flop 27-10 is reset by the clock signal pt 13 of the clock generator and set by the output signal of the OR circuit 27-11 . The signals of the AND circuits 27-18, 27-12, 27-14 and 27-15 are present at the inputs of this OR circuit.

Aq the inputs of the AND circuit 27-12 are the output signal of the sign comparator 27-16 and the output signal of the AND circuit 27-13 . The AND circuit 27-13 is opened by a clock signal pt0 of the clock generator (FIG. 15) and a function table signal FT 503 generated during subtraction.

The AND circuit 27-14 is opened by a clock signal pt 15 of the clock generator and a function table signal FT 507 . The function table signal FT 507 is generated with command 18 (equality check) and with command 19 (size check).

The clock pulse pt IS of the clock generator (FIG. 15) and also the function table signal FT 508 are also present at the inputs of the AND circuit 27-15. This function table signal is generated during the fourth test of the add or subtract commands, ie when the program counter generates a signal PPC 4.

The clock signal pi0 of the clock generator (FIG. 15) and the function table signal FT 502 of the encryption device (FIGS. 10 and 12) are present at the inputs of the AND circuit 27-17. The function table signal FT 502 is used for all add commands, ζ. Β. at command 10.

The signs of the operands stored in the registers RP-I and RP-2 are present at the inputs of the sign comparison device 27-16. The inputs of the sign comparison device are connected to the output terminals 14A-12B 1 to 14A-12BS of the twelfth digit of the register RP-I and to the output terminals 14B-12B1 to 14B-12B5 of the twelfth digit of the register RP2 .

The sign comparison device 27-16 consists of a number of AND circuits for comparing the signs of the operands contained in the two registers RP-I and RP-2. If the signs are not the same, a signal is fed to the input of the AND circuit 27-18, and if the signs are the same, a signal is coupled to the AND circuit 27-12. Devices for performing such tasks are already known in the art and are therefore not described here.

If one of the two AND circuits 27-14 and 27-15 generates an output signal at time pt ₁₅ , this signal is fed to the setting input of the complement flip-flop 27-10 via the OR circuit 27-11, so that the flip-flop a signal CPL is generated at the instant pt _ie. This signal is fed to the OR circuit 27-19, which generates the signal CPE at the time pt _16. If a signal is coupled from one of the two AND circuits 27-17 and 27-27-13 to the AND circuits 27-18 or 27-12 at the point in time pt ₀ , the output of the AND circuit 27-19 is Signal CPE generated at time pt _0. It can also be seen from the drawing that the outputs of AND circuits 27-18 and 27-12 are also coupled to the setting input of complement flip-flop circuit 27-10. The signal CPL is therefore generated at the point in time Pt ₁ on the basis of a signal which is fed to the flip-flop circuit from the AND circuit 27-17 or 27-13. In the latter case, the signal CPE is generated one pulse time before the signal CPL.

Adding comparison work

Before the addition and comparison unit is described in detail, some basic principles follow Considerations. A biquinary code is used in the present computer system, i. H., a digit encoded according to this code consists of five bits, the first three of which are quinary Represent part, while the fourth and fifth digits identify the binary part or the parity control bit be used. As the L-code described earlier shows, the quinary part is different for the digits 0 to 4 and then repeated in the same order for the Digits 5 to 9. The computer can distinguish between two digits using the binary code, which have the same quinary part. For this purpose, the digits 0 to 4 are given a binary, "0" and the Numbers 5 to 9 are assigned a binary "1". As the L-code also shows, for every even digit entered in has an even number of binary ones in the first four digits, a binary "1" and odd for each Digit with an odd number of binary ones in the first four digits, a binary "0" provided for the purpose of parity control. In other words, the decimal "2" has a binary "1" as Parity check bit, because the ones of their quinary and binary parts result in an even number. Against it the decimal "3" has a binary "0" as the parity control bit, since the ones of its quinary and binary Partly result in an odd number.

The adding-comparator works according to the principle, according to which the quinary and binary parts of the individual Digits are treated separately from one another and combined with one another in order to be used in the arithmetic and logic unit

93 94

to form the correctly encrypted answer. SHOULD From the above description follows

z. B. the numbers 1 and 7 are added together, so that an addition in which the operands so the quinary part of the "1", namely 001, must have the same sign, and a subtraction, quinary part of the "7", 011, can be added. in which the signs of the operands are different The result of this addition is the quinary value 5, arithmetically representing one and the same operation -111, who order either the number 3 or the number 8. In other words: the computing elements, can interpret. By its binary part it becomes the one to carry out this operation in the before-number 7, however, has still been completed, so that the lying computer system is provided to deal with The result is a value of 1111, which is used as a parity check digit for an add command such as a subtract command or a subtract command. Contains "1" and thus indicates that the result of io is reversed if the operands have just beAddition 8 is called. have the written algebraic sign. An add command, in addition, when adding two quinaries in which the operands have different signs divide a quinary carry signal generated if the have, as well as a subtract command, in which the pre-sum 5 or greater. In other words: If characters of the operands are the same, so require the quinary part of the number 2,001, to the quinary part 15 essentially the same for its implementation Adding 111 to the number 3, then in this operation.

In the case of a quinary carry signal, a sub-correct Answer (i.e. it is done in the traction by adding the binary part of the answer, a binary "1" is added to the complement and added to the end of the minute). This principle of generating an over-20 is added. In the present system, datragssignals is still used in conjunction with the addition-comparison unit at the complement of the subtrahend to 10 ge described in more detail. forms by in the one shown in FIG

As has already been mentioned elsewhere, the complement circuit arrangement forms the complement of the signs of the operands or the algebraic to 9 and then adds a bit to the lowest-order sign of the contents of the register RP-I 25-valued digit of the difference obtained RP-2 is in the twelfth digit of this register. Saved in connection with the following description. Instead of these sign values, the result is that the content of the register RP-I nen but also numerical values are stored in the twelfth position at the end of the minute and the content of the register RP-2 , which is included in the description. represents the subtrahend. This is important in that "unsigned" state is referred to. 30 as the logic of the present computing system thereof

Before the operation of the adder is based on the fact that, in the case of a complement formation, comparison work is described, the contents of the register and should have the same sign (e.g. in the case of a subtraction in which the operand digit is repeated another basic rule) in which way the sign of the RP-2 is to be viewed as a subtrahend, ie that operands are evaluated algebraically. The complement is to be formed in this context. The following must be observed: If the signs of both times are the same as the complement to the register RP-2 operands and if there is an add command, then it is formed. If, on the other hand, another complement is formed by the complement flip-flop 27-10, a no-complement signal CPE and the register RP-I are also formed for the content of (FIG. 27). Another CPL generated. The result of such an addition 4 ° complement formation is the sign of the register RP-I with an arithert. Have mathematical subtraction required (ie in the case of a sign and addition different from the operands, in which the summands different intentions are again added, have characters, or in the case of a subtraction in which the complement toggle 27-10 the signs of the operands are the same) when a complement signal generates CPE and CPL , where the subtrahend has a greater absolute value than the minuend formed by the complement to the subtrahend. The re-formation of the will. If the result of this second complement is carried out by transferring the information via arithmetic operation from the most significant - the shift register, the normal digit is generated, the result takes the subtraction or the content of the intermediate character of the register RP- I at. Results contrast 50 rule memory process RP-2, and from there to shall be forwarded no over- Komplementschaltungen in Fig. 21 in earnings this second operation contract from the most significant digit, the register or buffer memory RP-I must at this Content Result, the complement can be formed again, and RP-2 is with »Minuend« or »Subtrahend«, with the result then having the opposite prefix. The content of the buffer RP-I characters of the register RP-I receives. If, however, it is also a question of a subtraction or an instruction and the operands which represent, while the contents of the buffer store have the same sign, a complement signal RP-2 can be an addend. As already created in Ver CPE and CPL . If the answer is binding with F i g. 10 was mentioned, if the event is carried over, this response receives the sign of the result of the arithmetic processing of the operand of the register jRP-1. If, however, there is no carry over, the registers i? Pl and RP-2 from the adding-verdann must also be stored again in the register .RP-I for this response. Complement can be formed, whereupon the result. If, on the other hand, the operating mode of the present adding section is not the same when a sub-type is carried out, the signs of the operands are not equal, 65 comparison work is based. These basic rules are a no-complement signal CPE and CPL is generated in the detailed description that follows. The result of this fourth operation receives the operation of the adder-comparison unit with in this case the sign of the register RP-I. consider.

FIG. 17 shows a block diagram from which the flip-flops for the various control signals of the signs can be seen. A sign toggle circuit 17-10 is assigned to the register RP-I and is switched to its set state by an output signal of the AND circuit 17-11 and to its reset state by an output signal of the OR circuit 17-12. The output line coming from the decryption device 17-13 and a clock signal pt 0 are present at the inputs of this AND circuit 17-11. The decryption device 17-13 has five input lines 14 ^ -12G1 to 14A-12G5. As already described in connection with FIG. 14A, the lines IAA-U G 5 to 14 A -12 Gl represent the second signal path via which the information supplied to the register RP-I in parallel can be transported to other parts of the system. The decryption device 17-13 is already known in the art and in the present case consists of a coincidence device, the lines 14A-12G4 to 14A-12G1 of which act as blocking lines, while the line 14A-12 G 5 represents a transmission line. The decryption device or coincidence matrix 17-13 is arranged in such a way that the encrypted bits of a plus sign (10000) generate an output signal on the line 17-14 if there is actually a plus sign in the twelfth digit of the register RP-I. Under the influence of an output signal appearing on line 17-14 and a clock signal piO that is switched on at the same time, the AND circuit 17-11 generates a signal, whereby the flip-flop 17-10 is switched to its set state and thereby a signal on the line 17 -15 is coupled to indicate that the register RP-I contains a positive sign. This positive sign signal appearing on line 17-15 is labeled PRAS. It can be seen from the drawing that the clock signal pt0 is also coupled to the OR circuit 17-12 at the same time. As already mentioned, when two signals are coupled to a pulse-shaping multivibrator, the setting signal takes precedence over the reset signal, so that the multivibrator is switched to its setting state. In the present case, however, the coupling of the signal piO to the OR circuit 17-12 ensures that the flip-flop 17-10 is switched to its reset state if no output signal is coupled to the line 17-14 from the encryption device 17-13 . Switching the flip-flop 17-10 to its reset state indicates that the sign contained in the register RP-I is negative. As shown in FIG. 17 as can be seen, the signal N is present at the other input of the OR circuit 17-12, which has the task of resetting the flip-flop 17-10. The signal N is known to be generated when a command register IR-I (F i g. 10) contained instruction is executed and the next instruction from the instruction register ^ is to be re-stored in the instruction register IR-I //?. In the present case, the coupling of the signal N ensures that the flip-flop 17-10 is switched to its reset state for each new command, so that the signal for the sign possibly required by a new command can be generated anew.

F i g. 17 also shows the sign toggle circuit 17-16 for the register RP-2. The output lines of the AND circuit 17-17 and the OR circuit 17-18 are applied to the inputs of this flip-flop 17-16. The flip-flop circuit 17-16 is switched to its set state by the signal from the AND circuit 17-17, while the flip-flop circuit is switched to the reset state by the signal from the OR circuit 17-18. The input lines to the AND circuit 17-17 are similar to the input lines to the AND circuit 17-11. The one input line to the AND circuit 17-17 establishes the connection to the decryption device 17-19, which in turn establishes the second signal path for the bits of the twelfth digit of the register RP-2 via the lines 14B-12C5 to 14B-12G2 . The clock signal ptO can be switched on at the other input of the AND circuit 17-17. The OR circuit 17-18 also has two inputs, the first input for coupling the clock signal pt0 and the second input for coupling the signal N being provided. Both signals serve the same purpose as the signals coupled to OR circuit 17-12.

As is known, a digit can also be stored in the twelfth digit position instead of a sign value. The computing system must therefore be able to determine whether the twelfth digit actually contains a sign or not. For this purpose, the flip-flops 17-20 and 17-21 are provided, which determine whether there is actually a sign in the twelfth digit of the register RP-I or RP-2. The flip-flop 17-20 has two inputs, the first of which is connected to the output of the AND circuit 17-22. By an output signal of this AND circuit 17-22 to flip-flop is switched lzustan d in its SET 17-20 and thus generates a signal PANS, thereby indicating that a sign is in the twelfth digit. The output signal of the decryption device 17-22 and the clock signal i0 are present at the inputs of the AND circuit 17-22. The decryption device 17-23 is already known in the art and has been described in connection with the AND circuit 17-26. The flip-flop circuit 17-20 is switched to its reset state by the OR circuit 17-24. The clock signal pt 13 and the signal N are present at the inputs of this OR circuit 17-24. At time pt ₁₃ , ie during an add or subtract command, or when the signal N is generated, the flip-flop 17-20 is switched to its reset state, so that a signal PANS is generated which indicates that the register contains no sign .

The inputs to the flip-flop 17-21 are similar to the inputs to the flip-flop 17-20, with the OR circuit 17-25 of the OR circuit 17-24 and the AND circuit 17-26 of the decryption device 17-23 and the AND circuit 17-22. The AND circuit 17-26 is shown as a decryption device. The plus sign is represented by bits 10000 and the minus sign by bits 00010, as is well known. From the representation of the information units for

The plus and minus signs result in the fact that the presence of a binary signal "1" in the fourth, third or first bit position indicates that there is no sign in the twelfth digit position. Lock signals are therefore coupled to AND circuit 17-26 via lines 14B-12G4, 14S-12G3 and 14B-12G1.

In summary it can be stated that with the help of the in Fi g. 17, the information stored in the twelfth digit position of the register RP-I or RP-2 can be checked whether it represents a sign and, if so, whether this sign is positive or negative. The first test is carried out by the flip-flops 17-20 and 17-21, the second test by the flip-flops 17-10 and 17-16.

The device shown in FIG. 20 is used to generate further sign signals. This circuit determines whether the sign signals are coupled directly or not. The term "direct coupling" or "direct connection" used in the present description means that the information units contained in the twelfth digit position are fed directly to the result circuit arrangement (FIG. 25) and not to the AND circuits of the adder-comparison unit. In some cases, the sign of the result is determined directly on the AND circuit 25-11 (FIG. 25) or on the OR circuit 255-17 (FIG. 22) in conjunction with the signals PRAS and PRAS . If there are numerical values in the twelfth digit position, these can also be fed directly into the result circuit (FIG. 25). The circuits provided for this purpose are shown in FIG. 20 shown.

From Fig. 20 it can be seen that, in accordance with the output signal of the AND circuit 20-11, a signal PALPH and the reverse signal PALPH are generated or not, depending on the conditions. The AND circuit 20-11 has two inputs to which the clock signal pt 11 and the function table signal F7500 are present. As is known, the function table signal FT 500 is generated when an add or a subtract instruction is to be carried out. The signal PALPH only indicates that the sign of an operand can now be transmitted directly if a direct coupling is desired.

Like F i g. 20 further shows, the signal PAMP and the signal PAMP are generated at the output of the OR circuit 20-12 after a delay of one pulse time. The signal PAMP indicates that the information contained in the twelfth digit of the register RP-I (Minuend) is to be fed directly into the result circuit (FIG. 25) such as, for example, into the AND circuit 25-15. The OR circuit 20-12 has two inputs, the first input being connected to the output of the AND circuit 20-13 and the second input being connected to the output of the AND circuit 20-14. The AND circuit 20-13 has four inputs; the first input has already been discussed in connection with the output of the AND circuit 20-11. The signal UFL , which is generated by the complement flip-flop circuit 27-10 (FIG. 27) and indicates that a complement formation is not required, is connected to the second input. The generation of the signals CPE, CTE, CPL, CP and OFL is described in connection with FIG. 27 described. ChaLt to the other two inputs of the AND-S ung 20 -13, the sign signals PANS and PBN are coupled, the g of the discrimination arrangement in Fi. 1 7 were generated. As is known, the signal PANS indicates that a sign is in the twelfth digit place of Regist ers RP -I, while the signal indicating pbNs that RP-2 is a sign in the twelve digit order of the register. If there is a sign in the twelfth digits of the registers RP-I and RP-2 and a complement formation is not required, see v. A signal PAMP is generated by the pulse delay device 20-15. From the description of the signs in connection with the AND circuit 20-13, it follows that when a signal CPL is switched on and an add command is carried out (function table signal FT 500), the sign of the minuend is shown with the correct sign and fed directly to the result circuit in FIG is.

The AND circuit 20-14, which the OR

Controls circuit 20-12 has five inputs. The input signals FT 500, pt 11 and PBNS have already been described in connection with the AND circuit 20-13. The fourth signal PANS applied to this AND circuit merely indicates that there is no sign in the register RP-I. The function table signal FT 504 present at the fifth input is generated either with an add or with a subtract command.

If the twelfth digit of the register RP-I is not a sign, but a digit, while the register RP-2 contains a sign, an output signal is generated by the AND circuit 20-14, which indicates that the register RP -I digit information contained has priority over the sign information of the register RP-2 and is to be fed to the response circuit (Fig. 25).

The circuit arrangement for the direct coupling of the subtrahend can also be seen from FIG. The signal for the direct coupling of the subtrahend is denoted by PASP . As shown in Fig. 20, the signals PASP and PASP are generated by the pulse delay device 20-16. The input of the pulse delay device 20-16 is connected to the OR circuit 20-17, which in turn has two inputs; one input is connected to the AND circuit 20-18 and the other input to the AND circuit 20-19. Four input signals are connected to the inputs of the AND circuit 20-18: The first input signal is the signal PBNS, which indicates that there is no sign in the register RP-2. The second input signal is the clock signal pt U from the clock generator (FIG. 15). The third signal is the function table signal FT 500, which indicates that the AND circuit is in the preparatory state for add and subtract commands. The fourth input signal is the signal PANS, which indicates that there is a sign in the register RP-I. The AND circuit 20-18 thus generates an output signal when there is no sign in the register RP-2 , so that the digit information contained in the twelfth digit position of the register RP-2 is fed directly into the response circuit (FIG. 25) -

509 538/373

100

which ensures that this digit information is not lost. '

Before the AND circuit 20-19 is discussed, it should be pointed out once again that the complement to the subtrahend has been formed and added to the minuend before a further complement formation is carried out. For the purpose of description, the result of this latter addition is referred to as "initial result". The arithmetic unit transports the initial result to register RP-I. If a complement had to be formed in order to determine the initial result, the sign of the initial result is not the result of a direct injection, since - as FIG. 20 shows - the AND circuit 20-13 is not open (CPL not switched on). The sign of the initial result is therefore generated by the OR circuit 25-11 (FIG. 25) on the basis of an output signal from one of the AND circuits 25-31, 25-32 and 25-33. The generation of this sign is described in connection with FIG. 25 described in more detail. As already mentioned in the description of the sign, if the complement is formed again, the end result obtained in this way is provided with the original sign of the minuend or with the opposite sign of this minuend. This must be taken into account in the description of the AND circuit 20-19 which now follows.

If the complement is formed again, the function table signal FT 508 is generated and fed to the circuits in which the complement to the content of the register RP-I, ie the complement to the initial result, is formed. The AND circuit 20-19 represents one of the circuits which are required for the formation of the complement again. Since the content of the register RP-I corresponding to the initial result appears as a subtrahend, i.e. is passed through the shift registers which normally process the subtrahend information, the signal PASP must be generated in order to transfer the sign of the content of the register RP-I . On the basis of the determination of the computer that a new formation of the complement is necessary, the function table signal TF 508 and also the clock signal pill are connected to the AND circuit 20-19. In this way, the complement to the numerical content of the register RP-I, i.e. without a sign, is formed, while the sign of the initial result is passed on directly. As can be seen from the further description of the repeated formation of the complement, the sign of the initial result is correctly generated in accordance with the rules for the algebraic evaluation of the signs in the case of the end result, although the complement must be formed again for the numerical part of the initial result.

18 shows the AND circuit arrangement in order to be able to transport information from the register RP-I in parallel and in series to the adder-comparison unit. As stated earlier, the content of the register RP-I is often referred to as a minuend, although in reality it may represent an end or an instruction. Conversely, the content of the register RP-2 is often referred to as a subtrahend, although in reality it can represent an addend. From the drawing it can be seen that one of the outputs of the AND circuits 18-11 to 18-15 with 14.4-31, 14.4-33, 14.4-34, 14.4-35 and 14.4 -36 is designated. These inputs are connected to the output lines of the RP-I shift registers shown in Figures 14A and 14C. As already mentioned elsewhere, the function table signal FT 504 is generated in the case of an add or subtract command. So there is such a thing

ίο add command before and information signals occur at the same time on the output lines of the shift register of the buffer RP-I , the AND circuits 18-11 to 18-15 are selectively opened in accordance with the occurrence of the information signals. In other words: If all lines 14/1 in FIG. 18 an information signal is coupled, the signals P ^ Ml, PAMl, PAMZ and PAMA are connected via the corresponding OR circuits 18-16 to 18-20 to the AND circuits assigned to them in FIGS. 21 and 22. It can be seen from FIG. 18 that the reverse input signals, ie the signals TXM1, ΤΑΉ1, TÄM3 and TÄM4, are generated when no information signal occurs on one or all of the lines 14, 4. These reverse signals are generated by connecting the output lines to an inverter. These inverters, such as. B. pulse reversers 18-27 are known in the art. Such an arrangement closes the signals belonging to a pair, such as. B. the signals PAMl and PAMl mutually off. These reverse inputs are also provided to the circuitry shown in FIGS. As can be seen from the description of FIG. 21 and 22, the signals PAM and FZM are combined with the signals PAS and TÄS (FIG. 19) in order in this way to provide further signals, such as the signals PJ (FIG. 21), which correspond to the Designate the value of the operands.

As shown in FIG. 18 can also be seen, the influence of the information signals occurring on one or all of the lines 14, 4 and, with the simultaneous coupling of the function table signal FT 504, the signals PM1, PM1, PM3, PMA and PM 5 are generated. These signals PM essentially correspond to the signals PAM which have been delayed by one pulse time. The signals PM1 to PM4 are used to compare the operands with one another. These signals are therefore transported via the lines shown in FIG. 18 to the matrix (FIG. 13), which will be described later. The signals TM shown in Fig. 18 represent signals PM which are generated by inverters, such as. B. the reversing member 18-28, have been reversed. Due to the arrangement, the signals PM and TM are mutually exclusive. The signals TM are generated when no information signals appear on the lines 14, 4. The signals PM 5 and PM 5 become the one shown in FIG. 25 B supplied to the circuit arrangement shown in order to co-determine the control bit. This process will be described in more detail in connection with FIG. 25B.
Like F i g. 18 shows, five AND circuits 18-21 to 18-25 are also provided, each having two inputs. These AND circuits are connected at their outputs to the OR circuits 18-16 to 18-20 assigned to them.

101

102

the. The function table signal FT 508 is coupled to one input of the AND circuits and a signal corresponding to a binary “0” is coupled to the other input. As will be described in more detail below, the function table signal is generated when another complement formation is required. It is known that when the complement is formed again , the information contained in the register RP-I (initial result) is treated as a subtrahend and fed to the input circuits which are normally used for transferring information from the register RP-2 (FIG. 19). Since the complement to the information contained in the register RP-I is formed during the recomplement formation and since the arithmetic unit is designed in such a way that the operands must always be added together in order to obtain the result, the AND circuits 18-21 to 18- 24 binary zero signals are supplied from a zero register 18-26. These binary zero signals are fed to the arithmetic unit as minuend via the last-mentioned AND circuits, so that the complement of the contents of the register RP-I is only added to zeros, which ensures that the complement of the contents of the register jRP-1 leaves the arithmetic unit as the end result. The control bit circuit in FIG. 25B is supplied with zeros by the AND circuit 18-25 in order to ensure that the check bits formed by the complement of the contents of the register RP-I are not changed.

F i g. 19 shows the circuit arrangement in order to be able to supply the arithmetic unit shown in FIGS. 20 and 21 with the information from the register RP-2 in series and in parallel. Like F i g. 18 shows, for the subtrahend are AND circuits 19-12, 19-13, 19-18, 19-19 and 19-20 provided which generate an output signal when the associated lines 14 B information signals are coupled to them and if at the same time a displacement signal occurs on line 19-11.

The circuit arrangement in FIG. 19 operates in a similar manner to the circuit arrangement in FIG. 18. If an information signal appears on the lines 14B (FIG. 19), the input signals PAS1, PAS 2, PAS 3 and PAS 4 are optionally assigned to them AND circuits are turned on via the respective OR circuits 19-14, 19-15, 19-21 and 19-22. From Fig. 19 is obtained, d ate the ends ents Preche reverse signals (FAST, TASI, TAES TÄS3 and 4) are produced selectively when B 14 is present on the corresponding lines no information signal. These reverse signals are also fed to the circuit arrangement shown in FIG. As already mentioned in connection with FIG. 18, the signals PA S and TÄS (FIG. 19) are combined with the signals PAM and PAM (FIG. 18) to generate further signals, such as e.g. A signal PO (Fig. 21) indicating the value of the operands.

Assuming that a function table signal FT 504 is switched on, the signals PAl, PAl, PA3, PA 4 and PA 5 are also generated due to the coupling of information signals to each line 14Λ. These signals have been delayed by one pulse time each by the pulse delay devices 19-16, 19-17, 19-29, 19-30 and 19-31 assigned to them. The signals PA 1 to PA 4 are used to carry out comparison or equality checks on the operands. The signals are therefore connected from the lines shown in FIG. 19 to the matrix shown in FIG. 23, which will be described in more detail below. The signals TA are generated when B 14 is present on the lines no information signal. To determine the control bit, the signals PA5 and TÄ ~ 5 are fed to the circuit arrangement shown in FIG. The determination of the control bit is described in connection with FIG. 22 described in more detail. As already in connection with the similar circuit arrangement in FIG. As mentioned in Fig. 18, the signals PAS and PA are generated by passing the signals PAS and PA through an inverter, respectively. These inverters, such as inverters 19-32 and 19-33, which are provided for generating the signal PAST and TUT , respectively, are already known in the art. Both the signals PASl and PAST and the signals PAl and TAT are mutually exclusive.

From Fig. 19 it can also be seen that the five AND circuits 19-24, 19-25, 19-26, 19-27 and 19-28 each have two inputs. The function table signal FT 508 is present at one input of these AND circuits, while the information signals transmitted by the lines 14, 4 of the register RP-I are coupled to the other input. As has already been described in connection with the formation of a recomplement, the content of the register RP-I is regarded as a subtrahend and is transmitted via the current paths which are normally used by the information in the register RP-2 , ie via the AND circuits 19-12 to 19-20. The AND circuits 19-12 to 19-20 are also controlled by the shift signal coupled to the line 19-11, so that when such a shift signal is switched on, these AND circuits are opened when the lines 14 assigned to them B an information signal occurs. The input signals (PAS and PAS) of the subtrahend, which are generated on the basis of the output signals of the AND circuits 19-24 to 19-28, are thus generated under the influence of the information stored in the register RP-I , ie the initial result. When the complement is formed again, the signals PAS and TÄS are fed to the arithmetic logic unit shown in FIGS. 21 and 22 in order to be combined there with signals PAM representing binary zeros. This process has already been described in connection with FIG. The AND circuit 19-28 is provided for the transmission of the signal PAS or PA'S to the control bit circuit so that control bits can be generated from the information transmitted by the register RP1.

For a better understanding of the operation of the adder-comparison unit, it is assumed that the encrypted decimal +3 is in the register RP-I and the encrypted decimal +2 is in the register RP-2. It is also assumed that an add command is to be carried out and that the addition of the numbers +3 and +2 results in +5. From the arrangement in Fig. 14A it follows that in the first position of the five shift registers from top to bottom the encrypted decimal as

103

104

11100 is saved. The plus sign is stored in the twelfth position, also from top to bottom, as 00001. From the arrangement of FIG. 14B, the encrypted decimal 2 is stored as 11001 in the first position of the five shift registers, also from top to bottom. In the twelfth position is the plus sign, also stored from top to bottom as 00001. As already mentioned in connection with FIG. 18, the function table signal FT 504 is present when the add instruction is carried out, whereby the AND circuits 18-11 to 18-15 are prepared. Since at the same time on each line 14 Λ-31, 14 Λ-33 and 14,4-34 an information IO

signal is present, the AND circuits 18-11, 18-12 and 18-13 are opened and thus transmit an output signal to the OR circuits 18-16, 18-17 and 18-18 assigned to them. The output signals of these OR circuits represent the signals PAM1, PAM2 and PAM3 . Since no information signals appear on the lines 14 / 1-35 and 14 / 1-36, the AND circuits 18-14 and 18-15 are not opened either . T he OD ER circuit 18-19 therefore generates a signal ΡΑΜΆ, while the OR circuit 18-20 generates a signal PM 5, as also in connection with FIG. 22 will be described. For a better understanding of the addition (+3) + (+2), the signals generated during this addition are entered in Table 1.

Table 1
Exercise: Add +2 to +3 = 10011 (RP-Z) to 00111 (RP-I)

Signals for processing the binary and quinary digit parts

Description of the signals

Fig. 18: PAMl, PAMl, PAM3, ΥΑΜΆ PMl, PM 2, PM 3, ΤΉΆ, PM 5

Fig. 19: PAS1, PAS2, VXSZ, PA ~ S3 PA 1, PA 2, TÄJ, ΤΆΆ, PA 5

Figure 21: PDB

P / 3, P / 4, P / 6

Figure 23: FAO

Figure 24: PCQ F2.3

Figure 26: TC

Minuend (auger) input signals to the adder
Minuend (Augend) input signals to the parity and parity control circuitry

Subtrahend (addend) input signals to the adder
Subtrahend (addend) input signals to the parity and parity control circuitry

Indicates that the binary parts of the eye end and add end are the same

Indicates that an operand is 2, that an operand is 3, that at least one operand is less than 5

Response signal of the adder; indicates that the quinary part of the result is equal to 0. The result is therefore the number 0 or 5

Indicates that the addition of the end and end (quinary part) resulted in a quinary carry
Convert signals P / 3 and PJ 4 to a signal indicating that one operand is 2 and the other operand is 3

Indicates that there is no carry from the most significant bit position

As FIG. 19 shows, a signal “1” is present on lines 14B-30, 14B-31 and 14B-34 in accordance with the above addition example. With the simultaneous coupling of the shift signal to the AND circuits 19-12, 19-13 and 19-20 via the line 19-11, these AND circuits are therefore opened. The outputs of the AND circuits 19-12, 19-13 and 19-20 are assigned to them OR circuits 19-14, 19-15 and 19-23 fed, in turn, generate the output signals PASL, PAS2 and PA. 5 The signal PA5 will be described in connection with FIG. Since no signals corresponding to a binary "1" are present on lines IAB-32 and 14B-33, no output signals are generated by the associated AND circuits 19-18 and 19-19; the associated OR circuits 19-21 and 19-22 therefore generate the signals PAS3 ~ and ΡΑϋΆ. After the generation of the signals required to handle the +3 and +2 decimals has been described, the description of the second operational phase in the adder now follows.

Fig. 21 shows a matrix consisting of AND circuits, the outputs of which are selectively coupled to a number of OR circuits. The columns of this matrix represent the output lines of the respective AND circuits, while the rows correspond to the input lines of these AND circuits. The black connection points correspond to the connection points of the respective AND circuits. In other words: the first column 21-19 contains two black connection points 21-17 and 21-18. These black connection points indicate that the AND circuit represented by column 21-19 is opened with simultaneous coupling of the signals PAM3 and PAM T and thus transmits an output signal to the OR circuits 21-20. In Fig. 21 the 16 lower lines correspond to the arithmetic unit. This arithmetic unit generates its own signals that indicate the numerical value of the respective operands. The top

105 106

The two lines marked CPE and CPE represent the two operands or both represent the circuit that is designated in this description with a “0” or “5” or their complement corresponding complement circuit. To be observed. Similarly, the AND circuit associated with a particular delay device 21-26 generated by the pulse signal PJ 2 OR circuit indicates that one of the two operands or both of the two operands is a no-complement signal (CPE) that correspond to either a “1” or “6” or their complementary nine's of the input signals of a ment. The signal PJ 3 indicates that other associated AND circuits represent that a complement signal (CPE) is applied to one of the two operands or both of them. As neither a »2« or »7« or their complement has already been mentioned, will correspond to the subtrahend or the io. The signal PJ 4 indicates that one of the contents of the register RP-2 normally forms the grain - both operands or both of either one element. This process will now correspond to "3" or "8" or their complement, as shown by columns 21-21 and 21-22, and the signal PJS finally indicates that one of the AND circuits has been described. The AND of the two operands or both of either circuit 21-21 is in operation if a no-complement signal (CPE) is present at their inputs 15 of a "4" or "9" or their complement escaped, speak.

d. H. if the formation of a complement is not required, the inputs of the

is borrowed. As described in the coincidence OR circuit 21-30 (FIG. 21) shown in FIG. As matrix shows lie at the inputs of the AND Ängen seen from the drawing, is located on the signals TÄST and PAS3 to the switching 21-21. This AND circuit can therefore start from the numbers 0 AND circuits, the input signals of which the Ge and 5 are opened, since the L code can be seen from the above-described signals from the minuend and subtrahend is that only the digits. For example, from Fig. 21 it can be seen that the len 0 and 5 in the first digit position (FAST) are input signals that are represented by a binary as on the line 21-31 as in the third digit position (PAS J). Circuits are present that have signals zero. The AND circuit 21-22 is in Be / MM 3 "and PAM1 as well as the signals TÄSTi and drove when the AND circuit 21-21 represent information PAST . These signals would mean, is supplied in complementary form. To the that The inputs of the AND circuit 21-22 are thus a consideration of the other signals PAS1 and PAS 3 connected to the inputs again be seen that the figures showing these circuits, that at each of these aND have Schalqumären value speak the numbers 4 and 9 corresponds obligations counter signals from the registers RP-I and. As already mentioned, the sub-RP abut -2. One of the oR circuit 21-30 trahenden or the content of register RP-2 normally generated output signal formed below with Simalerweise the complement, if 35 gnal PDQ is referred to, therefore, indicates that the is necessary . The lines on which the signal e quinary values of the operands are equal. The Si CPE and CPE occur, therefore, represent the input signal PDQ, that of the with the output of the OR signals from the subtrahend 21-32 is generated, in this description the complement of the relevant digits to 10 means that the digits of the operands are formed the same. As with a number of other quinaries.

In systems, however, the grain is initially used. Now the inputs to the OR

plement to 9 formed and then a carry circuit 21-37 (Fig. 21) is described. From the intended for the least significant digit. The drawing can be seen that the line in F i g. The arithmetic unit shown in FIG. 21 works with the nine's complement coupled to the OR circuit 21-37. The number 0, through which the input signal does not open an output signal of an AND-AND circuit 21-21, is therefore a circuit, since on this line 21-40 only the complement is the number 9, which in turn represents the AND a black connection point is. Circuit 21-22 opens. Similarly, that of the drawing can also be seen that the input signal coupled to the number 5, through which the AND circuit 21-21 is opened 50 line 21-40, is the number 4 as a complement, which in turn is signal ΡΑΜΆ . Another consideration of the one in turn the AND gate 21-22 opens. A comparison input signals to OR circuit 21-37 indicates that equal to that in FIG. 21 depicted AND circuits at a complementation PAS4 the signals and with the L-code shows that an OR arrangement and CPE applied, while conversely, the AND circuits assigned to the signals device are coupled when coupling 55 PAS% and CPE if no development of a no-complement signal CPE or a complement needs to be formed. With an-complement signal CPE mutually complement their words: The OR circuit 21-37 thus shows to form 9. the value of the binary digit of the operands

The first five OR circuits 21-20, 21-23, has. The output signal of the OR circuit 21-13, 21-14 and 21-24 are each connected to a number of AND circuits, the output of which is fed to the signal PJ 6 to create. Since the output signals fed to these OR circuits are real or the non-complementary signals that are. The individual outputs of the AND an output signal of the OR circuit wirings 21-37 show the possible numerical value of the function, those signals are welc he in the BiOperanden. In other words: If the output digit corresponds to a "0" (PAM ~ 4 and PASf), the signal of the OR circuit 21-20 is the pulse - that means the delay device 21-25 supplied by the pulse delay device, which the Si 21 -33 generated signal PJ 6 that at least one generates signal PJ1 . This signal indicates that one of the operands is less than 5.

107 108

A consideration of the inputs to the ORing device 21-28 supplied to the signal PJ 4

Circuit 21-38 shows that this circuit can generate the. The output signal of the OR switch

Signal ΡΛΜ 4 and in the case of a complement formation device 28-11 of the delay device 21-33

the signal ΤΆ ~ $ Ά are present, while conversely that is supplied to generate a signal PJ 6, and that

Signal PAS ~ i is turned on when no complement 5 output signal of the OR circuit 22-13 is the

is required. The OR circuit 21-38 generates pulse delay means 21-35 supplied to

thus an output signal if at least one of the generate the signal PDB.

Operand contains a "1" in its binary position. As mentioned above, the signals are

The encrypted by the pulse delay device 21-34 PJ , so that with the help of a single

The generated signal PJ 7 thus indicates that at least 10 signals have two different information values.

one of the operands is 5 or greater. can be carried. The signal P / 3 shows e.g. B. at,

The inputs are now that one of the two operands, or both, the OR circuit 21-39 described below. From the character quinary value 2 can have, which in the present statement can be seen that the input signals the case that one of the two operands or AND circuits, whose outputs with the OR 15 also both either the number 2 or the number 7 circuit 21-39 are connected, which represent counter signals, as can be seen from the L code. This is what the registers RP-I and RP-2 represent. So are signal PJ 4, however, indicates that one of the two z. The Quinärwert 3 ent provided as at the inputs of te from the Spal 21-4 1 DAR operand or both AND circuit speak the signals 4 and PAM. As can be seen from the L code, PAS 4 is on. The output signal of the OR circuit 20 speaks this binary value of the number 3 or the number 8. 21-39 thus indicates that the binary parts of the operand The signal P / 6 indicates that one of the two operands are the same. Accordingly, the randen or both is less than 5, since the signal from the pulse delay means 21-35 ER- PJ 6 is only generated when one of the two sired signal to PDB that the OPE Binärteile the operands, or both, in his Binary digit a "0" are equal. »5 has. The PDB signal indicates that the operand

As already in connection with those in Fig. 18 and have the same binary values. Since the signal P / 6

19 illustrated circuit arrangements indicated that at least one of the two operands

was, the signals P75, TJl and PDB of the is less than 5, so both operands must

Inverse members are generated which are smaller than 5 with the respective offsets.

went to their assigned pulse delay 30 As F i g. 21 shows give the output signals in devices connected . These inverters, to a certain extent, provide information about the numerical value of the are already known in the art. Under consideration operands. In order to obtain the final result of an arithmetic operation carried out by viewing the addition example (+2) + (+3) he adder , it turns out that the generation of all signals can thus be maintained, these output signals, however, have to be described on the left-hand side the 35 to be further evaluated. For this purpose, Fig. 21 will have been listed. the signals P / of the decryption matrix (Fig. 24)

From Fig. 18 and 19 as well as from Table 1 results. The individual columns of these resolutions

that the following input signals on the arithmetic logic unit matrix correspond to an AND switch

(Fig. 21) are present: PASl, PAS 2 TAS ¹ S, ΤΆΊϋΆ, while the individual rows of the matrix

PAMl, PAMI, PAM3 and PAM4 ~. Since the two 40 are one input line of these AND circuits

In this example, operands have the same prefixes. Make the black connection points

have characters, can thus be found on the basis of FIG. 27 represents the connection points of the AND circuit.

quickly determine that the inverting member 27-20 of the AND circuit shown in Fig. 24

and signals generated by the flip-flop circuit 27-10.

CPE or CPL are switched on. 45 draws. The F signals give in connection with the

There are now the input lines of the number combination of the Ope- F i g. OR circuits 21-20 shown in FIG. 21 are bordered, although these themselves are not indicated. 21-23, 21-13, 21-14, 21-24, 21-30, 21-37, 21-38 and So shows e.g. B. the F signal F 0,0 that each described 21-39. Has a binary value of 0 from the operand listed in Table 1. For better signals, it can be seen that the OR circuit 50, in this context, reference is made to the inputs 21-13, an output signal in accordance with the output signals of the two input signals of the connection points of the AND circuit represented by column 24-15 . Like F i g. 24 shows, created 21-11 and 21-12 . The OR circuit 21-14 speaking to the AND circuit 24-15 generates an output signal in accordance with the signals of the signals P / 1 and PDQ. As already the input signals at the connection points 55 in connection with FIG. 21 shows 21-15 and 21-16. The OR circuit 22-11 generates the signal P / 1 that one of the two operands has an output signal in accordance with the input or both of a "0" or "5" or their output signals at the connection point 22-16, and the Complement corresponds. The signal PDQ indicates that OR circuit 22-13 generates an output signal against, as is well known, that the operands have the same in correspondence with the input signals at the 60 quadratic values. Since the quinary values of the numerical connection points 22-17, 22-18 and 22-19. The len 0 and 5 are equal to "0" and since the signal PDQ indicates other OR circuits 21-20, 21-23, 21-24 , that the quinaries of the operands equal to 21-30 and 22-12 produce no output signals. both operands must have a binary value

From FIG. 21 it can also be seen that the have which corresponds to a "0". The signal F0,0 shows

output signal of the OR circuit 21-13 of an IM 65 indicates that the quadratic values of the two operands

pulse delay device 21-27 is supplied, are equal to "0". A consideration of the input signals

which generates a signal P / 3. The output signal of the AND switch shown in FIG.

OR circuit 21-14 , the pulse delays show that the F signals are always on.

show that the quinary value of the operands corresponds to the numbers standing next to F-signals in each case the total binary value of two Opeden F-signals. With randen. The other words generated on the basis of these F signals: The signal F 1,4 indicates that the th output signals FA always indicate the qui-quinary values of the operands of a "1" and a "4" närwert, the by which correspond to the signal in question; the signal F2,3 indicates that the number assigned to the Qui- 5 FA is marked. So the närwert of one operand results in a "2" and the z. B. the binary value of the other operand of a "3" supplied to the OR circuit 23 / 4-13. Signals F0,1, F3,3 and F2,4 speak an output signal, etc. FA 1, which indicates that the result a quinary how from FIG. 24 can be seen further, the value 1 has. Similarly, the output signal FA 2 signals F supplied to two OR circuits 24-14 and 24-16 io that the result has a quadratic value 2. These two OR circuits are used. The output signal FA 3 indicates that the result for evaluating the signals F in order to determine whether a quinary value is 3, and the output signal FA4 should be a quinary carry or not. We indicate that the result has a quinary value of 4. Before the transfer of the F / 4 signals to the control unit was determined, a quinary result circuit must be described in FIG Signal FA will be discussed that in ßer. This example is generated at the inputs of the OR circuit. With this case-24-14 there are therefore F-signals whose quinary play are the signals P / 3, PJ 4, PJ 6 and PDB equal to 5 or greater. From this it follows that one has been begotten. Like F i g. 24 shows, is generated on the basis of the OR gate 24-14 signal 20 of the arrival at the connecting points 24-11 and 24-12 PCQ indicating that a quinärer transfer take place lying signals PJ 3 or P / 4, the signal F 2.3 must, since the quinary values of the two operands generate 5. This signal indicates that the one is Ope- or greater. Conversely the OR are rand a Quinärwert 2 and the other operand circuit 24-1 6 eführten train signals is smaller than 5, has such a Quinärwert. 3 As is known, the SID showed that the signal TCQ is generated, which thus indicates that 25 signals P / already have the same information value, but that no quinary carry has to be carried out. just a little less accurate. For example, this shows

The F signals are the in Fi g. 23A illustrated signal P / 3 indicates that one of the two operands or

th OR circuits 23 / 4-12 to 23 / 4-16 trains - both can also have a quinary value of 2. By

leads to generate the signals FA. These signals combine two signals P / or through com-

show the quadratic value of the result or the combination of a signal P / with a signal PDQ.

total binary value of the two operands. In Fig. There is a single signal F - in the present

23 A is the output signal of the OR circuit

23 / 4-12 marked with FAO . The drawing shows the two operands, although these themselves

it can be seen that the OR-scarf is not displayed at the inputs.

tion23 ^ 4-12 the signals F0,0, F 1,4 and F2,3 are applied. From Fig. 24 it can be seen that the signal F2,3 is present. As is known, the F signals indicate which quadratic value the operands have together via the line 24-13 to the OR circuit 24-14. In order to generate an output signal there, in other words: The signal F 0,0 indicates that the gen. The output signal of this OR circuit is the quadratic values of the operands equal to "0". Referring to Figures 24-14, there is signal PCQ, which indicates that in the previous drawing it can be seen that the total binary 40, for example, is required to be a quad. the operand, which is represented by in each case one of the F signals 23 / 4-11 coupled to the OR circuit 23 / 4-12 via the line OR circuit 23 / 4-12 is equal to "0". In other words: to generate the FAO signal there. This signal FAO The signal F0,0 coupled to the line 23 / 4-17 indicates that the total sum of the quinaries of the indicates that the numerical value of the two operands (+3 and +2) clears the binary value 0 equals "0". That speaks on the FAO line. A comparison with the L code shows that the output signal indicates that the number 6, which in the present case represents the correct total binary value of the two operands or the result of the operand addition, equals the quinary-quinary value of the result » 0 «is. Also has value 0 or 000. The input 50 coupled to the line 23.4-18 indicates the quadratic value of the result by the signal FA , but the output signal F 1.4 indicates that the one operand does not provide this information, since without the quadratic value 1 and the other operand has a quinary binary value of the result that cannot be determined value 4, which together result in the quinary value 5, can determine whether the result is 5 or more or less than - as already mentioned - 5. In other words: This corresponds to O in the present case-quinary value. The session 23 / 4-12 generated by the OR circuit 23 / 4-12 on the basis of the input signal FL, 4 signal FA O indicates that the output signal generated by the quadratic value of the result therefore correctly indicates that tes is 0 and that the result is therefore the number 5 or the result has a quinary value 0. Likewise corresponds to the number 0. As already described in connection with the input table 1 coupled to line 23 / 4-11, a signal output signal F 2,3 indicates that one of the operands has been generated a 60 PCQ, whereby the fourth or fourth in quinary value 2 and the other operand has a quinary - the binary digit of the result has a value of 3 stored in it. Also these two quinary values will result. The result therefore corresponds to the number 5 and together the value 5, which corresponds to the quinary value 0 and not the number 0.

speaks. In this case, too, the priorities in the case of the present addition

OR circuit 23 / 4-12 the correct output 65 example arithmetic opera-

signaiF / 4O generated. functions are described in connection with Fig. 25

In a similar way, they represent the others, but let's start with some other circuit

OR circuits 23 / 4-13 to 23 / 4-16 supplied arrangements are discussed. Although these will

111 112

further circuit arrangements for the present connection with Fig. 18 and 19 was described, ent addition example not required, but they generate the signals ¥ Ä speak the input signals of the input signals for the re-subtrahends shown in Fig. 25, which are delayed by a pulse time and sultats circuit arrangement. Were reversed for the sake of convenience. The signals PM correspond to this result circuit arrangement compared to the input signals of the minuende, which therefore it seems expedient to discuss the generation of these likewise delayed by a pulse time and additional signals already now. To have been returns. The AND circuit 23-11 is used for this purpose, first of all, as shown in FIG. 23 when a circuit arrangement with two digits is described at its inputs. gen whose first and second bit positions are the same and

In the present computing system, circuits io each contain a “0”. From Fig. 23 is also

provided to the two operands with each other can be seen that the AND circuits 23-12 to

to be able to compare. So z. B. be opened in place of 23-14 when at their entrances

Adding the +3 and +2 operands to an instruction two digits are present in their first and second

be provided, after which it should be determined that bit positions are the same. The output signals of the

whether the operand +3 is equal to the operand +2. 15 AND circuits 23-11 to 23-14 are the

Before the matrix shown in Fig. 23 is sampled OR circuit 23-15 is applied to an output

first, some information about the signal to be generated, which indicates that the relevant

How the computing system works in the event that both digits are used in their first and second

two operands and one subsequent bit position are the same.

Jump instruction. In the present computing system, the matrix represented by the signals in FIG. 23 is opened to compare two FÄ3, FM 3 and PDB . The AND circuit 23-16 is opened. These AND-scarf information words are provided. In this case, however, the device is opened when the third bit positions are only compared one digit at a time. The terms of these two digits are the same, that is, an equal operation in each case is contained in an instruction 18 or 19 "0", and if also caused by one that will be described later. The 25's complement operation indicates that the four-comparison operation is essentially one sub-th bit positions are equal. As a comparison by fraction. Is a number from another subtract a subtraction is made, resulting sohiert by first the complement to subtract with a US Fi g. 21 (OR circuit 21-39) that a henden is formed and is then generated for the minuenden signal PDB when the fourth bit positions are added, so the relationship of FIG. 30 can actually be the same. In other words: The absolute values of the two numbers in relation to one another are the same as those in FIG. 23 matrix of coupled system voices by determining whether the difference is a signal YÄ and PM represent approximate information carry-over of the last digit. Is z. B. represent the signals that are not subtracted number 7 from the number 3 by the complement process, so that results have been changed, while the complement of the number 7, the number 3; the subsequent output signal of the OR circuit 21-39 (Fig. 21) send addition 3 + 3 results in 6 and does not require any change due to the formation of the complement. Transfer. In general, it can be determined that, if a complement signal CPL is present, despite the fact that the subtrahend is greater than the minuend, the fact that the signals PAM 4 and PAS 4 are the same - as in the example just described - from the AND- Circuits no signals no carry is required. Conversely, in 40 to the OR circuit 21-39, in the event of a transfer failure, the minuend greater than the same is transferred. The PDB signal therefore becomes subtrahend or equal to this. A comparison is generated . The same applies to the two same signals z. B. carried out when information words with ΡΑΜΆ and PASl. The OR circuits are to be compared to a reference value (e.g. 23-15 and 23-18 are output signals that produce an address with the addresses of a particular 45 if the compared digits are actually group) to determine whether the information words are the same are. The output signals of the OR switch agree with this reference value. In addition, lines 23-15 and 23-18 are fed to the AND circuit 23-19 lying between two limit values in order to open this circuit and information words are compared in order to permanently generate a signal PEQB . This output signal determines whether a word is greater than the lower limit value of the AND circuit 23-19 and d in the inverse element (e.g. during a sorting process). From 23-20, reversed in order to praise the signal PEQB, it follows that len, if the compared digits are not the same. In this way the two signals information obtained by a subtraction PEQB and "PEQE are mutually exclusive.
Fig. 23A shows a flip-flop 23Λ-21, which results in the end carry, and on the other hand a signal PEQ is generated at the same time when it is checked as a result of a clock whether the words are the same. Otherwise, the ptO signal has been switched to its setting state and is pressed: If the words are not the same and the result is. The signal PEQ is applied as long as there is an end carry, so it can rightly be concluded from this that the information words are compared with one another that the minuend is greater than 60 den, provided that a comparison of two of the subtrahends. The description now follows that numeral n does not generate the signal PEQB. The signal PEQB of the equality circuit arrangement in FIG. 23. The signal PEQB is generated when two digits compared with one another The rows of the matrix shown in this figure are not equal. By means of this speaking AND circuits, the inputs of which are gnal, the flip-flop circuit 23 ^ 4-21 is represented by the columns of the matrix. So 65 and generates the signal PEQ.

For example, line 23-11 corresponds to an AND switch as long as the PEQ signal of the flip-flop

device, at the four inputs of which the signals PZT, 23A-21 are present, this means that during the

PI, TAT, and FM2 are present. As in the comparison of the two information words, no unequal

I 190 704

113 114

small digits were discovered. From the fact that i- is, and because the input signal PCQ indicates that the description it follows that a carry carried out with the aid of the total binary value of the operands requires a matrix shown in FIG. 23. The result, which can be combined by the equality check with a further check of the signals fed to the AND circuit 26-14, in order to determine whether a 5 is set, must be 10 or greater. In addition, there is a carry and the minuend is thus greater, the AND as the subtrahend is also due to the output signal. The equality check as well as the circuit 26-15 causes a carry, since the check as to whether the minuend is greater, the first output signal PJl of this AND circuit indicates that the line for triggering a jump command by at least one of the operands is greater than 5, leads. Should z. If, for example, a limit value is determined in an arithmetic operation at the same time, but a second input signal is also determined, then when this PDB is found it must indicate that the operands are the same and the limit value is often in the normal sequence, the result must therefore be 10 or greater.
broken and a jump made. The AND circuit 26-16 generates an output signal (initial carry), which indicates that the least significant digit position of the signal PEQ in the result circuit arrangement is increased by one (FIG. 25) ) used. The role that this is supposed to play so that the signal PEQ in the circuit arrangement (FIG. 25) complement to 10 can be formed during a complement operation. The output signal of this AND circuit 26-16, as well as when a jump is carried out (Fig. 28), is played, will be generated in detail below by writing this to one of its inputs. 20 signal CPE indicates that a complement

Before describing the circuit arrangement in must be formed and that on its other one-Fig. 25, a further clock signal pi0 present in the circuit arrangement, the clock pulse for voltage in FIG. 26, is described. Which in Fig. 26 represents the initial carry,
presented circuit arrangement produces at least two As F i g. 26 furthermore shows, the pulse-width control signals which, for better understanding 25, delay device 26-18 are a complement of the result circuit signal RCP shown in FIG. 25 is formed. The input of this impulse arrangement will already be discussed here. How delay device is with the output of the AND-F i g. 26 shows, the carry signal PC is connected by the circuit 26-10. The pulse delay device 26-11 is generated at the inputs. A ser AND circuit 26-10 is the clock signal transfer signal PC is generated in order to advance the numeric 30 pt 12, the complement signal CPL, the blocking radio value of a digit by one. tion table signal Fr 508 and the blocking signal FC, the input signal for the pulse delay device, the generation of which has just been discussed. From device 26-11 comes from the OR circuit 26-12, the drawing shows that the complement has four inputs. ment AND circuit 26-10 through the function

The first input of the OR circuit 26-12 is 35 table signal Fr508 and the carry with the output of the AND circuit 26-13 yerbun signal PC is blocked. As already with the description, at whose inputs the signals PALPH, FA 4, exercise of the sign was mentioned, a PC and PJ 1 need to be present. The output signal of the renewed formation of the complement not carried out to AND circuit 26-13 primarily indicates that, if the complement of one of the operands must be formed by the input signal FA 4 and the total value of the result of the number 9 must correspond. The result represented by the operand signal, a carry from the most significant FA 4, required a quinary digit. If the signal PC is valued at 4, so that it is generated by the arithmetic processing, the AND circuit 26-10 of the input signal generated by the two operands is blocked. As will be described in detail in connection with the instructions for the AND circuit 26-13 either the result 9 45 tion commands or must correspond to 4. Since, in order to open the AND, a function table signal FT 508, in addition to an on circuit 26-13, also generates other control signals at the same time. Since this must be possible under certain circumstances, this indicates that at least a second, repeated complement formation erroneously of one of the operands is greater than 5. The signal can be initiated if the radio function FA, which indicates the result, can therefore only be provided by the table signal FT 508, which represents the number 9. Since, in addition, RCP is prevented from being generated in advance of a second signal. The outgoing operation (input signal PC) of an over-computing system assumes that if a carry signal is present, the formation of the complement formation of the output signal also results in the formation of a new carry signal in the AND circuit 26-13. In order to generate the AND circuit 26-10 for the (PC) , since the F / 4 result, which was caused by the generation of the RCP signal, the number 9 was generated at the present operation, by which the an input of this AND circuit, the signal transfer signal PC coupled from a previous operation of CPL. The occurrence of a 9 converted into 10 and thus a carry carry signal PC necessitates the generation of the signal for the next digit position. The signal RCP is interrupted in the manner just described, which is also interrupted to the AND circuits 26-14 60.

and 26-15 is switched on, indicates that a »di-

rectified feed ”does not take place and the generation processes which the input signals for

of the transmission signal PC are carried out the result circuit arrangement (Figs. 25 and 22)

can. produce. As Figs. 25 and 22 show, there are five

In a similar manner, the OFF 65 also turns OR circuits 25-10, 25-11, 25-19, 25-25 and

output signal of the AND circuit 26-14 a carry 22-19 is provided. The outputs of this OR

signal is generated because the signal PJ1 in turn indicates that circuits are assigned to AND circuits 10-53

that at least one of the operands 5 or greater (Fig. 10) via the pulse delay devices

115 116

25-46, 25-47, 25-48, 25-49 and 22-20 supplied to represent digit 6. A comparison with the L code

to be fed back to the register RP-I. shows that the digit 1 or 6 is a binary "1" in the

The first OR circuit 25-10 generates an out first bit position requires. Due to the output output signal, which is denoted by Al. The signal signal of the AND circuit 25-15 is thus provides, in Al the first (least significant) bit position 5, this first location, a binary "1" used. In a similar figure, which was generated on the basis of an arithmetic and operational way at the AND circuit 25-16 tion. The drawing shows the signal FA 2 on in addition to the signal TÄLPH. lent that the OR circuit 25-10 has six inputs. As is well known, the signal FA 2 indicates that the R has been activated. The first input to the OR circuit resulting from an arithmetic operation has a quadratic value 2, 25-10 is connected to the output of the AND circuit io so that the result is either connected to the number 2 or the 25-12 , at the two inputs of which the number? represents. A comparison with the L code signals PASP and PA 1 are present. As is well known, shows that the PASP signal in the first bit position of the digit 2 or 7 indicates that the twelfth digit must contain a binary "1". This binary "1" becomes the position of the subtrahend and therefore the information is to be fed in directly through the output signal of the AND circuit. The signal PAl indicates that 15 is inserted 25-16 in the first bit position.
The AND circuit 25-17 contains a small register of the subtrahend a binary "1" is located in the twelfth bit position of the first shift. Innovation. As can be seen from the drawing, if the one in the twelfth digit position is at one input to this AND sound information corresponding to the PASP signal, the FA 3 signal, which indicates that this is to be fed in directly, is this AND result of the arithmetic operation opens the quadratic value of circuit 25-12 and has its output signal of "3". The result corresponds to either OR circuit 25-10 which is then fed with one of the number 3 or the number 8. A comparison with the binary "1" in the first bit position of the result shows an L code that is in the first bit position who adds. The second input of the OR circuit 25-10 digits 3 and 8 must be a binary "1". This is connected to the output of the AND circuit 25-13. 25 is linked by the output signal of the AND circuit, at the inputs of which the signals PAMP and 25-17 are reached. From Fig. 25 it can be seen that PAfI are present. As already mentioned before, the AND circuit 25-17 also a carry indicates the signal PAMP that the twelfth signal can be present. If this carry signal is located in the digit position of the minute end, the AND circuit 25-17 is blocked. Since tion is to be inserted directly into the result. If 30 contains the signal FA 3 indicates that the result corresponds to either the first bit position of the twelfth digit position of the digit 3 or the digit 8, so if the end of the minute would be a binary "1", the AND- the two digits are carried over into 4 or 9 circuit 25-13 opened and its output signal converted. A comparison with the is fed to the OR circuit 25-10 , but the L code shows that both the digit 4 and a binary "1" in the first bit position of 35 and the digit 9 are not a binary "1". included in the first bit result inserts position. Due to the AND switch

The AND circuits 25-14 to 25-17 generate the transfer signal applied to the device 25-17, these output signals are therefore blocked at the other four circuit inputs, so that no binary "1" is coupled to the OR circuit 25-10. can be used in the first bit position.
From the drawing it can be seen that on 40 each of the following, the OR circuit will now be described at an input of the other n four U ND circuits 25-11 . The output signal A 2 of these 25-14 to 25-17 is the signal PALPH . As loading OR circuit corresponding to the other point it was mentioned in the second Bitreits, displays the position of the individual digits result signal PALFH contained to that the information of the twelfth binary value. It can be seen from the drawing that the digit position should not be added directly to the result in the output circuit of the OR circuit. The result circuit can therefore 25-11 an inverting element 25-18, which take this information from another source. Output signals of the OR circuit 25-11 to the AND circuit 25-14 are next to the reverses. The OR circuit 25-11 has eight EinSignal P ~ ÄL ~ FH nor the transfer signal PC and gears that go with the AND circuits 25-20 to the signal FA 0. As the L code shows, 50 means 25-24 and 25-31 to 25-33 are connected. The coupling of the signal FAO to the AND switching AND circuits 25-20 and 25-21 are designed 25-14 so that the calculation result forms the quadratic value that the information signals from the second has the "0"; the result thus either contains the bit position of the twelfth digit position of the word digit 0 or 5. However, it can be fed in directly to the one obtained. Add a carry to the AND switch number, so that the number 0 or 5 that was generated before, 25-20 and 25-21 are slightly different, the number 1 or 6. A difference from the AND circuits described above the same with the L code shows that when converting 25-12 and 25-13, since the first-mentioned AND- the digit 0 to 1 and when converting the digit 5 circuits, the reverse signals of the AND- to 6 a binary » 1 «must be set in the first bit position. Signals connected to circuits 25-12 and 25-13 must be set. So must be 0 60 for the result number. So must z. If , for example, a carry is added to open the gate circuit or 5, the TMl signal will be switched on 25-20, while due to the AND circuit 25-14 a binary rend, the AND circuit 25-21 is opened when "1" inserted in the first bit position. the signal TJl is present. These are reverse signals

At the UN D circuit 25-15 is next to the required, since that of the OR circuit 25-11

Signal PALPH still the signal FA 1 on. As is known, 65 output signal generated by the inverter

the signal FA 1 indicates that the result of a is reversed. These in the output circuit of the OR

Arithmetic operation has the quinary value of "1", so circuit 25-11 the inversion is necessary.

that the result is either the digit 1 or the dig to convert the memory code into the L code.

your. However, this reversal is for the Veran circuit 25-24 is in addition to the signal PALPH demonstration of the mode of operation of the adding-Ver nor the signal FA 4, which indicates that the equivalent is irrelevant. If the result of the arithmetic operation signal is generated, the binary value of the PAMP is generated, indicating that the twelfth has a "4" and therefore either the digit 4 or the digit of the end of the minute represents the digit 9 directly in the result. As the L code shows, it should be contained, and in the second, both digits, there is a bi-bit position (PM 2) of the twelfth digit in the second bit position, actually a "1". If the signal FA 4 alone were able to produce a binary “1”, the AND circuit 25-24 would open despite the incomplete opening, and an AND circuit 25-20 would generate a binary “1” output signal “1” «In contrast to the L code to be inserted in the second bit position of the result, ₁₀ a binary» 0 «in the second bit position, since the output signal of the OR circuit 25-11 The signal FA 4 can therefore be the AND circuit of a binary "0" corresponds, which not only open in the inverter 25-24, but requires 25-18 to be converted to a binary "1" and also the carry signal PC. If the digits 4 are inserted into the second bit position of the result and 9 are carried over, the result is the digits 4. The rest of the operation of the AND circuits i ₅ and 10, the second bit positions of which do not contain any binary "1" gen 25-20 and 25-21, essentially corresponds to that contained. If the result of the arithmetic operation of the AND circuits 25-12 and 25-13 operation corresponds to the signal FA 4 and there is a carry and therefore no longer needs to be described in more detail for signal PC , the AND circuit 25-24 will become opens and generates a binary "1"

As Fig. 25 shows, there is a _{speaking output signal at each input 20} , which is transmitted via the OR

of AND circuits 25-22 to 25-24, the signal circuit 25-11 fed to the inverter 25-18

PALPH on. As mentioned earlier, it shows where the signal becomes a binary "0" for the

the signal PALPH indicates that the result is converted at the time of its second bit position.

Generation no direct feed-in should take place. The three remaining AND circuits 25-31 to The result circuit can therefore use its information to generate the result. To the

get tion from another source. For the following seven inputs of the AND circuit 25-31 lie

quietly e Besch friction, it is assumed that the following signals Si to: the carry signal PC

gnal PALPH is angschaltet. At the AND circuit signal PR AS, the clock signal ptl2, the signal CPL,

25-22 there is also the FAQ signal. the signal PANS, the signal PBNS and the radio-this signal causes the table signal FT 504 in the second bit position 30. All of these signals are

a binary "0" is inserted. As previously described elsewhere. Around

has been set, the signal FA 0 indicates that the meaning of the output signal of the AND switch

The quinary value of the result is equal to "0" and that the direction 25-31 can be recognized, it is assumed that the

second bit position of the result in agreement signal pt 12 represents the clock signal and that the mung with the L code does not contain a binary "1". 35 Function table signal FT 504 indicates that the

So if the signal FA 0 is generated and is equal to the AND circuit when an addition is carried out

If the PALPH signal arrives early, the AND switch or subtraction can be opened. In this

device 25-22 is open and its output signal the relationship must be taken into account that the

OR circuit 25-11 supplied, which then an arithmetic unit during the operation of the AND switch

generates a signal corresponding to a binary "1" that deals with the sign. To be there-

from the inverter 25-18 to a binary "0" bypass signal PRAS therefore indicates that the minuend

converts and has a positive sign in the second bit position of the result and that - like the

is used. Signals PANS and PBNS indicate - both the

At the AND circuit 25-23, in addition to the minuend and the subtrahend, a sign signal PALPH is also applied to the signal FA 1, 45 contained. The activation of the signal CPL means that the result of the arithmetic operation tet, that a complement is being carried out, has the binary value 1 and the second bit position also does not contain a binary "1" due to the occurrence of the carry. So if the signal FAX signals on the line 25-26, as is known, is generated and is due to the AND circuit 25-23 that the minuend is greater than the subtrahend. If no carry signal PC is on, the minuend of this 50 is positive and a complement AND circuit has generated an output signal that is used for formation and a final carry, then OR circuit 25-11 is fed, which must be followed by the plus sign (10000) of the minute end into which a signal corresponding to a binary "1" result is inserted. Since all testifies to the opening that the required condition is converted by the inverter 25-18 into a "0" of the AND circuit 25-31 and is fulfilled in the second bit position of the rain, a result is used by this circuit . When the final binary “1” is generated, the corresponding output signal is generated; the carry signal PC , on the other hand, blocks the AND switch to the inverter 25-18 via the OR circuit 25-23. A comparison with the L code device 25-11 is supplied. In this inverse term shows that the digits 1 and 6 will have a binary 1, the signal will have a binary "0" for the second bit. If a carryover is added to these digits, the result is converted. As is known, the digits 2 and 7 result, which will contain the negative sign through the digits a binary "1" in its second bit position 00010 and the positive sign through the digits. So the AND circuit 25-23 10000 is shown. In the following, the is now blocked by the carry signal, the OR transmission path of the output signal of the AND circuit 25-11 is fed to a binary "0" circuit 25-31 in conjunction with FIG. 18 in wrote.

converted to a binary "1" and then shown in Fig. 22 shows the insertion of the information in

the second bit position is used. The fifth bit position of the result at the AND. As from Fig. 22

ι iyu / U4

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120

As can be seen, the line 25-27 is connected directly to the OR circuit 22-19. That of the Signal "1" generated by AND circuit 25-31 is therefore transmitted from OR circuit 22-19 and inserted in the fifth bit position. This process is necessary so that the answer or the a plus sign can be provided for the result. The response circuits for the first, third and fourth bit position generate zeros unless otherwise prepared. For the transfer therefore only the circuits for the second and fifth bit positions need a sign to be prepared.

The description of the operations shown in FIG. 25 AND circuit 25-32 shown. This AND circuit is also used to generate a sign. It can be seen from the drawing that the AND circuit 25-32 contains seven inputs to which in part the same signals are applied as to the AND circuit 25-31. The AND circuit 25-32 is effectively success conditions: As the input signal indicative of PRAS, the Minue nd has a negative sign. The input signals PBNS and PANS mean that both the minuend (register RP-I) and the subtrahend (register RP-2) contain a sign. The function table signal FT504 indicates that either an add or a subtract instruction is being executed. The signal CPL in turn indicates that a complement is being formed. Finally, there is no carry signal PC to disable the AND circuit at time pt ₁₂ . If the minuend has a negative sign when forming a complement and if there is an end carry signal at the point in time pt ₁₂ , the result must adopt the sign of the minuend, in this case the negative sign. In this case, a binary "1" would be inserted in the second bit position of the response. Since the final carry signal would block the AND circuit 25-32, a signal "0" would be generated, which would be fed to the inverter 25-18 via the OR circuit 25-11, where it would be converted into a binary "1" provide the correct information unit for the second bit position. If the output signal of the AND circuit 25-32 is followed via the line 25-29 and the OR circuit 22-19 (FIG. 22), it can be seen that a signal "0" goes directly into the fifth bit position of the response is used, which corresponds to the representation of the negative sign.

The AND circuit 25-33 is also used to generate a sign. This AND circuit, which has six inputs, is effective under the following conditions: There are signs in the twelfth digit positions of the minuend and subtrahend, as indicated by the signals PANS and PBNS. The function table signal FT 504 indicates that an add or subtract instruction is being performed. The signal CPL indicates that a complement is being formed. If all these conditions are met and the PEQ signal is also present, which indicates that the digits compared with one another during a match check are the same, the AND circuit 25-33 is opened and generates an output signal "1" which is sent to the inverter 25-18 via the OR circuit 25-11 and converted there into a binary "0" for the second bit position of the response. If two digits compared with one another are the same, there is the possibility of a negative zero state, since, as is well known, a subtraction is carried out during the comparison operation. The AND circuit 25-33 prevents this negative zero state, since the signal PEQ indicates that the two digits are the same, and the output of the AND circuit 25-33 ensures that a

ίο plus sign (10000) is generated by inserting a "0" in the second bit position and a "1" in the fifth bit position. The binary "!" For the fifth bit position is fed to the OR circuit 22-19 via the line 25-30. It should be noted that the PEQ signal is normally generated for a comparison and subsequent jump. However, the signal is always generated when a possible negative zero state is to be prevented.

The signal 3 for the third digit position of the result is transmitted from the OR circuit 25-19. This OR circuit has five inputs to which the output signals of the five AND circuits 25-34 to 25-38 are present. It can be seen from the drawing that the AND circuits 25-34 and 25-35, similar to the AND circuits 25-12 and 25-13, have the task of feeding the information signals directly into the response circuit. In other words, the AND circuits 25-34 and 25-35 have the task of coupling the information of the twelfth digits of the minuend and subtrahend directly to the response circuit. Like F i g. 25 shows that the PAMP signal and the PM3 signal are present at the inputs of the AND circuit 25-34. The signal PAMP indicates that the information of the twelfth digit of the end of the minute is to be fed directly into the result circuit. If there is a binary "1" in the third digit position (PM3) of the twelfth digit, the AND circuit is opened by these two signals and generates an output signal that is transmitted via the OR circuit 25-19 and a binary "1 «For the third digit of the result. The AND circuit 25-35 operates in a similar way to the AND circuit 25-34 and is therefore no longer described here. At one input of the other three AND circuits 25-3 6, 25-37 and 25-38, the signal PALPH is applied , which indicates that these AND circuits must receive result information, since the information is fed directly into the Result switching cannot be carried out.

In addition to the PALPH signal, the FA 2 signal and the carry signal PC are also present at the AND circuit 25-36. The signal FA 2 shows that the result of the arithmetic operation contains the quadratic value of 2, ie that the result corresponds to either the number 2 or the number 7. The carry signal PC indicates that a carry must be carried out.

A comparison with the L code shows that there is no binary "1" in the third digits of the number 2 and the number 7. If, on the other hand, the digits 2 and 7 are increased by one when the carry signal is switched on, so that the digits 3 and 8 result, a comparison with the L code shows that these digits have a binary "1" in the third bit position exhibit. So the AND circuit 25-36 by the signal FA 2 and the carry signal

121 122

If the PC is open, it generates a carry signal at a binary "1", this means that the corresponding output signal, from which the digit 4 becomes 5 or the digit 9 becomes 0. The OR circuit 25-19 is transmitted and the signal PDjB indicates, however, that the quinaries of the signals for the binary "1" of the third bit position of the operands are equal. The signal FA 4

represents. 5 can therefore not be a "9", since the

At the AND circuit 25-37, in addition to the combinations that represent the number 9, unequal signal PALPH is also applied to the signal FA 3, which has binary parts. The result digit corresponds shows that the result of the operation the fourth therefore the number Corresponds to say the signal FA 4 Quinärwert of 3 has. A comparison with the L code of the number 4 and this number should be based on the indicates that this binary value represents the number 3 or 8 represents the circuit of the carry signal PC increased by one and that both digits are in their third bit position, so a "1" must have a "1" in the fourth bit position. The signal FA 3 must therefore be used. The AND circuit 25-42 is opened together with the signal PALPH at the AND and generates a circuit 25-37 corresponding to a binary "1", this is opened and the corresponding output signal generated by the OR an output circuit 25-25 corresponding to a binary “1” for the fourth bit position of the result signal which is provided by the OR circuit 25-19 transfer digit.

gen and the "1" for the third bit position of the AND circuit 25-43 contains five inputs.

Provides result number. The blocking signals FA 4 are present at these inputs

In addition to the and PCQ, the signal PALPH and the signals PJ 6, signal PALPH , the signal FA 4 and the over- «° and P / 7 are also present at the AND circuit 25-38. The signal PJ 6 indicates that at least carry signal PC . The signal FA 4 indicates that one of the operands is less than 5. The signal P / 7 result of the arithmetic operation, the quadratic value of 4, indicates that at least one of the operands has greater than one. From the L code it follows that in is 5. Both signals act as pass signals, a "1" must be inserted in the third bit position. If one of the operands is less than 5 and the carry signal PC is greater than 5 in this AND circuit 25, the result is greater than 5, and 25-38 is supplied as a blocking signal. From the L-Code its binary digit can either contain a "1", it can be seen that the quinary value of the "4" is either the or not. In the present case, however, number 4 or number 9 need to represent. If only the result digits up to and including 9 are carried over, then the digit 4 becomes 5 and the digit 9 is to be viewed (in the binary part of which a "1" is converted to 0. However, these digits are in 30), since a result between 10 and 14 does not have the third bit position no "1". The carry “1” in the binary part contains and no number combination signal PC is therefore used to block the AND circuit in which the one digit less than tang 25-38 is present. As a result of this blocking, one digit is greater than 5 and the other digit is greater than 5, and the output signal corresponding to binary "0" is generated and added together - results in 15 or more. This is different from that which is transmitted by the OR circuit 25-19 expressed 35: The AND circuit 25-43 generates a “1” for and the “0” for the third bit position of the result - the binary part of the result is a “1” if the digit represents . If, on the other hand, the carry signal sum of the operands is between 5 and 8. If this is not on, but the signal FA 4, the AND "1" is generated, regardless of whether a circuit 25-38 is opened and generates a signal "1", carry or not. The AND circuit 25-43 which is provided for the third bit position. 4 ° is blocked by the signal FA 4. Namely lies

In the following, the circuits are now loaded as a result, the number 9 and a carry must be carried out

languages that carry out the information signals for the fourth, this digit would have to be 9

Generate bit position of the result digit. That of the four- or 0's are converted, with the "1" in their

The information signal corresponding to the bit position would be omitted. So is one of the operand

is generated at the OR circuit 25-25, the 45 of which is less than 5 and the other is greater than 5 and

six inputs with the six AND circuits both result in between 5 and 8, so

25-40 to 25-45 are connected. As already in, the AND circuit 25-43 causes that in the binary

connection with similar AND circuits for which part of the result a »1« is inserted, namely

whose bit positions are described by the result digit regardless of whether a carry is carried out

the AND circuits 25-40 and 25-41 have 50 or not. The transmission of a "9" is in

the task, the connection with the AND circuit 25-45 in the twelfth digit positions

information contained in the minuend and subtrahend.

feed directly into the result circuit. The AND circuit 25-44 has three inputs. The AND circuits 25-40 and 25-41 work on which the signal PALPH, the signal PDB and, essentially like the AND circuits 25-12 and 55, the quinary carry signal PCQ issue. The Si-25-13 and are therefore not described in any more detail at this point as the PCQ indicates that a quinary carry has been previously described. At the other UN D circuits 25-42 is, while the signal PDB means that the Bibis 25-45 is in each case the signal PALPH , which parts of the operands are the same. If the binary display shows that the result circuit at the point in time parts of the operands are equal, the total of the generation of this signal does not result in any information. there could be a carryover. Are the

At the AND circuit 25-42, in addition to the quadratic parts of the operands, are greater than 5, so will

Signal PALPH nor the signal PDB, the carry through the resulting quinary carry one

signal PC and the signal FA 4. The AND "1" is inserted into the binary part of the result. the

Circuit 25-42 generates an output signal when 65 AND circuit 25-44 is opened when actual-

the result of the arithmetic operation the quinary value lent a quinary carry and the binary

which represents "4". This quinary value corresponds to parts of the operands that are equal. In this case it will

Neither the number 4 nor the number 9. If there is an output signal »1« from the AND circuit 25-44

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124

generated, which is transmitted by the OR circuit 25-25 and inserted into the fourth bit position of the result digit.

The AND circuit 25-45 has five inputs to which the blocking signals PCQ and PC, the signal PALPH and the pass signals PJ 6 and PJ 7 are present. The signal P / 6 indicates that at least one of the operands is less than 5; the signal PJ 7 means that at least one of the operands is greater than 5; The structure of the AND circuit 25-45 corresponds essentially to the AND circuit 25-43. Of the; The only difference is that the "1" required for the fourth bit position of the result is generated by the AND circuit 25-45 if the total is between 5 and 9 and no carry is required. This difference with respect to the AND circuit 25-43 is achieved by the locking signal PC being fed to the AND circuit 25-45 in place of the signal FA 4 fed to the AND circuit 25-43. if there is a carry, regardless of whether the result is 9 or less than 9, the AND circuit 25-45 is blocked. If, on the other hand, there is no carry and the sum of the operands is 9 or less than 9, the AND circuit 25-45 generates a signal “1” for the fourth bit position.

It should be noted that both the AND circuit 25-43 and the AND circuit 25-45 are blocked by the quinary carry signal PCQ. Both AND circuits normally generate the output signal A 4 under the influence of the signals PJ 6 and P / 7, which indicates that a digit is 5 or greater. On the other hand, one operand is greater than 5 (P / 7) and the other operand is less than 5 (P / 6) and if a quinary carry signal (PCQ) is generated, the result must not contain a "1" in the fourth bit position.

22 shows the circuit arrangement which generates the control bit signals or the signals for the fifth bit position of the result. The AND circuits 22-11 and 22-20 to 22-22 each have three inputs. It can be seen from the drawing that the signals PAS, PM 5 and the signal PC (no carry signal) are present at the inputs of the AND circuit 22-11. The output signal of the AND circuit 22-11 therefore indicates that two even digits are added together and produce an even result if there is a control bit "1" in the minuend (PM 5) and in the subtrahend (PAS) and no carry (PC ) is present. The fifth bit position of the result must therefore contain a "1" as the check bit. The output of AND circuit 22-11 is coupled to AND circuit 22-13 through OR circuit 22-12 . The AND circuit 22-13 has three inputs to which the complement signal CPL, the signal PALPH and the output signal of the OR circuit 22-12 are present. The AND circuit 22-14 has also three inputs against which the output de r AND circuit 22-12 as a blocking signal sign al PALPH and the non-complement signal CPL. If at the moment it is assumed that no complement is formed, the result is that the AND circuit 22-13 cannot be completely opened because the signal CPL is not switched on. The AND circuit 22-14 could not be fully opened when an output signal of the OR circuit 22-12 is present, since this output signal would block the AND circuit. If, under this condition, a signal "1" is generated by one of the AND circuits 22-11 and 22-20 to 22-22 and fed to the AND circuits 22-13 and 22-14 via the OR circuit 22-12 , a signal "0" would be generated by the OR circuit 22-17, which is converted to a "1" in the inverter 22-18 and fed to the OR circuit 22-19. In this way, a »1« ίο would be inserted in the fifth bit position of the result.

The AND circuit 22-20 generates an output signal if there is a check bit "1" in the fifth bit position of the subtrahend (PA 5) and a check bit "0" in the minuend (PM 5). In this process, the even number of the subtrahend is added to the odd number of the minuend, so that the result is an odd number. If there is a carry at this point in time, there must be an even

so result result. The AND circuit 22-20 therefore generates a "1" signal. If it is again assumed that its complement must be formed, the AND circuit 22-13 is not completely opened, since the signal CPL cannot be switched on at its input. The AND circuit 22-14 would also remain blocked, since the output signal of the OR circuit 22-12 blocks this AND circuit. The output signal “0” of the OR circuit 22-17 is therefore converted into a “1” in the inverter 22-18 and fed to the OR circuit 22-19. In this way, the correct check bit "1" is provided for the fifth bit position. The AND circuit 22-21 is opened when there is a control bit "0" in the subtrahend (P3T5) and a control bit "1" in the minuend (PM5) and the carry signal PC is also present. This signal combination means that an odd number of the subtrahend is added to an even number of the minuend, so that the result is an odd result. The input signal PC to the AND circuit 22-21 indicates that there is a carry, so that the result is now even and requires a "1" for the fifth bit position. Assuming that again no complement needs to be formed, the AND circuit 22-13 is not fully opened since the signal CPL cannot be turned on. The AND circuit 22-14 is also blocked again by the output signal of the OR circuit 22-12. The "0" signal generated by the OR circuit 22-17 is converted to a "1" signal in the inverter 22-18 and thus corresponds to the check bit of the result. The AND gate 22-22 is opened when starting in Subtra s (PA?) An odd number and the minuend (PM S) is also an odd number and if at the same time as the signal is PC. Adding the two odd numbers results in an even number. The result must therefore be even and contain a "1" in the fifth bit position. The signal TC is present at the third input of the AND circuit 22-22 and thus indicates that there is no carry that would convert the odd result into an even digit. When fully opened, the AND circuit 22-22 therefore generates a "1" signal which is fed to the OR circuit 22-12. If in this case too it is assumed that no complement has to be formed, the AND circuit 22-13 remains blocked, since there is no signal CPL

125 126

is present. In addition, the AND circuit can be coupled to the carry signal PC. 22-14 by the output signal of the OR circuit. As is known, this carry signal PC was blocked again in 22-12. The signal “0” generated by the OR circuit, so that the AND circuit 25-14 da circuit 22-17, is then again not opened. The OR circuit that converts the signal “1” in the inverter 22-18 cannot therefore generate an output signal Bit position. position results in the signal »0«.

If, on the other hand, a complement would have to be performed while simultaneously- A consideration of the inputs to the OR switch-

The generation of an output signal from the AND circuit 25-11 shows that the AND circuits

Circuits 22-11 and 22-20 to 22-22 are formed, 25-20 and 25-21 cannot generate an output signal.

the AND circuit 22-13 would be opened, since neither the signal PAMP nor the signal

and a signal "1" has been generated to the OR circuit PASP. From table 1 it can be seen

Connect 22-17. This signal »1« would then result in the signals FAO and PALPH being generated,

closing in the reversing element 22-18 in the test bit- The AND circuit 25-22 is therefore opened, see above

signal »0« and would thus 15 that an output from the OR circuit 25-11

the correct control bit for the fifth bit position signal can be transmitted. This initial

of the result. How that of the AND signal is reversed in the reversing element 25-18, where-

Circuits 22-11 and 22-20 to 22-22 generated a "0" for the second bit position of the result

Signal indicates, the result is precisely when it is provided.

rend its complement would be odd. The 20 The inputs to the OR circuit 25-19 are for

The complement signal would therefore represent the third bit position of the result as a control bit

Require digit 0 in the fifth bit position. Would be provided. Here, too, it can be seen that the AND

on the other hand, the OR circuit 22-12 has no output signals, and circuits 25-34 and 25-35 have no output signals

signal and would not have to generate a complement, since neither the signal PAMP nor the

the AND circuit 22-14 would have a 25 signal PASP turned on. Since the AND-scarf

Generate signal »1«, which then in the inversions 25-36 to 25-38 also no signal FAO,

element reversed and switched on as test bit "0" in the fifth but a different signal FA

Bit position would be used. must, these AND circuits remain blocked. from

The AND circuits 22-15 and 22-16 have those of the OR circuit 25-19 so there is no output task, which generates an output signal contained in the twelfth digit position. The result is This information is to be fed directly into the result circuit, i.e. the number 0 for the third bit position of the result. At the input of the AND circuit 22-15 tates.

the signal PASP is applied , which indicates that the The signals for the fourth bit position are generated at Subtrahend directly to the result circuit via the OR circuit 25-25. This OR should be carried. If the subtrahend contains a "0" 35 Circuit 25-25 receives a "0" from the AND circuits trollbit, the AND circuit 22-15 25-40 and 25-41 do not generate any signals, since the PAMP signals are opened and generate a Signal »1«. This signal "1" and PASP are known not to be generated. Also, the inverter 22-18 is not opened via the OR- the AND circuit 25-42, since circuit 22-17 is fed, where it converts neither the signal FA 4 nor the signal PC into a test bit signal "0" and the OR circuit 40 became. Likewise, the AND circuit 25-43 ge-22-19 remains in order to provide the control bit "0" of the result for the fifth bit position, since the signal PJ 7 was not generated here. In contrast, as can be seen from Table 1, the AND circuit 22-16 feeds an AND circuit 25-44 in a similar manner, since the signals PCQ, PDB were sent to its one signal "0" from the fifth bit position of the minuend and PALPH to the OR circuit 22-17, the inverter 45 are connected. The output signal of this AND circuit 22-18 and the OR circuit 22-19 in the fifth 25-44 is fed to the OR circuit 25-25, bit position of the result on. to get a "1" for the fourth bit position of the result

Provide the inputs to the OR circuit 22-19. The result for the qui-

those of the AND circuits 25-31, 25-32 and the när- and binary part 1000. How a comparison with that

25-33 are already generated in conjunction with 50 L-Code shows, corresponds to the encrypted result

Fig. 25 has been described. As is well known, 1000 becomes the number 5 and thus represents the correct answer

through these three AND circuits signals to the. Further examples can be used in conjunction with

OR circuit coupled when the sign is similar to the adding-comparator

signals are generated. carry out.

The signals generated by the AND circuits of the present example shown in FIG. 22 are generated in the circuit arrangement. From Table 1 erTable 1 is listed. In connection with this fact that the AND circuits 22-11 and belle as well as with FIG -10 is 60 output signal "0" of the OR circuit 22-12 which wrote. The AND circuits 25-12 and 25-13 AND circuit 22-14 is opened. The outputs are not open at this point, since the signal "1" of the AND circuit 22-14 will only be generated via the signals PASP and PAMP in connection with the OR circuit 22-17 to the inverter 22-18 twelfth digit. As Table 1 shows, the FAO signal is generated and if the correct control bit "0" is entered there. The AND circuit 65 converted.

25-14 is therefore the only circuit which is completely. The processing of the

can be opened. This AND circuit shows information from the two twelfth digits

but still another input line to which wrote. As is well known, the present one existed

127

Arithmetic problem in the addition (+3) + (+2). As the L code shows, the plus sign is represented as 10000. The signals used in conjunction with 128

a plus sign contained in the registers RP-I and RP-2 are shown in Table 2.

Tabel

Signals for processing the signs

Description of the signals

Figure 17: FANS, TENS

PRAS, PRBS
Figures 18 and 19: PM5, PAS

Fig. 20: PALPH (except PALPH
at point in time pt ₁₂ )

PALPH (at point in time pt ₁₂ )

PAMP

TZST

Indicates that Augend and Addend signed values are in the twelfth digit position included

Indicates that Augend and Addend have plus signs

Indicates that there is a control bit "1" in both fifth bit positions

Indicates that there is no direct feed into the result circuit

Shows the time for direct feed-in

Direct feed of the number

No direct feed of the subtrahend

As Table 2 and Fig. 25 show, no output signal is generated from the OR circuit 25-10 because the AND circuits 25-12 and 25-13 are not open due to the absence of the signals PA 1 and PAfI. Signals FA must be present at the inputs of the other AND circuits that provide input signals for the OR circuit 25-10 . However, it can be seen from Table 2 that these signals FA are not generated. A “0” is therefore generated as the information signal for the first bit position. The AND circuit 25-15 coupled to the input of the OR circuit 25-11 is open, however, since the signals PAMP and TMI are present at its inputs. The output signal of this AND circuit 25-15 is fed to the OR circuit 25-11 and reversed in the inverter 25-18 in order to provide the information signal "0" for the second bit position. The information signal for the third bit position is supplied to the OR circuit 25-19. However, a comparison with the signals shown in Table 2 shows that the AND circuits 25-34 to 25-38 are not open. The OR circuit therefore provides the information signal “0” for the third bit position. The information signal for the fourth bit position is generated at the OR circuit 25-25. Since the AND circuits 25-40 to 25-45 are not open here either, this OR circuit generates an information signal “0” for the fourth bit position.

So after the binary and quadratic parts of the sign of the result are equal to zero (or plus), must now the generation of the control bit signal will be described, which is used to evaluate the complete encrypted result sign 10000 is required.

For this purpose, FIG. 22 and Table 2 are referred to. Only the AND circuit 22-11 is open, since the signals PA 5, PM 5 and TC are present at its inputs. The output signal of the AND circuit 22-11 is supplied to the OR circuit 22-12, the output of which is coupled to the AND circuits 22-13 and 22-14 to the AND circuit 22-13 to partially open and the AND - Lock circuit 22-14. The AND circuit 22-14 does not generate an output signal because it is blocked by the output signal of the OR circuit 22-12. The AND circuit 22-13 does not generate an output signal either, since the signal CP must also be present at its input, which, however, is not generated at this point in time. The AND circuits 22-15 and 22-16 also do not generate any output signals, since the signals KT5 and FMS are not present at their inputs. The information signal “0” is therefore generated by the OR circuit 22-17, which is reversed in the inverter 22-18 in order to provide the information signal “1” for the fifth bit position of the result sign. A comparison with the L code shows that the encrypted sign 10000 thus correctly indicates a plus sign.

As already described in connection with FIGS. 23 and 23A, the signal PEQ, which indicates that digits or words are the same, is used primarily to initiate a jump. The jump is caused by the circuit arrangement shown in FIG. The description of this circuit arrangement shown in FIG. 28 now follows. As shown in Fig. 28, this arrangement includes five AND circuits 28-11 to 28-15. The outputs of these AND circuits 28-11 to 28-15 are connected to the inputs of the OR circuit 28-2 so that the latter can generate an output signal which is designated PCTA on the line 28-17. This signal PCTA means that a transfer of control or a jump is to be carried out. The signal PCTA is delayed by one pulse time in the pulse delay device 28-18. As a result, a signal PCT appears on line 28-19, which also indicates that a jump is to be carried out; however, this signal is delayed by one pulse length with respect to the PCTA signal. As can be seen from the time information in brackets, the signal PCTA is generated at time i ₅ and the signal PCT is generated at time t _6. In order to better recognize the meaning of the output signals of the AND circuits 28-11 to 28-15, the input signals of these AND circuits will now be described.

129

130

The AND circuit 28-11 has four inputs to which the function table signal FT 506, the signal PRAS, the signal PRBS and the clock signal pt 13 are present. The function table signal FT 506 is generated at an instruction 19 and supplied to the AND circuits 28-11, 28-12 and 28-13. As will be described further below, the command 19 is a command that determines whether or not the minuend is greater than the subtrahend

h di bid

suluten value, the minuend has the smaller algebraic value. If, therefore, a carry signal is generated which indicates that the minuend has a larger absolute value, the smaller algebraic value is not passed on by the AND circuit 28-13, since the transfer of control or the jump from command 19 is only is then initiated when the minute end is greater. On the other hand, if the signal PC is not generated and has

is equal to the subtrahend. Through the two of the smaller absolute value _i0 minuend and therefore, the AND-S 28-11 signals applied PRAS chaltung the greater algebraic value, is indicated by the PRAS and is that the minuend einposi- AND circuit 28-13, an output signal generated, tive sign and the subtrahend a negative, which indicates that a jump is taking place. Has a sign. The minuend must therefore be greater. The description of the input ais of the subtrahend now follows. Are therefore due to the AND 15 signals to the AND circuit 28-14. As can be seen from the circuit at the same time, the signals PRAS drawing are present at this AND and PRBS , so the AND circuit 28-11 circuit generates next to the clock signal pi 13 also an output signal that indicates that the minuend function table signal FT 505 as well as the signal PEQ is actually greater than the subtrahend. It will be on. How the inputs to the AND circuit 28-12 20 are still written in connection with the instruction 18, the function table signal is described. If the minuend generated a positive prefix FT505 when executing a command 18, sign (signal PRAS) and the subtrahend a nega- The signal PEQ is already in connection with F i g. 23 tive sign, then this condition would have been described by the As is known, this signal AND circuit 28-11 will be controlled. The AND generated at the beginning of a comparison and remains while circuit 28-12 therefore has the task of being switched on at the end of the comparison until it becomes firmly effective when the minuend and subtrahend are set that two compared have positive signs . Are the digits in the registers are not the same. At this moment, the operands located RP-I and RP-2 are equal, so a signal YEQ is generated, while the equality toggle generates a signal PEQ , as already in connection with circuit 23 Λ-21 of its setting state in the connection with FIG 23 was described. If this reset state is switched over. The command 18, signal PEQ coupled to the line 28-20, has the task of determining whether the two are in the, thereby locking the AND circuit 28-12. Operands contained in registers RP-I and RP-2 If, on the other hand, the PEQ signal is not generated, then (minuend and subtrahend) can be the same. If it is assumed with certainty that the minuend equality check establishes that both operands and the subtrahend are not only the same positive signs, then the signals will also have, but are also unequal. The determination made by PCTA and PCT indicating that whichever is greater depends solely on the jump to be made. The AND switch presence or absence of the transition 28-14 thus generates an output signal when an application signal PC (PC at time pt _is ) from. Since the signal PEQ is received at the time pt _{ls, it is known} that the generation of the carry signal 40 is present and indicates that the compared with one another indicates that the minuend is greater than the subtrahend. Digits of the two operands are the same, and when the signal PC occurs on line 28-21 at the same time the function table signal FT 500 is present and the other signals PRAS are present at the same time, it is switched and indicates that an instruction 18 has passed, FT 506 and No -P £ Q, the AND- is carried out. This opened by the AND circuit 28-14 circuit 28-12 and generates an output 45 generated output signal is the OR circuit signal, which indicates that the minuend is greater than 28-2 supplied on line 28-17 the signal of the subtrahend. PCTA and on line 28-19 that an im-

At the inputs of the AND circuit 28-13 pulse-length delayed signal PCT is generated, the clock signal pt 1 3, the; F unktionstabellensignal at the inputs of the AND gate 28-15

FT 506 and the PRBS signal are present as the pass signal, 50 the clock signal tS and the output signal are present, while the PC signal is also present as a blocking signal at the OR circuit 28-1. At the entrances of the lies. Here, too, it is pointed out again that there are a number of jumps in the OR circuit 28-1, the AND circuit 28-11 becomes effective when the signals from the synchronizing devices are applied, the subtrahend a negative and the minuend a positive, which indicate that for others Facilities of the tive sign. The AND circuit 28-13 55 computing system, such as. B. the input and output forwards, on the other hand, takes effect when minuend and subdirections, a jump is necessary so that they have negative signs. Because the sub-facilities can do their job. As trahend has a negative sign, if the AND circuit 28-13 is still written in connection with the commands 18 and 19 via the line 28-22, the OR circuit 28-1 receives a signal PRBS . Determining whether the 60 input signal is algebraically greater than the nega- and output devices due to a test of the in-negative minuend.

tive subtrahend, depends on whether the carry-over can thus be determined

signal PC (PC at time pt ₁₃ ) is generated or that a jump through a signal PCTA or PCT is not. As is known, the carry signal PC is used to initiate, these signals indicating, inter alia, that the absolute value of the minuend 65 is generated when two certain values are greater than the absolute value of the subtrahend. Operands have an equality or size check So the minuend and subtrahend have negative advances via the AND circuit 28-14, with characters and the minuend referring to the larger AND circuits 28-11, 28-12 and 28-13 fixed-

509 538/373

131

132

it is set that the minuend is greater than the subtrahend.

The functions of the signals PCTA and PCT in connection with the command circulation control unit shown in FIGS. 10 and 11 will now be described. As is known, a signal PCT was generated by the command circulation control unit 10-22, which signal was fed to the AND circuit 10-37 via the OR circuit 10-60. The M digits from the command register IR-I can also be coupled to the AND circuits 10-37, since in the event of a jump, these M digits are relocated from the command register / jR-1 to the control counter 10-35, where the new Provide address from which the new instructions in connection with the jump can be taken. The meaning of the signals PCTA and PCT results in particular from a repeated consideration of FIG. 11.

As FIG. 11 shows, a signal PCTA is present at the input of the OR circuit 11-33. The output signal of this OR circuit 11-33 is coupled to the flip-flop circuit 11-4, which resets it and thus ends the display that a new command is being relocated from the command register IR-2 to the command register IR-I. The termination of this display results from the consideration that the new command requested by the transfer of control is located in a memory location which is identified by the M digits of the command contained in the command register IR-I; the instruction originating from an earlier command and stored in the command register IR-2 must therefore not be re -stored in the command register IR-I . Rather, the driven by the M-number of the command located in the instruction register IR-I instruction to the instruction register IR-2 has to be transported to be from there finally re-stored in the instruction register IR-I. The flip-flop 11-4 is therefore switched to its reset state and thus ensures that the further sequence of operations does not proceed as if the old command was still in the command register IR-2 , which is now in the command register / jR- 1 should be saved.

It can also be seen from FIG. 11 that a signal PCT is applied to the OR circuit 11-36. The output signal of this OR circuit causes the flip-flop 11-2 to be switched to its set state in order to provide an end pulse for the command currently being executed. In other words: As soon as it is certain that a jump is to take place, an end pulse must be generated so that the command executed at the beginning of the jump (command 18 or 19) can be ended a short period later.

Like F i g. 11 further shows, a signal PCT is also applied to the OR circuit 11-13. The output signal of this OR circuit causes the switch-off toggle circuit 11-1 to be switched to its set state, thereby generating a switch-off signal. As is known, this shutdown signal is passed to the command decoder 10-17 (Fig. 10) to ensure that the system is shutdown and does not provide the function table signals normally generated by the / digits. This switch-off period is important insofar as the jump caused by a jump instruction only has the task of triggering a new instruction which tells the machine which operations it now has to carry out on the basis of this jump. In other words: If the signals PCTA and PCT are present , the machine must follow another command cycle, and the command remaining in the command register IR-I must therefore not exercise any control function during this time. The function table signals generated by the instruction that initiated the jump must be terminated. The signal PCT is therefore coupled to the flip-flop 11-1 via the OR circuit 11-13, whereby this flip-flop is switched to the setting state and generates a switch-off signal.

From FIG. 11 it can also be seen that a signal PCT is also present at the AND circuit 11-39, whereby this is blocked. In addition to this signal PCT , the clock signal i6 as well as the setting signal of the flip-flop circuit 11-4 and the reset signal of the flip-flop circuit 11-3 are also applied to this AND circuit. The output signal of the AND circuit 11-39 is coupled to the OR circuit 11-38, the output signal of which causes the control counter 10-35 to be incremented by one, ie from C to C + t. The new address Cf-1 in the control counter 10-35 normally represents the address of the command which is then relocated from the memory to the command register IR-2. If, however, the signal PCT is present , a different address is stored in the control counter 10-35, namely the M digits of the command contained in the command register IR-I. The incremental signal for the control counter is blocked because the M-digits transferred to the control counter 10-35 must not be increased by one in this case, because the control of an address may not be successful and therefore a second control is saved in the control counter M address must be carried out. If the address in the control counter 10-35 were to be increased by one in this case (M + 1), the control counter would, after an unsuccessful first activation of the memory, activate an incorrect memory location in its second query. This process will be described in connection with commands 18 and 19.

In addition, the signal PCT is coupled to the OR circuit 11-20, and the output signal of this OR circuit 11-20 is connected to the AND circuits 10-37 (Fig. 10) via the OR circuit 11-60. As FIG. 10 shows, when there is a jump, ie when a signal PCT is generated, the M digits of the command stored in the command register IR-I are stored in the control counter 10-35 via the AND circuits 10-37. To 10-37 to completely open the AND circuits, thereby enabling this re-storage, in addition to these M-digits must still be present, the signal PCTA. This signal is fed to AND circuits 10-37 through OR circuit 10-60.

The signal PCTA is also used to disable the AND circuit 11-17. As is known, the output signal of this AND circuit is coupled to the pulse delay device 11-18 in order to provide a pass signal on the line 11-42 for the AND circuits 10-36. Like F i g. 10 shows, the AND circuits 10-36 have the task of sending the address information contained in the control counter 10-35 to the memory address decryption method.

133

134

direction 10-64, so that after a successful interrogation of a first command (when the MNB signal is switched on) another command can be interrogated. While a signal PCT is being generated, ie when there is a jump, the address stored in the control counter 10-35 must not activate the memory because a command has been removed, since in this case the control counter 10-35 would query a command that is no longer required. The signal PCT _{present at the instant i ß} thus blocks the AND circuit 11-17 and thus prevents the information contained in the control counter 10-35 from being able to pass through the AND circuits 10-36.

As shown in FIGS. 10 and 11, the AND circuits 10-12 α have four inputs to which the delayed signal N, the M-digit signals, the signal PCT as a blocking pulse and the clock signal i6 are present. If a jump is carried out, the M-digits in the command register IR-2 cannot be re-stored in the command register IR-I , since the M-digits of the command contained in the command register IR-I are currently being stored in the control counter 10-35 serve there as a new basis for orders. At the same time, the M-digits from the command register IR-I control the memory location in which the instruction necessary for the conditional jump command is located. As FIG. 10 shows, the iV digits in the instruction register IR-2 can be re-stored in the register IR-I via the AND circuits 10-12 without influencing the address of the other instruction required to carry out the jump. The signal PCT is therefore coupled to the AND circuits 10-12 α as a blocking signal and thus prevents the M digits in the command register IR-2 from being re-stored in the command register IR-I.

The table below shows the functions of the PCTA and PCT signals.

PCTA toggles the flip-flop 11-4 to its reset state, thereby preventing the flip-flop 11-3 from being set, and this in turn prevents the generation of an N signal until the instruction whose address is represented by the M digits is from the instruction register IR-2 can be re-stored in the command register / jR-1;
is coupled to the AND circuits 10-36 via the OR circuit 11-20. These AND circuits are thus opened and can forward the M digits to the address decryption device 10-64;

is transmitted from the OR circuit 11-36 as an end pulse and causes the flip-flop circuit 11-2 to be switched to its set state. The AND circuit 11-29 is partially opened by the setting output signal of the flip-flop circuit 11-2 and can thus generate a signal iV after the signal PCTA has been generated;

is transmitted from the OR circuit 11-13 in order to switch the flip-flop 11-1 into its setting state, thereby generating a switch-off signal until the command called up by the M digits of the command 18 or 19 is in the command register IR- I is relocated.

PCT blocks the AND circuit 10-12 α and thus prevents the M digits from being transferred from the command register IR-2 to the command register IR-I ;

is coupled by the OR circuit 11-20 to the AND circuits 10-37 in order to open them so that the M-digits of the instruction 18 or 19 can be reloaded from the instruction register IR-I into the control counter;

blocks the AND circuit 11-17 and thereby prevents the generation of a pass signal, so that the address in the control counter is not sent to the address descrambler can be transferred;

blocks the AND circuit 11-39, so that the control counter when storing the M digits is not immediately switched to the counter. That way you can use the M-digits also control the memory from the control meter if the memory is activated during a direct control from the command register LR-I should have been occupied.

Accounting orders

For a better understanding of the central processing plant, all are shown elsewhere “Accounting commands” in connection with the commands shown in FIG. 87 to 94 shown timing diagrams described. These timing diagrams show the timing of the various signals that during these commands from the central shown in the form of block diagrams (Figs. 10-28) Processing plant are generated.

The data transfer instructions will first be described. These commands cause the contents of a specific memory location to be re-stored in the register RP-I or RP-2, or they cause the contents of one of these registers to be re-stored in a specific memory location. 87 is the timing diagram for instructions 15 and 12 (data relocation instructions) which cause the contents of a memory location identified by the five iV digits of an instruction to be relocated to register jRP-1 or RP-2 . Both data relocation instructions 12 and 15 will be discussed together since the signals generated by instruction cipher 10-18 in response to any of these instructions are essentially the same, except that instruction 12 generates a function table signal intended for register RP-2 during the function table signal generated by instruction 15 is intended for register RP-I .

The format of the two commands has already been described elsewhere. But let it be again pointed out that commands 12 and 15 - like all commands - consist of twelve digits, The two most significant digits marked with / digits denote the designation for the one to be carried out Represent command. The next five most significant digits, the IV digits, identify a specific location in memory, while the remaining five digits or M-digits in these commands are not be used. The commands 15 and 12 have the following format:

15 NNNNN XXXXX,
12 NNNNN XXXXX,

135

136

where X represents a digit that cannot be deciphered.

From the earlier description of the accounting commands it follows that the command 15 causes the contents of a memory location identified by the IV digits to be re-stored in the register RP-I , while the command 12 causes the content of a memory location identified by the IV digits is transferred to the register RP-2 . In the first line of the timing diagram in FIG. 87 indicates the pulse times during which the content of the command register IR-I is available in the form of signals. In this context it is assumed that the instruction stored in the instruction register IR-I represents an instruction 12 or 15 with the format specified above. It is known that the / - and iV digits of an instruction stored in the instruction register IR-2 are transmitted by the AND circuits 10-12 (FIG. 10) at the time t ₅ and are stored in the instruction register IR-I at the time t _e. As shown in the first line in FIG. 87 as can be seen, the command 12 or 15 is located in the command register IR-I from time t _e. As the second line of the timing diagram shows, the program counter (FIG. 16) generates an output signal PPCl which, as is known, represents the normal or reset signal of this counter.

Either the output line PL 151 or PL 121 is excited by the decryption device 10-17 under the influence of the signal PPCl generated by the program counter and on the basis of the / digits stored in the command register IR-I and characterizing the command 15 or 12. The output line PL 151 is energized during the first stage of the command 15 and the output line PL 121 is energized during the first stage of the command 12. As a result of the energization of one of these two output lines of the decryption device 10-17, the encryption device 10-18 is used to generate the function table signals FT600 and FT1WS during the periods shown in the timing diagram in FIG. 87 illustrated time segments caused. The AND circuit 10-36 (FIG. 10), among other things, is blocked by the function table signal FT 600 , so that the control counter 10-35 cannot control the memory for the purpose of taking a new command. As already mentioned earlier, the AND circuit 11-22 is also blocked by the function table signal FT 600 , so that the memory-free signal MNBt 2 generated as a result of a successful control of an operand does not pass through the AND circuit 11-22 and thus does not the toggle switch 11-4 cannot adjust. As is known, the flip-flop 11-4 normally indicates that an instruction is being taken from memory. The function table signal FT 700 is generated at the time ^ and causes the AND circuits 10-15 to transmit the N digits of the command 12 or 15 to the memory address decryption device, so that the content of the memory address identified by the iV digits of the central processing system can be fed. The activation of the memory by means of the ΛΓ digits of a command is shown in the seventh line of the timing diagram and takes place at time t _Q. Assuming that the selected memory unit is not otherwise occupied, a memory-free signal MNB is generated, which appears at time J ₁ . This memory-free signal MNB is fed to the AND circuit 16-16 of the program counter for the purpose of generating the signal PPC S 2. As is known, the AND circuit 16-16 is controlled not only by the memory-free signal MNB, but also by the function table signal FT 600 and the clock signal ti . This AND circuit can also be blocked by a signal appearing on the line PL 143 of the decryption device 10-17

ίο be. However, no signal is coupled to line PL 143 during the present commands 12 and 15. In contrast, the function table signal FT 600 shown in the fourth line of the timing diagram (FIG. 87), the memory-free signal MNB and the clock signal ti are applied to the AND circuit 16-16. As a result of the coupling of these signals, this AND circuit thus generates the signal PPC 52. At time t ₇ , the read signal PYMR1 is also generated. This signal is from the AND circuit

ao 12-18 (FIG. 12A) is generated at time t ₇ and causes information to be read out from the memory at time t ₀ . The signal PPC S2 is fed to the flip-flop circuit 16-19 of the program counter, which causes this to generate the signal

as PPCl ends and the signal PPC 2 is generated instead. As the ninth line of the timing diagram (FIG. 87) shows, the second stage of command 12 or 15 is initiated in this way.

If the command 15 is in the command register IR-I , the output line PL 152 of the decryption device 10-17 is excited by those signals which were generated on the basis of this command and on the basis of the output signal PPC 2 of the program counter (FIG. 16) . On the other hand, if command 12 is in command register IR-I, line PL 122 is energized under the influence of signal PPC 2 from the program counter. These signals appearing on lines PL 152 and PL 122 are shown in the tenth line of the timing diagram in FIG. By energizing the two lines PL 152 and PL 122, the command encryption device 10-18 is caused to generate the function table signal FT 610, which is connected to the final pulse AND circuit 11-32 (FIG. 11). AND circuit 11-32 transmits _{a signal at time i 5} , provided that neither signal RCP is generated by device 26-18 (Fig. 26) nor signal N is generated by AND circuit 11-29. As is known, the signal N, which was switched on at an earlier point in time and caused the currently executed command 12 or 15 to be re-stored from the command register IR-2 to the command register IR-I, caused the flip-flop circuit 11-2 via the OR circuit 11-37 (Fig 11) deferred. During the execution of the present command, the signal N is therefore not present and thus cannot disable the end pulse AND circuit 11-32. The recomplement signal is also not generated with this command, since this signal is only generated in connection with the add and subtract commands to be described below. After coupling the function table signal FT 610, a signal at the time t ₅ is therefore fed from the AND circuit 11-32 to the setting input of the flip-flop 11-2 via the OR circuit 11-36, so that this flip-flop starts generating _{at the time ί β} of an adjustment output signal begins. By the setting signal of the toggle switch

137 138

11-2, AND circuits 11-29 and 11-14 are called information at time t _{7 of} the second

prepared so that the currently executing execution stage is transferred to the register RP-2 via the AND

fail at time t _{s of} the next short period can be supplied to circuits 10-24,

ends because either the AND circuit 11-14 As the fifteenth line of the timing diagram in FIG

the setting of the shutdown toggle 11-2 5 Fig. 87 shows, the function table signal

or the AND circuit 11-29 causes the FT620 in the second stage of command 12 or 15

Signal N generated. generated. This signal begins from the time t _x

The second stage command is in command register IR-I and lasts until time t ₀ . the end

15, then in the second stage of this command, i. H. 16 it can be seen that the function table

while the signal PPC 2 from the program counter erio signal FT 620 and the clock signal tO to the AND

is generated, the function table signal FT704 from circuit 16-17 of the program counter is turned on

the command encryption device 10-18 and thereby generate the signal PPCS-2X,

testifies. On the other hand, if the command register IR-I is located, this signal PPCS-2X is sent to the setting input

command 12, in the second stage this is sent to the flip-flop circuit 16-20 of the program counter.

Command, that is, switches during the generation of the signal 15. When coupling the signal PPCS-2X

PPC 2, the function table signal FT 706 from the changes the flip-flop 16-20 as the only one of the

Command encryption device 10-18 is created. Flip-flops 16-18 belonging to the program counter,

The function table signals FT706 and FT704 16-19, 16-20 and 16-21 show their status. Had the

if the command encryption device program counter generates the signal PPC 2 beforehand, see above

10-18 at time i ₆ during the second stage 20 is achieved by switching the toggle switch 16-20

of the command to which they are assigned. That no further line PPCl to PPC 4 excited any more.

Function table signal FT 704 is used for blocking. The program counter does not generate any signals

the AND circuit 14 C-41 and thus prevents more to the AND circuits of the command decryption

the transmission of the hold and shift signal selungsvorrichtung 10-17 coupled so that this

of the flip-flop circuit 14C-27, which are also not opened for the register 25 AND circuits.

RP-I is provided. The stop signal of the toggle switch The program counter is incremented after

device 14C-27 cannot send to the PPC2X for the 60 stages, so that the function table signal FT 610

of the register RP-I provided 60 round-trip AND is switched off by the end pulse AND circuit

Circuits 14C-15, 14C-25, etc. can be coupled after this AND circuit has a

the. In other words: The function table 30 has transmitted the end pulse. As is well known, it will

signal FT 704 is used to clear the register RP-I, signal N only at time i ₅ after transmission

because the bits within each memory element of a signal from an end pulse AND circuit

of the register can no longer circulate. (e.g. 11-32) is generated. The signal N causes the

The Funktionstabellensigrtal FT 706 is coupled to the re-storing of a new command from the command AND circuit 14C-4D and has DIE 35 register IR-2 in the instruction register IR-I to time same function as the function table signal t in point _6. If the program counter therefore remains set to PPC 2 at time FT 704, ie it prevents the transfer of point t ₅ , ie if it were not switched on after the hold signal of the PPC 2 X assigned to the register RP-2 , the AND flip-flop 14C would -32. In other words: In circuit 11-32 a short period after the generation of the function table signal FT 706 40 a first end pulse and a second end pulse, the register RP-2 is cleared. generate at the same time during the one

As the fourteenth line of the timing diagram is entered into the command register IR-I in a new command. 87 shows the function table signal is being stored. This would of course be undesirable, and FT70S or FTIQTI at time t _{7 of} the second of the program counters (FIG. 16) is therefore generated after the level of instruction 15 or 12, respectively. The function 45 PBC2X switched on. By advancing the table signal FT 705, circuits 10-25 are coupled to the 60 input ANDs of the program counter from PPC 2 to PPC 2 X , which connect the read line to the function table signal FT 706 or FT 704- HSB-R with the register jRP- 1 (Fig. 10). switched, so that the information contained in one of the two registers These input AND circuits to the register RP-I or RP-2 up to the input RP-I are also shown in FIG. 14C and there with 50 storage of a new instruction in denotes the command 14C-12C1, 14 C-II Cl etc. In adults register IR-I is not deleted, generation of the function table signal FT705 is In the case of the instructions 12 and 15 can thus zualso the information be found sammenfassend during the first stage, that the N-CLOSE command 15 through the iV -Digits of this command remote from the first command (PPCl) the memory was called for the purpose of driving to the read line HSB-R while removing an operand. The second stage is coupled and simultaneously the function table signal FT 600 circuit 10-25 is transported to the register i? Pl via the AND. testifies, so that the control counter at this point in time, on the other hand, is the command 12 in the command - do not drive the memory because of a command register IR-I, then instead of the function table. If the memory is free, the memory signal FT 70S, the function _table signal FT 707 60 free signal MNB is generated, whereby the program is switched on at the time ΐ Ί during the second execution counter (Fig. 16) to PPC2 level of this command is generated. The function table and new function table signals are generated, signal FT707 is coupled to the 60 input AND switches which store the queried operands 10-24 (FIG. 10), which read into one of the previously cleared registers Connect i? Pl and line HSB-R to register RP-2 . 65 .RP-2 initiate.

The function table signal FT707 thus allows to illustrate the individual operational

that during the first execution stage of the NEN is the sequence of instructions 12 and 15 in the

Command 12 is listed by the iV digits of this command from the two tables below.

139

140

Data transfer instruction 12
(N) RP-2. Format: 12 NNNNN XXXXX

Function table signal

surgery

The program counter is in the PPCl position

FT 700 Transports the N digits in the command register IR-I to the address decryption device at time t ₇

FT 600 Prevents a new command from being taken and advances the program counter to FPC 2 when the memory-free signal MNB is generated

The program counter is in position PPC 2

FT610

FT706
FT707

FT62O

Generates EP at time t ₅
Clears the register RP-2

Transports the information extracted from the memory at time t ₇ to register i? P-2

Switches the program counter to PPC2 *

The program counter is in the PPC 2 X position

PPC 2 X is not evaluated, so that no function table signals are generated. On the other hand, 3 », the command is terminated at time t _s as a result of the end pulse that was generated during the program counter setting PPC 2.

Data transfer instruction 15
(JV) RP-I. Format: 15 NNNNN XXXXX

Function table signal

surgery

The program counter is in the PPCl position

FT700 Transports the iV digits in the command register IR-I at time / ₇ to the address decryption device

FT 600 Prevents the removal of a new command and advances the program counter to PPC 2 when the memory-free signal MNB is generated

The program counter is in position PPC 2

FT610 Generates EP at time t ₅

FT704 Clears the register i? P-l

FT70S Transports the information taken from memory to register ÄP-1

FT 620 Advances the program counter to PPC 2 X at time t ₀

The program counter is in the PPC 2 X position

PPC 2 X is not evaluated, so that no function table signals are generated. In contrast, the command is terminated at time ^ as a result of the end pulse that was generated during the program counter setting PPC 2.

Next, the data transfer instructions will be described, which store the contents of the registers RP-I or RP-2 in a memory location identified by the iV digits of the relevant instruction. 88 shows the timing diagram for instructions 13 and 16, which store the contents of registers RP-I and i? P-2 in a memory location identified by the ^ digits of instructions 13 and 16, respectively. As already in connection elsewhere

jo was mentioned with the accounting commands, command 13 causes the contents of register i? P-2 to be re-stored in a memory location identified by the five iV digits of this command, while instruction 16 causes the contents of register RP-I to be re-stored into a memory location identified by the five JV digits of instruction 16. The data relocation instructions 13 and 16 are discussed together since the signals generated by the instruction encoder in response to any of these instructions are essentially the same, except that instruction 13 is the function table signals for register RP-2 and instruction 16 is the function table signals generated for the register RP-I. The commands have the following format:

13 NNNNN XXXXX, 16 NNNNN XXXXX.

In the first line of the timing diagram in FIG. 88 indicates the pulse time during which the content of the command register IR-I is available in the form of signals. As the second line of the timing diagram shows, the program counter (Fig. 16) produces an output signal PPCl which, as is known, represents the normal or reset signal for this counter.

Either the output line PL 131 or PL 161 is energized by the decryption device 10-17 under the influence of the signal PPCl generated by the program counter and on the basis of the / digits stored in the instruction register IR-I and identifying the instruction 13 or 16. The output line PL 131 is energized during the first stage of the command 13 and the output line PL 161 is energized during the first stage of the command 16. As a result of the energization of one of these two output lines, the command encryption device 10-18 is caused to generate the function table signals FT 600 and FT700 during the time periods shown in the timing diagram in FIG. The AND circuit 12-18 B 4 (FIG. 12A) is blocked by further signals appearing on the line PL 131 or PL 161. This AND circuit normally generates a read signal PYMRl _{at time Z 7.} The read signal is therefore suppressed during the execution of one of these relocation or write commands. As already mentioned earlier, the AND circuit 10-36 (FIG. 10) is blocked by the function table signal FT600, so that the control counter 10-35 cannot drive the memory for the purpose of removing a new instruction. In addition, the AND circuit 11-22 is also blocked by the function table signal FT 600, so that the control unit of the command circulation device 10-22 (FIG. 11) cannot react to the memory-free signal MNB generated when an operand is queried. The function table signal FT 700 is generated at time i ₇

35

40

141 142

generates and causes the AND circuits 10-15 to the input AND circuits 10-45 (FIG. 10), the transfer of the JV digits of the instruction 13 or 16 are assigned to the register RP-I . These AND circuits to the memory address decryption device connect the memory elements to the HSB-W write line, so that the 60 information units of an open memory location identified by the JV digits are selected and the content of the 5 edge is located . register RP-I or RP-2 on the write lines thus, when the signal function table FT 703

HSB-W can be written into this memory location because it can be stored in the command register IR-I. Assuming that the commands 16 and on the basis of the output signal PPC2

JV digits marked controlled memory of the program counter is generated, so the content of the position is not otherwise occupied, a _memory register RP-I is via the write line HSB-R to

cher-free signal is generated, which transports memory at time t _t and there into the memory

appears. As already indicated in connection with the commands iV digits of command 16

12 and 15, the memory location is stored which was activated during the first off-free signal MNB of the AND circuit 16-16 of the executive stage of this command. gram counter so that the signal PPC2S ₁₅ is generated. If the function table signal FT 710 is generated, so is generated. The signal PPC2S causes the contents of the register RP-2 at the point in time that the program counter is switched on to PPC 2 in the same way via the write line HSB-R in, so that the second stage of the command passes through marked the N-digits of the command

13 or 16 can start. This point in time is stored in the memory location. It should be noted that the eighth line of the timing diagram in Fig. 88 provided DAR ₂ o in the registers RP-I and RP-2 contained. The memory-free signal MNB will also be coupled together at the time t _i to the write line angedem of the AND circuit 11-42 (FIG. 11), but the memory will only be fed to the memory at the time with the clock signal ti . Reach the starting point t ₅ as a result of the pulse delay,
In summary, it can be stated that the output of a pulse delay device 11-43 35 the write commands 13 and 16 are coupled through in two stages, which in turn are passed the memory-free-Si. In the first stage, the radio signals MNB t2 are generated. This memory-free signal generation table signals FT 700 and FT 600, where- MNB t2 is connected to a final pulse AND circuit by the // digits of the respective command in memory 11-35, the output signal of which via a rather at the time t _{7 can} control and equal-OR circuit 11-36 at the input of the Kipp- 30 timed the control counter 10-35 is blocked, so that circuit 11-2 is coupled. At the end pulse this the memory for the purpose of removing another AND circuit 11-35 is also the radio command can not control. That in the case of a tion table signal FT 709 on. This functionally successful control of the memory generated table signal FT 709 is generated in the first execution memory free signal MNB initiating the initiation stage of command 13 or 16 (eleventh 35 of the second command stage, namely the preparation line of the timing diagram), but is delayed by one im- the output AND circuits 10-45 or 10-46 pulse time, so that its waveform one of the registers RP-I and RP-2 appears to be longer than the waveform of the function table signals FT 703 due to the coupling pulse time or FT 710. of the signals that generate this function table signal. If command 13 has to be executed, this will be the result. The function table signal FT709 is generated 40 function table signal FT 710 and the In is transported to the memory on the basis of the output signal PPCl of the program of the register RP-2 , the gram counter and on the basis of the output signal Command register IR-I storage table signal FT 703 generated and the content of the th command generated. The signal PPCl is supplied to the memory from t ₆ to register RP-I.

ij at. The timing diagram shows that it should be noted that both the read commands 12 function table signal FT709 from t ₇ to including and 15 and the write commands 13 and 16 are each light. The AND circuit 11-35 transmits to be carried out in two stages. Therefore, after generation of the read commands require the memory-free signal to the execution, however, two short MNB an end pulse at the time i ₂ for switching periods or sixteen pulse periods, while the set input of flip-flop 11-2. These final 50 write commands require only a short pulse to be carried out in the tenth line of the timing diagram in a period or eight pulse times. This Fig. 88 can be seen. The difference arises from the fact that the function table signal FTIQß is generated from the memory for a short period in the second execution stage of the instruction 16 read commands 12 and 15 for the extraction of information, while in the same stage of the instruction 13 the 55 gen, while the Write commands this pre-function table signal FT 710 is generated. Each course is omitted.

according to which of the two commands in the command re- A comparison of the read with the write commands

gister IR-I is stored, it is shown at time i ₄ that several read commands one after the other, ie

the second stage (PPC 2) either the function can be carried out without a shutdown period,

table signal FT703 or FJ710 generated. The reason for this is that these commands are each in

Function table signal FT 710 will be executed for about 60 off two short periods, whereby for

input AND circuits 10-46 or 14B-12D1 at time t _{7 of} the second short period

etc. of the register RP -2. coupled. This AND new command is queried by the control counter 10-35

Circuits connect the storage elements in which, since at this point in time the functional

to which the 60 information units of a 6g table signal FT 600 are not available. Is a command 12

Operands are located, i.e. completely executed with the HSB-W or 15 write line, so is located

(Figures 10 and 14B). The function table signal of the next command to be carried out already in the

FT703 is located at one input of the 60 IR-2 failure registers and can be entered in the command register

143

144

IR-I can be relocated. If, on the other hand, a number of write commands 13 or 16 are executed, the switch-off period is provided as follows: Assuming that a write command is being executed and is therefore in the command register IR-I and that the next command stored in the command register IR-2 is also a Is a write command, no new command can be requested from the control counter 10-35 during the execution of the first write command, since the function table signal FFoOO is switched on. However, if the first write command has been completely executed, a signal N is generated since setting output signals are generated by the flip-flops 11-3 and 11-2 (FIG. 11). On the basis of this signal N , the second write command is therefore transferred from the command register IR-2 to the command register IR-I . In contrast, no new command can be stored in the command register IR-2 , since no further command could be queried while the first write command was being executed. The control counter 10-35 cannot activate the memory during the execution of the second write command either. During the short period in which the second write command is being executed, the flip-flop 11-3 is not set. When the second command has ended, no signal iV is generated either, and the switch-off trigger circuit 11-1 (FIG. 11) is set as can be seen in the last line of the timing diagram. In this case, the program _{counter is} not reset at time t e, since signal N is not generated. The switch-off toggle circuit 11-1 is set, however, and thus blocks the output of the command decryption device 10-17. This means that no function table signals are generated that would otherwise control the components of the central processing system. As long as the toggle switch 11-1 is set, a new command can be requested from the control counter 10-35, since the function table signal FT600 is not present. Requested commands are stored in the command register IR-2 and then re-stored in the command register IR-I

To illustrate the individual operations, the sequence of commands 13 and 16 is shown in the two listed in the tables below.

Write command 13
(N) RP-2. Format: 13 NNNNN XXXXX

Write command 16
(N) RP-I. Format: 16 NNNNN XXXXX

Function table signal

surgery

The program counter is in position 1

FT 700 Transports the iV digits located in the command register IR-I _{at time i 7} to the address decryption device. Blocks the memory read signal at time t ₇

FT 600 Prevents the control counter 10-35 from taking a new command. Switches the program counter to PPC2 when the MNB signal is present. Prevents the command circulation control unit from driving the address decryption device

FT 709 Generates EP when the memory-free signal MNB is coupled

The program counter is in position 2

FT 703 Couples the content of register i? Pl at time i ₄ to the HSB-W write line

Unconditional jump command 05

Function table signal

surgery

The program counter is in position 1

FT7Q0

FT 600

FT 709

Transports the iV digits located in the command register IR-I at time t ₇ to the address decryption device

Prevents a new command from being taken through the tax meter 10-35

Generates EP when the memory free signal MNB is coupled (AND circuit 11-35)

The program counter is in position 2

FT710

Couples the content of the register RP-2 at time t. to the HSB-W write line

Next, the unconditional jump instruction 05 will be described. It is assumed that the computer before receiving command 05, the operations in accordance with a first group of commands has executed. The M-digits of the command 05 are sent to the control counter 10-35. The one from the command 05 is taken from the memory location indicated by the five M-digits of the command is marked.

Although the computer system executes the computer program in a certain order (e.g. in Agreement with the first command group set by the control counter 10-35), so must under certain conditions this sequence is interrupted and a completely different part of the memory be controlled for the purpose of taking a new command group. If this interruption of the normal sequence regardless of that prevailing in the computer system at the time of the interruption State, a command must be provided which is designated as "unconditional jump command".

90 shows a timing diagram from which the sequence of command 05 can be seen. As the first line of this timing diagram shows, the command is located in the command register IR-I at time t ₆ and has the following format:

05 XXXXX MMMMM,

where X represents a number that cannot be evaluated.

Like the second digit of the timing diagram in FIG. 90 shows, a signal PPCl is generated by the program counter (FIG. 16) when the command 05 is stored in the command register IR-I. As a result of the command 05 in the command register IR-I and the signal PPCl generated by the program counter, the decryption device 12-17 C (FIG. 12) decrypts the line (not shown).

145 146

device PL 105 energized. This process is shown in the third function table signal FT 600 as the blocking signal on line of the timing diagram. By which is switched on. The function table signal FT 613 is the output line PL 105 generated by the decision in the first execution stage of the command 05, processing device 12-17C coupled signal is during the connection of the signal PPCl; the command encryption device 10-18 to FIG. 5 lasts from the time * ₇ to the time t ₃ . The generation of the function table signal FT 600 initiates the memory-free signal effective at time t _z (sixth line of the timing diagram). At the same time , the function table signals FT 701 (SE and OR circuit 11-23 to the setting input bente line), FT 614 (fourth line) and FT 613 (eleventh of the flip-flop circuit) can therefore be MNB ti via the AND circuit 11-21 11-4 (Fig. 11) coupled who creates line). io den. Usually, generating the

As already mentioned earlier, the radio function table signal FT 600 is indicated that tion table signal i <T600 at the time ^ generated by the loading signal contained in the command register / jR-1 and as a blocking signal to the AND circuits 10-36, an operand and no operand is missing Command removed from being switched on in order to prevent it from being supposed to. The memory-free signal MNB, insbeson control counter 10-35 particular the memory 15 for removal ί MNB ti, the other with a successful Ansteueeiner first command group at the time _Ί tion is produced, therefore should the Befehlsumlaufansteuert. At the same time, the function table control unit will not influence and indicate that a signal FT 600 is also being transferred to the AND circuit 11-22 command. In the present case (FIG. 11) coupled as a blocking signal, while it must be controlled by the M-digit AND circuit 16-16 (FIG. 16) as a pass as far as the command signal contained in the command register IR-I will. At the last-mentioned 05 marked memory location for the removal AND circuit, the clock signal ti of an instruction is also present in the same way as the memory-free signal MNB . an operand is taken. The queried word

As the seventh line of the timing diagram shows, it actually represents a new command, so that the function table signal FT701 is generated at the time of command 05, the function table signal FT 613 point i ₇ for a pulse length due to the im and to the AND -Circuit 11-21 angekopfehlsregister IR-I stored command 05 as well as on pelt, whereby the generated memory-free signal reason of the program in position PPCl is connected MNBtI to the toggle circuit 11-4 is generated counter. The function table signal FT 701 and thus indicates that a new command to be sent to the 25 AND circuits 10-14, that the error register IR-I is being transported. The function with the M digits of the table signal FT 613 in the command register IR-I thus allows the memory-free signal MNB generated during the borrowed command 05 of the memory address decisions of the command 05 to be supplied to the processing device. Also via the AND circuit 11-21 and the OR if at time f ₇ , the read signal PYMR1 circuit 11-23 can be coupled to the setting input of the Kippam output of the AND circuit 12-1854 35 circuit 11-4. Known- (Fig. 12A) generated. Both the read signal PYMR 1 borrowed is indicated by the setting of the flip-flop as well as the output signal of the memory address 11-4 that an instruction is transported from the memory to the decryption device to the memory command register IR-I ,
forwarded, where they take effect at time t _0. In addition to the connection to the AND circuit

If the from the M-digits of the command 05 is 40 11-21 the function table signal FT 613 is free via the selected memory unit, then a memory- the AND circuit 11-27 is generated on the reset side of the free signal MNB , which for Time t _t flip-flop 11-3 as well as to the control counter 10-35 (ninth line of the timing diagram) coupled to the input, as has already been described in connection with FIG. 10 AND circuits 16-16 of the program counter. Thus, Fig. 10 shows that the radio (Fig. 16) as well as to the AND circuit 11-42 attached 45 table signal FJ 613 is coupled to the input of the AND, the output of which is coupled to the input of the IM circuit 10- 61 (Fig. 10) together with a pulse delay device 11-43 (Fig. 11) is applied. Clock pulse ίΟ is coupled. The output pulse of this AND circuit 10-61 that is connected to the AND circuit 16-16 is the first memory-free signal, the program counter input of the 25 AND circuits 10-37 via the (Fig. 16 ) switched to PPC2 so that the 50 OR circuit 10-60 is fed. The other on-signal PPC _{2 takes} effect at time i 2. Through the passage of the AND circuit 10-37, the output of the memory of the 25 flip-flops 1 to 25 of the command register free signal MNB , which is fed to the AND circuit 11-42, is also connected to the pulse delay IR-I , in which the M -Digits stored device 11-43 are controlled so that at the same time-. The output of the AND circuits 10-37 point t ₂ also a memory-free signal MNB ti for 55 is connected to the input of the control counter 10-35 is available. The creation of the memory free. At time t ₀ , the function table pulse MNB ti is also present in the tenth line of the time signal FT 613 at the control counter 10-35, as shown in the diagram, while the output signal is to clear the counter so that new information PPC 2 from the program counter can be stored in the twelfth line. So it is represented by that of the timing diagram. The memory free 60 AND circuit 10-61 transmits a signal as to which signal MNß ti is applied to two AND circuits of the control counter which the input AND circuits 10-37 of the command circulation control unit shown in FIG 10-35 open. Coupled in the tilting scarf. In detail, the memory lines 1 to 25 of the command register IR-I are stored. Signal MNB ti is sent to the input of the AND circuit. Circuit 65 circuits 10-37 coupled into the control counter 10-35 -11-22. Are stored at the AND circuit 11-21. The transfer of the M digits is also applied to the function table signal FT 613 from the 25 flip-flops of the command register, while the IR-I is still in the control counter 10-35 in FIG. HB at the AND circuit 11-22

147

148

shown during the ninth and tenth short periods of the central processing plant.

Like the fourth line of the timing diagram in FIG. 90 shows, the function table signal FT 614 is generated under the influence of the command 05 stored in the command register / Ä-1 and on the basis of the output signal PPCl of the program counter (FIG. 16) at time f ₇ . The function table signal FT 614, together with the clock signal t. connected to the final pulse AND circuit 11-34 (Fig. 11). This AND circuit 11-34 therefore generates an end pulse at time ^ which is coupled to the setting input of the flip-flop circuit 11-2 . The setting output of the trigger circuit 11-2 prepares the AND circuit 11-29, which then generates a signal N when the trigger circuit 11-3 is set at the same time as the trigger circuit 11-2 . The AND circuit 11-14 is also controlled by the setting output signal of the flip-flop 11-2, the output signal of which is set by the switch-off flip-flop 11-1 via the OR circuit 11-13.

As stated previously, the AND circuit 11-27 is opened by the function table signal FT 613 and the clock signal ti , so that the signal generated by this AND circuit during the command 05 at the time ti is sent to the reset input of the flip-flop circuit 11-3 ( Fig. 11) can be supplied via the OR circuit 11-28. By resetting the toggle circuit 11-3 , the command following command 05, which belongs to the first command group and is initially in command register IR-2 during execution of command 05, cannot be re-stored in command register IR-I. This is useful insofar as all further commands are to come from memory locations that are identified by the M digits of command 05. Since the flip-flop 11-3 is in the reset state, the signal N cannot be generated at the output of the AND circuit 11-29 (FIG. 11). The circuit AND 11-14 lying on the set input of flip-flop 11-1 shutdown will therefore not locked, so that the clock signal TS from the AND circuit 11-14 via the OR circuit 11-13 to the set input of flip-flop 11 -1 can be coupled. As shown in line 13 of the timing diagram in FIG. 90 and from line 16 of the timing diagram in Fig. HA, the switch-off flip-flop is always set after execution of the command 05. The resetting of this flip-flop, however, is carried out by the signal JV coupled via the OR circuit 11-11 , if the through the M-digits of the command 05 called up from the memory and stored in the command register IR-2 command is relocated for the purpose of execution in the command register IR-I.

All commands that are subsequently called up by the control counter 10-35 are identified by the M address of command 05. In other words: The further commands to be carried out are taken from the storage locations Af + 1, M + 2, M + 3 , etc.

The function table signal FT 600 coupled to the AND circuit 16-16 of the program counter (Fig. 16) switches the program counter in conjunction with the memory-free signal MNB from PPCl to PPC 2. If this process occurs (line 12 of the timing diagram) on, the output signal of the program counter remains ineffective, since during the storage of the command 05 in the flip-flops 51 to 60 of the command register IR-I, the AND circuits of the decryption device 12-17 C (Fig. 12) do not connect to the output line PPC2 of the program counter are connected and thus cannot receive any signals from the decryption devices 12-YtA and 12-17 .B.

In summary it can be stated that the M-digits of the command 05 are for direct control of the memory is used for the purpose of taking another command and also in the control counter 10-35 can be saved. The M-digits of this command cause the next Command in this new command chain is taken from memory and executed. The following Command is then taken from memory location M + 1 under the influence of the control counter.

To illustrate the individual operations, the table below shows the operations performed during the Function table signals generated by command 05 and their functions are listed.

Unconditional jump command

Function table signal

surgery

FT 614 Generates end pulse at time * ₇

FT 600 Prevents commands from being taken by the control counter 10-35 (Fig. 10). Switches the program counter to PPC2 when the memory-free signal MNB is present.

FT701 Causes the M address in the command register IR-I to trigger the address decryption device at time t ₇

FT 613 Clears the control counter 10-35 and causes the in the command register / i? -! contained M-address is stored in the tax counter. Resets the flip-flop 11-3 and the flip-flop 11-4 when the memory-free signal MNB is switched on

Unconditional jump command 14

Next, the unconditional jump or return instruction 14 will be described. The command 14 corresponds in principle to command 05, but also carries out additional operations. He has the following format:

14 NNNNN MMMMM.

With command 14 the five M-digits are stored in the control counter 10-35. The next instruction is therefore taken from the memory location identified by the five M digits. As long as command 14 is stored in command register IR-I , the control counter contains the five digits that originally caused command 14 to be removed from memory location M + 2. These five digits are stored in the memory location identified by the five iV digits of command 14.

149

150

is drawn. Instruction 14 therefore carries out the same operations as instruction 05 and stores over them In addition, the content of the control counter is entered in a specific memory location. Command 14 has the same Advantages like the unconditional jump instruction 05 and offers the programmer the possibility to again to return to a command chain or to navigate to a memory location that is determined by the content of the Control counter is identified, this content is in turn in a memory location that is identified by the N digits of command 14. This possibility is achieved in that the Content of the control counter to be written into the memory for part of an unconditional jump command 05 is made.

For a better understanding of command 14, reference is made to the description of the various block diagrams of the central processing system and the timing diagram of this command shown in FIG pointed out.

As line 1 of the timing diagram shows, command 14 is stored in command register IR-I at time t _e and remains there for a total of three short periods. Command 14 is carried out in three stages. For this purpose, three output signals PPCl, PPC 2 and PPC 3 are generated by the program counter. The program counter is also reset at the same time by the signal N, which caused the transfer of the command from the command register IR-2 to the command register IR-I , so that it can generate the signal PPCl. On the basis of the command 14 contained in the command register IR-I , the command decryption device 10-17 therefore generates the signal PL 141 under the influence of the signal PPCl of the program counter. The first stage of the command 14 thus begins. The one generated by the decryption device 10-17 Signal causes the command encryption device 10-18 to generate the function table signals FJ700, FT 600 and FT 617.

The function table signal FT 600 is shown in line 7 of the timing diagram and, in the manner already described elsewhere, a pulse time is generated after the command 14 has been stored in the command register IR-I . The function table signal FT 600 prevents, among other things, that the control counter activates the memory.

As line 4 shows, the function table signal FT 700 is available at time ^ and is coupled to the 25 AND circuits 10-15 which connect the output of the flip-flops 26 to 50 of the instruction register IR-I to the memory address decryption device. The N-Zit remote from the command contained in the command register IR-I can therefore control the memory via the address decryption device (FIG. 10).

Line 5 of the timing diagram shows that the signals of the iV address reach the memory at time * ₀ . The signal PL 141, which is fed to the command encryption device 10-18 in order to cause the latter to generate the above-mentioned function table signals, is also sent via the OR circuit 12 A-1% Al as a blocking signal to the AND circuit 12A-18BA (Fig. 12A) coupled.

A consideration of the AND circuit 12A-WBA shows that this circuit is blocked by the signal PL 141, so that the clock signal ti cannot appear as a read signal PYMR1 on the output line. This blocking is necessary insofar as the content of the control counter, through which the command 14 + 2 is to be taken, is to be written into the memory location identified by the iV digits of the command 14.

If the instruction 14 currently stored in the instruction register IR-I was retrieved from the memory at the time when the control counter contained the ίο address C, the instruction in the instruction register / i? ^ Would normally be taken from the storage location C + 1, and the current one As already mentioned in connection with FIG. 11, HA and HB, the address in the control counter would be C + 2 15-. However, if the command located in memory location C + 1 could not be re-stored in command register IR-2 because the memory was occupied, the control counter would contain address C + 1 while command 14 is being executed. As long as the command 14 is executed, it is useful if the relationship between the memory address from which the command 14 was taken and the address of the control counter that is to be written into the memory location identified by the iV digits of the command 14 , remains constant. In the present case it was determined that the value to be written into the memory by the control counter should be two greater than the address from which instruction 14 was taken. If the command registers IR-I and IR-2 contain different instructions at the time of execution of the command 14, the above-mentioned relationship remains constant. However, if no command can be transferred from the memory to the command register IR-2 (unsuccessful activation of address C + 1), the toggle circuit 11-3 is reset and thus indicates that there is no new command in the command register IR-2 . There is therefore only a difference of one between the address from which the command 14 was taken and the content of the control counter, while the difference two would have been retained if the memory had been activated successfully, since in this case the control counter to C + 2 would have been switched on and the toggle switch 11-3 would have been switched to its setting state. The reset output of the flip-flop circuit 11-3 is connected to the AND circuit 11-40 (Fig. 11), at which also the function table signal FT 617 (line 8 of the time-So diagram), the memory-free signal MNB and the Clock signal ti are present. If the memory has been successfully controlled by the M digits of the command 14 (not to be confused with unsuccessful control by the address C + 1), the memory-free signal MNB is generated at time t _6; the function table signal FT 617, which is also switched on, serves to further prepare the AND circuit 11-40. The final opening of this AND circuit and thus the generation of an output signal is effected by the reset output signal of the flip-flop circuit 11-3. If the toggle circuit 11-3 is in its reset state due to the fact that the command register IR-2 does not contain a new command, the AND circuit generates an output signal at time t _t (line 9 of the timing diagram) which is sent to the counter input of the control counter 10-35 is coupled via the OR circuit 11-38, whereby the in-

151

152

halt (C + 1) is increased by one and thus results in C + 2. The function table signal FT 613 therefore only causes the control counter 10-35 to advance when the toggle circuit 11-3 is in its reset state and thus indicates that there is no new command in the command register IR-2. If the control counter is incremented in this way, its content corresponds to address C + 2, in which C denotes the address from which command 14 was taken.

The memory-free signal MNB generated on the basis of the successful activation of the memory (iV digit of command 14) is - as already described - fed to the input AND circuit 16-16 of the program counter. This AND circuit is controlled by the function table signal FT 600, which is present during the first stage of the command 14. The AND circuit 16-16 therefore generates _{a signal at the time J 1, as} a result of which the program counter is switched from PPCl to PPC 2 , so that the second stage of the command 14 can begin at the time ^. Before describing the second stage, it should be mentioned that the function table signal FT 600 is generated by a one-pulse delay device (FIG. 12A). The signal is therefore present during the time segment t _{2 of} the second stage of the command 14, ie when the signal PPC 2 is also present. The function table signal FT 600 can therefore also block the AND circuit 11-22 of the command circulation control unit 10-22 (FIG. 11). This prevents the signal MNBt 2 generated by the delay device 11-43 at the time i ₂ on the basis of the memory-free signalMMB from passing through the AND circuit 11-22 and influencing the command circulation control unit.

By advancing the program counter to PPC 2, the decryption device 12-17 C energizes the line PL 142, causing the encryption device 10-18 (FIG. 12) to generate two new function table signals. These new function table signals FT 708 and FT 612 are generated during times f ₄ and t _s , respectively, and are shown in lines 12 and 13 of the timing diagram, respectively. The function table signal FT708 is coupled to the AND circuits 10-39 and 10-40 shown in the upper right corner in FIG. As shown in FIG. 10, 25 AND circuits 10-39 are provided, to which the 25 information units are also fed in parallel, which represent the five digits stored in the control counter 10-35. In addition, 35 AND circuits 10-40 are provided to which the seven digits, that is to say the 35 information units stored in the register 10-38, are fed. The seven digits in this register are not deleted; they represent the value 0500000. The 60 AND circuits (25 AND circuits 10-39 and 35 AND circuits 10-40) are also prepared by the clock signal * 4. These AND circuits are individually connected to the 60 lines of the main write line HSB-W . When the function table signal FT 708 is generated, the content of the control counter (C + 2) is therefore coupled to 25 of the 60 write lines HSB-W at time ^. In addition, at the same time when the function table signal FT 708 is switched on, the content of the register 10-38 is coupled to the remaining 35 write lines HSB-W via the AND circuits 10-40. A machine word consisting of twelve digits is fed to these write lines, with the seven most significant digits coming from register 10-38 and the five least significant digits from control counter 10-35. The word formed in this way has the following format: 0500000 CCCC 2, with the last five

ίο digits, CCCC 2, are two greater than the memory location from which command 14 was originally taken. This machine word has the form of the command 05 already described and is fed to the memory via the HSB line at time i ₅ (line 14 of the timing diagram). The machine word 05 is stored in the memory location identified by the five digits in the command 14. In this respect, command 14 corresponds to the previously described writing

ao command.

The function table signal FT 612, which is also generated in the second stage of the instruction 14, is on together with the clock signal t13, which was generated at the same time as the clock signal tS

* 5 the AND circuit 16-15 of the program counter (Fig. 16) is switched on. On the basis of these two signals, the AND circuit 16-15 generates the signal PPCS3, which is coupled via the OR circuit to the setting input of the flip-flop circuit 16-20 and via the OR circuit 16-11 to the reset input of the flip-flop circuit 16-18 . These flip-flops receive the PPCS 3 signal at time t ₅ and change their output signal at time i ₆ to create a new AND circuit (16-24)

in the matrix 16-26 to control. The AND circuit 16-24 generates the signal PPC 3 under the influence of the output signals of the flip-flops 16-18 to 16-21, so that the third and last stage of the command 14 at the time i ₆ (line 15 of the time-

diagram) can begin.

On the basis of the output signal PPC 3 of the program counter and the command 14 stored in the command register IR-I , the command decryption device 10-17 generates the signal PL 143.

Under the influence of this signal, the encryption device 10-18 generates the same function table signals that were generated during the first stage of the instruction 05. The third stage of command 14 corresponds to the first stage of command 05. During the third stage, the iV digits of command 14 are sent to the memory for the purpose of removing a new command and are also stored in the control counter 10-35 to create a new reference point to receive further commands from memory. The function table signals FT 600, FT 614, FT613 and FT701 generated by the output signal appearing on line PL 143 are shown in lines 7, 17, 19 and 20 of the timing diagram in FIG. 91.

Lines 23 to 26 show the effect of the function table signal FT 613 on the command circulation control unit, and line 27 shows the point in time at which the command identified by the M address of command 14 reaches the command register IR-I.

By means of the signal PL 143, the encryption device 10-18 not only generates the above-mentioned function table signals, but also blocks them

153

at the same time the input AND circuit 16-i6 of the program counter (Fig. 16). As is known, the function table signal FT 600 is generated in the third stage of the command 14, since the memory is controlled by the M digits of the command 14. As a result, the memory-free signal MNB is generated and the AND circuit 16-16 is opened at time t _t , so that it generates an output signal. If the AND circuit 16-16 were not blocked by the signal PL 143, the signal PPCS 2 would be coupled to the setting input of the toggle circuit 16-19 , which controls the matrix 16-26 of the program counter, causing the signal PPC 3 to be prematurely would be switched off.

In summary, it can be stated that command 14 must be carried out in three stages (PPCl, PPC 2 and PPC 3). In the first stage, the memory address M + 2, from which instruction 14 was taken, is compiled by re-setting the control counter and combining the five digits contained in the counter with the seven digits of the register 10-38 . In addition, the five JV digits of the instruction 14 located in the command register / jR-2 can control the memory during the first stage, so that the composed word with the format of an instruction 05 can be stored in the memory location identified by the five iV digits.

In the second stage, the word corresponding to the format of a command 05 is stored in the memory via the HSB-W write line.

As is well known, the third stage of command 14 corresponds essentially to the first stage of command 05, d. that is, at this last stage, the M-digits of instruction 14 can save memory for removal of a trigger a new command. In addition, these M-digits are transported to the tax counter, so that new commands can be controlled from here.

To illustrate the individual operations, the table below shows the operations performed during the Command 14 generated function table signals and their functions are listed.

Unconditional jump command 14
Return

Function tables
signal

surgery

The program counter is in position 1

FT700

FT 600

FT617

Causes the iV address in the command register IR-I to trigger the decryption device at time t ₇ . PL 141 blocks the memory read signal PFMR 1 at time t ₇

Prevents the control counter 10-35 from polling a command

If necessary, switches the control counter to C + 2 after coupling the memory-free signal MNB, ie if there is no new command in the command register IR-2

40

45 154

Function tables
signals

surgery

The program counter is in position 2

FT708

FT612

Causes the coupling of the word 05 00000 CCCC 2 to the write lines at time t _v , the digit value 05 00000 being connected to the seven positions MSD and the content of the control counter to the five positions LSD of the write lines

Switches the program counter at time i ₅ to PPC 3

The program counter is in position 3

FT 600

FT701

FT613

FT 614

Prevents a command from being taken. PL 143 prevents the program counter from advancing when the MNB signal is switched on, and FT 600 prevents the control counter from activating the address decryption device

Forwards the M address located in the command register IR-I via the AND circuits 10-14 to the address decryption device at time t ₇

Clears the control counter and saves the M address contained in the command register IR-I at the time t ₀ via the AND circuits 10-37 in the control counter. Resets the flip-flop 11-3 at time ^ and sets the flip-flop 11-4 when the signal MiVS i2 is switched on

Generates end pulse

Shift command 07

Next, the move command 07 will be discussed. This command causes the content

of the register .RP-I by one of the value of the ninth and the number of places corresponding to the tenth digit of the command is shifted to the right. the The tenth digit of the command 07 represents the most significant and the ninth digit represents the least significant digit. B. the tenth digit a "1" and the If the ninth digit represents a "0", the command 07 would indicate that the contents of the register jRP-1 is shifted ten places to the right. The whole word including the prefix

characters shifted so that the content of the NN least significant digit positions becomes the content of the NN most significant digit positions, where NN can be between 0 and 29 and is of course represented by the ninth and tenth digits of the command word 07. Before command 07 is now described with the aid of the timing diagrams, it should be pointed out that the command only requires one stage to be executed, that is, the pro-

509 538/373

155

156

The gram counter always generates the same output signal, namely PPCl. However, the number of short periods required to execute the command changes with the number of shifting operations, which is determined by the two digits in the iV (ninth and tenth digits) of the command. Command 07 is extremely useful and is widely used in electronic computing systems.

The timing of command 07 is shown in the timing diagrams in FIGS. 89A and 89B. Line 1 of the timing diagram in Fig. 89A shows that instruction 07 is in instruction register IR-I , which has the following format:

07 NNXXX XXXXX.

From the format it can be seen that the eight least significant digits are ΑΓ digits that are not to are deciphered. The ninth and tenth digits of the command indicate how often the shift has to be while the two / digits contain the value 07 to indicate that it is a Move order. As already described in connection with Figs. 13 and 13A, are the countdown AND alarms only for a value stored in the iViV digits is provided that is not greater than 29.

In the description of the present computer system, however, only the shifts between 0 and 5 need to be taken into account, since the shift command for the number 12 corresponds to the shift command for the number 0 and the shift command for the number 13 corresponds to the shift command for the number 1, etc. Displacements longer than 11 are, however, advantageous for machines that work according to the so-called doubling system. However, this system is not described in detail here. The description of command 07 is therefore generally limited to those cases in which the number stored in the ninth and tenth digits of the command does not exceed the value 11. However, examples are also given in which the value stored in the iNW digits is greater than 11. As line 1 of the timing diagram in Fig. 89A shows, instruction 07 can be stored in instruction register IR-I for a period of five short periods. As already mentioned above, the number of short periods during which the command 07 is in the command register IR-I depends on the number of shifts determined by the MV digits. If the number stored in the MV digits corresponds to a value between 0 and 2 (i.e. less than 3), a short period is required to execute command 07. If the value stored in the iVW digits is between 3 and 9 inclusive, two short periods are required for the execution of the command. If the value stored in the AW digits is between 10 and 17 inclusive, three short periods are required. If the value of the AW digits is between 18 and 25 inclusive, four short periods are required, and if the value of the MV digits is over 26, five short periods are required. Command 07 is described using four examples. In the first and second examples, it is assumed that the NiV digits correspond to the value 0 and 2, respectively. In the third example it is assumed that the NN digits correspond to the value 7, and in the fourth example it is assumed that the 2ViV digits correspond to the value 11. From these details it can be seen that a short period is required for the first and second example, two short periods for the third example and three short periods for the fourth example in order to execute command 07.

It is now assumed that instruction 07 is in instruction register IR-I (line 1 of the timing diagram in FIG. 89A). As is well known, the command 07 when the signal N is generated from the command register / i? -! relocated to the command register IR-I. This signal simultaneously switches the program counter to the PPCl position. The output signal PPCl generated by the program counter in this position is shown in the second line of the timing diagram. After completing this command, the program counter is again indicated by a

ao further signal iV switched to the PPCl position. The function table signals FT 601 and FT 602 are shown in lines 3 and 4 of the timing diagram. These function table signals are present as soon as command 07 is entered in command register IR-I.

a5 stores is. The two signals then remain that way switched on for a long time until command 07 is executed.

The function table signal FT 601 is coupled to the AND circuit 15-20, which connects the output signal of the delay device 15-16 to the delay device 15-21, whereby the clock signals pt 15 and pi0 to pt 6 are generated. These clock pulses are at the top of the timing diagram in FIG. 89 and labeled pt. As already described in conjunction with the clock (Fig. 15), the clock signal corresponds to pi 15 the clock pulse 1 7. Furthermore it is apparent from Fig. 15 that the delay means 15-21 pi by coupling an output 14 of the delay means 15 16 generates the clock pulses pt 15 to pt 16 as long as the function table signal FT 601 is switched on.
The function table signal FT 602 is applied to the AND circuit 14C-29, the output of which is connected to the hold and shift toggle circuit 14C-27. This hold and shift toggle circuit 14 C-27 is known to generate the shift signal PRAH as soon as it receives a signal from the AND circuit 14 C-27. The clock signal pi 15 from the clock generator (FIG. 15) is also applied to the AND circuit 14 C-29 as a pass signal. An input signal is coupled to the shift side of the hold and shift flip-flop 14 C-27 at time pz _{15 , whereupon this flip-flop generates the shift signal PRAH at time pi 0} , that is, this signal becomes a pulse time after the clock signal pi 15 is switched on generated. The output of the hold and shift flip-flop 14 C-27 is shown on the fifth line of the timing chart in Fig. 89A. The hold and shift toggle circuit 14C-27 generates this shift signal PRAH until it is switched to its reset state by an output signal from the OR circuit 14C-28 (FIG. 14C). The number of shifts of the digits in the register i? Pl corresponds to the number of im-

157

158

pulse or cycle times t during which the signal PRAH is present.

The sixth and seventh lines of the timing diagram in FIG. 89A show the generation of the function table signals FT 501 and FT 615, respectively. The function table signals FT 501 and FT 615 are generated by the command encryption device 10-18, to be precise one pulse time after the relevant command (in this case the command 07) has been stored in the command register / i? - !. These two function table signals remain switched on until one pulse time after the same command has been saved from the command register IR-I . The function table signal FT 501 is applied to the wraparound AND circuits of the register RP-I (14,4-28, Fig. 14C; 10-51, Fig. 10) so that the contents of the register from the least significant digit position to the most significant Digit position of this register can be traced back. As is known, the register RP-I (FIG. 14) has five wraparound AND circuits each connected to one of the shift registers of the register or buffer memory RP-I .

The function table signal FT 615 is fed to the AND circuits 14C-30 and 14C-31 which are connected to the hold input of the hold and shift toggle circuit 14C-27 via the OR circuit 14C-28. This function table signal FT 615 blocks the AND circuits 14 C-30 and 14C-31 so that the hold and shift toggle circuit 14C-27 cannot be switched to their hold state during command 07 via these two AND circuits . As will be described in connection with the add and subtract commands (commands 10 and 11), the AND circuits 14C-30 and 14C-31 have the task of switching the flip-flop 14C-27 to the reset state during the execution of these commands.

The function table signal FT 615 is also fed to the selected inputs of the flip-flops 41 to 50 of the command register IR-I and the decryption matrix 13-31 (or the countdown AND circuits) assigned to the outputs of these flip-flops. As can be seen from the representation of the flip-flops 41 to 50 of the instruction register IR-I and the decryption matrix 13-31 (FIG. 13A), the shift signal PRAH generated under the influence of the function table signal FT 602 is applied to the selected inputs of the flip-flops and all AND circuits the matrix 13-31 with the exception of the AND circuit 13-33. A consideration of the decryption matrix 13-31 also shows that the function table signal FT 615 is also fed to all AND circuits of the matrix 10-31 with the exception of the AND circuit 13-33. The shift signal PRAH and the function table signal FT 615 are both required to control the shift / decryption matrix and the flip-flops 41 to 50. As the timing diagram in FIG. 89A shows, the shift signal PRAH generated by the flip-flop circuit 14 C-27 is available at time t _Q or pt ₀ . The function table signal FT 615 is also available during the same time. The AND circuits of the decryption matrix 13-31 with the exception of the AND circuit 13-33 and the AND circuits that control the inputs of the flip-flops 41 to 50 can therefore receive an input signal at the time pt _{0 at the earliest.} The output signals of these flip-flops 41 to 50 of the command register IR-I, which indicate the reduced count, appear at time t _{v. In} other words, the pulses by which the flip-flops 41 to 50 of the xo command register IR-I cause the reduced count to be displayed are switched on a pulse time earlier than the output signals generated by these flip-flops.

Line 8 of the timing diagram in FIG. 89A shows the point in time at which the end pulse EP is generated for the command 07, and line 9 shows when the signal N is generated under the influence of the end pulse. As can be seen from line 8 of the timing diagram, five possible end pulses are provided for command 07, the generation of these pulses depending on the number of shifts that are to be carried out according to the ninth and tenth digits of the command. If the number identified by the ninth and tenth digits of the command a5 is less than 3, the end pulse is generated during the first short period in order to switch the flip-flop 11-2 into its setting state. The signal N generated by the AND circuit 11-29 under the influence of the output signal of the flip-flop 11-2 causes the instruction to be executed within a short period by causing a new instruction to be transferred from the instruction register IR-2 to the instruction register IR-I . If the iVTV digits of the command (ninth and tenth digits) correspond to the value 3 or if their value is greater than 3 but less than 10, the command is terminated during the second short period. If the iVTV digits of the command are equal to 10 or greater than 10 but less than 18, the command of the third short period is terminated. If the AW digits of the command are equal to 18 or greater than 18 but less than 26, the command is terminated in the fourth short period, and if the NN digits are far greater than 26 but less than 29, the command is 07 ended in the fifth short period, calculated from the time of its storage in the command register IR-I. It can be seen from Fig. 11 that the AND circuit 11-31, the output of which the final pulse toggle circuit 11-2 switches to its set state, receives the function table signal FT 615 from the command encryption device 10-18. In addition, the clock signal i7 of the clock generator (FIG. 15) and the signal PSR 3 X from the AND circuit 13-28 (FIG. 13A) are also present at the input of this AND circuit. The signal PSR 3 X indicates that the value stored in the flip-flops 41 to 50 of the command register IR-I is less than three. If this state occurs at the time pt ₇ during the execution of the command 07, the AND circuit 11-31 generates an end pulse by which the flip-flop circuit 11-2 is switched to its setting state. It has already been mentioned in connection with FIG. 11 that the setting of the flip-flop 11-2 generates the signal N so that the next instruction can be executed.

Line 10 of the timing diagram in Fig. 89A shows when the relocation decoder

159 160

(ie the flip-flops 41 to 50 of the command under the influence of the signal PSRO, which register IR-T) is switched on. As already indicates that the ninth digit is equal to 0, as was mentioned earlier, under the influence of the signal PSR 3 X, which signals 41 to 50 of the command register IR-I indicates that the ninth and Shift counters that are smaller than the tenth MV digits (shift counts are 5 or greater than 3, the AND circuit 13-30 coding device) does not advance the signal PSR OO. This signal indicates, are tet, as to the shift flip-flop that in the flip-flops 41 to 50 of the loading 14C-27 WOR switched to its set state is entden fail register IR-I number stored a "0" and hence the time t ₀ the mismatch. The signal PSR 00 is generated under the influence of the exercise signal PRAH . During each cycle of the output signal of the flip-flops 41 to 50 pulse time, in which the shift flip-flop of the instruction register IR-I , which is switched to its setting state via the 14C-27 , AND circuit 13-28 is the generation of the signal that is, the value stored in the flip-flops 41 to 50 of the PSR3X and via the AND circuit 13-33 causes the command register IR-I to generate the signal PSRO by one.
reduced. As is well known, the flip-flop 15 Both signals are coupled to the inputs of the ANDs 41 to 50 of the command register IR-I, a pulse circuit 11-30 which times the signal PSR O in order to generate an output signal. With and- generated if the following words are also present at your input: The output signal, function table signal FT 615 generated by you, is present. The signal is compared to the PSR 00 coupled to its input and is delayed by one pulse time to the AND circuit 14 C-29 as an input signal. The 30 blocking signal is coupled and also connected via the OR circuit 14C-28 (FIG. 14C) appearing on the lines PV 41 to PV 50 to the hold output signals of the flip-flops 41 to 50 of the input of the flip-flop 14C-27. Instruction register IR-I, which is transmitted via the matrix 13-31 and Under the circumstances mentioned, ie if the input AND circuit MV digits of instruction 07 shown in FIG - 25 signal PSR 00 generated at time ^ or pt _ls. are fed back, the counter will only switch on like a consideration of the hold and shift pulse time later. In other words, bungs-Kippschaltungl4C-27 shows, by which the the shift counter performing tilt signal PSR is 00 C-29 blocked the AND circuit 14 are circuits in each pulse time t WEI once so that the retaining and displacement Toggle switch switched. 30 14C-27 not in their displacement or adjustment

The sequence of command 07 can now be switched to state. This will be

Hand of four examples in connection with the achieved by that as a result of the lock signal PSROO

A timing chart described in Fig. 89B. In these the clock signal pi 15 the AND circuit 14C-29

Examples assume that the cannot go through. The Shift Tilt

MV digits of command 07 have the value 0, 2, 7 or 11 35 circuit 14C-27 is therefore not

to have. mode switched and can therefore also

First of all, it is assumed that the displacement signal PRAH is not generated in the nine. th and tenth digits of the in the command register IR-I It follows that the hold and shift stored command has the value 0. In this exercise flip-flop 14C-27 no shift case, so no shifts are required, 40 signal PRAH is generated if the content of the ninth and shift flip-flops 14C-27 and tenth digits of the command 07 are initially 0. Instruction register IR-I may therefore not set consisting of the flip-flops 41 to 50 of the command, otherwise a shift signal register IR PRAH ER-I existing displacement counter would be generated. Lines 11, 12 and 13 of the time diagram therefore only produce signals which show the value 0 grams in FIG. 89B indicate the generation of the Si 45. The signal P & R3AT is at time t ₇ signals PSAO, PSROO and PSR3X. These signals are available. The final pulse AND circuit is generated when the ninth and tenth digits 11-31, which - as already described above, with the exception of command 07 initially represented the value 0 - the signal PSR3X, the clock signal i7 and len. The signal PSRO is controlled by the AND circuit receives the function table signal FT 615 , generates 13-33 of the matrix 13-31 generated as soon as there is an end pulse in the command 50, which is a command 07 at the setting input of the error register IR-I . That is, flip-flop 11-2 (Fig. 11) is coupled. this signal is generated at time ί _β or i ₁₄ . Assuming that there is a further command in the command register The input signals of this AND circuit 13-33 IR-2 , so that the toggle indicators when opened indicate that the digit in the nine circuit 11-3 has been switched to its setting state stored value is equal to 0. The signal 55 becomes, the clock signal tS runs through the AND switch. PSRO is connected to the AND circuit 13-30 together 11-29 and causes the generation of the Sims with the function table signal FT 615. With this signal N a new one is coupled. The signal PSR3X is stored by the AND error in the instruction register IR-I , where circuit 13-20 generates. As already described before, the execution of command 07 is terminated. The signal PSR 3 X indicates that the 60 In the second example of the command 07, the value of one in the ninth and tenth digits of the assumed that the JViV digits, the number stored in the ninth command register IR-I less and tenth digit positions of the command register than 3. The signal PSR 3 X is also included in the command located IR-I , generated less than the beginning of the cycle time t _e or pt _u , since the ANDs are 3 and in particular equal to 2. The timing circuit 13-28, which generates this signal, is controlled only by signals from the flip-flop circuit in the timing diagram in FIG. 89 B. The values 41 to 50 of the command register IR-I generated value 02 will be at the same time as the storage. of the command in the command register IR-I in the toggle

161 162

circuits 41 to 50 of this command register. In the third example, it is assumed that the stores. The signal PSR X 3 is thus produced, so-ninth and tenth digits of the instruction 07 soon the command 07-I IR einge- storage-I IR is stores the value 7 at its in the command register into the command register. Corresponds to the content of the iViV digits. The shifting of the digits as well as that of the command 07 to the value 2, the signal 5 is generated downshifting the counter consisting of the flip-flops 41 PSR3X at the time r ₆ or pt _u (line 14) to 50 of the command register IR-I . As in the previous example, after the generation of the shift from the AND circuits 11-31 and 11-29, a signal PRAH is generated at the time i ₀ by the stop end pulse or a signal N. and shift toggle circuit 14 C-27. The value stored for line 10 of the timing diagram in FIG. 89A shows that at time t _{5 of} the first short period in the toggle, the value stored only at the time switches 41-50 corresponds to point i ₀ or pt _a , ie two a "2" so that the signal PSR3X is generated. Pulse times after the original storage (line 18 of the timing diagram in Fig. 89B). The Sides command 07 in the command register IR-I. If the signal PSR 3 X remains switched on for all values in the command register IR-I from the flip-flops 41 to 50, which are less than 3 shift counters the first time switched on. The signal is therefore also available at time i ₇ , the value in it of 2 in 1 becomes available around the second short period. The final changes. This process occurs at time t _t or the pulse AND circuit 11-31 (FIG. 11) generates da-Pi ₁ instead. If the value ao end pulse contained in the flip-flops 41 her at time t _{7 of} the second short period corresponds to one to 50 of the command register IR-I , which corresponds to the setting input of the flip-flop "1", ie in particular the value entered in the circuits 11-2 via the OR Circuit 11-36 flip-flops 41 to 45 of the command register IR-I are fed, so that the AND circuit generates the AND circuit at the output of the AND-stored least significant digit of a "1", so circuit 11-24 can generate a signal N 13-35 in the Decisions- Through this signal, the output signal PSV16 is generated at the beginning of the third lungsmatrix 13-31. This short period of restoring a new command signal PSV 16 is initiated together with the signal PSR 3 X from the command register IR-I into the command register IR-Z by the AND circuit 13-28 at the input of.

AND circuit 13-29 coupled. This AND- Since the shift counter, which the toggle circuit 13-29 generates thereupon the signal PSFIl, gen 41 to 50 of the command register IR-I , which indicates that the in the ninth and tenth 30 times t _s the counter reading 2 reached, the result is digit positions of the command register IR-I, so that the signal PSFIl, which corresponds to a "1" number, corresponds to a "1". Since the two correspond to the one pulse time later, that is to say input signals point _{6 present} at the time AND circuit 13-29, are generated. The signal PSFIl will indicate that firstly the number less than 3 and secondly 35 pelt stored in the two digit positions the AND circuit 14 C-29 as a blocking signal, and at the same time the least significant digit of these two digits 14C- 28 (FIG. 14C) at the hold input is equal to or greater than 1, the signal PSFIl thus indicates that circuit 14 C-27 is switched on. The hold and Vernur another shift can be carried out shift toggle circuit 14 C-27 thus receives at must (ie that the time t _e in the toggle circuits 41 to 50 corresponds to a signal at its hold input and the digits stored correspond to a "1") . The Si 40 thus stops the generation of the shift signal signal PSFIl is connected as a blocking signal to the AND switch PRAH at the time i ₇ (line 5 of the journal 14C-29 and coupled at the same time via the diagram in FIG. 89A). At time t ₇ or pt _7, OR circuit 14 C-28 at the hold input of the second short period corresponds to that in the toggle-hold and shift toggle circuit 14 C-27 connections 41 to 50 of the command register IR- I switched. As in the case of the other flip-flops 45, the value stored is a "0", so that the output signal of the circuit 13-33 is also the signal PSR 0 generated by the AND of these devices, the hold and shift flip-flop 14 C-27 on the AND circuit 13-30 is coupled, compared to its input signal by one pulse time. At the same time, this AND circuit 13-30 is delayed. The hold signal is therefore only a pulse signal and the function table signal FT 615 as well as the time after the coupling of the signal PSFI1 to the signal PSR 3 X. The AND circuit 13-30 holding and shifting toggle circuit 14 C-27 therefore generates the signal PSR 00, which generates the AND. The shifting process can therefore only take place one circuit 14 C-29 as a blocking signal and via the pulse time after the signal PSFIl OR circuit 14 C-28 has been switched on to the hold input of the. A pulse time after the coupling of the flip-flop 14 C-27 is coupled. The signal PSFH becomes the signals PSR 00 (line 16-55 PSR 00, however, has the same effect as the signal of the timing diagram in FIG. 89B) and PSR 0 (line 17 PSVU and changes the state of the toggle switch of the timing diagram in FIG. 89B) the ANDing 14C-27 does not. In the fourth example, connected circuits 13-33 or 13-30 are generated, since the assumption that the ninth and tenth digits of the flip-flops 41 to 50 of the command register IR-I command 07 are now the same at the time this value is stored 0 is. The command signal 60 in the command register IR-I with the value 11 PSR 0 is sent to the OR circuit 14 C-28. The shifting of the digits in the register couples and at the same time as a blocking signal to the AND -RP-I as well as the switching back of the counter, which is connected from circuit 14 C-29, which signals the input to the flip-flops 41 to 50 of the command register for the hold and Shift-Kippschal- IR-I exists, starts again after the generation tang 14 C-27 provides. The signal PSR 00 has the same effect as the signal PSFH for every shift signal PRAH at time i _0, and the hold and shift toggle switch changes the state of the toggle switch 14C-27 14C-27 (line 5 of the timing diagram in FIG. 89A ). not. The one at time t _{± of} the second short period in the

163

164

The value stored in flip-flops 41 to 50 therefore corresponds to a "2", whereupon the signal PSR 3 X is generated at the point in time shown in line 18 of the timing diagram in FIG. 89B. The signal PSR 3 X remains switched on for all values stored in the command register IR-I that are less than 3. The signal is therefore also available at time I _{1 of} the second short period. The end pulse AND circuit 11-31 (FIG. 11) therefore generates an end pulse at time t _{7 of} the third short period, which is coupled to the setting input of the flip-flop circuit 11-2 via the OR circuit 11-36. In this way, the signal N can be generated at the output of the AND circuit 11-24 , whereby at the beginning of the fourth short period a new command can be transferred from the command register IR-2 to the command register IR-I . Since the shift counter consisting of flip-flops 41 to 50 of command register IR-I reaches counter reading 2 at time t _t , signal PSVU, which corresponds to a "1", is generated one pulse time later, ie at time t _2. The signal PSFIl is coupled as a blocking signal to the AND circuit 14C-29 and at the same time via the OR circuit 14C-28 to the hold input of the flip-flop circuit 14C-27 & . The holding and displacement flop 14C-27 thus obtained at the time f _2, an input signal and thus, the generation of the shift signal PRAH at the time t _a a (line 5 of the timing diagram in F i g. 89 A). The value stored in the flip-flops 41 to 50 of the command register IR-I at the time t _s or pt _{n of} the second short period thus corresponds to a "0", so that the AND circuit 11-33 generates the signal PSRO which is sent to the AND Circuit 13-30 is turned on. The function table signal FT 615 and the signal PSR3X are also present at this AND circuit 13-30. Under the influence of these signals, the AND circuit 13-30 generates the signal PSROQ, which is coupled as a blocking signal to the AND circuit 14C-29 and at the same time via the OR circuit 14C-28 to the hold input of the flip-flop circuit 14C-27 will. However, the signal PSROO has the same effect as the signal PSKIl and does not change the state of the flip-flop 14C-27.

In summary, the following can be stated: The command 07 only requires a group of function table signals of the command encryption device 10-18 (Fig. 10) · The program counter is not incremented with this command, and the length of the command depends on the number of shifts , identified by the number stored in the ninth and tenth digits of the command. The shift takes place clockwise so that the storage elements of the register RP-I which contain the least significant digit are connected to the inputs of the storage elements which contain the most significant digit of the operand in the register RP-I. If the ninth and tenth digits of command 07 represent the value 0, signals (e.g. PSROO) are generated which prevent the shifting process and at the same time cause a new command to be stored in the command register IR-I after a short period. On the other hand, if the ninth and tenth digits of command 07 correspond to a value other than "0", the shift toggle circuit 14C-27 is caused to generate the shift signal PRAH , which remains on until the required number of shifts has been carried out. The end pulses for the command 07 are generated by the AND circuit 11-31 at the time t ₇ under the influence of the signal PSR3X , which is always present when the value of the ninth and tenth digits of the command becomes 3 or less. If only a single shift is still to be carried out, the shift counter consisting of the flip-flops 41 to 50 of the command register IR-I has the value 1, whereupon the signal PSV 16 (FIG. 13A) is generated, which in connection with the signal PSR 3 Y causes the generation of the signal PSFIl at the output of the AND circuit 13-29 (FIG. 13). This signal PSFIl is coupled to the hold input of the hold and shift flip-flop circuit 14C-27, whereby this starts the generation of the shift signal PRAH.

ao represents. Since the flip-flop 14 C-27 has a delay of a pulse length, the displacement signal PRAH after connection of the signal PSFIl is switched off only after the execution of the last shift.

Data transfer command 07
Orbital displacement; simple accuracy

Function table signal

FT601

FT602

FT501

FT615

surgery

Clock cycle pt begins at time pt _is

Sets shift and flush toggle circuit 14C-27 at time pt ₁₅ if shift counter (toggle circuits 41 to 50 of instruction register IR-I) is not initially "0"

Brings the contents of the jRP-1 register in circulation again

Advances the shift counter consisting of flip-flops 41 to 50 of the command register IR-I when shifting

Resets the shift and clearing toggle switch 14C-17 of the register RP-I when the shift counter shows "1". This ends the shift when the display shows »0«

Generates end pulse at time t ₇ when shift counter, consisting of flip-flops 41 to 50 of register ΛΡ-1, shows less than 3.

Next, the add and subtract instructions 10 and 11 will be described. These orders too consist of a twelve-digit word g with the following format:

10 NNNNN XXXXX (add command),
11 NNNNNXXXXX (subtract command).

165

166

The additions and subtractions caused by instructions 10 and 11 represent algebraic operations In these operations, the signs of the operands must therefore be used when controlling the Calculation processes are also taken into account. Should, for example, two Operands with different signs are combined with one another, so represents the arithmetic operation represents a subtraction. If, on the other hand, the two operands to be combined have the same sign, so an addition takes place. The same rules apply to a subtract command, however only in reverse.

In principle, the add and subtract instructions are very similar to one another and are therefore described together. With both instructions it is assumed that one of the operands has already been stored in the register RP-I by an instruction 15. The other operand is controlled by the iV digits of command 10 or 11. The first two stages of the add or subtract instruction correspond essentially to the already described read instruction 12, since the JV digits of instruction 10 or 11 during the first stage of the instruction control the memory for the purpose of removing an operand and then this operand in the second stage is stored in the register RP-2.

In the third stage of the add or subtract instruction, the operands stored in registers RP-I and RP-2 are passed through the adder, and the sum or difference determined in the adder is then stored back into register RP-I as the initial result. If an arithmetic subtraction is to be carried out by the adder, the complement flip-flop circuit CP shown in FIG. 27 must be switched to its setting state so that the complement can be formed for the subtrahend and added to the minuend. A consideration of the third stage of the add or subtract instruction shows that, in the case of an arithmetic subtraction, the operand to which the complement is to be formed is always in register RP-2 . The table below shows the conditions under which a complement formation must be carried out for commands 10 and 11.

Sign register RP-I

Sign register RP-2

complement

Add command 10

No (CF)
No (CF)
Yes (CP)
Yes (CP)

Subtract command 11

Yes (CP)
Yes (CP)
No (CF)
No (CF)

At the end of the third stage of the add or subtract instruction it must be determined whether the initial result in the register RP-I is in the correct form or as a complement. If there is no complement formation in the add or subtract instruction, the initial result in register RP-I is always in the correct form. If, on the other hand, a complement has to be formed, the initial result in register RP-I may or may not be in the correct form. Precautions must therefore be taken to determine whether complex formation must take place. If such a complement formation is necessary, it must also be determined whether the complement does not have to be formed again for the initial result. As already mentioned, the complement is always formed for the value that is in register RP-2 . If the operand in register RP-2 is greater than the operand in register RP-I , the result is stored in register RP-I as a complement to 10 if a complement is formed. If, for example, the operand -70000000000 is in register RP-I and the operand +30000000000 in register RP-2 is to be added to this operand, the formation of the complement to the value in register RP-2 and the Adding this complement to the operand in register RP-I gives the correct result.

(D
(2)

RP-I RP-2

.... -70000000000 .... +30000000000 70000000000 70000000000

Final carry .. 140000000000 Add tens complement of the
Register RP-2 to register RP-I.

From the example above it can be seen that if the result is correct, there is a carry. As mentioned earlier, this carry could indicate that the absolute value in register JRP-1 is greater than or equal to that in register RP-2

(1) RP-I +300,000,000,000

RP-2 -70000000000

(2) 30000000000 30000000000 is absolute value (RP-I greater than RP-2 or equal to RP-2).

If, on the other hand, the two operands in registers RP-I and RP-2 are interchanged in the same arithmetic operation, the result is in the form of the tens's complement.

Add the tens complement of the
Register RP-2 to register RP-I.

60000000000 result is available as a tens complement.

167

From this example it can be seen that the result is a complement and no carry is generated if the operand in register RP-2 is greater than that in register RP-I during the addition. The absence of a final carry signal enables the fourth stage of the add or subtract instruction to be carried out and at the same time indicates that the absolute value in register RP-2 is greater than the absolute value in register RP-I (RP-2 greater than jRP- 1).

If the fourth stage is required, the complement to the initial result in the register RP-I is formed by simply coupling the content of the register RP-I to the same inputs of the adder to which the content of the register RP-2 is normally connected At the same time, zeros are coupled to the inputs of the adder, into which the content of the register RP-I is normally fed.

In the case of an add or subtract instruction, the sign of the result can always be determined as follows: firstly by determining whether a complement is required, secondly by comparing the signs of the operands in registers RP-I and RP-2 and thirdly by comparing them the relative values of the operands to be processed. If the operands have the same sign, no complement is formed in the case of the add instruction 10, and the result is given the sign of the operand stored in register RP-I. The same applies to the subtract instruction 11 if the signs of the operands are different. Both cases are listed in the table below.

No complement formation

Sign register .RP-I

Sign register RP-2

sign

Add command 10

Subtract command 11

+ (RP-I) ~ (RP-I)

+ (RP-I) - (RP-I)

If, on the other hand, the operands have unequal signs when the instruction is executed, a complement is formed and the result is given the sign of the larger operand, which is either in register RP-I or in register RP-2 . If the operands have the same sign and command 11 is executed, a complement must also be formed. In this case, the result is given the sign of the operand in register RP-I , if it is greater. If, on the other hand, the operand in register RP-2 is larger, the result is given the opposite sign of this operand. These sign rules correspond to the laws of algebraic addition and subtraction. The table below shows the various options for creating signs.

168

Complement formation

Result sign,
if RP-I
greater than RP-2

Result sign,
if RP-I
smaller than RP-2

Add command 10

RP-I - RP-2 +
ίο ÄP-1 + RP-2 -

Subtract command 11

RP-I - .RP-2 AP-1 + RP-2 +

The sequence of the individual operations of the add and subtract commands will now be discussed in connection with the timing chart shown in Fig. 92. As mentioned earlier, these will

ao commands carried out in the following three or four stages: firstly, selection of the operands, secondly, relocation of the operands, thirdly, addition of the Operands and fourthly, repeated formation of the complement (but only if necessary).

As the line of the timing diagram in FIG. 92 shows, instruction 10 or 11 is located at time r _e mi instruction register IR-I. As already mentioned, the program counter (FIG. 16) generates the signal PPCl at the same time. Due to the add command in the command register IR-I and under the influence of the signal PPCl, the output line PL101 of the command decryption device 10-17 is energized (line 3), causing the command encryption device 10-18 to generate the function table signals FT600 and FT700 will. If there is a subtract command in the command register IR-I , the line PL 111 is energized instead of the line PL 101, whereby the encryption device 10-18 is also caused to generate the function table signals FT 600 and FT 700 (lines 4 and 5 of the timing diagram in Fig .92). The first parts of the add and subtract commands are identical to the command 12 already described and are therefore no longer described in detail. It should only be mentioned that the address NNNNN of the memory identified by the command 10 or 11 is activated in this stage. By that generated on the basis of a successful activation of the memory at time t _i

Memory-free signal (line 6 of the timing diagram) the program counter (Fig. 16) is incremented, whereby the signal PPC 2 is generated. The command encryption device 12-18 (FIG. 12) is controlled by this signal, so that the second stage of the command 10 or 12 can _{now begin at time i 2.}

In the second stage of the add or subtract command, either the output line PL 102 or PL 112 of the command decryption device 12-17 is energized (eighth line of the timing diagram), depending on whether the command 10 or 11 is in the register IR-I . The energization of one of these lines causes the command encryption device 10-18 to generate the function table signals FT 706 and FT 612. These signals are shown in lines 9 and 10 of the timing diagram. The function table signal FT 706 is sent as an inhibit signal to the AND circuit 14C-40 (Fig. 14C)

169

170

coupled to the hold output of shift and hold toggle 14C-32 of register RP-2 . In this way, the function table signal FT 706 causes the register RP-2 to be cleared before the operand identified by the address NNNNN of the add or subtract instruction is stored.

The function table signal FT 612 is coupled to the AND circuit 16-15 located at the input of the program counter, specifically together with the clock signal pi 13, which is generated synchronously with the clock signal tS. As is known, the program counter is switched from PPC 2 to PPC 3 by the output signal of this AND circuit (line 12 of the timing diagram), so that the third stage of instruction 10 or 11 can begin _{at time i e.}

During the third stage of the add or subtract command, the decryption device 10-17 is caused to generate an output signal on the line PL 103 on the basis of the signal PPC 3 and on the basis of the other signals generated by the add command in the command register IR-I (line 13 of the timing diagram). On the other hand, if the subtract command is in command register IR-I , then line PL 113 is energized instead of line PL 103. By coupling a signal to the line PL 103 or PL 113, the command encryption device 10-18 is caused to generate the following function table signals:

Function table signal FT 707 (line 11),
Function table signal FT 500 (line 14),
Function table signal FT 504 (line 14),
Function table signal FT 510 (line 14),
Function table signal FT 601 (line 13),
Function table signal FT 602 (line 13),
Function table signal FT 610 (line 13).

The function table signal FT 707 is generated under the influence of the output signal PPC 3 and the add or subtract command located in the command register IR-I at time t ₇ . It should be noted that the function table signals FT 601, FT 602 and FT 610 are generated directly by the lines PL 103 and PL 113 and remain switched on as long as the program counter is in position PPC 3. In contrast, the function table signals FT 500, FT 504 and FT 510 are respectively delayed by a pulse time and have a pulse period longer than the signal PPC 3. It is also noted that, by a coupled to the line PL 103 signal, the encryption device for generating the function table signal FT 502 (line 15) is initiated, while the function table signal FT 503 (line 16) is generated by coupling a signal to the line PL 113.

At this point, the complement flip-flop 27-10 shown in FIG. 27 will be discussed for a brief moment. This complement flip-flop circuit 27-10 receives the clock signal pi 13 from the clock generator (FIG. 15) at its reset input at time t _s , ie a pulse time before the start of the third stage of the add or subtract command. This flip-flop circuit therefore generates the signal CPL at the time i ₆ or pi _14. Since the signal CPL is not present in this case, the signal CPE can not be generated either. In other words: the signal CPE is generated at the time i ₆ together with the signal CPL .

The function table signal FT 502 generated during an add instruction and the clock signal piO of the clock generator (FIG. 15) are coupled to the AND circuit 27-17 (FIG. 27), whereupon this AND circuit generates an output signal. In this case, the clock signal pi 0 is generated by the delay device 15-21 (FIG. 15), since the function table signal FT 601 is present with this command. As is known, the aforementioned delay device 15-21 is caused by the function table signal FT 601 to generate the clock signals pi 15 and pt0 to pi6. The other input to the AND circuit 27-18 is generated by the sign comparison AND circuits 27-16 when the operands of the registers i? Pl and RP 2 have different signs. Under this pre-

ao setting, ie with different signs and when an add command is carried out, the AND circuit 27-18 generates a signal at the time i ₀ , which is sent to the input of the OR circuit 27-19 and to the setting input of the complement flip-flop

as 27-10 is coupled. On the basis of the signal from this AND circuit 27-18, the signal CPE is generated at the output of the OR circuit 27-19 at the beginning of the clock time i _0. In addition, the cycle time is at the beginning pt _r the signal CPL am setting output of

Complement toggle 27-10 generated. The OR circuit 27-19 is controlled by the signal CPL of the complement flip-flop 27-10, so that the signal CPE is present as long as the signal CPL. The complement flip-flop 27-10 is therefore switched to its state CPL by a clock signal pil3 in the event of an add command (function table signal FT502), so that it generates an output signal at time pt _u. Signal CPE is also generated at the same time. If the operands have different signs during the execution of the instruction 10, the AND circuit 27-18 generates a signal which is fed to the input of the OR circuit 27-19 and the setting input of the complement flip-flop circuit 27-10 , thereby generating the signals CPL and CPE .

The function table signal PT 500 is coupled to the AND circuit 26-10 together with the signal CPL of the complement flip-flop 27-10 and the clock signal pt 12. In addition, this AND circuit 26-10 receives the carry signal PC from the pulse delay device 26-11 and the function table signal PT 508. The latter two signals are fed to this AND circuit as blocking signals. The output signal of the AND circuit 26-10 controls the pulse delay device 26-18, which generates the recomplement signal RCP at the time pt _13. If no carry signal is generated at time pt ₁₂ (when the last digit passes through the adder) and the signal CPL is present, indicating that an arithmetic subtraction is taking place, the recomplement signal RCP is generated. As is known, the signal RCP is required if the carry signal PC is not generated when the most significant digits of the two operands in the registers RP-I and i? P-2 are added, since the absence of the carry signal at this point in time indicates that the just received

509 538/373

171 172

The initial result is available as a tens complement. The signal CPL is also sent to the input

on the other hand, the carry signal PC at time t _{12 of} the three AND circuits 25-31, 25-32 and 25-33

is generated, the RCP signal is not generated because it is coupled, the output signals of which are the OR

control the calculation result just obtained in its correct circuit 25-11 of the final result circuits; in the form. 5 As you know, these three AND circuits are only

27 shows that the function table signal FT 503 and actual sign generated during a subtraction at the time / ^ ,, when the result command is generated when an add or the clock signal ptO is carried out to the AND circuit 27-13 an- subtract command will. As already coupled in, whereupon this AND circuit was described a binding with the adder, output signal is generated that has these AND circuits 25-31 to 25-33 connected to the AND circuit 27-12 at one of the inputs io . The task of inserting the correct sign into the signal of the sign comparison AND circuit result while an add is being carried out is another input of the AND circuit 27-13 or a subtract command, if switched on during an adding 27-16, if the in the Registers jRP-1 command that have unequal signs or, in the case of a sub- and RP-2 operand, the same pre-traction command are the same. Have in this em Z character ONTEXT. With this prerequisite, that is to say, it should be noted that the signal CPL is also coupled to the same sign and when an AND circuit 20-13 (FIG. 20) is carried out. Subtract command, the AND circuit 27-12 generates this AND circuit also receives the signals at the time pt _Q, a signal that the input of the PANS and PBNS, which indicate that the two OR circuits 27-19 and the setting input 20 Operands of the registers RP-I and RP-2 signs of the complement flip-flop 27-10 supplied digits in their twelfth digit positions. will. On the basis of the output signal of the AND AND circuit 20-13 receives during the circuit 27-12 is also the signal CPE pt at the output of OR formwork adder or Subtrahierbefehls to time Tung 27-19 at time = ₀ ER punktpi _u a control signal from the AND circuit testifies. In addition, the 25 20-11. The output signal of the AND circuit 20-13 complement flip-flop 27-10 at the time Pi ₁ is generated to the pulse delay device 20-15 on the signal CPL . The OR circuit 27-19 point pt _{12 is} generated by the signal CPL of the coupled, whereby this the signal PAMP to the time flip-flop 27-10. This signal PAMP is the signal controlled so that the signal CPE is applied for as long as the minuend is fed directly into the as the signal CPL. 30 Result switching. The signal PAMP is under

When executing a subtract command (radio other connected to the AND circuit 25-15,

tion table signal FT 503) thus becomes the complex which controls the OR circuit 25-11 (FIG. 25).

ment flip-flop 27- 10 ^ d urch the clock signal, the AND circuit 20-13 therefore generates an output

ptl3 switched in their state CPL, so that signal, whereby the signal generated PAMP rd wi, w hen

this flip-flop at time pt _u an off 35 in the add or subtract command generates the signal CjPL

output signal generated. At the same time pt _{u is} witnessing. This signal CPL is during a

the signal CPE is also generated. Have generated the Ope add instruction if the signs of the Ope

When command 11 is executed, the same prefixes are the same. In contrast, the signal CPL at

sign, the AND circuit 27-12 generates a subtract command if the sign

Signal generated which is not equal to the input of the OR 40 of the operands. In such a case

Circuit 27-19 as well as at the setting input, the result receives the sign of the operand

Complement flip-flop 27-10 is turned on from register RP-I. That under these circumstances

whereby the signals CPL and CPE are generated. generated signal PAMP causes the AND-

The from the i n Fig . Circuits 25-15 shown in FIG. 27 for transmitting the most significant generated signals CPE and CPE are connected to the AND sign of the register RP-I in the output circuits of the arithmetic unit (FIG. 21) of the adder.

couples. The signals CPE and CPE are each activated. The signals CPL and CPL are also activated

but only to the AND circuits in FIG. 21 connected to the AND circuits 22-13 and 22-14,

on, the Operan the subtrahend from the re- order of the AND circuits 22-11 and 22-20

gister RP-2 received. The signal CPE causes the 50 to 22-22 generated control bit signals to be corrected

to forward the operand of the register RP-2 from the arithmetic unit to or. This process was already carried out in

its correct form, d. H. not as a complement connection with F i g. 2 described. Finally will

can be processed. On the other hand, the signal causes the CPL signal to be sent to the reset input of the

CPE that the arithmetic unit couples the nine's complement flip-flop EQ (FIG. 23A). on

to the operand of the register RP-2 . 55 In this way, the flip-flop EQ is

The signal CPE is also reset with the signal ptO stand PEQ . The reason for this measure of the AND circuit 26-16 (FIG. 26) being switched on will be described in connection with the conditional jump commands 18 and 19 at the output of the pulse delay device.
26-11 generate the carry signal FC at time ^ to After checking the status of the complements. This signal PC is a 60 flip-flop circuit will now be described, an initial carry signal that is generated to determine what effect the other function table signals have on the nine's complement of the operand from the register (with the exception of the function table signals FT 502 register RP-2 to the Zeh's complement umzuwan- and FT 503) on the other circuits of the in dein. As has already been mentioned, this add and subtract carry signal PC shown in FIGS. 18 to 25 will also have to the elements shown in FIG. As is well known, AND circuits were coupled in the first set that these two stages of the add or subtract instruction require a carry signal in order to form the correct result of further operands by the iV digits of the add. or subtract command. In addition, was

173 174

During the second stage, the register RP-2 is cleared by PAMP, so that the digit information located in the twelfth digit position of the function table signal FT 706 in view of this register RP-I is directly evacuated. The third stage of the add or subtract command (FIG. 25) can be fed into the result circuit. The signal PAMP is then AND-leads the function- 5 circuits 25-13, 25-20, 25-34 and 25-40 generated _{at time i 7 to the} table signal FJ 707 to the input AND-switch. If there is a numerical value in the twelfth numbering 10-24 (FIG. 10) of the register RP-2 coupled to the register RP-I , then pelt is used, so that the 60 information units are transferred to this via the AND circuits mentioned coupled to the operand called up by the N-digits of the adding or output lines AI to A-4 of the adding unit to subtract command in the Re- ίο and is thus retained in the result. Can be stored on gister RP-2 . in this way the words e.g. B. Commands in

The function of the digit position provided for the sign table signal FT 601 generated during the third stage is used as a pass signal which does not contain a sign but a digit value, AND circuit 15-20 and as a blocking signal to which are processed. The function table signal AND circuit 15-17 (Fig. 15) is turned on. The signal of the AND circuit 15-20 is also coupled to the AND circuits by 15 FT 504 , the second 25-31 to 25-33 of the response circuit arrangement delay device 15-21 for generating the (FIG. 25). This function clock signals pi 15 and pt0 to pt 6 caused. The functions connected to the table signal, the sign AND circuit, the AND circuit 15-17 are opened at the point in time pt ₁₂ , so that the pre-table signal FT 601 prevents the output character of the result from being determined.
signal of the delay device 15-14 to the circuit that is switched on during the third stage of the adder or delay device 15-16 . Be subtracting command also generated function table, the clock signal pi 6 in the case of its lensignal PT 500 is connected to the five AND circuits generation by the delay device 15-21 10-53 (Fig. 10), which is the result of the OR -Circuit 15-18 switched on, 25 arithmetic operations are obtained and this result is transferred to the. The clock signals pi7 to ptl4 will thus restore registers RP-I . As is well known, these five AND circuits 10-53 are generated for a long time by the delay device 15-16 , each with one such as the function table signal FT 601 and the output lines A -1 to AS of the adder thus the delay device 15-21 for generating (F i g. 25 and 22). The function table of the clock signal pt 6 causes. 30 signal PT 500 is used together with the function

The function table signal FT 602 is connected to the table signal FT 504 to the AND circuit 20-14 with the clock signal pt 15 from the delay, which generates the signal PAMP. In addition to device 15-21 to AND circuit 14C-29, function table signal FT 500 is coupled to the. This delay device 15-21 coupled to the input of the AND circuit 20-18 was previously caused by the function table signal 35 whose output signal via the OR circuit FT 601 to generate this clock signal. 20-17 to the pulse delay device 20-16 The output of the AND circuit 14 C-29 is turned on to generate the signal PASP. (FIG. 14C) is coupled to the shift input of the In addition to the function table signal FT 500 there are hold and shift toggle circuits 14 C-27 at the inputs of the AND circuit 2 0-18 (FIG. 20). This flip-flop circuit therefore also generates the signals PBNS and PANS at 40 and the clock _{instant pi 16} generates the shift signal PRAH, where signal pill on. This AND circuit 20-18 generates the signal PASP digit by digit from the contents of the register RP-I when the signal for the sign is transported up to the adder. The function- related digit position in register RP-2 contains a table signal PT 510 together with the clock digit value and in register RP-I there is a signal pi 15 coupled to AND circuit 14 C-33 plus or minus sign . The signal PASP pelt, whose output signal to the shifting is to the AND circuits 25-12, 25-21, 25-35 input of the hold and shift toggle and 25-41 and to the AND circuit 22-15 of the 14 C-32 is coupled (Fig. 14 C). This toggle result circuit is coupled. If the signal circuit is therefore generated at the point in time pt _16, the PASP at the point in time pt ₁₂ at the output of the pulse shift signal PRBH, which generates the content of the delay device 20-16 , then the register RP-2 is transferred digit by digit into the Adder located in the sign position of the register RP-2 can be transported. borrowed numerical value directly into the result

That feeds during the add or subtract command and is therefore retained. The function table signal FT 504 generated by this measure is supposed to again achieve that the value stored in AND circuits 18-11 to 18-15 (FIG. 18) coupled to the sign position so that the value stored in the register RP -I issued an instruction in register RP-2 retained shifted digits of the input circuit of the adder remains.

Works can be supplied. The last of the function circuit 20-14 generated during the third stage of the table signal FT 504 is also connected to the AND add or subtract command, which generates the signal PAMP 60 table signals, the signal PT 610 is described. The AND circuit 20-14 receives at the time this function table signal of Endimpulspunkt pt signals PANS and PBN and the AND circuit 11-32 _n in Fig. 11, the signal PANS clock pulse 1 5 is fed together with the function table signal PT 500.. From Fig. 11 it can be seen that indicates that in the twelfth digit position of the that the AND circuit 11-32 is a digit value through the output register RP-I , while the 65 output of the pulse delay device 26-18 he signal PBNS indicates that The recomplement signal RCP generated in the twelfth digit is blocked. The position of the register RP-2 is signed. The output of the AND circuit 11-32 is in line. The AND circuit 20-14 therefore generates the signal 23 of the timing diagram shown in FIG. It shows

175 176

by its generation, that the signal RCP was not, is in a repeated complement formation

has been generated. the complement to the temporary im

As has already been described in the same way as the initial result stored in connection with the add-/ -ver register RP-I , the result of the in this is done by the in the register RP-I contained. The input circuit information shown in FIGS. 18 and 19 is fed into the adder via those channels or arrangement of information for equality shift registers and parity checks are carried out for a pulse duration that is normally delayed for storing the. In addition, the numerical information of the register RP-2 in the adder mation delayed by one pulse time after they serve. In this way, the initial result located in the register RP-I for the purpose of representing the signals PJ is treated as a subtrahend; has been bined (Fig. 21). These two signal - the formation of the complement to these initial delays represent equivalent delays in the result then takes place in the in FIG. 21 with regard to the information. The connected circuit arrangement. Through the formation of the Kommit F i g. 25, the combined form of the insertions for the information signals contained in the register RP-I was delayed at the output of the OR. correct shape. As is already known in connection with FIG. 26, the output signals were described, the Rekomple-F i g. 25 OR circuits shown via the ment signal RCP under the influence of a Kom-And circuit 10-53 to the register RP-I feedback signal CPL, a function table signal. In other words: the information ao FT 500, a clock signal pt 12 and based on the signals that run through the adder are delayed by the absence of a carry signal and two pulse times. This is generated in the function table signal FT 508. Since the signals shown during lines 17, 18 and 19 to be an add or subtract command take into account the function. table signal FT 500 is generated (line 14), is the

The register RP-I leads to a time i ₀ 25 g in F i. 26 AND circuit 26-10 shown in the shift by. A renewed consideration of the case of a complement formation always partially opened F i g. 14 C shows that the AND circuit 14 C-29 net in order to be able to generate the complement signal at the time pt _ls at the time pt ₁₂ and thus to be able to generate it. This recompletion signal flip-flop 14 C-27 in its shifted state is only possible in the case of an over-switching. Taking into account that none of the carry signals are generated in the 30. In the description of the present electronic computer used toggle - repeated formation of the complement, however, a pulse delay is assumed from an Im- it is assumed that a final transfer signal does not cause the pulse time, so it follows that this is generated by the and the complement signal RCP so-Kippkreisl4C- 27 provided displacement is also present. As FIG. 16 shows, the resignal at the time ί _{β is} generated. The same applies to the complement signal RCP, the flip-flop 16-21 is switched to its setting state for the shift generated by the flip-flop 14C-32 and generates a display signal. This last shift signal then the signal PPC 4.

As can be seen from line 21 of the timing diagram, the individual shift operations are switched on in register RP-2 . How does the complement signal RCP become the time-fi g. 92 shows, the shift register 40 point pt _{13 is} generated. Was Although the AND gate 26-10 RP-I fourteen shift pulses and the comparison pt already at the time completely opened _12, shift register RP-2 twelve such pulses to-the Rekomplementsignal RCP appears only to out. The difference in the number of Ver time pt _ls , since the output signal of the AND shift pulses, which are fed to the two registers RP-I circuit 26-10 via a pulse delay and RP-2 , results from the previously 45 device 26-18 was directed. Due to the coupling-mentioned delay of two pulse times, which make the development of the complement signal RCP necessary at the time, the shift register point pt _iZ , the flip-flop circuit 16-21 (Fig. 16) in RP-I is switched to its setting state after the information has been stored generated to advance the adder twice, so that time pt _u an output signal, whereby the AND information from the adder can be fed back to the register 50 circuit 16-25 for generating the signal PPC 4 RP-I. Is induced with others. The words in line 22 of the timing diagram : The information that the signal PPC4 shown in the first position appears so was contained at the beginning of the register RP-I , is only used during the pulse time pt _u . The register RP-I is reloaded by the signal PPC 4 and that of the third shift signal from the adder into decryption signals of the decryption device. This process is 55 lines 12-17 α and 12-17 b , the AND switch is shown in line 17 of the timing diagram in FIG. lines of the decryption device 12-17 c ge-From time t ₂ on, twelve shifts must be switched on and generate training pulses on line PL 104 so that the signals from the signal. This 104 coupled adder transmitted to the line PL to the register RP-I infor- mation signal is 12-18 a completely into this register is stored is supplied to the encryption device 60, whereupon these pt at the time _and the radio may be. In contrast, to feed the function table signals _J FT602, FT 601 and FT 610 and twelve digits of the register RP-2 into the adder at the point in time pt _ls, the function table signals only require twelve shift pulses. Generate FT 500 and FT 508. The function table

In the following description it is assumed that signals FT 601, FT 602 and FT 610 are in line 22

that a complement is formed (CPL) and that 65 is shown while the function table signals

There is no carry signal, which indicates that FT 500 and FT 508 can be seen from line 20.

that a further formation of the complement is required by the function table signal FT 601

As already described elsewhere, the clock generator for further generation of the clock

177

178

signals pi 15 and pt 0 to pt 6 caused due to the opening of the AND circuit 15-20. It should be noted that the function table signals FT 601, FT 602 and fT610 are continuously switched on during the transfer of the operand from time pt _u on. Due to the permanent ^{activation of the function table signal J 5} ToOl, the clock signals pi are therefore still available. The function of the function table signal FT 602 is to fully open the AND circuit 14C-27 at time pt _ls (FIG. 14C) in order to generate a shift signal for the register RP-I. As is well known, the RP-I register contains the initial result; the register RP-I must therefore receive a shift signal so that this initial result can be fed out for the purpose of forming the complement again. This withdrawal for the purpose of forming the complement again is shown in line 18 of the timing diagram. As FIG. 11 shows, the AND circuit 11-32 is opened by the function table signal FT 610, so that an end pulse from the AND circuit 11-32 via the OR circuit 11 at the time t _{5 of the present short period or the formation of the recomplement} -36 is generated. This end pulse is shown in line 24 as of the timing diagram.

The function table signals FT 500 and fT508 are now described below.

The AND circuits 10-48 and 10-66 (or the AND circuits 18-21 to 18-25 and 19-24 to 19-28, FIGS. 18 and 19) are opened by the function table signal FT 508. The AND circuit 10-48 has the effect that the information contained in the register RP-I can be transferred via the shift registers which are normally provided for transferring the information contained in the register RP-2 . By transferring the information from the register RP-I via the shift register for the information from the register RP-2 , the initial result from the register RP-I can be treated as a subtrahend, so that the complement to this initial result in the circuit arrangement in Fig. 21 can be formed. At the same time, the function table signal FT 508 also opens the AND circuit 10-66, so that zeros can be inserted in the positions of the minuend in the adder. In this way, the complement of the initial result is added to zeros and is therefore then available as the correct end result. Like Fi g. 20 shows, the AND circuit 20-35 is also opened by the function table signal FT 508 at the time Pi ₁₁ and generates the signal PASP, which indicates that the sign of the subtrahend, which in reality represents the sign of the initial result, is fed directly into the result circuit (Fig. 25) is fed. Like F i g. 26 shows, the AND circuit 26-10 is disabled by the function table signal FT508, which prevents a second recomplement signal from being generated by the pulse delay device 26-18.

The function table signal FT 500 has to fulfill some of the same tasks as during the adding process. So z. B. the function table signal FT 500 coupled to the AND circuit 10-53 so that the end result, ie the complement to the initial result, can be stored back by the adder via the AND circuits 10-53 in the register RP-I. As shown in FIG. 20, however, the function table signal FT 500 cannot generate a signal PAMP since no signal PANS is applied to the AND circuit 20-20 ^{and no function table signal / 7} T 504 is applied to the AND circuit 20-14. For this reason, the PAMP signal is not generated.

In summary, it can therefore be stated that the recomplement signal RCP is generated at the time pi ₁₃ and thereby causes the generation of the signal PPC 4 at the time pt _u. The signal PPC 4 causes the generation of the function table signals FT 601, FT602, FT610, FT 500 and fT508 via the assigned lines PL. These function table signals are used to open the corresponding AND circuits so that the initial result in register RP-I can be fed into the adder via those shift registers which are normally used to transfer the information in register RP-2. In this way the initial result is treated as a subtrahend; the formation of the complement to this subtrahend then takes place in the circuit arrangement shown in FIG. The complement to this initial result represents the end result which is stored back into the register RP-I by the adder via the AND circuits 10-43 which were previously opened by the function table signal FT 500.

To illustrate the individual operations, the table below shows the operations performed during the Commands 10 and 11 generated function table signals and their functions are listed.

Algebraic add instruction 10

(N) - » RP-2. Format: 10 NNNNN XXXXX (RP-I) + (RP-2) _ ». RP-I

Function tables
signal

surgery

The program counter is in position 1

FT 700 Transports the ^ address contained in the command register IR-I to the address decryption device at time i ₇

FT 600 Prevents the selection of a command. When the memory-free signal MNB is present, switches the program counter to PPC 2 and prevents the control counter from activating the address decryption device

The program counter is in position 2

FT706
FT 612

Clears memory RP-2

Switches the program counter at time pt ₁₃ to PPC 3

The program counter is in position 3

FTlOl

Transports the operand from the memory via the read line to the register RP-2 at the time pt _ls (i ₇ )

509 538/373

Functional

tabular

signals

FT 601
FJ602
FTSOl

FTSVl FTSM

FTSQO

FT610

RCP

179

surgery

Starts pi cycle at time pi ₁₅ (i ₇ )

Sets the toggle switch of the register RP-I at the time pt ₁₅

Sets the shift-toggle switch of the register RP-2 at the time pi ₁₆ and transports RP-2 to the subtrahend of the adder

If the signs are not the same, the complement flip-flop is set, thereby generating the initial carry signal

Transports jRP-1 to the minuend ^{ao of} the adder. Actuates the control for the direct feeding of the sign into the result circuit. Controls signed input signals to the adder

Transports output signals of the adder to register RP-I at time pi ₂ . If there is no carry over from the most significant digit, a recomplement signal is generated. Correction cycle is initiated when complement is formed

If the complement signal is not present, the end pulse is generated at time i ₅

Recomplement signal is generated at time i _ls if there is no final carry

Switches the program counter to PPC 4 . Resets flip-flops 11-4 and 11-2. Prevents the transfer from the command register IR-2 to the command register IR-I. Prevents setting of the toggle switch 11-1

The program counter is in position 4

40

FT601
FT602

FT 508

FT500

FT610

Starts the pi cycle at time pi ₁₅

Sets the toggle switch of the register RP-I at the time pt ₁₅

Transports RP-I to the complement input of the adder. Leaves decimal zeros in the minute-end input of the adder. Actuates the control for the direct feeding of the sign of the subtrahend into the result circuit. Sets complement flip-flop, which creates initial carry. Blocks the complement signal

Transports output signals of the adder to register RP-I from pt _s to pt ₁₃ . Actuates control for direct feeding of the sign

Generates end pulse at time i ₅

180

Algebraic subtract command 11

(N) ^ RP-2, format: UNNNNN XXXXX (RP-I) - (RP-2) - »- RP-I

Function tables
signals

surgery

The program counter is in position 1

FT 700

FT 600

Transports the address iV located in the instruction register / 22-1 to the address decryption device at time i ₇

Prevents the selection of a command. When the memory-free signal MNB is present, switches the program counter to PPC2 and prevents the control counter from activating the address decryption device

^a 5 program counter is in position 2

FT706
FT 612

Clears register RP-2

Switches the program counter to PPC 3 at time pt _ls

The program counter is in position 3

FT701

FT 601
FT 602
FT501

FTS03 FT504

FTSOO

FT610

Transports the information in memory via the read line to register RP-2 at time pt _ls (i ₇ )

Starts pi cycle at time point pt _ls C ₇ )

Sets the toggle switch of the register RP-I at the time pi ₁₅

Sets the toggle switch of the register RP-2 at the time pi ₁₅ , whereby RP-2 is transported to the subtrahend of the adder

With the same sign, complement flip-flop is set, whereby the initial carry and equality checker are generated

Transports RP-I to the minu end of the adder. Actuates control for direct feeding of the sign. Controls the sign input signals to the adder

Transports the output signals of the adder to register RP-I at times pi ₂ to pi ₁₃ . If there is no carry over from the most significant digit, the recomplement signal RCP is generated. Correction cycle is initiated when complement is formed

If the complement signal is not present, the end pulse is generated at time i ₅

181

182

Function tables
signals

surgery

RCP recomplement signal is generated at time pt _m if there is no final carry. Switches the program counter to PPC 4. Resets flip-flops 11-4 and 11-2. Prevents the transfer from the command register IR-2 to the command register ZR-I. Prevents setting of the toggle switch 11-1

The program counter is in position 4

FT 601
FT 602

ΡΓ508

FT 500

FT 610

Starts pi cycle at time point pt ₁₅

Sets the toggle switch of the register RPl at the point in time pt _ls

Transports RP-I to the complement input of the adder. Leaves decimal zeros in the minute-end input of the adder. Actuates the control for the direct feeding of the sign of the subtrahend. Sets complement flip-flop, which creates initial carry. Prevents the recomplement signal

Transports output signals from the adder to register RP-I at times pt ₂ to pt ₁₃ . Actuates control for direct feeding of the sign

Generates end pulse at time t ₅

As the next command group, commands 18 and 19 are described, by means of which the equality or. Size check for a conditional jump instruction is carried out. These commands also consist of a word containing twelve digits with the following format:

NNNNNMMMMM (equality check), NNNNN MMMMM (size check).

The equality and size check for a conditional jump is carried out using two commands and allows the electronic computer to switch to another program after certain conditions have been determined. As already mentioned in connection with FIG. 28, the normal sequence must sometimes be broken when it is determined that two particular numbers or operands are the same. On the other hand, the program can provide that the normal sequence is interrupted if one number is greater than the other. For this case, the computing system is designed so that it can determine when the minuend, ie the content of the register RP-I, is greater than the subtrahend, ie the content of the register RP-2. With the exception of two function table signals which are used in connection with Fig. 28, the two commands 18 and 19 are the same. The two function table signals are the function table signal FT 508, which is generated in connection with the instruction 18, and the function table signal FT506, which is generated in connection with the instruction 19. For the description of instructions 18 and 19 it is assumed that there is an operand in register RP-I which is to be compared with a second operand contained in register RP-2. It should also be pointed out once again that a comparison corresponds to a subtraction.

The commands 18 and 19 are described with the aid of the time diagram shown in FIG. 93, ίο The time diagram is divided into six short periods, which are correspondingly designated at the top of the time diagram for a better overview. As line 1 of the timing diagram shows, the command information is located in the command register IR-I at time t _e. This applies to all commands described so far, since the AND circuits 10-12, which forward the / digit information (in this case the / digits of the command 18 or 19), are open at the time t _s , so that the output signals ao of the flip-flops 51 to 60 of the command register IR-I are present at time t ₆ . As already described in connection with the other commands, the command remains in the command register ZR-2 until a signal N is generated, whereby the information on the AND circuits 10-12 and 10-12 α in the command register ZR -I can be relocated. This signal N is partially generated under the influence of an end pulse of the flip-flop 11-2, which in turn is generated by a corresponding function table signal, such as. B. the function table signal FT 610 is generated. This end pulse is generated because a certain command is executed in a certain number of short periods. The signal N is therefore only generated when the command has been completely executed. The signal N shown in line 18 of the timing diagram caused the current command to be re-stored in the command register IR-I . This signal N also switched the flip-flop 16-18 to its setting state in order to generate the signal PPCl at time pt _6. This signal PPCl is shown in line 2 of the timing diagram. The signal PPCl is combined in the decryption device 12-17c with the information signals of the decryption devices 12-17 'and 12-17 & in order to provide a signal PL 181 for the command 18 and a signal PL 191 for the command 19. As line 3 of the timing diagram shows, the signals PL 181 and PL 191 are generated at the time ί _β and remain switched on as long as the signal PPCl is applied.

The function table signal PT 600 or PT 700 is generated by the decryption device 12-18 & on the basis of the signal PL 181 (or PL 191). These two function table signals are shown in lines 4 and 5 of the timing diagram. Like F i g. 10 shows, the AND circuit 10-15 is opened by the function table signal ΡΓ700, so that the // digits of the command contained in the command register ZR-I can control the memory for the purpose of removing the operand to be compared. Line 5 of the timing diagram shows that the function table signal PT700 occurs at time i ₇ . Fig. 10 shows that at the time Z ₇ a clock signal is coupled to the AND circuit 10-15 so that it is completely opened. As already mentioned, the function table signal FT 600 is generated at time ^ and used as a blocking

183 184

signal is switched on to the AND circuit 10-36 in order to prevent the control counter 10-35 from coupling the storage input of the flip-flop circuit 16-20 via the OR circuit 16-13 to the setting this is switched to its setting state and controls time t ₇ . Since in the present case one and one signal PPC 3 is generated. At the same time, the operand and no command is taken from the memory. If the signal PPCS 3 is to be used via the OR circuits 16-11, the AND circuit 10-36 is connected and 16-12 to the reset inputs of the rocker arm. The function table signal FT 600 is coupled to lines 16-18 or 16-19, whereby the device 11-22 also switched to the AND switching program counter shown in FIG. 11 is coupled to its third position in order to become this AND circuit. As can be seen from Fig. 14C, the will lock. This indicates to the system that 10 AND circuit 14 C-14 is not being polled by the function table. In addition, the signal FT 706 is blocked, so that the register RP-2 ge function table signal FT 600 is connected to the AND switch and which has just been given by the iV digits of the device 16-16 (FIG. 16) as a pass signal turned on. The command stored in the command register IR-I is also connected to this AND circuit that can receive the requested information.
Memory free signal MNB and the clock pulse ti 15 The comparison process begins after generation. The AND circuit 16-16 generates a signal of the signal PPC 3. The signal PPC 3 is in the PPCS 2, the function of c-line 7 with the infor or fitted with decryption device 12-17 of the timing diagram is described. If the mationssignalen of the decryption device control of the memory are successful, 12-17 α and 12-176 are combined in order for the command 18 to be the memory-free signal MNB ao at the time t _t the signal PL 183 and for the command 19 the Signal generated. This process must already be provided in connection with PL 193. The signal PL 183 (or the other commands as well as in connection with PL 193) has been written to the encryption device in FIG. Line 6 of the time 12-18α coupled, which then shows the function diagram that the memory-free signal MNB table signals FJ707, FT 601, FT 602, F7510, is generated at time t _%. Generated with generation 25 FT 507, FT 505, FT 504, FT 501 and FT 610. of the memory-free signal MNB is that part of the loading The function error _{occurring at time pt 15} , in which the operand is selected, is ended. table signal FT 707 causes the complete öff-The command now causes the operand voltage of the individual C-AND circuits (Fig. 14B). is restored. This operation is the C-These AND circuits provide the input-forwarding the program counter by PPC 2 30 signal-AND circuits are known to the initiated on. As is known, at time / ₇ the information coupled to the read line HSB-R is generated in signal PYMR (FIG. 12A) so that the register RP-2 can be stored in the memory. To indicate that a read operation and not a write operand is being carried out with the operation in register RP-I. Operands to be compared are therefore based on this

F i g. 16 shows that the AND circuit 16-16 has been removed from the memory at 35 and has been re-stored in the control-simultaneous coupling of a function table register RP-2 . The comparison signal FT 600, a memory-free signal MNB and both are in registers RP-I and RP-2, as is a clock signal ti , and the signal borrowed operands is generated by PPCS 2 in the comparison cycle. This signal PPCS 2 guides the. As is well known, the conditional jump command flip-flop 16-19 has the task of making a comparison between two opetets and thereby generating the signal PPC 2 for the edges, so that the computing system sets the second level of the program counter. Line 7 of the time positions can indicate whether the normal sequence of the arithmetic diagram shows that the signal PPC2 for the time program should be interrupted. Line 14 of the point t _{t is} generated. This agrees with the previous timing diagram (FIG. 93) shows that the function description is consistent, according to which the output signal 45 table signal FT 505 in connection with the command of a flip-flop is delayed compared to its input signal 18 and the function table signal FT 506 in verum one pulse time is. link is created with command 19. aside from that

The signal PPC 2 is shown in the decryption is from the same line that the function decryption devices 12-17 α and 12-17 δ 50 generated by the two devices 12-17 c with the information signals of the conditional jump commands are table signals FT 602, FT 507 and FT 610 combined by the time, in order for the signal PL 182 point t _{e of} the second short period to be switched on for the command 18 and the signal PL 192 to remain ready for the command 19 as the signals PL 183 and PL 193 are switched on. The signal PL 182 (or PL 192) is in.

Line 8 of the timing diagram shown in FIG. Line 15 of the timing diagram shows that the radio under the influence of the signal PL 182 (or PL 192) 55 tion table signals FT 510, FT 504 and FT 501 generates the encryption device 12-18α at the time ^ or pt _{15 of} the second short period Function table signals FT 706 and FT 612. Generated from and a pulse time after the termination of line 10 of the timing diagram, it can be seen that the signals PL 183 and PL 193 are switched off. Function table signal FT 612 switched on until now, the description of how the signal PL 182 (or PL 192) is applied has remained in the description. 60 jump commands assume that the function table signals required for the function table signal FT 706 is already generated in an implementation of these conditional jump commands erAND circuit at time pt ₁₃ in connection with the signal PPC 2 and have therefore been deformed. For a better understanding of this radio pulse time after the termination of the signal PL 182 tion table signals, a short one follows . As FIG. 16 shows, the AND circuit 65 becomes the description of FIG. 28.

16-16 by the function table signal FT 612 to the die in FIG. 28 AND circuit 28-14 shown

Time point pt _ls fully opened and that is generated by the function table signal FT 505 and

Output signal PPCS3. This signal PPCS3 is generated by the clock signal pi 13 and a signal PEQ

185

186

opens. As is known, the function table signal FT 505 is generated in connection with an instruction 18 which carries out the equality check for the conditional jump. In addition, it has already been established in connection with FIGS. 23 and 23A that the flip-flop circuit 23-21 is switched to its setting state when two operands are processed in the adder by the clock pulse pt0 and therefore generates the signal PjEQ as long as two digits compared with one another are equal . If it is found that two digits are not the same, the AND circuit 23A-21 is switched to its reset state and thereby generates the signal PEQ. The PEQ signal is therefore present during the entire comparison of two words, as long as two corresponding digits are the same. As already mentioned in connection with FIG. 23 and 23A, this signal PEQ is sent to the one shown in FIG. 28 AND circuit 28-14 shown coupled. As a result of this coupling, the AND circuit 28-14 is always partially opened when two operands are being processed. If at the time of the comparison of the contents of the two registers RP-2 and RP-I the function table signal FT 501 is generated in connection with an instruction 18 and this comparison shows that the two operands are the same, then the AND circuit 28- 14 completely opened at the time pt _ls or t ₅ and generates an output signal which is connected to the OR circuit 28-2. The signal PCTA is generated by the OR circuit 28-2 at the time i _{5 and} the signal PCT is generated at the time t e. This process has already been described in connection with FIG. The generation of these two signals PCTA and PCT in connection with an instruction 18 indicates that an equality check has taken place and that the operands compared with one another are equal, so that a jump must be made.

The functions of the AND circuits 28-11 to 28-13 in connection with the instruction 19 will now be described below. The function table signal FT 506 is generated in connection with an instruction 19. The purpose of this command is to determine whether the content of register RP-I is greater than the content of register RP-2. The function table signal F7 "506 is coupled to the AND circuits 28-11 to 28-13, so that in the event that the other signals are connected to these AND circuits at the same time, an output signal is generated by one of these AND circuits which indicates that a signal PCTA must be generated. at the inputs of the aND circuit 28-11 are in addition to the function table signal FT 506 nor the signals PRAS, PRBS and pt was already described earlier. As 13, the signal PRAS indicates that t he Inh alt of the register i? Pl is positive; the signal PRBS , however, indicates that the content of the register i? P-2 is negative. In the algebraic sense, the content of the register RP-I must therefore be greater than the content of the register .RP . the output signal produced from the aND circuit 28-11 -2 is coupled to the OR circuit 28-2, whereupon this signal PCTA and a pulse time later, generates the signal PCT. in addition to the function table signal FT 506 and the clock signal pi 13 are at the AND circuit 28-12 also supplies the signals PRAS and PC as pass signals. As already mentioned in connection with FIG. 28 was mentioned, the content of the register .RP-I must be greater than the content of the register .RP-2 if the content of the register i? Pl is positive and a final carry is present. The AND circuit 28-12 must therefore provide an output signal at time t ₅ (or pt ₁₃ ) which indicates that a jump is to be carried out. It can happen, however, that the contents of register .RP-I are positive and there is a final carry, even if the two operands are the same. Should

ίο z. If, for example, the digits 5 are compared with one another (taking into account that such a comparison requires a subtraction), the contents of the register .RP-I may be positive and a final carry would result, although with regard to the instruction 19 no jump should take place, since this command tries to determine whether the content of the register RP-I is greater than that of the register i? P-2 and not just equal to the content of the register i? P-2. Signal PEQ, which indicates that the operands are equal, is therefore coupled to lines 28-20 to disable AND gate 28-12 and the generation of signal PCTA τα. prevent. The AND circuit 28-13 also has a function in connection with the command 19. The signal PRBS, the function table signal FT 506 and the clock signal pt 13 are applied to this AND circuit as the pass signal. In addition, the transmission signal PC is applied to this circuit as a blocking signal. The AND circuit 28-13 is provided for the case when the contents of both registers .RP-I and .RP-2 are negative. If these two contents are actually negative and there is no carry signal, this means that the contents of the register i? Pl is less negative in the algebraic sense than the contents of the register i? P-2. The content of the register RP-I must therefore be greater than the content of the register RP-2. If, on the other hand, a carry signal is present, this would mean that the content of register .RP-2 is less negative than the content of register .RP-I; in this case the content of the register RP-2 would be larger in the algebraic sense than the content of the register RP-I. The AND circuit 28-13 must therefore be blocked. Assuming that there is no carry, the output signal of AND circuit 28-13 is coupled to the input of OR circuit 28-2 _{at time pi 13.} This OR circuit then generates the signal PCTA and a pulse time later the signal PCT.

It can also be seen from FIG. 28 that an output signal of the OR circuit 28-1 is applied to the AND circuit 28-15. The output signal of this AND circuit 28-15 is coupled to the input of the OR circuit 28-2 at time t ₅ in order to change its control signals (PCTA and PCT). The input signal to the OR circuit 28-1 comes from various flip-flops which are located in the input and output devices and which will be described in more detail in connection with the input and output synchronization devices. These individual flip-flops are checked to determine whether a handover of control is justified. If the status of a tested multivibrator of the input and output synchronizing devices indicates that a handover of control is to be carried out, and a test command is issued, a signal is coupled to the OR circuit 28-1. This signal causes the AND switch

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device 28-15 opened in connection with the clock signal t _s , so that its output signal can be connected to the OR circuit 28-2, whereby the signal PCTA and a pulse time later the signal PCT is generated. A line shown at 28 A-I is also present at the input of the OR circuit 28-2. As will be described in connection with FIG. 28A, this input represents the overall test of the 99 loops, which will be described in detail at a later point in time. For the moment, it is sufficient to know that the system can use commands 99 to check numerous states in the synchronizing devices and thereby determine whether one of these synchronizing devices must be operated. The main or overall test covers all synchronizing devices at the same time. If one of these devices is in the waiting state, the main test ensures that control is transferred; In accordance with the currently applicable command 99, the system then begins testing various parts of the input and output devices. During this check, a signal for the OR circuit 28-1 can arise. In this case, the output signal of this OR circuit may require an additional jump, which causes the system to either continue to search for that part of the input and output device that is in the waiting position or to stop the search process. This operation will be explained in conjunction with the description of the synchronizers and in particular in conjunction with FIG. 28A.

It should be noted that when a command 18 or 19 is stored in the command register IR-I, the comparison of two operands caused by this does not necessarily have to show that the operands are the same or that the content of the register RP-I is greater than the content of the Register RP-2. If, in the case of instruction 18, the operands are not the same or if the content of register RP-I is not greater than the content of register RP-2 (instruction 19), there is no jump, but the machine continues its normal computer program, that is, the next command comes from the control meter. However, if the execution of instruction 18 or 19 shows that the operands are the same or that the content of register RP-I is greater than the content of register RP-2, another program must be used, ie it finds a conditional jump takes place. To describe the measures necessary for this, it is assumed for a moment that the signals PCTA and PCT have been generated.

In general, it can first of all be stated that a new instruction must be relocated from memory to instruction register / 22-2 when there is a jump, the address of this new instruction being represented by the M digits of the instruction currently in instruction register IR-I , in in this case is indicated by the command 18 or 19. While the current command (18 or 19) is in the command register IR-I , the control counter contains the address C + 2, in which C indicates the memory location from which the command (18 or 19) now in the command register IR-I was taken. As already described elsewhere, the counter is always incremented by one digit when a command is transferred from the command register IR-2 to the command register IR-I . Since a new command is to be queried by the address represented by the M digits, the next or second measure must be taken to ensure that the control counter is not incremented when the M address is in it. These precautions are necessary because in the event of an unsuccessful direct control of the memory by the M-digits, which takes place from the command register IR-I via the AND circuits 10-14, the memory must be controlled again, this time from the control counter . The M digits must therefore remain stored in the tax meter until the memory is activated.

has been successful. Would the tax meter switched to M + 1 and would be the control of the M-digits Memory address via the AND circuits 10-14 unsuccessful, the M-digits could

ao recorded memory location can no longer be accessed a second time; the command contained in this memory location could therefore no longer be taken. As a third measure, precautions must be taken to ensure that the address in the control counter cannot activate the memory at the beginning of the command 18 or 19, since an operand is to be taken at the beginning of the jump in order to carry out a comparison between two control operands. For this purpose - as already described in this chapter - the function table signal FT 600 is coupled to the AND circuits 10-36. As a fourth precondition for executing a conditional jump, a switch-off signal must be generated as soon as the system detects, by generating the PCTA signal, that a jump is justified. This switch-off signal switches off the function table signals until the new command identified by the M address is stored in the command register IR-I. In addition to these four measures, precautions must also be taken to ensure that the command circulation control unit, by which a series of control signals are generated on the basis of an end pulse, is influenced by the control transfer signal or jump signal PCTA and PCT so that the new command, ie the command containing the M address can be stored in the command register IR-I.
The above general information is in the following description in connection with FIG. 93 and 11 must be taken into account. It is assumed at the same time that the memory-free signal MNB has been generated. Before the time / _{e of} the second short period, that is, before the command 18 or 19 is stored in the command register IR-I , the command identified by the address C + 1 is transmitted at the time t _{0 of} the second short period via the AND circuits 10-10 stored in the command register IR-2. The instruction 18 or 19 is therefore located in the command register IR-I at the time t _{6 of} the second short period and contains the address C. At the time t _{0 of} the second short period there is an instruction in the command register IR-2 which is identified by the address C + 1 is marked.

In addition, the address C + 2 is located in the control counter 10-35 at the time t _{e of} the second short period, provided that the memory-free signal MNB is present. This follows from the fact that that was before

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the memory-free signal MNB ti generated at the time t _{e of} the second short period (FIG. 11), the flip-flop 11-4 switched to its set state. The AND circuits 10-10 are opened by the setting output signal of this flip-flop circuit 11-4, so that the command, which is identified by the address C + 1, can be stored in the register IR-I. The setting output signal of the flip-flop circuit 11-4 was coupled at the same time to the AND circuit 11-39, the output signal of which was connected to the control counter via the OR circuit 11-38, as a result of which it was switched from C + 1 to C + 1 .

These processes are described in the following description of the conditional jump (Figs. 93 and 11) to be taken into account in order to better understand the process of this conditional jump.

As already mentioned elsewhere in connection with commands 18 and 19, the memory-free signal MNB was generated at time t _{t of} the second short period due to the query of an operand to be stored in register RP 2 (line 6 of the timing diagram in Fig. 93). This memory-free signal MNB is connected to the AND circuit lasts for about two short periods and _{ends at the time i 6 of} the fifth short period.

As has already been mentioned elsewhere and can also be seen from line 14 of the timing diagram, the function table signal FT 610 is generated in the third stage in order to participate in the comparison process of a conditional jump instruction. As can be seen from FIG. 11, the function table signal FT 610 is coupled to the AND circuit 11-32 which, at time t _{5 of} the third short period, generates an output signal EP (end pulse) which is sent via the OR circuit 11-36 to the Toggle circuit 11-2 is coupled, whereby this is switched to the setting state (line 17 of the timing diagram). The setting output signal of this flip-flop circuit 11-2 is coupled to the AND circuit 11-17 via the OR circuit 11-16 in order to open it completely. This AND circuit is already partially opened by the clock pulse t6. The output signal of this AND circuit 11-17 is fed to the pulse delay device 11-18, the signal of which is coupled to the input of the AND circuits 10-36. The AND circuits 10-36 are thus replaced by the

tüng 11-42 (Fig. 11), whose output end pulse shown in the completely open signal is fed to the pulse delay device 11-43 and the address can thus be passed on by the control counter, whereby it addresses the memory-free signal 10-35 - Provides decryption device 10-64 MNB ti . Transport this memory-free signal. In other words: at the time

When the end pulse is generated (line 16), the system works as if it had never been interrupted by a comparison process. This is necessary insofar as the system does not yet know at this point whether the PCTA signal is being generated. If the signal PCTA is not generated, the system must continue to work as if it were through the

MNB ti is normally connected to the AND circuits 11-21 and 11-22 in order to couple their output signal via the OR circuit 11-23 to the setting input of the flip-flop circuit 11-4. As has just been mentioned, the setting output signal of this flip-flop is coupled to the AND circuits 10-10 in order to open them so that the information requested can be stored in the command register IR-I. However, since in the present case an operand and not an instruction is to be taken, the information must not be in

35 comparison process would not have been interrupted. Therefore, the command is queried, the address of which is in the control counter. As line 6 of the timing diagram shows, the memory-free signal MNB

the command register IR-2 can be stored. You 4 ° of the fourth short period based on the query of the

must rather be fed to register RP-2. In order to ensure that the operand is not stored in the instruction register IR-I , the function table signal FT 600, the generation of which has already been discussed in connection with line 4 of the timing diagram, is coupled to the AND circuit 11-22 in order to control it block and thereby prevent the generation of an output signal that would otherwise switch the flip-flop 11-4 to its setting state. In this connection it should be noted that the flip-flop circuit 11-4 was switched into its reset state by the clock signal £ 0 of the second short period via the OR circuit 11-33. Since the flip-flop 11-4 cannot be set and since the AND circuits 10-10 are therefore not open, the operand cannot be stored in the instruction register IR-I either.

The comparison of the two operands in the register RP-I and RP-2 begins in a certain sense at the time ^ of the third short period in accordance with the function table signals FT 505 and FT 506 (line 14). This comparison must be carried out for at least twelve pulse times so that the individual digits of one operand can be compared with the opposite digit of the other operand. From line 14 it can therefore be seen that the comparison process generates a command, the address of which is in the control counter. The memory-free signal MNB ti generates a second memory-free signal MNB t2 via the pulse delay device 11-43, which is coupled to the AND circuit 11-22. Like F i g. 93 shows, the function table signal FT 600 is not present during this fourth short period, so that the AND circuit 11-22 can be completely opened. The output signal of this AND circuit 11-22 is connected to the setting input of the flip-flop circuit 11-4 via the OR circuit 11-23.

As has already been described in connection with FIG. 11, the output signal of the toggle switch 11-4 is connected to the AND circuit 11-25 at time t ₀ , the output signal of which causes the switchover of the toggle circuit 11-3 to its set state. The setting output signal of the flip-flop circuit 11-3 enables the generation of the signal iV via the AND circuit 11-29 when the other input signals are present at the same time at this AND circuit 11-29. The flip-flop 11-3, however, was switched to its set state under the influence of the memory-free signal MNB t2 of the first short period at time t _{0 of} the second short period and has not been reset since no signal N has been generated since it was switched. Line 17 of the timing diagram shows

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the output of the flip-flop 11-2, which was reset at the time when the signal N was generated in the first short period (line 18). This flip-flop was then switched to its set state at the time t _{e of} the fourth short period due to the end pulse of the AND circuit 11-32 . As line 17 of the timing diagram shows, the flip-flop 11-2 generates an adjustment output signal at time t _{5 of} the fourth short period. Line 3a shows the output signal of the flip-flop 11-3. This signal is a signal from the setting output of the multivibrator, which is generated at time pt _x or t _{& of} the fourth short period. As line 18 shows, the signal N is therefore generated on the basis of the output signals of the flip-flops 11-2 and 11-3 at time t _s or pt _{lt of} the fourth short period.

The pulse N generated in line 18 at time t _{5 of} the fourth short period causes the / digits and JV digits of the instruction identified by the address C + 1 to be relocated to the instruction register / Ä-1. This process can be seen on line 23 of the timing diagram. As is known, the AND circuits 19-12 are opened by connecting a signal N at the time i ₅ , while the AND circuits 10-12 a are opened by a delayed signal N at the time ί _β . Like F i g. 28 shows, this arrangement is necessary insofar as the machine must decide whether a jump takes place or whether the signal PCTA must be generated at time pt ₁₃ or i _5. If the machine determines at time t _{B of} the fourth short period that a handover of control is justified, the next command to be queried is a command whose address is identified by the M digits of the command in the command register IR-I . The machine therefore does not want the M-digits of the command located in the command register IR-2 to be stored in the M-digit positions of the command register IR-I , since this would destroy the address of the new command which would be required in the event of a jump. If, on the other hand, no jump is required, the M-digits of the command in the command register / i? ^ Can be re-stored in the command register / JR-1 _{at the time ί β.} So no required information is lost. In order to prevent the M digits of the command located in the command register IR-2 from being stored in the M digit positions of the command register / i? -L at the time ί _β in the event of a jump, the signal PCT is sent to the AND circuits 10-12 α coupled to block these AND circuits so that the M-digits in the command register / i? -L cannot be lost.

In connection with line 19 of the timing diagram , it is assumed that a signal PCTA has been generated by the AND circuits 28-11 to 28-15 shown in FIG. 28 at the time t _{s of} the fourth short period. Line 20 of the timing diagram shows the signal PCT at time t _{fi of} the fifth short period. The signal PCT is coupled to the AND circuits 10-37 via the OR circuit 10-60 (OR circuit 11-20, FIG. 11) so that the M digits can be stored in the control counter 10-35. This process is shown in line 21 of the timing diagram. The signal PCTA is also connected to the OR circuit 11-13, the output signal of which is set by the flip-flop circuit 11-1, whereby a switch-off signal is generated (line 22). The shutdown signal prevents the generation of the function table signals until the new command is in the command register / i? -! is located. Normally, the flip-flop 11-4 would be switched to its set state by the memory-free signal MNBtZ, which was generated on the basis of the signal MNB ti of the fourth short period (in line 6). The signal PCTA shown in line 19 of the timing diagram is, however, coupled to the OR circuit 11-33 in order to reset the flip-flop 11-4 at time t _5. By resetting the flip-flop 11-4, the flip-flop 11-3 cannot be set by an output signal from the AND circuit 11-25 at time t _{0 of} the fifth short period (line 3a of the timing diagram). Since the flip-flop 11-3 is not set at the point in time t _{s of} the fifth short period, no signal N is generated at this point in time, that is to say after the generation of the signal PCTA. From line 26 it can be seen, however, that the function _table signal FT 701 is generated at the time pt ls. The output signal of the decryption device 12-18 & generated on the basis of this function table signal is shown in FIG. This function table signal FT701 is applied to the AND circuits 10-14 so that the M digits can be supplied to the address deciphering device in order to drive the memory for the purpose of extracting the instruction required by the branch instruction. The signal PCT is also connected to the AND circuit 11-39 at the time t _{e in order} to disable this circuit in order to prevent the control counter from being incremented before the address identified by the M digits has been successfully activated.

Under the influence of the address identified by the M digits, a memory-free signal MNB is generated at time I _{1 of} the fifth short period, provided that the memory is not occupied at this time. However, if the memory is occupied and the M-digits are in the control counter, this counter is only switched on after the memory has been successfully activated so that the M-digits are not lost. Under the influence of the memory-free signal MNBtI generated in the fifth short period (line 6), the memory-free signal MNBi2 is generated by the delay device 11-43 (FIG. 11), which is coupled to the AND circuit 11-22 will. Since the function table signal FT 600 is not generated at this point in time and thus this AND circuit 11-22 cannot inhibit and, in addition, since the toggle circuit 11-2 is set, the AND circuit 11-22 is completely opened. The output signal generated by it is fed to the OR circuit 11-23. By the output signal of this OR circuit 11-23, the flip-flop 11-4 is switched to its set state at time t _{2 of the sixth short period.} Under the influence of the setting output of the flip-flop circuit 11-4, the AND circuits 10-10 are fully opened, so that the command, the address of which is represented by the M digits, can be stored in the command register IR-2.

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This process is shown in line 24 of the timing diagram.

The memory-free signal MNB t2, which is generated on the basis of the M address during the fifth short period, is coupled to the setting input of the flip-flop circuit 11-4, the output signal of which starts from time i _{3 of} the fifth short period to time t ₀ of remains switched on for the sixth short period. Because the output signal is the Kippchert. As is known, the signal iV is connected to the AND circuits 10-12 and 10-12 α so that the command located in the command register IR-2 can be stored in the command register IR-I. Line 25 of the timing diagram shows the time at which the command identified by the M address is transferred from the command register IR-2 to the command register IR-I. In summary, it can be stated that

circuit 11-4 at time t _{e of} the sixth short- i _o that an operand is switched off by an instruction 18 or 19

period is present, it is taken from the six memory at time t ₆ and placed in register RP-2

first short period to the AND circuit 11-39 is stored in order with a in the register RP-I

couples. To be compared by the fourth command located at time t _s. Are the

Signal JV generated for a short period is equal to the toggle-switch operand (command 18) or is the content of the

tungll-3 (line 3a of the timing diagram) in its ₁₅ registers RP-I larger than the content of the register

Reset state switched so that this RP-2 (command 19), the signals PCTA and

Flip circuit 11-3 generated from time t _{e of} the fifth PCT (Fig. 28). Before creating this Si

For a short period up to time t _{0 of} the sixth signal PCTA and PCT , the system works as if

Short period is in their reset state. the operands have not been compared with one another

At the time of the sixth short period, ₂ o would be. If a jump is required, then through

therefore, all signals at the AND circuit 11-39, the signals PCTA and PCT, indicate the following operations that are required to open this circuit

are. Under the influence of these pass signals, the AND circuit 11-39 generates an output signal which is coupled to the OR circuit 11-38. The output signal of the OR circuit 11-38 advances the control counter by one digit, so that the address M + 1 is located in the control counter 10-35 at the time t _{7 of the sixth short period.} If the memory could not have been successfully controlled by the M digits, the memory-free signal MNB would _{not have been generated at the time Z 1 of} the fifth short period, and the AND circuit 11-22 would not have been fully opened to the Toggle toggle switch 11-4 in their setting state. As a result, the AND circuit 11-39 would not have been fully opened and thus would not have been able to advance the control counter 10-35 by one digit. As line 17 of the timing diagram shows (FIG. 93), the flip-flop 11-2 generates an adjustment output signal at time t _{e of} the sixth short period, which is fed to the OR circuit 11-16. The output signal of this OR circuit 11-16 causes the AND circuit 11-17 to open completely at time i ₆ . The output signal of this AND circuit 11-17 is fed to the pulse delay device 11-18, the output signal of which is coupled to the AND circuits 10-36, whereby the new address (M + 1) of the control counter can control the memory for the purpose of extracting the command which is to be stored in the command register IR-2. This process is shown in line 27 of the timing diagram.

Assuming that the memory could be successfully controlled by the address M + 1, the memory-free signal MNB is generated at time t _{t of the sixth short period.} At the time i _{0 of} the sixth short period, the flip-flop 11-3 is switched to its set state, since the flip-flop 11-4 has been set under the influence of the memory-free signal MNB of the fifth short period. Since both flip-flops generate a setting output signal at the time t _{5 of} the sixth short period, the signal N is generated at this time, whereby the command identified by the address MMMMM is transferred from the command register IR-2 to the command register IR-I .

triggered:

1. The M-digits of the command in command register IR-2 are prevented from being re-stored in command register IR-I , so that the M-digits of command in command register IR-I (command 18 or 19) are not lost can.

2. The M-digits of the command in the command register IR-I (command 18 or 19) control the memory and are simultaneously transported to the command counter.

3. The command counter is not incremented until the M digits of command 18 or 19 have successfully controlled the memory.

4. The shutdown signal is generated, which means that function table signals are only generated again when the command identified by the M address is stored in the command register IR-I.

5. The signal N is generated so that the command identified by the M address can be transferred from the command register IR-2 to the command register IR-I . After this command identified by the M address has been re -stored in the command register IR-I , the system goes back to the program sequence that took place before command 18 or 19, with the / digits of the new command generating a new group of function table signals, to perform the operations of the new command.

The table below shows the function table signals generated in connection with command 18 or 19 as well as their functions.

Command 18

Equality check for conditional jump command (JV) -> RP-2. Format: 18 NNNNN MMMMM

If (RP-I) = (RP-2), M- + control counter. If (RP-I) Φ (RP-2), increment control counter by one. (RP-I) remains unchanged and (N) remains in RP-2. All twelve digits are compared with one another.

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Function tables
signals

surgery

FT612

The program counter is in position 3
FT707

FT601
FT 602

FTSlO

FT 507
FT505

FT 504
FT501

FT 610
FJ701

Conditional jump size check
(N) -> RP-2. Format: 19 NNNNN MMMMM

If (& P-1) is greater than (RP-2), M-> control counter. If (RP-I) is equal to or less than (RP-2), increment control counter by one. (RP-I) remains unchanged and (N) remains in RP-2. All twelve digits are compared with one another.

196

Function table signal

surgery

The program counter is in position 1

FT700 Transports the address N contained in the command register IR-I to the address decryption device at time t ₇

FT600 Prevents the selection of a command. Switches the program counter to PPC 2 when the memory-free signal MNB is present

The program counter is in position 2
FT706 Clears register RP-2

Switches program counter to PPC 3 at time pt _ia

Transports the information contained in the memory via the read line to the register RP-2 at the time pi ₁₅

Starts the pi cycle at time pi ₁₅

Sets the toggle switch of the register ÄP-1 at the point in time pi ₁₅

Sets the toggle switch of the register RP-2 at the time pi ₁₅ . Transports i? P-2 to the subtracting end of the adder

Sets complement flip-flop, which creates initial carry

Tests toggle the equality circuit at time pi _ls to generate the PCTA and PCr signals when RP-I = RP-2

Transports ÄP-1 to the minuend of the adder

Re-circulate EP-1. Sets flip-flops of register jRP-1 at time Pi ₁₁

Generates end pulse at time i ₅

Was generated by the PCT signal. Transports the M-digits from the command register IR-I to the address decryption device

Command 19

The program counter is in position 1

FJ700 Transports the address N contained in the command register IR-I to the address decryption device at time t ₇

FT 600 Prevents a command from being taken. Switches the program counter to PPC 2 if the memory free signal MNB is present

The program counter is in position 2
Clears register RP-2

FT706
FT612

Switches the program counter to PPC 3 at time p / ₁₃

The program counter is in position 3

FT707

FT 601
FT602

FT 510

FTSVJ FTS06

FT 504
FT 501

FT610
FT701

Transports the information from the memory via the read line to register äP-2 at time pi ₁₅

Starts the pi cycle at time pi ₁₅

Sets the slide toggle switch of the register i? Pl at the time pt _ls

Sets the shift-toggle switch of the register RP-2 at the time pi ₁₅ , whereby jRP-2 is transported to the subtrahend of the adder

Sets complement flip-flop, which creates initial carry

Checks whether i? Pl is greater than jRP-2 at time pi _ls in order to generate the signals PCTA and PCT if RP-I is greater than .RP-2

Transports .RP-I to the minuend of the adder

Re-circulates .RP-I. Sets slide-toggle switch of the register .RP-I back

Generates end pulse at time t _s

Was generated by the PCT signal. Transports the M-digits from the command register IR-I to the address decryption device

Next, we will discuss the exhaust command, which is of the format 00 XXXXX XXXXX . As mentioned in connection with some other commands, the .Xf digits of the discharge command are digits that cannot be deciphered.

The exit command serves as a blank space within the program, which is to be used at a later point in time can be used or which can be used as a replacement for a command removed from the program can. The inclusion of the outlet command results in greater flexibility in the computer system.

197 198

Must ζ. B. the program sequence is interrupted, the same short period is switched on. The signal den, so instead of the outlet command, an unconfirmed PPCl and the information signals from the Entdingter jump command 05 can be provided, whereupon the coding devices 12-17 α and 12-176 who the machine through a certain subroutine in the decryption device 12-17 c can carry along, which are combined in the original program 5 in order not to contain the signal PL 201. On the other hand, it becomes the sub-process. Function table signals FT 600 and FT 700 are generated by this signal PL 201, so the unconditional jump command 05 or. As the timing diagram in FIG. 94 shows, another command from the program begins signal PL 201 is removed at time t _{e of} the second short term and instead the discharge command is inserted while the two function tables are being used so that the machine can quickly skip this command signals FT 600 and FT 700 at time t _{7 of} the. This process will be produced below for the second short period. As already described in detail in. Conjunction with a number of other commands-Located be located in the instruction register IR-I an outlet was written, are under the influence of the command, then the 00-digit (/ Numeric) of the unloading table 15 function signal FT 600 a number Operaschlüsselungsvorrichtungenl2- 17a and 12-176 executed with tions. First, the AND circuits 12-17c are combined by the radio signal PPCl in the decryption device table signal FT 600 in order to block the signal PL 00, so that they testify in the control counter 10-35. This signal PL 00 will not be able to control the memory at the encrypted address. Selungseinrichtungl2-18fiE coupled to there the 20 This is necessary to generate function table signal FT 614 by the command. The 20 an operand is queried and the transmission discharge command is stored at time t ₆ in the command of this operand in the register RP-I in front of the down register IR-I . How the AND question of the next command must be ended. Besides circuit 11-34 can be seen, this circuit is blocked by the function table signal FT 600 by the function table signal FT 614 at time 25, the AND circuit 11-22 is opened in order to prevent point t _7. The end pulse generated by this AND circuit ensures that the operand called up, the AND switch, is passed through to the setting input of lines 10-10. In addition, 11-2 is to be coupled by this flip-flop. The blocking can be achieved at the time that only after a ER- t ₀ generated output of this flip-flop 11-2 cessful removal of a command and not according to the AND circuit 11-29 is turned on, so 30 a successful removal of an operand that for Time t _{5 of} the short period that is generated on the N signal. By storing the function table of the outlet command in the command signal PT700, the AND circuits 10-15 register IR-I are followed, a signal N is generated, which opens the iV digits of the command 20 from this command the command register IR-2 is reloaded in the command register IR-I in the address codes of the command register IR-I. The management device can be stored in order to control the discharge command within a short period of time from there to the memory for the purpose of removing an open after it has been stored in the command register.

IR-I ended. As in line 16 of the timing diagram in FIG. 94 shows that the removal command 20 is next loaded at time t _{6 of} the second short period. In the case of certain programs generated by the present 4 ° signal PYMR 1 so that the memory machine is executed, it is expedient to show that a read and not a write process, an operand or a word from which, should take place. To remove the generation of the signal PYMR 1 store and this operand in which has been discussed in connection with Fig. 12A, einzuspeichern register RP-I, provided that in the AND circuit 12 to 1854 this signal register RP-2, a certain condition exists. Generated for 45 PYMRl. Line 7 of the timing diagram shows that instruction 20 is provided for this extraction, which means that the memory at time t _{0 of} the second has the format 20 NNNNN XXXXX . Short period is activated; Line 8 shows that with this command, the five N digits represent the reason for this activation of a memory-free signal. Memory location in which the operand to be stored in register MNB at time t _{x of} the second short period is RP-I is located. The Χ-Ίλί- is thus attested, whereby it is indicated that the Speifern this command put not to be deciphered rather is not occupied. In other words: The digits represent. The memory could be used to remove the operand. The command 20 is now successfully controlled in connection with. The memory fig. 94, 14B, 14C, 16, 12, 11 and 10. The timing diagram in FIG. 94 shows how the free signal is connected to the AND circuit 11-42, and 55 (FIG. 11) is coupled, the output signal of which is supplied to the command 20 at the time t _{e of} the second short-period pulse delay device 11-43 , in the command register IR-I. As already in connection with which the memory-free signal MNBtI is generated with other commands and in connection with.

Was described in Fig. 11, the command in the memory-free signal to the MNB is located in register7jR-2 information through the ER 60 Fig. 16 shown in AND gate 16-16 Verzeugung a signal N to the command register IR-I binding with the function table signal FT 600 and relocated. From Fig. 16 it can be seen that the coupled to the clock signal ti. This AND switch toggle switch 16-18 set by the signal N then generates the signal PPCS2, which becomes while the trigger circuits 16-19 to 16-21 trigger circuit 16-19 is supplied. A pulse time can be set back, whereby the signal PPCl er 65 is generated later, ie at the time ^ of the second short. As the time diagram in FIG. 94 shows, the signal PPC2 is then generated, which becomes the signal PPCl at time t _{6 of} the second indicates that the control counter 10-35 is generating its second short period and remains in its position _{until time i 2} has been switched. This signal PPC 2

199 200

is in the decryption device 12-17 c with the line 14 5-12 & 5 occurring signal as a blocking

to be able to receive the signals from the decryption devices signal. This circuit arrangement

12-17 α and 12-17 b combined, the signal voltage is provided so that the computing system

PL 202 at time t _{2 of} the second short period can determine whether the twelve digit positions

provide. This signal PL 202 becomes an input to the 5 of the operand in register RP-2.

Encryption device 12-18a supplied, whereupon the formation signal "1" or an even number is located.

these the function table signals FT 610, FT 704, It is assumed that in the twelfth digit

FT 70S, FT 620 and FT 509 generated. represent an even number and that therefore

As FIG. 11 shows, the function table in the check bit signal FT 610 provided for the twelfth digit is coupled to the AND circuit 11-32 in the register RP-2 with a binary "1" so that the AND -Circuit to the chert. Is located in the twelfth digit time t _s generated final pulse of the OR general arrangement of the fifth channel (shift register) is a "1", 11-36 tion can be supplied to the tilt is so the coupled to the line circuit 140-1265 11-2 . This end pulse is converted into an output signal via the inverter to a "0" line 11 of the timing diagram (FIG. 94) at time 15. In this way that appears represented by the i _{5 of} the second short period. As already the AND circuit 145-25 output signal generated in connection with numerous other commands on the line 14 BAIeS, while that was written by the AND, the output signal of the flip-flop circuit 145-26 is generated on the line circuit 11 -2 occurs first to the AND circuit 11-29 145-12 / 5. From the drawing it can be seen, coupled to this AND circuit in part, that the opening occurring on line 145-12 / 5, so at time t ₅ the third short-wave signal to the AND circuits in the hold period a signal JV can be generated. When the individual stages of the register RP-I are looped out, the output signal of the flip-flop 11-2 is switched, e.g. B. to the AND circuit 14C-16, coupled to the AND circuits 11-17 , so that the individual information units that are the output of these AND circuits to 25 in the twelfth digit position of the register RP-I time ί _{β are} a pulse delay device, under the influence of which can be supplied on the line 11-18. Be removed by the output 145-12 / 5 occurring signal. signal of this pulse delay device 11-18 On the other hand, the AND circuits 11-36 are opened by the on the line, so that 145-12 eS coupled signal "0" the input the address in the control counter 10-35 dem. 30 may be AND circuit 14C-12 el not locked, so that memory for the purpose of interrogation of the next instruction the extracted from the memory information in the züge- leads, of course, presuppose twelfth of the digit position of the register RP-I eingespeizung that in the Command register IR-I can be stored. The task of command 20 is to ensure that the command does not require access to memory. This ends because the operand, ie the twelfth. Finally, the output signal of the toggle switch digit is stored in the register RP-I , 11-2 is still sent to the AND circuit 11-14 if it is in the corresponding digit des couples This process is for instruction 20, but register RP-2 was an even number. Similar circuit arrangements are of no significance and are therefore not described in detail here for the remaining circuit arrangements. Digits of the register RP-2 and for each of the in the

The function table signal FT705 is sent to digits to be stored together with 40 registers RP-I .
Lent C-AND circuits coupled, which can summarize the connection between the read line HSB-R and that is caused by the command 20 that a level of the individual shift register of the intermediate through the iV digits of this Represent command of designated schenspeicher RP-I . For example, from the operand that is stored in the register RP-I , FIG. 14C, it can be seen that the function table 45 is even when the corresponding digits of the register signal FTOS to the AND circuit 14 C-12 el to RP-2 . The individual digits of the is switched through, whereby information in the first operand queried by command 20 is checked at bit position of stage 12 of the first shift register whether the corresponding digits of the register RP-2 are stored in the star of the buffer RP-I located operands are even, can. As shown in Fig. 94, 50 are treated separately by the. Each digit of the interrogated function table signal FT 705, the input AND th operands, the corresponding digit of which is currently in the second short register RP-2 in the ReSchaltung at time t ₇ , is partially opened in the register RP-I period. inserted. Is located in all digit positions

As Fig. 14B shows, if the function table is not an even number, the original

signalfT509 received a number of pairs of AND 55 borrowed information in register RP-I .
Circuits supplied, with for the test bit positions

in the fifth shift register of the intermediate storage General Description of the Input and Output Memories RP-2 each have a pair of such AND switching devices
is provided. So is z. For example, from FIG. 14B it can be seen that the function table signal FT 509 is coupled to 60 In the following description of the input and the AND circuits 145-25 and 145-26, various output devices are coupled. The drawing also reveals commands from the central processing system that the AND circuit 145-25 with a Um-, which is connected to control the input and output precautionary elements 14 5-12 k 5, to the directions , the synchronization devices and lines 145-12 & 5 coupled signals serve as 65 through the distributor. These commands to be able to provide their interpretation signal for this AND circuit as well as the functions generated by them. The AND circuit 145-26 is also connected to table signals for the processing system are connected in the inverter 145-12 k 5 , as shown in the table below.

201

Command 31 XXXDD MMMMM

Function table signals

FT 614
FT 809

FT 831 (t ₄ and t.)

Operation 202

Check drum DD action toggle switch (DD = O ₁ , O ₂ ...); if toggle switch is set, transfer control to M and reset toggle switch. If toggle switch is reset, continue with the current program flow.

Command 37 XXXXX MMMMM

Set drum shift in forward direction. If set backwards, it switches Direction relay in forward direction. Control passes to M.

Function table signals

IO

Generates end pulse

Transports the digits 6 and 7 from the command register IR-I to the register AB

Checks drum action toggle switch

FT FT 837 O ₄ and i ₅ )

surgery

Generates end pulse

Sets the direction toggle switch indicated by the DD digits stored in the ^ tB register in the forward direction. Control goes to M if toggle switch is set in reverse direction

Command 32 XXXDD XXXXX

Set the drum toggle action (DD = O ₁ , O ₂ ... ).

Functional
table signals surgery FT 614
FT 809 (i ₇ )
FT 832 (i ₄ ) Generates end pulse
Transports the digits 6 and 7
from the command register IR-I
to register AB
Sets the action toggle switch
the drum DD one

Command 35 XXXXX XXXXX

Set drum-magnetic head assembly.

Function table signals

FT614

FT 835 (i ₄ and r ₅ )

surgery

Command 36 XXXXX MMMMM

Set drum shift in reverse direction. If set forward, this will switch Direction relay in reverse direction. Control passes to M.

Command 38 XXXXX XXXXX

Set the magnetic head in the upper position.

Function table signals

FT836 (i _{4 and} i ₅ )

surgery

Functional
table signals surgery FT 614
FT 838 O ₄ ) Generates end pulse
Represents the magnetic head assembly
identified by the ./IB register
drew on the drum
upper tape positions 50-99

Command 39 XXXXX XXXXX
Set the magnetic head in the lower position.

Function table signals

⁴⁰ FT FT

Generates end pulse

Represents magnetic head assembly at the point indicated by the yiss register Drum a

45 operation

Generates end pulse

Represents the magnetic head arrangement identified by the ^ 4ß register Set the drum to the lower belt positions 00-49

55 Command 41 XXSXX XXXXX

Store the contents of the memory address register of the synchronization device 5 in the five least significant digits of the register RP-I ; put zeros in the seven most significant digits of the register RP-I . The relocated address is not regenerated in the memory address register.

Function table signals

Generates final pulse ° ^FT614

Sets the direction toggle switch in reverse direction 65 FT820 (t _v i ₀ , Z _1. Control goes to M , and i ₂ ) specified by the DD digits stored in the AB-Rq- ^ft ^ ²¹ (h) register

when toggle switch in forward direction set operation

Generates end pulse

Inserts decimal zeros into the seven most significant digits of the register RP-I

Blocks the precedence instructions so that the contents of the address register can be stored in the register RP-I

509 538/373

203

Function table signals

FJ817 (i ₇ and ί ₀ )

FT704 (g

FT819 (i ", i ₂ , i ₃ , i ₄
i _{e and} i ₇ )

surgery

Initiates read-write cycle for the address register of synchronization device S.

Clears register RP-I

Blocks the transport of the address register signals the pulse shaping elements of the address register

204

Command 50 XXSXX MMMMM

Check sector toggle toggle switch of drum synchronizer S. If toggle switch is set, pass control to M and reset toggle switch. If toggle switch is reset, continue with the current program flow.

Function table signals

FT 614

FT 850 (i ₄ and i ₅ )

Command 42 XXSXX XXXXX

Has the same task as the command 41, except that the relocated address in the memory address register of the synchronization device S is renewed.

surgery

Generates end pulse

Checks the sector toggle switch or action switch of the synchronizer S

Functional
table signals surgery FT614 Generates end pulse FT821 (i _t ) Puts decimal zeros in them ben highest digit digits of the register RP-I FT820 (i ₇ , i ₀ , t _x Blocks the precedence statements, and ig) thus the content of the addresses registers to register RP-I can be saved FT817 (i ₇ and i ") Directs read-write cycle for the address register of the syn chronizer 5 a FT704 (i,) Clears register RP-I

Command 52 XXSDD XXXXX

Connect drum synchronizer 5 to drum DD and reset the availability toggle switch of drum synchronizer 5 to start-up.

Function table signals

35

40

Command 43 XXXSX XXXXX

Has the same task as command 42, except that command 43 is only for the synchronizing devices of magnetic tapes applies.

surgery

45

Functional
table signals surgery FT614 Generates end pulse FT 809 Transported the in command number contained in register IR-I ern 6 and 7 to the y4ß register FT 821 Put decimal zeros in the seven most significant digits of the Register RP-I FT 820 Blocks the precedence statements, thus the content of the addresses registers RP-I saved who can FT 874 Directs read-write cycle in Address register of the tape syn chronizer 5 a FT704 Clears register RP-I Clearing control element

FT 614 Generates end pulse

FT809 (i ₇ ) Transports the in the command

register IR-I into the viß register

FT 852 A (t _± ) Switches all drums off

the synchronizer S from

FT 852 B (i ₄ ) Switches drum DD to Syn

chronising device S and at the same time disconnects drum DD from all other drum synchronizing devices. Provides availability toggle switch
the drum synchronizer 5 back into operation

Command 53 XXSXX XXXXX

Switch on the drum synchronizing device S in position 1 and re-store the starting address from the five least significant digits of the register RP-I in the memory address register of the synchronizing device S.

6o

65

Functional
table signals surgery FJ614 Generates end pulse FT814 Prevents evacuation of the tape Input buffer memory through the Belt synchronizer gene FT 815 Applies to drum read synchro nizing device: clean up output buffer FT820 (t _v t ₀ , t _t Blocks the precedence statements, and t ₂ ) so that the in the register RP-I be sensitive address in the adres senregister saved who can

205

206

Function table signals

FT817

FT 819 (f _o , t ₂ , t _z h,
i _{8 and} i ₇ )

FT 818

FT 853

surgery

Function table signals

Initiates a read-write cycle in the 5 FT address register of the synchronization device S.

Blocks the transport of the output signals from the address register to the pulse shaping elements of the address register

Transports the address in the five least significant digits of the register RP-I to the pulse shaping elements of the address register

Applies to drum synchronizer S: Sets the start flip-flops for operating mode 1

FT819 (t ₀ , t ₂ , t ₃ ,
and t ₇ )

FT 818

FT85S (t _a )

surgery

Initiates read-write cycle for the address register of synchronization device S.

Blocks the transport of the output signals from the address register to the pulse shaping elements of the address register

Transports the address in the five least significant digits of the register RP-I to the pulse shaping elements of the address register

Sets the start flip-flops for operating mode 2 of the synchronizer 5 a

Command 54 XXSXX MMMMM

Sets availability toggle the drum synchronizer S in the inoperative position; also switches off the synchronizing device S from the drums if this device is a write synchronizing device. Command 56 XXSXX MMMMM

Check drum synchronizer availability flip-flop S. If toggle switch is reset (commissioning), continue with the current program sequence. If toggle switch is set (inoperative position), transfer control to M.

Function table signals

FT 614
FT 854

surgery

Function table signals

Generates end pulse

Sets the availability flip-flop for the drum synchronizer 5 in the inoperative position. Switches all drums from the drum write synchronizer from

FT614

³⁵ FT8S6 (t ₄ ) operation

Generates end pulse

Carries out the commissioning test in the synchronization device 5

40 Command 57 XXSXX XXXXX

Proceed with the current operation on the drum synchronizer.

Command 55 XXSXX XXXXX

Switch on the drum synchronization device S in position 2 and store the starting address from the five least significant digits of the register RP-I in the memory address register of the synchronization device S.

45 Function table signals

FT 614
iT857 O ₃ )

surgery

Generates end pulse

Sets the start flip-flop of the drum synchronizer

em

Function table signals

JT614
FT 814

FT 815

FT820 O ₇ , i ₀ , t
and t ₂ )

surgery

55

60

Generates end pulse

Prevents the tape synchronizer from clearing the tape input buffers

Clears drum read synchronizer S input buffers

Blocks the priority instructions so that the address in register RP-I can be stored in the address register

Command 58 XXSXX XXXXX

Store the sector tape address of the sector address register of the synchronizer S in the register RP-I . The sector address is stored in digits 3 and 4, the tape address in digits 9 and 10; zeros are inserted in the remaining digits. The word stored in the register RP-I thus has the following format: OOßßOOOOSSOO.

Functional
table signals surgery FT614
FT704 (t ₀ ) Generates end pulse
Clears register RP-I

207

Function table signals

surgery

Function tables signals

FT 614 FT704
FT 859

FT 858

surgery

Generates end pulse
Clears register RP-I

Transports the contents of the ^ B register to digit positions 9 and 10 of the register RP-I. Inserts decimal zeros into digits 3 and 4 of register RP-I

Inserts decimal zeros into digits 1, 2, 5, 6, 7, 8, 11 and 12 of register RP-I

Command 60 XXXST MMMMM

Check availability toggle switch for

the

Belt control of the synchronizing device S. If toggle switch is set (state FREE), continue with the current program sequence. If toggle switch is reset (BUSY state), pass control to M.

Functional
tables
signals surgery FT 614 Generates end pulse FT 809 Transports digits 6 and 7 from
Command register IR-I to the. ^ B register FT 860 Checks the availability toggle switch of the
Belt control

208

Function tables
signals

FT 858 (t _t ) Transports the sector address of

the drum synchronizer to digits 3 and 4 of the register RP-I
Transports the tape address from the drum synchronizer to digits 9 and 10 of register RP-I
Inserts decimal zeros into digit positions 1, 2, 5, 6, 7, 8, 11 and 12 of register RP-I

Command 59 XXXXX XXXXX

Store the contents of the / IB register in digits 9 and 10 of the register RP-I ; put decimal zeros in the remaining digit positions. The word stored in the register RP-I thus has the following format: 00 / 4BOOOOOOOO.

Command 61 XXXXX MMMMM

F7614
FT 861

surgery

Generates end pulse

Checks the availability toggle for read-write control the belt synchronizer

Command 62 XXXXX MMMMM

Check the availability of the read lines by checking the flip-flops for forward and Read backwards. If one of these flip-flops is set (BUSY state), transfer Control on M. If both flip-flops are reset (state FREE), drive along current program sequence.

Function table signals

FT 614

FT 862

surgery

Generates end pulse

Checks the availability of the read lines for the tape synchronizer

Command 63 XXXXX XXXXX

Link control of the tape synchronizer to the selected tape device and reset the availability toggle of the line controller to the BUSY state. The selection process takes 200 microseconds. When finished, the band select toggle is set.

Function tables
signals

surgery

FT 614 Generates end pulse

FT 863 Sets the trigger circuits for the

Control the belt synchronizer beforehand

Transports the least significant digits from the v4B register into the Tape selection register and to the decryption device

Command 64 XXXSX MMMMM

Check band selection toggle switch of synchronizing device S. If toggle switch is set (selection process finished), transfer control to M and reset toggle switch. If toggle switch is reset (selection process not completed), continue with current control sequence.

Check availability toggle for read-write control of the tape synchronizer. If the toggle switch is set (FREE state), continue with the current program sequence. If toggle switch is reset (BUSY state), pass control to M.

Function tables
signals

FT 614
FT 809

FT 864

surgery

Generates end pulse

Transports digits 6 and 7 from the command register IR-I to the ^ 4B register

Checks band select toggle switch

209

Command 66 XXXXX MMMMM

210

Store the control information contained in the digits 8, 9, 10 and 11 of the register RP-I in the command register of the tape synchronizer. The word consisting of control information contained in register RP-I has the following format: XIKLG XXXXXXX
The servo is checked to see if the direction of rotation of the tape needs to be switched. If switching is required, continue with the current control sequence. If switching is not required, transfer control to M.

Function tables
signals

Function tables
signals

FT614 FT866

surgery

Command 67 XXXXX MMMMM

Switch on the tape drive of the tape device connected to the synchronization device. If the servo is rewound, continue with the current control sequence. If the servo device is not rewound, pass control to M.

Functional surgery tables signals Generates end pulse fT614 Switches the tape run with the synchro FT 867 connected tape device and checks whether tape device is rewound

Command 68 XXXXX XXXXX

Initiate read or write operations on the connected tape device.

Function tables
signals

FT6U FT 868 FT 816

surgery

FT614 FT809

FT 869

surgery

Generates end pulse

Transports the digits 6 and 7 in the command register IR-I to the y4ß register

Checks ten word flip-flop circuit of the tape synchronizer S

Command 70 XXXXX XXXXX

Proceed to current operation on the tape synchronizer.

20th

Generates end pulse

Transports the digits 8, 9, 10 and 11 in register RP-I to the command register of the tape synchronizer

Checks the direction with the Synchronisierein- ^a5 interconnected tape device, whether the direction of circulation of the tape has to be switched

Function tables
signals

FT614 FT 870

surgery

Generates end pulse

Performs read or write operations on the tape synchronizer for another ten words

Command 71 XXXXX XXXXX

Go ahead with the operation of the tape synchronizer on the second space in between the blocks if it occurs after reading ten words. When writing, set put a space between the blocks and write another ten words.

35

Function table - 40 signals FT614 FT 871

45 FT 870

surgery

Generates end pulse

Inserts space between blocks for writing. Reads at Read past the space between the blocks if it appears

Performs read or write operations on the tape synchronizer for another ten words

Generates end pulse

Initiates read and write operations

Clears the tape synchronizer input buffer

55

6o command 72 XXXXX MMMMM

Check band availability flip-flop. If flip-flop is set (state FREE), drive continue with the current control process. When toggle switch is reset (BUSY state), pass control to M.

Command 69 XXXSX MMMMM

Function tables
signals

Check ten-word flip-flop on belt synchronizer S. If flip-flop is set, pass control to M and reset flip-flop. When flip-flop reset, driving with current Steue- FT approximate running away.

surgery

Generates end pulse

Checks availability flip-flop of the belt synchronizer

509 538B73

211

Command 73 XXXXX MMMMM

212

Check toggle switch for the reading space between the blocks and toggle switch for the writing space between the blocks. If either of these flip-flops is set, pass control to M. If both flip-flops are reset, continue with the current control flow.

Command 78 XXXXX XXXXX

Set belt control to 0 and set the availability toggle switch the belt control to the state FREE.

Function tables
signals

Functional

tabular

signals

FT614 FT 873

surgery

Generates end pulse

Checks toggle switch for reading space between blocks and toggle switch for writing space between blocks,

surgery

FT 614 Generates end pulse

FT 878 Generates selection end pulse, which

resets the band selection toggle and the availability toggle for the belt control after a corresponding delay in the state FREE

Command 74 XXXXX XXXXX

Relocate the starting address from the five least significant digits of the register RP-I into the memory address register for the tape synchronizer.

Functional

tabular

signals

surgery

FT614 Generates end pulse

FT820 Locks the precedence statements so that

the address in register RP-I can be stored in the address register

FT 874 Initiates the read-write cycle for

the address register of the tape synchronizer

FT819 Blocks the transport of the output

signals from the address register to the pulse shaping elements of the address register

FT 818 transports the lowest in the five

significant digits of the register RP-I located address to the pulse shaping elements of the address register

Command 76 XXXXX MMMMM

Check inter-band toggle switch. If toggle is set, continue with the current control sequence. If toggle switch is reset, pass control to M.

Function tables signals

FT614 FT 876

surgery

Generates end pulse

Checks the interlock flip-flop of the tape synchronizer Program control loop

The "program control loop" is mentioned several times in the following description. Here-

_a5 is a program permanently stored in the main memory of the system, which is used to switch the central processing system on during its work cycles of varying duration.

F i g. Figure 28B shows a simplified flow diagram of the program control loop. As the block 28 # -1 28 B illustrated in the block diagram shows the commands contained in the control loop include first a the Hauptaufprüfung. The effect of this main check consists of the question: "Is one of the connected input and output devices on hold?" If so, the control loop goes over to the loop check 99, which is shown in block 285-2. The loop test 99 checks for the appropriate groups of input and output devices until the group is found which is waiting for a command from the central processing system. The loop test then causes the program control loop to start the correct auxiliary program which controls the input and output device that is on hold. Each secondary program has numerous transfer points, so that control of the central processing system can be passed back to the program control loop so that it can repeat the main check. In this way, the control unit of the central processing system repeatedly comes under the influence of the program control loop, which results in constant monitoring of the input and output devices.

If the result of the main test (28 BI) indicates that no input and output devices are waiting to be switched on at the moment of the test, the program control loop can turn to the variable port 28B-6 . Is z. For example, if the main audit is on line L of the program, line L + 1 would be variable and would have access to one of the processing facilities or other ancillary programs. In other words: If the main check (2825-1) is answered with "No", the program control loop can cause the central processing system to execute the

213 214

Block 28 5-3 the flip-flop circuit D of one of the two how many summary commands are to be checked in a certain arithmetic unit. As stated below, the moment is located in the memory block. When a is written, the toggle circuit D of a device memory block is empty and no summary arithmetic unit is set, if this arithmetic unit has received a group of summary commands in execution for the assigned device and is 5, the counter position shows 0. Whenever a is ready for this central processing system summary command has been executed, it is sent for processing. This total counter digit is one smaller.

Orders are not orders in the sense that if they finally exclude all summary orders

have been passed or stored by a built-in decryption device and if

the processing plant can be decrypted. Perhaps not the flip-flop D by the arithmetic unit

the more they appear in the form of pseudo-code-has been set, the changeable

combinations that are initiated by the program of processing completion X through the program, the

management system can be interpreted to real commands to a less important program control loop

to generate from the processing plant, which then transfer function, z. B.. On "Editing" (block

control the input and output devices. So save 15 285-4).

If the arithmetic unit is running during the operation of the devices, the arithmetic unit in Fig. 28B by blocks 285-4 and stores the summary instructions in a series of adjacent memory locations and 285-5 designated operations of the program are also chosen arbitrarily and are used in this invention Deciphering word (D word) is not described in detail in a given language. On the other hand, the location of the storage unit, in a typical case 20, is the execution of certain typical summary items under the storage address 2500. The D word consists of instructions that require the cooperation of the drum and tape from parts N and M (similar to parts JV and M devices , described below,
The circuit arrangement for checking the last memory location of the package summary main check (ie for reentrying the error, which is started by the arithmetic unit in the memory) is shown in FIG. 28A . Mark how they were saved. At the same time, Fig. 28A shows, the arithmetic unit includes the flip-flop D to this circuit arrangement. If a number of test AND circuits 28 A-3 are now tested, the flip-flop circuit D in block 285-3 is tested to 28 ^ 4-8, each of which has three inputs. This is followed by the transfer of the control of the central processing system to the address 2500. 30 is the function generated by the encryption device of the zen-proves when testing the trigger circuit D, central processing system that this trigger circuit is not has been set, then the table signal FT 899 is switched on. If the program enters this function again in the program control table signal FT 899, the encryption loop enters the main check. If, on the other hand, the device of the central processing system is set to the flip-flop circuit D , the word "D" 35 time i _{4 is} generated when the command register is taken and the variable connection .Sf to IR-I of the central processing system is set to operate by block 285-5 is wrong 99. This command 99 has the format, according to which the program 99 XXPXXMMMMM and generates, in addition to the radio, the program control loop with the main table signal PT899 and an end pulse 614. aufprüfung. After the. variable 40 In the format of command 99, the eighth digit connection X each digit P identified by block 285-5 can be between 0 and 6, has scanned the operation, which corresponds to the word when the main check is carried out "D" marked successive digit P has the value 0. This digit is taken from the memory in the summary commands and either executed or decrypted the assigned 45 10A-31 to the in Fig. 28A are supplied to darge device memory blocks. A device memory set to generate signal PSO. This signal PS Q block comprises a certain part of the core memory via the OR circuits 28.4-14 to chers, which the programmer has reserved for each input and output 28 ^ 4-19 to the corresponding AND circuits output device. Each in and out 28./4-3 to 28 ^ 4-8 coupled. On the third and output device, its own memory block is assigned to the last input of the test AND circuits 28A-4 , which z. B. from three or four side by side to 28 ^ 4-8 are the output signals of the OR-lying memory locations, where the on circuits 28 ^ 4-9 to 28 ^ 4-13. Each of these OR circuits to the corresponding input and output device is collectively stored with a corresponding summary command. The corresponding group of action flip-flops is connected. If the summary command is found from the packet that has been taken from the input and output devices, it is only executed if it is held. These action flip-flops are activated when the device memory block is empty. If the set, if a certain device, the device memory block contains one or more further these flip-flops, contains an additional summary command, then it will, on the other hand, also be stored in the device memory block. That sums up to 60. For example, the OR circuit 28-9 with the logical commands are taken from the device memory block in the setting outputs of the individual sector switchover in the order in which they were stored there. As will be described below, Marian commands in the order of their Ent- the sector switchover toggle switch is guaranteed to stand up. 65 mel is set if information is assigned to a memory sector consisting of all device memory blocks, a keyword 100 words. This keyword contains a counter or should be read out. In a similar place, which provides a statement for the program, the OR circuit 28 ^ 4-10, whose output

215

216

output is applied to the test AND circuit 28.4-5, connected to the setting outputs of the individual ten-word flip-flops, which are located in the various tape synchronizers. As will be described later, these ten-word flip-flops are set when the synchronizing device associated with this flip-flop circuit writes in or reads out ten words. The OR circuit 28 / 4-11, the output of which is connected to the test AND circuit 28 / 4-6, is connected at its input to the setting output of all drum action toggle circuits. A drum action toggle switch is located in each drum and is set as soon as the drum has completed a switching or setting process The OR circuit 28 / 4-12, the output of which is applied to the AND circuit 28 / 4-7, is connected to the setting output of a certain group of drum action flip-flops for drums 7-12. The purpose of this arrangement is described in more detail elsewhere. Finally, the OR circuit 28 Λ-13, the output of which is applied to the test AND circuit 28 / 4-8, is connected to the setting output of all the selection flip-flops of the various tape synchronization devices. These flip-flops are set when the selection process by which an appropriate tape synchronizer has been selected has been completed. The final test AND circuit 28 / 4-3 is connected to the setting output of a clock test toggle circuit 28 A-20 . This flip-flop is set every 8.33 milliseconds by a 120 Hz pulse from a 60 Hz power source. The setting output signal of this flip-flop is also fed to a secondary test AND circuit 28 / 4-21 Function table signal FT 895 generated by the encryption device 10-18 of the central processing system is present. The output signals of all test AND circuits 28.4-3 to 28 / 4-8 are coupled via the OR circuit 28 AI and a pulse delay device 28 / 4-30 to the OR circuit 28 / 4-2 shown in FIG. 28A . This circuit arrangement is intended to cause the central processing system to make a conditional jump to the M address part of the command 99 as soon as an output signal is generated by the OR circuit 28-1.

As already mentioned, the main inspection is that of all input and output devices at the same time it is checked whether there are further instructions from the central processing system need, through the command 99 and a "0"

ao corresponding number P causes. The command 99 with a digit P corresponding to the digit 0 generates the function table signal FT 899 and the signal PSO at time ^. These two signals represent two of the three signals that are required to

a5 an output to the AND circuits 28 / 4-3 to produce 28 / 4-8. If the third signal is also present, which is received from the clock test multivibrator or from the OR circuits 28 / 4-9 to 28 / 4-13 are generated, the AND circuits 28 / 4-3 to generate 28 / 4-8 an output signal which causes a jump to the M address identified by command 99 will. The individual code combinations for the main test and the Loop test 99 listed in the table below.

Home Inspection and Command 99 address Command format interpretation 60 99.oro; orooi4o Perform main inspections on the input and output devices.
When one of the flip-flops of the input and output devices is on
is set, transfer control to 00140; otherwise go with the present
ongoing program sequence 61 05XXXXXMMMMM Unconditional jump to MMMMM. The address MMMMM is ver
changeable to control the control of the toggle switch D, to Pro
programs for saving and executing summary
Commands as well as passed to other, less important programs
can 140 99xx \ xxoq \ si If any of the sector toggle flip-flops are set, submit
Control on 00151; otherwise continue with the current program
sequence continues 141 99XX2XXM15A When one of the ten word flip-flops is set, hand over control
ration to 00154; otherwise continue with the current program sequence 142 99ΖΑΓ3ΖΖ00159 If clock check flip-flop is set, pass control to 00159;
otherwise continue with the current program sequence 143 99ΖΛΓ6ΛΓΛΓ02465 With any of the select flip-flops set, give control
at 02465; otherwise continue with the current program sequence 144 99; ΟΓ4ΪΑ: 00163 When any of the drum action flip-flops are set, hand over
Control on 00163; otherwise continue with the current program
sequence continues

217

Various checks and orders

218

address

Command format

interpretation

151

152

153

154

155

50XX1XXMMMMM

50XX2XXMMMMM

50XX3XXMMMMM

69XXX1XMMMMM

69XXX2XMMMMM

156
158 69XXX3XMMMMM
69XXX5XMMMMM 159 95XXXXXMMMMM 160
162 163 99ZZ5ZÄT00170 164 3100001MMMMM 165
169 3100002MMMMM
3100006MMMMM 170
175 3100007MMMMM
31000012MMMAiM 176 Error program 2465 64XXX1XMMMMM 2466
2468 64XXX2XMMMMM
6AXXXAXMMMMM

When the sector switching toggle of the drum synchronizer 1 is set, give control to MMMMM; otherwise continue with the current program sequence

If the sector switching toggle of the drum synchronizer 2 is set, give control to MMMMM; otherwise continue with the current program sequence

If the sector switching toggle of the drum synchronizer 3 is set, give control to MMMMM; otherwise continue with the current program sequence

If ten word toggle of tape synchronizer 1 is set, give control to MMMMM; otherwise continue with the current program sequence

If ten word toggle of tape synchronizer 2 is set, give control to MMMMM; otherwise continue with the current program sequence

\ Tests of ten-word flip-flops from other tape synchronizers

If clock check toggle is set, pass control toMMMMM; otherwise continue with the current program sequence

[Various commands

If action toggle is set to any of drums 7 through 12 , pass control to 00170; otherwise continue with the current program sequence

If drum 1 action toggle is set, pass control to MMMMM; otherwise continue with the current program sequence

The same applies to action toggle switches for drums 2 to 6
[The same applies to action toggle switches for drums 7 to 12

If tape synchronizer 1 select toggle is set, pass control to MMMMM; otherwise continue with the current program sequence

\ Applies analogously to selection flip-flops for belt synchronization devices 2, 3 and 4

As the table shows, the main test is located, for example, in memory address 60. It also shows that the test AND circuits generate an output signal when one of the action flip-flops assigned to the OR circuits 28.4-9 to 28.4-13 is set or if the clock test toggle switch 28.4-20 is set. This output signal generated by the AND circuits is fed via the OR circuit 28 AI into the circuit arrangement for the conditional jump shown in FIG. 28A in order to transfer the control of the central processing system to address 140. It can also be seen from the table above that the loop test 99 begins in address 140, ie that the sector switchover toggle circuits of all drums are tested here. For this purpose, the number corresponds to? of the command 99 of the number 1. Due to a "1" in the eighth digit position,

the decryption device 10.4-31 generates the signal PSX. This signal PS1 is coupled to the input of the AND circuit 28A-4 via the OR circuit 28.4-15. The command 99 itself generates the function table signal FT 899, so that only one of the sector switching flip-flops of the drums needs to be set so that the conditional jump signal can be generated (FIG. 28). This jump signal then transfers the control of the central processing system to address 151. The individual testing of the sector switchover flip-flops is started at this address 151, this test beginning with the flip-flop for drum 1 and then continuing with this test up to drum 3.

From the above, it can be seen that the loop test 99 can determine which Operations take precedence when more than one synchronizer is on hold.

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So is ζ. B. from the memory address 140 of the pre-loop table to be available within at least 500 milliseconds it can be seen that the first check has been carried out. When the program for the control loop that is carried out by command 99 returns to the, the synchronizing toggle sector switching toggle circuits of the drum sync circuits of the high-speed chronization devices are always extended. So the 5 devices have to be checked first, since they are drums in front of all other input and output devices are more likely to be on hold than the directions are given priority, since they are with the largest other devices. Are the toggle speed working. As the address 141 shows, connections from several synchronizing devices are then subsequently set to the ten-word toggle setting, so the synchronizing device operating at high speed of the belt synchronizing devices goes to the first one. The table above also shows that the command from the central processing program specifies that command 99 passes through the output signals of the processing system again. After the individual groups of synchronizing devices in grams of this synchronizing device check the corresponding sequence of the speed with which the corresponding commands have been issued and after information is again transmitted from them , this 15 being returned to the control loop, the check is carried out as long as until the group toggle switch of the other synchronization device is found, in which the set toggle switch is still in the setting state, an override is found. The control is then prompted to the control program in order to transfer the necessary instructions to this second program of the relevant synchronization device, synchronization device, so that this device can give the necessary commands. The command 99AfXO causes that to get miss. this jumps after returning to the control loop like this. In addition, the table above (address 163) has to be continued for a long time until all synchronizers have received that the checking of the drum devices has carried out the necessary command information action flip-flops. To abbreviate that just in connection with the test program. First of all, the priority system described in the table above checks whether the drum that is waiting for the main test and for the loops belongs to drum group 1 to 6 or 7 to 12 test 99 based on the fact that certain hears. Mechanical input and output devices with large

Thus, when executing the command, greater speed will work than other inputs and

99 XX 5 XX 00170 (address 163) the action tilting 30 output devices so that they are accordingly

circuits for drums 7 to 12 checked. must be served with priority. Furthermore

If during this check it is found that one of the are also in one and the same class

Flip-flops is set, the arithmetic input and output devices, which take precedence over

program a jump to memory location 170. over other devices of the same class

With the help of the in the memory locations 170 to 175 have. So z. B. the sector switchover toggle switch

Sensitive six commands are then the individual device for the drum synchronizer 1 before

Action flip-flops for drums 7 to 12 of the sector switching flip-flop for synchronizing

individually checked in turn. The first safety device 2 checked. This priority order

Toggle switching of this group, which is in the setting within one and the same class as an aid

status is, causes the central processing 40 intended for the programmer.
processing system skips to a program again,

which begins in the memory location MMMMM. These distributors
The memory location is identified by one of the commands located in the memory locations 170 to 175. The distributor is shown in FIG. 29 as a block diagram . Is shown when executing the in memory location 45, whereby the information lines are determined by 163 command that the action thick lines, the control lines by thin flip-flops for the drums 7 to 12 are not a line and the address lines by dashed lines , so are marked in the memory locations 164 lines. As will be described one after the other in the individual commands up to 169 , the distributor controls the information . The first toggle switch of this group, the 50 tion flow between the individual input and output is in the set state , causes the devices and the memory. So z. B. the central processing system again skips over to a program of reading out information from a specific gram, which is located in the storage location sector of a specific tape of one of the drums MMMMM . This storage location is controlled by the distributor through and the writing of this information in one of the storage locations located in the storage locations 164 to 169, so called commands . It follows from this that the actual flow of information is the program that is involved in one of those MMMMMs. On the other hand, the individual on and off storage locations begin, which are formed by the commands in the output devices so that they contain certain storage locations 170 to 175 (drums 7 to 12) or required for carrying out the reading process by the instructions in storage locations 164 to 169 60 mechanical functions, such as B. tape and (drums 1 to 6) are marked, for that sector selection, under the direct influence of the zen drum, the action toggle switch of which is carried out by the central processing system.
represents was. As Fig. 29 shows, the two synchronizing

Devices 1 and 2 are provided for the execution of the subroutines, in order to provide numerous transfer points, whereby the reading of information from the drums and the control can be transferred back to the program control loop. This information can be written into the memory . These transfer points are to be controlled the other way around. Furthermore, the synchronous are programmed so that a transfer to the control devices 3 and 4 is provided, which

221 222

reading out and writing of information in veins so that the central processing system of the connection with tape devices as well as writing in the computer system that provides the control signals, control binding with printing devices. The printing device has a large number of input and output devices at the same time as such, devices can already be controlled in technology. ; knows. The synchronizers correspond to 5 um between the memory and the asynchronous Devices shown in other figures drove input and output devices information and contain lines 29-10 to 29-13 to be able to exchange information without the information the necessary control signals between the flow of operations word for word from the central processing unit To be able to control synchronizing devices and the management system they must, the on assigned input and output devices routed io flow of information involved initial memory address' will. saved in the mailing list and changed

To become the standard flow of information from one. For this purpose there is an address * of the relatively slow input and output devices senregister 29-50 is provided in which the addresses the fast, parallel writing or saving. Also belongs to the distributor To adapt the reading process in the main memory, the 15 must still change the address 29-52, in the the addresses are changed bit-wise from the input and output devices. Is the transportation In an information word read out in parallel and numerically in series from or to a memory formation terminated in a parallel information digit, the address will be converted into the change flow for the memory. facility 29-52 under the influence of the address

Modified for writing information from the 20 change control circuit 29-54. These

Memory in one of the input and output devices, address change control circuit 29-54 is through

is the opposite conversion of the information coupled to line 29-55 from the

tion flow required, d. that is, the synchronizing devices controlled from the memory, which the loading

drive type of the relevant input and output device read out in parallel at high speed

Information must be displayed in a slow bit-wise manner. In addition, the address change

information control circuit arranged allele and numerically in series by to the line 29-56

mation flow are converted so that the information switched on signals from the priority circuit eff

mation influenced by the input and output devices 29-92 to 29-95, which indicate which

can be turned. Synchronizer has priority.

For this purpose, the input buffers 30 are the start address for each item of information or 29-15 and the output buffer memory 29-18 in front of the word group results from the five least significant values. The input buffers 29-15 receive the relevant digits of the transport command located in the register RP-I of the central VerInformation in series from the input and output preprocessing system; these directions are supplied, which information for the address is supplied to the address control unit via the "memory, for example the address line 29-60 supplied in the arrangement. Under the influence, drums and tape devices showed. The address control unit 29- 62 the initial routing of this information about the information address is then stored via the line 29-64 in the address lines 29-20 and 29-21 is stored by the synchro-register 29-50,
nizing devices 1 and 3 controlled; The line 29-64 represents various lines lines 29-24 and 29-25, the information is fed to the 40, which includes the lines, input buffers 29-15. which due to a call to line 20-110

After the coupled read signals representing a complete word have written the address of the address digits in series into the input buffer memory 29-15, registers 20-50 via the address control unit, these digits will now switch on the address line 20-65. Addresses on through to the control lines 29-85 'or 29-87 α Toggle 45 of the line occur 29-65, are coupled to the address control signals changing means in parallel from the buffer memory 29-52 via the line 29-66 read out and over the 60 lines as well as the address lock controller 29-69. 29-30 and the 60 AND circuits 29-31 as well as At the same time, the read-out address is stored in the memory in the associated pulse-shaping elements and the address control unit 29-62 again circulated. 50 and back into the register via line 29-64

Output buffers 29-50 are written to in a similar manner. If the address is replaced by the

memory 29-18 Information from the memory is not locked via lock control 29-69, so it arrives

the 60 lines 29-32 and the 60 AND circuits via the lines 29-71 to the

29-36 and the associated pulse shaping elements mentioned address decryption device,

enrolled in parallel. The writing of information 55 Gets memory control over the line

mation in the buffer memory 29-18 is sent by a memory-free signal MNB to the 29-116, so the

Control lines 29-86 a, 29-87 b or 29-88 α read out address again, and which is derived from the

then coupled information on lines 29-37 resulting in first readout modified address

and 29-38 to 29-40 numerically in series - is sent to the address register via line 29-72,

read and the synchronizing devices 2, 3 60, the address control unit 29-62 and the line

and 4, from where they are fed via lines 29-64. On the other hand, it is the controlled one

29-43, 29-21 or 29-44 occupy the relevant input and storage location, the changed address will be used

Output devices is fed. not written in register 29-50, but

In the case of a high-speed computer system, the same address described here is returned to register 29-50

of the same type, the individual input and output 65 are saved in order to be used there for a new control.

devices are expediently designed so that tion of the same memory location is available

they have a relatively large amount of information with you. The register is controlled by

be able to process minimal control effort- signals made on line 29-110,

/ U4

223 224

which indicate that the selected memory location is free of synchronization by signals from the devices is. bodies have been set up to indicate that the

The address registers 29-50, the input and output device meeting the input buffer, access to the

memory 29-15 as well as the output buffer memory. These signals become the ent-29-18 also receive further signals from 5 speaking priority circuits over the line

the control units 29-80 to 29-83 of the various 29-102. Based on these signals as well as the

Address register and buffer memory. So z. B. from the relevant priority circuits 29-92 to

the control signals generated for reading from 29-95 and read out via line 29-104

Input buffer memory 29-15 or for the exchanged signals, a signal is sent via one of the

write into the output buffer memory 29-18 required lines 29-97 to 29-100 to one of the corresponding

are of the synchronizing devices to the control units 29-80, 29-81, 29-82 and 29-83 of the

the control units coupled to their corresponding address, address and buffer memory, which

register and buffer memory via lines 29-85 indicates that the associated synchronization device

switched on, the write signals for the unification being granted priority.

output buffer memory and the read signals for the output 15 Has z. B. the synchronization device 1 priority giving buffer memory over the lines 29-85 α received, a signal 29-86 α, 29-87 α, 29-876 and 29-88 α is transmitted over the line 29-97 to the address and buffer memory control unit. As will be described further below, 29-80 are switched on, whereupon this control unit couples a signal coupled to the 29-88 to the lines 29-85, 29-86, 29-87 and the signal to the line 29-110 Control signals is fed to the ao address register 29-50. On the basis of lines 29- * 5a, 29-86a, 29-87α, 29-876 and this signal, the address register reads the initial 29-884 generated, which takes the input buffer memory address from the information group from 29-15 or control the output buffers 29-18. which, together with the synchronizing device 1, is also output by the switched drum. These on function table signals of the encryption starting address would have previously been stored in the address register device 10-18 of the central processing system after the register had been cleared by a, which would have been connected via the line 29-90, which would have cleared the function table signal . In addition, the buffer memories are controlled by a synchronization selection signal from the operator through signals from the corresponding priority error register IR-I of the central processing system circuits 29-92 to 29-95, which was coupled via the 30 to the line 29-61. The An-lines 29-197 to 29-100 are transmitted. The start address is used by the central processing

Since it is possible for several input and output devices to simultaneously provide the memory to output devices via line 29-60, the address control unit 29-62 and via line 29-115.
control, the access to the memory must be controlled by prior The starting address to be read out will then be regulated. For this purpose 35 the address decryption device via the priority circuits 29-92 to 29-95 are pre-address control unit 29-62, the line 29-65, which control the sequence in which the address blocking control 29-69 and via the individual input and output devices access device 29-71. Is the controlled memory to memory received. Of course, must DA location not occupied, so the memory-free signal at the working at high speed inputs 4 ° MNB via conduit 29 to 116 to the address and is Auegabevorrichtungen and such. B. the drums, buffer storage control unit 29-80 switched on, where priority over all other input and output is indicated by that the controlled storage devices are given the opportunity to adjust the information that wrestle that information was read out as a result of overflow of the drum connected to the drum synchronizing devices 1 and 2 to be connected to the synchronizing device 1.
Ordered buffer memory 29-15 and 29-18 lost- Has the synchronizer 1 under entering. Since the drums normally cause more of the flow of information to be written into the memory on the line 29-85 α as a control signal that the information extracted from the drum for reading information from the memory is used in one of the input registers, the drum -Lesynchroni- 50 29-15 is written in, the priority and buffer memory control unit 29-80 is advantageously connected to the addressing device 1 via a control signal before all other input and output devices via the line 29-85. The control unit granted. Thereafter, the synchronizing device 29-80 causes the contents of the buffer rating 2, which was also written before the other input and output memories, which were previously written to input devices (with the exception of the synchronizing device) via the line 29-24 Reason one of the synchromesh 1) is given priority, since these other synchronizing apparatus 1 generated information on the line and output devices with low signals is read out.
process slower than the drums. The next priority in the synchronizing device 1 is then given the synchronizing digit counter indicates when the synchronizing device 3 has placed a complete word in the input band for reading or writing to 60 device 1, since the fourth buffer memory 29 assigned to the printing device -15 has been enrolled. As already mentioned nete synchronization device only at very low, a signal to the line speed can be operated. Turned on in 29-85, which indicates that the in-Fig. 29 shown synchronizing devices 1 output buffer memory located information out to 4 therefore have priority in the order of their 65 read and written in the memory reference numerals. target. This signal is used in the address and buffer

The exchange of information between the memory control unit 29-80 and evaluated via the

Memory and the various input and output lines 29-85 «of the corresponding memory unit

225

226

29-15 , whereupon the information located in this memory unit is read out and written into the memory in parallel via the main lines.

If the selected memory location is occupied so that it cannot be used by the synchronization device, the memory-free signal MNB, which is coupled to line 116 , is not generated.

chronizing device can again grant access to the memory during two consecutive time periods. In such a case, the repeated activation of the same memory location is prevented by control signals which are coupled to lines 29-56 and 29-57.

The address lock controller 29-69 operates in conjunction with a memory read signal control circuit located in the same block 29-69 .

testifies. The address and buffer memory control unit

therefore does not initiate the synchronization device either. This control circuit for the memory read signal scoring 1, which is located in the buffer memories 29-15, generates a signal on the line 29-73 which reads out the information. The synchronizer memory control unit is fed and indicates that

a read process is to take place in the memory. If this signal is not present, it is indicated that the control of the memory is always connected with a writing process. This memory read signal PYMR is generated by the signals appearing on lines 29-56, 29-57 and 29-55 , such as

In this case, device 1 only receives access to the memory when the previously controlled memory location has been vacated.

If the start address located in the address register 29-50 is sent via the line 29-64 to the address control unit 29-62 and via the line 29-65 to the address blocking control 29-69 and from there via the line 29-71 to the address decision ao transmission device, this address is simultaneously also fed to the address changing device 29-52 via the line 29-66, where it is changed in accordance with the address change controller 29-54 . This amendment ER- a $ input, the input buffer. A similar situation ensues on the basis of control signals that occur from the Iicher operational sequence when the input and synchronization devices were connected to line 29-55 and the priority circuit of that synchronization device to line 29-56 that was given priority. By the address change control, the address change means can e.g. B. be caused to change the address received via line 29-66 by adding the digits 00001 to this address. In this case, the new address would be one greater than the start address and would then be fed to the address controller 29-62 via the line 29-72. During this address change process, the address register - from which the address is destructively read out - is supplied with the address read out again via the address control 29-62. If the modified address is fed to the address controller 29-62 via the line 29-72, the starting address which has been stored again is removed from the reference numerals of FIG. 29 corresponding to the address register 45 and the modified address is stored and recorded. The priority switch shown in FIG. 30 or the start address remains stored in the address register, and the changed address is not taken into account, this process depending on the point in time at which a control signal at lines 29-93 and 29-92 are similar and are therefore the Line 29-110 is coupled. This control signal is not shown in detail because of its simplicity, in turn, depends on whether or not a successful control of the memory has taken place. This successful activation of the memory is indicated by the memory-free signal MNB on line 29-116 at 55-second intervals, the memory-free signal MNB, which occurs in its entirety in every 4-microsecond interval.

is described in more detail below.

The above general description of the operation of the distributor shows the normal process the events that occur during an input operation, d. H. if through an in and Output device information is transferred to the memory

Output devices receive information from memory. In this case, however, the information is not sent to the input buffer memory via the associated information lines, but to the output buffer memory 29-18 via the information lines 29-32, 29-37, 29-38, 29-39 and 29-40 in connection with fed to the assigned control lines.

The individual in FIG. 29 logical shown as a block diagram Circuit arrangements described in which the various control signals and information and Address signals are processed.

Priority circuits

FIG. 31 shows the priority circuit shown as a block in FIG. 29 for the synchronizing device 2. The connecting lines are in FIG. 31 through the

Device 29-92 is similar to the priority circuit 29-93 shown in FIG. The priority circuits 29-94 and 29-95 are also the priority circuits

The priority circuit for the synchronization device 2 has the task of determining whether the synchronization device 2 during the two 0.5 micro

indicates that the previously selected memory location was not occupied. If the memory-free signal MNB is not present on the line 29-116 and thus indicates that the memory was occupied, the address stored again in the address register 29-50 is retained while the modified address is lost.

The address lock control 29-69 prevents the dispatcher from accessing the same memory address again during two consecutive time periods. This measure is necessary because the priority circuits 29-92 to 29-95 of the same syn-

Short period for the control of the memory are made available before the other synchronization devices should be given access to the memory. These intervals are times t ₃ and t ₇ on the address line to the memory.

Like F i g. 31 shows the priority toggle switch

31-10 is switched to the setting state by the output signal of the AND circuit 31-12. The AND circuit 31-12 is opened by the signal 5 IRF and the clock signal ti, 6, provided that the blocking signal PID is not applied to the AND circuit. The clock signal ti, 6 appears during the second and

509 538/373

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228

sixth Vj microsecond intervals of each short period. The signal S 2 RF generated by the synchronizing device 2 is sent to the AND circuit 31-12 via the circuit shown in FIG. 29 shown line 29-102 coupled. This signal indicates that the synchronizing device 2 is requesting access to the memory. This signal is generated by the setting of the word interrogation toggle circuit 29-59 (FIG. 49) of the synchronizer 2.

Circuit 31-22 an output signal which is connected to the AND circuit 31-14 together with the clock pulse t2,6 , whereby the latter generates an output signal which the flip-flop circuit 31-10 resets either during the second or sixth clock time. This deferment then indicates that a particular device has gained access to the memory, and thus means that the synchronizer 2 will be out for the next 2 microseconds

Since the priority toggle switch 31-10 does not get access to the memory only through ao.

The flip-flop circuit 31-10 can also be connected to the OR circuit 31-22 and to the AND

the output signal of the AND circuit 31-14 generated at the time t ₂ or r _e can be reset, the result is that this flip-flop circuit 31-10 after it has been set by the AND circuit

Circuit 31-14 connected signals PZF or P4F can be reset. The signals P3F and

device 31-12 remains set for 2 microseconds 15 PAF indicate that one of the two synchronizing devices 3 or 4, which generates a lower priority, and thus in this time segment the signal PIF, which indicates that the synchronizing devices have access want to get to the store. facility 2 access to the storage facility is required. Since the flip-flop circuit 31-10 is designed so that the signal P 2 F , the AND circuit 31-16 is caused to produce a reset input signal by setting-on generation of the output signal P2A , so that the output signal is suppressed as long as the AND circuit 31-16 is not reset by the signal as long as a setting input PIF is present from the priority circuit 29-92 of the synchro signal. The flip-flop circuit 31-10 is blocked, which means that it is reset when the synchronizing device 2 shows that the one to be treated with higher priority no longer wishes to receive priority, which by synchronizing device 1 also access to 35 indicates the absence of the signal S2RF would require memory. If, on the other hand, the synchronizing device 3 is present at the AND circuit 31-16 and also the function table signal FT 820 of the
Encryption device 10-18 , it will
AND circuit also blocked. This function table signal FT 820 blocks the AND circuit 30
31-16, however, only if an address based on the program of the processing system
between the in F i g. 29 shown address register 29-50 and the register RP-I of the central

Processing plant is to be transferred. 35 postponed after their setting. The priority circuits for the other synchronizing devices are temporarily shut down until the new memory address is stored in the address register
has been.

The signal PIA, which indicates that the synchronizer 2 is given priority, is also coupled to the AND circuit 31-18 , whereby the delayed priority toggle circuit 31-20 is during either the first or fifth clock time

of the short period is set 45 by the clock signal i 1.5 , the signal PIF, which is shown in FIG. By setting this flip-flop, the AND circuit 31-16 blocks, in the other 31-20 the signal P 2 D is generated, which indicates priority circuits by similar signals for all that the synchronizing device 2 represented during the previous synchronizing devices, the previous ones Priority was given to the relevant synchronization device for 2 microseconds. This signal is again sent to the AND circuit.

device 31-12 , where it prevents the synchronizers 29-92 to

Flip circuit 31-10 during two successive 29-95 two signals are generated which are used for control of the following time segments of 2 microseconds each: the signals P 2 A and is set. This prevents the P 2 D. Both signals have a duration of at least synchronizing device 2 for two at least 2 microseconds. Similar signals P IA, PID, of successive periods are given priority again, P 3 A, P3 D, P4 A and P4D are generated by the others if no signal is generated by the AND circuit 31-14 , whereby the priority toggle circuit
31-10 is reset.

Normally, the flip-flop 31-10 is reset by the signal S 2 MD , which is from the in

or 4 access requested if synchronizer 2 was in the previous 2 microseconds Had priority and was given access to the store.

The delayed priority toggle switch 31-20 is reset by the same two clock signals, through which she was hired. Since these clock signals are delayed by 2 microseconds, the flip-flop 11-20 typically 2 microseconds

services, e.g. B. for the synchronizer 1, receive similar input signals, except that the input signals to the OR circuits corresponding to the OR circuit 31-22, which indicate that secondary synchronizers require access other than those shown in FIG Input signals differ depending on which synchronizer requires access. as well

Priority circuits generated. These signals are used for various control functions that will be described below.

F i g. 29, the address and buffer memory control unit 29-81 of the synchronizing device 2 is generated. As will be described below, however, this signal is only generated when an input and output device has received access to the selected memory location. By connecting the S2MD signal, the OR

Address and buffer memory control unit

The in Fig. Address and buffer memory controller, shown as blocks 29-80 for the synchronizer in FIG. 29 1 is shown in detail in FIG. This control unit provides the signals for the synchronization device 1 associated read control circuits of the address register and the signals for the connection of the read control circuit of the straight line

229

230

means 1 generated, which indicates that the odd buffer memory contains the information to be read out. The change signal, however, is generated by the signal SlF, which indicates that the buffer memory currently contains the relevant information. In order to generate the read or change signal, it is also necessary that, in addition to one of the signals SlD and Sl V , the signal SlMD and the clock signal ti, 2, S, 6 to the relevant

removed and the modified address is stored in order to use this way the address of the next to provide accessible memory location.

Since the buffers for the synchronizer 1 are input buffers, it must Address and buffer memory controllers 29-80 (Fig. 29) cause the information from Buffer memory in main memory over the line

and odd input buffer memory for the synchronizer 1 ready. Besides these signals,
which are used to control the aforementioned memories or registers is shown in FIG. 32
Arrangement still generates the signal SlMD , which
indicates that the selected memory location is not occupied and that a successful exchange of
Information between the memory and the input
and dispensers can take place. In addition, of the arrangement shown in Fig. 32, AND circuits will be turned on. The signal also generates the signal SIRFR , which indicates to the synchronizing SLMD that the device in question is fed to the feeding device 1 in order to be able to get its word handle to the memory. These clock interrogation flip-flops 46-59 (FIG. 46) also have a duration of one microsecond. and are during the cycle times t _x and t ₂ or t ₅

This is generated by the control unit 15 and f _{6 shown in FIG. 32.} These signals cause the generated signal SlAR is fed to the address register that the previously renewed address from the register via the line 29-110 (FIG. 29) is supplied to the
to turn on the synchronizing device 1 associated read control circuit of the address register.
This signal is the output signal of the OR 20
Circuit 32-30 generated by this when
at one of the AND circuits 32-12, 32-14, 32-16
or 32-18 the required coincidence input signals are present. That from AND circuit 32-12

The generated signal is fed to the OR circuit 32-30 and the AND circuit 29-31 (FIG. 29) and causes it to be stored in the address register.

End address located before storing a. For this purpose, the signal 51 RD resp.

read out new starting address and the memory SIR V the memories 29-15 via the in F i g. 29 is thus evacuated. This "clearing" signal is fed from the provided line 29-85 ". Generated by the signal of the AND circuit 32-12, when at its 30 SlRD , the read control circuit of the odd inputs, the function table signal FT 817 and register is energized, while the signal PSl is present at the same time through the signal SlRV. This radio control circuit for the read control of the even register antion table signal FT 817 is switched by the. It should be noted that the even coding device of the central processing registers and the odd registers are only generated in this way and the AND circuit 32-12 is used during the cycle times i ₀ and t _{7 in order to be able to distinguish them from one another} the line 29-90 as below in connection with the Re- (Fig. 29). The signal PS1 is described by gistera itself, if the S digit decryption device 10-31 these registers are only separate memory units (FIG. 10A) of the central processing system which are used one after the other. The signal to the AND circuit 32-12 via the 40 signal SLRD is connected to the OR circuit 32-20 line 29-61 (FIG. 29). This signal and the signal SlRV from the OR circuit PSl is the selection signal for the synchronizing 32-22 generated. The generation of these signals takes place device and indicates that the synchronization on the basis of output signals of the AND switching device 1 was selected. functions 32-16 or 32-18. The signals SlRD and

The AND circuit 32-14 generates the "read" and 45 SIi? F are therefore generated at the same time as the Regenerate «signal which is sent to the address register via read and change signals sent by the OR die OR circuit 32-30 is supplied. This circuit 32-10 can be provided. Read and regenerate signal is generated when OR circuits 32-20 and 32-22 generate

the AND circuit at the same time the clock signal is not only an output signal if the signal PIA transmitted by the ίθ, 3, 4, 7 and on the line 29-97 (FIG. 29) 50 AND circuits 32-16 and 32-18 output signals the priority circuit 29-92 are generated, but also when the AND are present. The read and regenerate signal has a circuit 32-24 and 32-16 respectively. For example, the evacuation signal generated by the AND circuit of the cycle times t ₇ and i _q or t ₃ and i _{4 is} generated by 32-24, the address from that part of the distributor 55 32-20 is coupled to the OR circuit, in order to read out the odd buffer memory address register which is to be cleared for the synchro. This signal is reserved by the AND switching device 1. This address is generated by device 32-24 when its inputs are then sent to the memory control unit in order to provide a fixed signal PS1 and the function table to determine whether the relevant memory location is occupied. signal FT 815 are present. The signal PS1 is renewed by the This address is renewed so that it is generated in the busy 60 decryption device 10A-31 and falls in the memory and when triggered again, it indicates that the synchronization device 1 has switched back to the centralization of the relevant memory location Processing plant has been selected. fortune stands. The function table signal PT 815 is on the other hand

The AND circuits 32-16 and 32-18 generate on the basis of the commands 53 and 55 , both of which generate the "read and change" signals, which are also fed to the connection of a synchronizing device to the OR circuit 32-30. Leave that on. In addition, the activation of the clock signal ti, 0 of the word counter 46-48 (FIG. 46) of the synchronization is required to open the AND switch read signal under the influence of the signal SID device 32-34.

231 232

The AND circuit 32-26, which provides the clearing signal which generates the read and regenerating signal, under the influence of the signal P 2 A and the clock signal for clearing the even register, is controlled by the signal PSl ί 0 at its input, 3, 4, 7 generated, the signal P 2 A from the pre-opening and the function table signal FT 815 being opened. Priority switching 29-93 via line 29-98 (FIG. 29) This opening takes place, however, under the influence of the 5 is transmitted. The output signal of the AND switching clock signal i3,4, so that the even register at a device 33-14 essentially corresponds to the point in time which is different from the time when the odd register is cleared is the output signal of the AND switching shown in FIG. This time difference is necessary because device 32-14. Differences in the input signals both registers have common output circuits for the OR circuit 33-10 compared to that, as will be described in more detail. OK OR circuit 32-10 (Fig. 32) results in this

The signal 5IMD, which indicates that the other controlled memory location at the AND circuit 33-15 (FIG. 33) is not occupied and that the read and change signal for the OR information is stored in the memory circuit 33-10 is provided. This read and cut-off is generated by the setting output. The memory change signal is generated by the AND circuit 33-15 ready toggle circuit 32-30 on the basis of an output 15 when the output signal of the AND circuit 32- 32 generated. Signal S 2 MD and the clock signal 1,2,5,6 are present. This AND circuit 32-32 sets the memory loading This read and decrease signal differentiates the flip-flop circuit 32-30 in its setting state, that is to say it differs from the same signal in FIG. 32, if at its inputs the signal PID from the priority circuit 29-92 as well as the memory-free 20 even and odd word count signals S2D and signal MNB from the memory control unit, which S2V (AND- Circuits 32-16 and 32-18 Fig. 32) indicates that the selected memory location is not present. This difference arises, of course, from is sets. By these two signals as well as the clock - the fact that the in FIG. 33 the control signal * 0.4 shown, the AND circuit 32-32 is opened. werk for an output buffer memory (29-18 in Since the memory-ready flip-flop 32-30 is provided by 25 Fig. 29), while the clock signals iO, 4 in Fig. 32 is also reset, you have provided control circuitry for an on-setting output signal SlMD a duration of delivery buffer memory (29-15) is provided. 2 microseconds. The signal is therefore z. B. during From the buffer memory shown in Fig. 33

of the cycle times t _t to i ₄ or i ₆ to i ₀ . From this control unit the control signals S 2 WD are generated and the AND circuits 32-16 and 30 S 2 WV are generated, which are used to connect the write 32-18 either during the cycle time t _t and i ₂ or control circuits of the the synchronizing device 2 serves an output signal associated with odd or even registers during the cycle times t _& and t _e. In this way, the signals 52 WD and S 2 WV are sent to the read-out control circuits of the buffer memory required buffer memories 29-18 (FIG. 29) via the Leiliche switch-on signal of a microsecond duration 35 fed to 29-86. These signals are provided by the opening of the AND circuits 33-20 and 33-22

The output of AND circuit 32-32 is generated. These AND circuits also correspond to the synchronizing device 1 as essentially the AND circuits 32-16 and 32-18, signal S IRFR via the line 29-85. except that at their inputs the signals 52D or This signal is present in the synchronizing device 1 40 52 V , through which a storage precedence to reset the word query toggle circuit is used in the odd and even registers instead of -46-59. The signal SlRFR is used to find out when there is access to the memory. So instead of the signal SlRF switched off, which the input signal 51MD the input signal priority toggle switch of the priority circuit S 2 MT is provided to switch the output signal compared to 29-92 in the setting state. The signal 45 in FIG. 32 arrangement shown by 2 micro- SlRFR thus indicates that the synchronizing device is to be delayed seconds. This additional delay 1 no more preferential access to memory of 2 microseconds is required in order to obtain the desired. from the memory and the input and output devices

The in Fig. Information to be transmitted, shown as block 29-81 between the main address and buffer memory control unit for the 50 memories and the input of the buffer memory off-synchronization device 2, is shown in detail in FIG. 33 can be exchanged. F i g. 33 is not shown. This control unit is in some back-up arrangement for the generation of signals, around which the one in FIG. 32 control unit shown to clear buffer memory, since such signals Belich. So z. B. the signal S2AR, which is already provided by the synchronizing device 2-AND circuit 33-10 (FIG. 33) to the read control 55.

switching on that part of the address register. The memory free flip-flop 33-30 corresponds

is coupled, which is reserved for the synchronizer 2 in all respects of the tilt shown in Fig. 32, under the influence of a clearing signal circuit 32-30 and generates a signal S 2 MD on provided. This clearing signal is generated by the AND reason of a signal of the AND circuit 33-32, the circuit 33-12, when the signals P52 and the function are coupled at the same time to the setting input of this flip-flop circuit at its inputs 60. Table signal FT 817 will be present from AND circuit 33-32, signal PS 2 also generating signal S2RFR, which indicates to the synchronizer that synchronizer 2 has been selected by controller 2 via the central processing system shown in FIG. Line 29-86 is applied to reset the word query evacuation signal of this AND circuit, therefore, corresponding to 65 flip-flop circuit 49-59 (Fig. 49). As essentially shown in connection with FIG. 32 and FIG. 33, the coupling of a written evacuation signal. In a similar way, the clock signal i0,4 the setting output signal S2MD is also the output signal of the AND circuit 33-14, via the AND circuit 33-38 to the setting

233

234

input of the memory transport flip-flop 33-40 coupled. The memory transport flip-flop 33-40 then generates a setting output signal S 2 MT which - as already described above - is connected to the input of the AND circuits 33-20 and 33-22.

This signal S 2MT has a duration of 2 microseconds, since the memory transport flip-flop 33-40 is reset by a clock signal t0, 4 which corresponds to the clock signal by which this flip-flop was set.

The address and buffer memory controller for the tape synchronizer 3 is detailed shown in FIG. 34. In some respects, this control unit is the same as that shown in FIG. 32 and 33 shown Control circuits for the drum synchronizers are similar except that for the belt synchronizers some additional signals are needed to perform a certain input and output function to be able to perform.

The in F i g. The OR circuit 34-10 shown in FIG. 34 as well as the line 34-12 and the AND circuits 34-14 and 34-15 correspond in terms of their functions and input signals to those in FIG. 33 AND circuits 33-12, 33-14 and 33-15 and the OR circuit 33-10 also shown there, except that the from F i g. 34 apparent input signals are provided for the synchronizing device 3 and that the function table signal FT 874 is generated in place of the function table signal FT 817 shown in FIG. The function table signal FT 874 is generated on the basis of the instructions 43 and 74 and has the same task as the function table signal FT 817 (FIG. 33), namely to clear the address register. Like F i g. 34 shows, the AND circuit 34-15 generates the signal 53 RFR when the signal S3MD and the clock signal ti, 2, S, 6 are present at its inputs. This signal S 3 i? Fi? is fed to synchronizer 3 via line 29-87 to reset the word interrogation toggle of that synchronizer.

The circuit arrangement shown in FIG. 34, which consists of the AND circuits 34-32 and 34-38 as well as the memory ready toggle circuit 34-30 and the memory transport toggle circuit 34-40, is that in FIG. 33 shown switching elements 33-32, 33-38, 33-30 and 33-40 similar. Also in Fig. 34, the signal S 3 MT is coupled as an input signal to the AND circuit 34-42, whereby this generates the signal S 3 ΒΛ when the clock signal t2, 6 is connected at the same time, which indicates that a buffer memory for a relocation of a further word is available because the relevant input and output device has been given access to the memory.

The signal S 3 RD, which is fed to the input buffer memory 39-16 via the line 29-87 in order to clear this memory, is generated by the OR circuit 34-20 when an output signal of the AND circuit is at its inputs 34-16 or 34-24 is applied. The AND circuit 34-24 generates an output signal when the function table signal FT 816, the signal P 3 A and the clock signal ti, 0 are simultaneously present at its inputs. The output signal generated by this AND circuit indicates that the synchronizing device 3 has been given priority over the other synchronizing devices, so that the buffer memory 39-16 can be cleared.

The other AND circuit 34-16 generates an output signal when the following signals are simultaneously present at its inputs: the signal S 3 MD, which indicates that the relevant synchronization device has been granted access to the memory; the signal S3 RBG from the synchronizing device 3, which indicates that a read operation is to take place; the signal S3 WCD which is the set output signal of the word control circuit of the synchronizing device 3 and which indicates that information is to be read out from the odd buffer memory 39-16; the clock signal 1 1,2,5,6 and the signal S3 WCAV from the synchronizing device 3, which indicates that currently none

is writing is in progress.

The OR circuit 34-22 generates the signal S3 RV which is applied to the read control circuits of the even buffer memory 39-14 via line 29-87. This signal S3RV is generated by the OR circuit when either a signal from the AND circuit 34-18 or a signal from the AND circuit 34-26 is present at its inputs. The input signal applied to the AND circuit 34-26, the signal t3, 4, is provided, so that the applied input signals, except that the signal i3,4 is provided as the clock signal, so that the evacuation of the even buffer memory 39-14 is not the same Time at which the evacuation of the odd buffer memory 39-16 takes place. This difference in time is necessary in so far as the buffer memories 39-14 and 39-16 have common reading lines.

The AND circuit 34-18 generates an output signal under the influence of input signals which are similar to the input signals applied to the AND circuit 34-16, except that the signal S3 WCV is provided in place of the signal S3 WCD. This signal S3 WCV indicates that the current buffer memory is to be used, since the last word was stored in this memory.

The AND circuits 34-24 and 34-27 generate the signals S3 WD and S3 WV, respectively, by which the read control circuits of the odd output buffer memory 40-20 and the even output buffer memory 40-18 are turned on, whereby in the content of the selected memory location can be stored in this register. The AND circuit 34-24 can be disabled by the signal W3CAV , which indicates that no write operation has been requested. If this signal W3CAV is not coupled , the AND circuit 34-24 is opened by the following input signals: the signal S 3 MT, which indicates that the relevant synchronization device has been granted access to the memory; the signal S3 WCD, which indicates that information is to be written into the odd buffer memory, and the clock signal ti, 2,5,6.

AND circuit 34-27 is controlled by signals similar to AND circuit 34-24, except that signal S3 WCV is provided in place of signal S3 WCD. This signal S3 WCV indicates that the next item of information is to be written from the main memory into the even buffer memory.

Address register

The in Fig. Address register shown as block 29-50 is shown in detail in FIG. This register consists of a 5-digit register

509 538ß73

235 236

for the 25 information units of the memory address pulse as well as in the reverse direction operated the next word, which is under the influence of the syn diode 35-33. The read control elements are norchronizing devices 1 to 4 written to the memory once by a 1 microsecond pulse or are switched out of this. This impulse is intended during the on that. The registers for these four synchronization devices are therefore contained in the microsecond half shown in FIG. 35 at the input of the write matrix 25 * 4. Like F i g. 35 shows, there is a control element of the relevant register part connected to the register for storing the address for the pelt, so that this write control element generates an output synchronizing device 1 from the cores 35-10, signal which is opposite to its input signal 35-11 and 35-12 , in which the first, the second or io is delayed by V * microseconds. In order to be able to alternately read out and write in the twenty-fifth information unit of the information, addresses are stored. For the sake of simplicity, the cores for the in the read control elements are controlled by signals formation units 3 to 24, which have been omitted from a ^ 4-phase clock for the sake of simplicity. Which are placed on the entrance. The write control elements are lines 35-17 to 35-19 occurring signals and 15, however, controlled by signals from a B-phase clock to the other (not shown) input transmitter. The B signals are compared to lines appearing signals are denoted by SMR (1 to the ^ signals shifted by 180 °. From the in 25) and correspond to the information F i g. 35 illustrated arrangement of the read and insert 1 to 25. The write control elements on the output lines can be seen that the signals occurring in a 35-23 to 35-25 are information contained with SAR ao line of cores during (1 to 25) denotes and also correspond to the information units 1 to 25 destructively out of a first microsecond half. The cores have been read and that identical winding arrangements (not shown) in the cores of the same row. Information during the subsequent second The cores and their individual windings are written in by half microseconds.
a circle and the associated lines are shown »5

SteDt. So contains z. B. the core 35-10 a write address controller
winding excited by the line 35-15. The address shown in Fig. 29 as block 29-62 when a signal is being controlled by the input amplifier 1 in Fig. 36 shows in detail where the line 35-17 is coupled, which represents a binary at block 36-10 the control circuit for the first "1" for the first information unit SMR 1 containing 30 bits of the address. The control circuit includes speaking. Upon coincidence of an on line 35-17, the AND circuit 36-12, the opposite due to the Nichtauftretenden output signal from the amplifier 1 with coupling of acting as a blocking signal radio to an output signal polarity of tion table signal FT 819, the first Informationsder write control circuit 35-21 is in the core unit of the address SAR 1 transmits. Inscribed a 1 during the 35-10. This 1 is left out of the 35 cycle times Z ₁ and t _s , this otherwise switched-on core 35-10 is not generated if the read function table signal FT 819 is not generated by the command 53 or 55 under the influence of the control circuit 35-20 by the signal 51 AR . The first in will. This signal 5 is IAR formation unit from the OR of the address is then generated at the circuit 32-30 and angekop to the read control OR circuit 36-14 as well as to the OR circuit scarf 35-20 via line 29-110 - 40 tion 36-16 coupled. That goes through this Anpelt. The output signal of the OR (read control circuit 35-20) resulting from the excitation of the read control member 35-20 coupling is a negative off circuit 36-14 is coupled to the input pulse shaping output signal on the read line 35-22, member 36- 18 forwarded. The signal SMR 1 generated by this pulse line for all of the address of the synchronization device 1 is then common to the associated cores. As a result of this 45 input amplifier 1 of the address register via the negative output signal, current flows through the in FIG. 29 line 29-64 shown , where read winding of the cores 35-10, 35-11 to 35-12, so it is renewed in the core from which the address that was read out on the corresponding output lines 35-23. Appear due to the delay up to 35-32 if an output signal in the input of the pulse shaping member is 36-18, the corresponding core a "1" is latched signal SMR 50 1 relative to the input signal SAR 1 previously. This is delayed by Va microseconds by the output amplifier. While the amplified from the output signal SAR (1 to 25). These comparable address register out read address in the same strengthened signals is stored back in each case one information unit cores again, so that they do not correspond to the address are then lost to the addressed, this address is at the same time the sensteuerwerk 29-62 (Fig. 29) via the Line 55 is fed to output pulse shaping element 36-21 via 29-64. As shown in FIG. 35, appears applied to OR circuit 36-16, where the signal on one of the read lines, such as e.g. B. the line 35-22, 5M51 is generated. This signal 5M51 becomes both a negative pulse when the content of these cores is to be read out to the address changing device 29-52 as well. Since the terminal is connected to the address lock controller 29-69. 35-20 normally at a positive voltage 60 This signal is also during the clock signal source, current flows through the resistor 35-32 t2,6 via the AND circuit 36-24 to the input and the diode 35-33 as well the corresponding ones of the OR circuit 36-16 are fed back so that there are resistors and diodes of the other core rows as opposed to that of the AND circuit 36-12 to ground. This current is interrupted and provided the original signal, the V2micro flowing through the read line, e.g. B. the read line is switched on for 65 seconds, a full microsecond 35-22 when the corresponding read control element is present.

35-20 is excited. This current flow results from a new address, which is made up of the values in the register RP-I

the negative contained five least significant digits generated by the read controller 35-20 and

237

238

is transmitted via terminals 14A-1G1 to 14A-5G5 , is entered in the address register via AND circuits, such as. B. the AND circuit 36-28 stored. The first information unit of this new address is represented by the signal PRA 1, which is coupled from the output lines of the register jRF-1 of the processing system shown in FIG. 14A (connection 14 A IG1) via the line 29-60 (FIG. 29) will. This signal is transmitted by the AND circuit 36-28, since the function table signal Fr818 is also applied to this AND circuit in the clock time I ₁ during the execution of a command 53 or 55 (connection of a synchronization device). This first information unit of the new address is then coupled via the OR circuit 36-14 to the input pulse shaping element 36-18 in order to form the signal SMR 1 there, which is the first bit to be newly stored in the address register via the bit shown in FIG Line 29-64 is fed. In a similar way, the remaining information units of the new address from the control circuits, such as. B. 36-40 and 36-41 controlled. The address changing device 29-54 provides the first information unit of a changed address, namely the signal SAM1, which is sent to the address register via the AND circuit 36-30 and the one shown in FIG. 29 line 29-72 shown is fed. Due to the simultaneous coupling of the clock signal * 3.7, the signal SA Ml is transmitted from the AND circuit 36-30 and fed via the OR circuit 36-14 to the input pulse-shaping element 36-18 in order to be there either at the clock time i ₀ or i ₄ to form the signal SMR 1. The other information units of the changed address SAM are controlled in a similar manner by the control circuits (e.g. 36-40 and 36-41).

An address in the address register can be stored in the five least significant digits of the register RP-I of the central processing system via the AND circuit 36-32. The signal SAR1 representing the first information unit of the address and the function table signal FT 821, which is generated during the cycle time J ₁ when one of the read commands 41, 42 or 43 are executed, are present at the inputs of this AND circuit 36-32. By connecting these two signals at the same time, the AND circuit 36-32 generates an output signal SAD 1, which via the circuit shown in FIG. 29 line 29-60 shown is coupled to the terminal 14 AI Hl of the register RP-I of the central processing system. The information units or bits of the five least significant digits are fed to the connections 14A-IHl to 14.4-5 HS , while the function table signal FT 821 provides decimal zeros for the remaining digits of the register RPl by inserting ones in the bit positions connected to the connections 14A -6A5 to 14A-12AS are connected.

In this way, the in FIG. 36 address control shown in block form the transmission circuitry for the first information unit of an address from the address register. These circuits thus control the storage of the address in the relevant bit position of the address register in agreement with clock signals and function table signals so that the Address either of the previously read address or of a new or changed address is equivalent to.

The control circuits for the other bits are of course those shown in block 36-10 similar. So are the control circuits for the second bit as blocks 36-40 and those for the twenty-fifth Bit represented as block 36-41. The control circuits for the information units 3 to 24 have been omitted for the sake of simplicity. All 25 bits of the address are in the address control is written in and read out in parallel.

Address change facility and control

F i g. 37 shows the address changing device (29-52, Fig. 29) and the control circuits (29-54, 29) for the changing device. The control circuits for the change of address are detailed in block 29-54 in FIG. 37 shown while the actual changing means is shown only as block 29-52 for the sake of clarity, since this device can consist of any number of adding and subtracting circuits are already known in the art. So z. B. the address changing device from a 5-digit special adder and subtracter that modify a five-digit address can by z. B. 00001 added or 00001 or 2499 subtracted, depending on what change is required for the operation to be performed by the synchronizer in question is.

Like F i g. 37 shows, the address changing device 25 has input signals SMS which correspond to the 25 information units which identify the memory location to be controlled. These signals are supplied to the address changing device via the line 29-65 shown in Fig. 29 and represent the signals generated by the output pulse shapers for the information units 1 to 25. These 25 information units, which designate the five digits of the address, are used in the address changing device modified under the influence of control signals. The control signals are generated either by the OR circuits 37-10 or 37-14 or by the AND circuit 37-12, depending on which change is to be made to the address. The signals generated by the address changing device are labeled SAM1 to SAM25 and correspond to the 25 information units of the changed address. These signals are coupled via the line 29-72 shown in FIG. 29 to the address control unit 29-62, where they form input signals corresponding to the information units 1 to 25 for the AND circuit 36-30 and the other, similar AND circuits.

The change process is controlled by the address change controller. In most cases, the value 00001 must be added to the address for such a change. This addition is controlled by the signal SNF which is connected from the OR circuit 37-14 to the address changing device. This signal SNF is generated on the basis of an output signal from one of the AND circuits 37-16, 37-18, 37-20 or 37-22 if the clock signal ti, 2,5, 6, the priority signal, is simultaneously applied to one of these AND circuits as well as that

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Operating mode signal is present. So z. B. the AND circuit 37-16 generate an output signal when there is coincidence between the following signals at its inputs: the clock signal 1 1,2,5,6, the signal PIA, which indicates that the synchronization device 1 has received priority, and the signal 51Ml, which is generated by the mode 1 flip-flop circuit 40 (FIG. 46) of the synchronizing device 1 and indicates that this synchronizing device is operating in mode 1

The AND circuit 37-18 works in principle like the AND circuit 37-16, since the first two synchronizing devices to which the AND circuits 37-16 and 37-18 are assigned, require that the address by adding the value 00001 is changed when these synchronizers are operating in mode 1.

The AND circuit 37-20 is assigned to the synchronizing device 3; this AND circuit generates a signal for the OR circuit 37-14 when the synchronizer 3 has been given priority, which is indicated by the signal P 3 A , and when the synchronizer 3 generates the signal 53Fl, which indicates that it performs a read or write operation in the forward direction.

A signal is coupled from the AND circuit 37-22 to the OR circuit 37-14 when the printing device has been given priority, which is indicated by the signal PAA. The printing device can operate in such a way that the only change that has to be made is to add the value 00001 to the previous address; no operating mode signal is therefore required for the AND circuit 37-22.

The signal SNB controls the address change means 29-52 when it must subtract the value 00001 from the previous address. Such a subtraction is necessary for reading in the reverse direction. The signal SNB is generated by the AND circuit 37-12 when the following signals are simultaneously present at its inputs; the signal P 3 A, which indicates that the synchronizer 3 has been given priority for reading and writing to tape; the clock signal ti, 2, S, 6 and the signal 5 "3Bl from the synchronizing device 3, which indicates that a reverse reading is currently taking place.

The signal SNA is generated by the OR circuit 37-10 and indicates to the address changing device that the value 2499 should be subtracted from the previous address. This signal is generated by the OR circuit when a signal from the AND circuit 37-24 or 37-26 is present at its inputs. So z. B. the AND circuit 37-24 a signal for the OR circuit 37-10 if there is coincidence between the following signals at its inputs: the clock signal ti, 2,5, 6; the signal PIA, which indicates that the synchronizer 1 has been given priority; the signal Sl M 2, which was generated by the mode 2 flip-flop 41 (Fig. 46) of the synchronizing device 1 and indicates that this synchronizing device is operating in mode 2, and the signal 51524, which indicates that the flip-flop »minus 2.499 « 45-17 (Fig. 45) is set.

The AND circuit 37-26 essentially corresponds to the AND circuit 37-24 and also has similar input signals, these input signals, however, being assigned to the synchronizing device 2.

From the description it follows that an address is normally changed by adding the value 00001 is added to the previous address. In this way, the memory locations are controlled one after the other when the input and output devices are operated in the forward direction will.

ίο Conversely, 00001 must be deducted from the address when the input and output devices operate in the reverse direction. In this The memory locations can be accessed in reverse order.

The change, in which the value 2499 is subtracted from the previous address, is connected with the drum stores. There are in each drum belt of the present computer system 2500 words stored. So if an exchange of information between the memory and the If drumming is not to begin at the beginning of the tape, but at a different point, it must be when it is reached of the end of the tape uses the memory address for the information associated with the start of the tape

as will be. To do this, however, the value 2499 must be taken from the last memory address to be subtracted to the first memory address of the consisting of 2500 words Group to arrive.

Address lock and memory read signal control

The address lock and memory read signal control shown in FIG. 29 as blocks 29-69 is shown in detail in FIG. This control includes AND circuits 38-10, 38-12 and 38-14 and other AND circuits (not shown) which couple the 25 information units of the memory address in the form of signals 5MS1 to SMS 25 to the address decryption device. The transmission of these signals is caused by the generation of the output signal PYMS of the pulse shaping element 38-18. This signal is generated by the pulse shaping element when a signal from the OR circuit 38-20 is present at its input. This signal of the OR circuit is in turn generated by an output signal of one of the AND circuits 38-21 to 38-24 which are assigned to the synchronizing devices 1 to 4. At the inputs of the AND circuit 38-21 is z. B. among other things, the signal P IA , which indicates that the synchronization device 1 has been granted priority. The presence of this signal and the clock signal rl, 5 causes the AND circuit 38-21 to generate a signal for the OR circuit 38-20, provided that the blocking signal 51MD is not applied to this circuit at the same time. This blocking signal 51MD is intended to prevent the same memory location from being accessed again if the same synchronization device was granted priority during two successive priority periods of 2 microseconds each. At the AND circuits 38-22, 38-23 and 38-24 similar input signals are present, which are provided for the other synchronizing devices and perform the same tasks as the input signals to the AND circuit 38-21. Since the clock signal 1 1.5 is applied to all AND circuits 38-21 to 38-24, among others , the signal PYMS appears at the clock times t ₂ and t _e

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AND circuits 38-10 to 38-14, so that the synchronizing device, which controls an input device information units SMS1 to SMS 25 of the address, is a buffer memory control unit (29-80 of these AND circuits during the mentioned to 29- 83) assigned, the two buffer memory th cycle times to the address decryption controls, so that the memory of the individual synchronization direction are transferred and the main memory 5 nizereinrichtungen are used alternately during the cycle times t _ä and t ₇ lock. can. So while z. B. in the odd memory

If the main memory is supplied with an address, rather a word is written in, the word located in the memory which is so required by the logic circuits of the memory waits to be read out of this memory - as will be described elsewhere - and into the main memory that the memory it is communicated whether a read or OK is to be stored as soon as the priority for the write process is to take place. This message assures that this process is available. If the word is fully followed by the signal PYMR 2, which is constantly stored in the odd memory, the AND circuit 38-26 is generated, if information is up to then also the betion in the even buffer memory read out from the memory and a sensitive one Information to be transported to the main memory transport output device. This has been 15 animals; the next word is thus then written into the signal is generated by the AND circuit 38-26, even buffer memory. At this point, if the signal PYMS is present at its input, it should be mentioned again that the terms "un- and if this AND circuit is not by the straight line" and "even" are only used to distinguish the output signal of the AND circuit 38-28 or by which the signal PIA is respectively assigned to a synchronization device. The AND circuit 20 th two buffer memories are used and 38-28 provides a locking signal when the synchro- otherwise have no further meaning. The in F i g. 39 nizing device 3 priority was granted. In the even and odd buffer memories shown, the AND circuit P 3 A and 39-10 and 39-12 represent the two half memories, the signal S3 RBG from the synchronizing device of the synchronizing device 1, that is to say the circuit 3 indicating that there are 25 mel read synchronizers assigned from this tape. Synchronizing device carries out a read operation, on the other hand, the even and odd memories are carried out. 39-14 and 39-16 of the synchronizer 3,

By the signal PXA, which indicates that the synchronization device assigned priority, ie the synchronization device 1 given priority for reading and writing to tape before drum read synchronization device 1. Which has been admitted, the AND circuit 38-26 is locked, so that the signal PYMR 2 is not generated when a read process in connection with the tape can be performed. This tells the memory that it should take place. For write operations, these are that a write operation is to be carried out. Output buffer memory 29-18 is provided. The puff

The signal PYMR 2 is generated by the AND circuit ferspeicher or register 39-10, 39-12, 39-14 and during the clock times t ₂ or t _e , since at 35 39-16 are constructed essentially the same, one of the Inputs of this AND circuit the Si- F i g. 39 shows one half of these registers, namely PYMS is present. The signal PYMR 2 is borrowed the part for the digits 1 to 6. For the purpose of club memory control unit via the in F i g. 29 are fed to the connection line 29-73 in these half registers. genes for numbers 3 to 5 have been omitted. As

40 has already been mentioned above, the other half

input feed storage register for the individual synchronization devices,

The information units shown in FIG. 29 as blocks 29-15 which are required for the storage of a total of 60 information buffer memories are shown in detail in FIG. 39 and are shown in a similar manner. This figure shows one half of a structured. The cores, such as B. the cores 39-18 to such buffer memory, while the other half 45 39-22, are only shown in the form of a symbol, since it is in the structure of the illustrated; the details of their windings are away-half equivalent. A full input buffer has been left. These symbols correspond to those in memory contains 60 magnetic cores for the 60 informa- F i g. 35 symbols are used for the cores of the unit units and is provided with a special input address register. You have essentially connected diesel synchronizer. The memory has read and write functions like the cores described in Merits as a buffer memory for the information integration with FIG be transported. In the case of elements with a special signal input and the input devices described here, the output of the read control elements does not relate to the information in series, ie one digit each consisting of five information units in the case of the address register in FIG. 35, all at once that is. So z. B. the write control member 39-25 is stored. The reading out, however, is controlled by the signal SlWVl , which is controlled by the parallel way, so that the information synchronizing device 1 is provided to the memory and controlled by tion via the main lines in the form of 60 parallel a clock with B-phase to in lelen information units is supplied. The inputs 60, the cores 39-18 to 39-22, the five information input buffers are therefore designed in such a way that units of the first digit are to be written in, from which they convert serial information into parallel information. Input buffer memory 39-10 via line 29- 24 your ability. were delivered after this information input

Most of the units described in this invention by the individual information line input and output devices can amplify the input amplifiers associated with the series are at relatively high speeds. That way, the first digit in the The first group of cores of the register 39-10 entered between the individual words small time intervals are provided. Everyone saves. The five information units appear

243 244

the second digit at the input amplifier, so the register 40-22 represents only a half register, the signal from the synchronizing device 1 represents the other half of which is constructed identically. SIWV 2 is coupled to the write control element 29-28. A word is sent from the output buffer

pelt, so that these information units of the second main memory via the main lines and 60 digits in the cores 39-29 to 39-33 of the register 5 AND circuits, which are written to the AND circuit 29-36 39-10. These signals, as they are similar, are in the form of 60 parallel pieces of information. B. SlWVl and S1WV2, which are supplied to the selective onion units. This AND circuit write the digits into the individual digit positions. 29-36 transmits the address to the clock times t _s cause, are generated by a digit counter and t ₇ by means of a connected clock signal ti, 4 of the synchronizing device, which is transmitted to the relevant the intermediate pulse-shaping element at the input and output device, in this case the line 29-32. This 60 parallel information of the synchronizer 1 is assigned. Post units appear as input signals PMR 1 up to and including all twelve digits in register 39-10. PMR 60. F i g. 40 shows the signals PMR 1 to PMR S stores and the synchronization device 1 priority PMR 6 to PMR 10 and PMR 46 to PMRSO, which has been granted access to the memory, before the information units of the numbers 1, 2 and 10 allow this l microsecond signal SLRF, that of represent. At the same time, FIG. 40 shows the cores in the OR circuit 32-22 of the buffer memory - in which these information units are stored - control unit 29-80 generates the information. The memory cores for the digits 5, 6 and 9 are tion, those in cores 39-18 to 39-22 and 39-29 are arranged in a similar manner and are for clarity up to 39-33 as well as in the remaining 30 information paths not shown in the drawing. The cores assigned to the half-register 39-10, whose half-register for the synchronization equipment is contained, at the same time via the output channels 2, 3 and 4 contain the cores for storing stronger OAl to CM30 in the form of signals SW1 of the digits 3, 4, 7, 8, 11 and 12. These are read out in pairs up to SW 30 . In a similar way, the storage of digits causes the same signal SIRV for the processing that the information contained in the other 25 of α-numerical information and (not shown) half registers is advantageous if ten information units are required, mation in the form of signals SW 31 to SW 60 around the individual characters of the α-numeric information is read out. These signals SWl to SW advertising to identify mation 60th The 60 information is transmitted via the line 29-30 to the AND circuit means a 29-31 read out from the main memory (Fig. 29), from where it is transmitted via a 30 word to the input amplifier IA 1 to the pulse shaping element and the main lines to the IA 60 coupled, which are common to the cores, get main memory. If the current register has been filled with one word, the corresponding information units for the one 39-10 are waiting for this particular synchronization device to be saved. This register on the signal 5 Ii? V, so that the input signals in the register can be selectively assigned to the synchronizing device that is correct for an existing piece of information transported to the memory, the twelve digits of the post-cores are stored, with this storage being stored in the input device by the control of the write control elements for the words in the cores of the odd register 39-12 in Fig. 40 depends. This is how you write, one digit after the other. B. the write control member 40-30 of the register ren in accordance with the signal of the digits 40 40-18 controlled by the buffer control unit 29-82, counter of the synchronizing device. In a similar way, so that in the cores of the register 40-18 only information-wise work the synchronizing device 3 tion for the synchronizing device 3 associated registers 39-14 and 39-16. nete input and output device em is stored.

As the digits of a word that is from memory

Output buffer memory ^{4S transported to} one of the output devices

is fed to this output device in series

The in F i g. 29 must be shown as block 29-18, the information that is in the output buffer memory is shown in detail in FIG. Figure 40 shows groups of cores of the output buffer. In this Fig. 40, the current register is included, sequentially from signals such as e.g. B. 40-10 and the odd register 40-12 each half-50 S3RV1 and S3RV2, read out, which represent the registers that excite the synchronizer 2 pull-read control elements 40-32 and 40-33. Are arranged. Both registers are shown in FIG. 40 as a block in this way, each of the five pieces of information 40-14 are represented. This block shows a first and second digit arrangement consisting of registration units, which corresponds to block 40-16, which is read out one after the other. Contains the signals for the even register 40-18 and the odd Re- 55 S3RVl and S3RV2 as well as the other signals for registers 40-20 . The even register 40-18 and the excitation of the read control elements of the output of the odd register 40-20 represent the two half-buffers are represented by the digit counters of the registers that are generated and rearranged by the synchronizing device assigned to the synchronizing device 3. The other halves of these registers correspond to these numbers for the output devices in series speak the registers 40-10 and 40-12 and 60 are to be read out. To read out these digits are not shown for the sake of simplicity. The syn- den uses the same output amplifiers as chronizing devices 2 and 3, so two outputs are z. B. the amplifiers 40-40 to 40-44, which are assigned to the signal registers, while the synchronizing signals S3LBl to S3LB 5 only provide an output register 40-22 direction 3 for the synchronizing device 4. assigned. For those with the synchronizer 65.

direction 4 connected printing device is only operation of the distributor

a register is required because the printing device The in FIG. 29 to 40 illustrated operation of the

is operated at low speed. Also, the distributor is best used in conjunction with the

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41 and, in connection with cycle time t _5, a signal which is understandable at the setting input in FIGS. 29 to 40. The time diagram shown in FIG. 41 for the delayed priority flip-flop 30-20 shows the time sequence is switched so that this flip-flop circuit has the same effect as the duration of the various signals. The generated in the signal PID , the areas also hatched in the memory timing diagram represent the 5 control unit and also represent signals as a blocking signal that are generated in connection with the synchronization to the input of the AND circuit 30-12, while the free leads is, so that due to the next time-off areas in connection with the synchronizing section i ₆ no priority is granted, although the device 2 represent generated signals. The radio signal SIRF is still present, provided that the Kippschaltionabelleensignals F are not reset in the form of blocks representation 30-10 by a reset signal, which are hatched vertically. is provided.

The cycle times i ₀ to t ₈ are shown in the timing diagram in The signal P IA is sent to the address and buffer F i g. 41 shown five times, each of these five memory control units 29-80 being supplied via the line 29-97 and time segments with a duration of 2 microseconds. This signal is used to open the AND corresponds to the time segments in which the priority 15 circuit 32-14 is determined again at its inputs. to which the clock signal t0,3,4, 7 is still present. By the

In the case of the signals shown in the timing diagram, the output signal of this AND circuit 32-14 is assumed that the synchronizing devices 1 causes the memory address register, which are currently and 2 are already in the process of being read or currently in which the synchronizing device 1 is assigned -Write process in connection with their allocated part of the address register to carry out stored drums. The further address will be read out and renewed. It is assumed that both synchronizers are made by the OR circuit 32-10, which are simultaneously requesting access to the memory; this the signal SIAR in this case during the clock simultaneous access is generated by the presence of the times t ₃ and t _{t of} the first priority period. Signals SlRF and S 2 RF as setting output 25 So a 1 microsecond signal SlAR signals of the word query flip-flops 46-59 via the lines 29-110 to the address register (Fig. 46) and 49-59 (Fig . 49) shown. These 29-50 are coupled, where the read control element 35-20 signals begin with the clock time t ₂ , shortly before that initiates the priority period contained in the cores 35-10 to 35-12. read out the necessary information and the 25 signals

These signals SlRF and S2RF are output signals to AND circuits 30-12 and generate as input 30 SAR1 to SAR2S during the clock time t _s. These 25 signals represent the 25 information 31-12 of the respective priority circuits 29-92 units of the memory address, which the Syn and 29-93 are coupled. It is assumed that the chronizer 1 tries to control
the AND circuit 30-12 by the signal SIRF The signals SAR1 to SAR 25 are opened via the and during the clock time t ₂ applied clock 35 line 29-64 to the address control unit 29-62 signal t2, 6 is opened. Since during the cycle time t ₂ leads where they circuits input signals for the AND Steuerdas PID signal as a blocking signal to the AND general arrangement of the individual information units dartung 30-12 is not present, generates these AND formwork filters (AND circuit 36- 12). This information provides an output signal that switches the priority toggle units of the address to the setting state during the clock circuit 30-10. 40 times I ₁ and t ₅ by an AND circuit, such as. B. The absence of this signal PID indicates that the AND circuit 36-12, transmitted, except when the synchronizing device _{1 has} the priority period of 2 microseconds that was started during these clock times ^ 1 and t _{5, ie when the opposite is not present} Priority was granted. By setting the currently executed command to clear the Reder priority toggle circuit 30-10, the signal 45 gisters is requested. The output signal of the AND switch PlF is generated. This signal is shown in the timing diagram 36-12 is applied to the input of the OR circuit and begins with the clock time t ₃ , since the priority 36-14 is coupled, which in turn is a signal for the trigger circuit 30-10 a delay one providing the input pulse shaper 36-18 resides in half a microsecond. 25 which generates the signals SMR1 to SMR 25th

As shown in FIG. 41, the signal S2RF is also 50. B. during the initial clock time t ₂ , but has 36-12 in the AND circuit, the synchronization device 1 priority OR circuit 36-21 is also transmitted in this case and as a result of the compared to the synchronization device 2. To the clock signals 12, 6 at the AND circuit 36-24 via synchronization device 1, this priority is given to the output pulse shaping element 36-21, the transfer, the AND circuit 31-16 is controlled by the 55 device 36-26 and the AND circuit 36- 24 locked again in signal PIF , so that it is brought into circulation despite the generation of the. In this way, the off signal P2F, the signal P2 A is not generated. output signal of the OR circuit 36-16 stretched and

The setting output signal of the priority becomes a 1 microsecond signal, which in the flip-flop circuit 31-10 generates the AND circuit during the clock times t _e and t ₇ 30-16, the signal P 1 ^ 4, which indicates that the Syn-60 is generated. This signal is when the SMS1 chronizer 1 signal was given priority. As shown up to SMS 25 , the information 25 showing the timing diagram in FIG. 41, the signal units of the P IA output from the address register begins with the clock time t ₃ . read address of the address changing device

This signal P ID is not only passed through line 29-52 as well as address lock control 29-69

29-97 to the address and buffer memory control 65 the line 29-65 is fed,

plant, but is also the AND- From the above description is evident-

Circuit 30-18 together with the clock signal ti, 5 borrowed in what way a device in this

fed. This AND circuit then generates the synchronization device 1 in the event that priority is given

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and how the memory address located in the address register for the synchronization device in question is read out in order to generate both the signals SMR 1 to SMR25 for the regeneration of the address and the signals SMS1 to 5MS 25 for the readout of the address.

The signals SMR 1 to SMR 25 are connected via the line 29-64 to the address register 29-50, where they are amplified by the input amplifier and generate information pulses on the lines 35-17 to 35-19, which are again fed into the cores 35- 10 to 35-12 are restored when the read control element 35-21 generates the negative output signal required for this due to the excitation of the read control element 35-20. Since the read control element 35-20 is excited by the signal Si AR at the cycle times t ₃ and t _i , this read control element generates a signal which appears at the cycle time t _s . The output signal of the write control element then appears at time t _e . In this way, the address is stored back in the register at time i ₈ .

The signals SMS1 to SMS 25 are fed to the address changing device 29-52 via the lines 29-65 and 29-66. These signals are also passed to the address lock controller 29-69 on line 29-65. On the basis of the signal PYMS generated by the pulse shaping element 38-18 , the address blocking control transmits the signals 5MS1 to SMS25 via the AND circuits 38-10 to 38-14. This signal is generated by the signal Pym PIA and the clock signal 1 1.5 in the simultaneous absence of the signal SIMD and thus appears during the clock time t _e of the first priority period.

The signal PYMR 2 of the AND circuit 38-26 is suppressed by the signal PIA. The absence of this signal PYMR 2 indicates that a write operation is to take place in the main memory.

The signals 5MSl to SMS 25 are fed to the memory control unit via the address line, and if - as will be described elsewhere in connection with the memory control unit - the memory location identified by the information units SMSl to SMS 25 is free, the distributor is sent at cycle time t ₀ the memory-free signal MNB is supplied to the second priority period. Simultaneously with the generation of the above-mentioned signals, the signal FlD is also generated and fed to the address and buffer memory control unit 29-80 via the line 29-97 so that the AND circuit 32-32 can be opened when the memory-free Signal MNB and the clock signal ίθ, 4 are present. In this way, the AND circuit 32-32 is opened at clock time / _{0 of} the second priority period and generates the signal SlRFR, which is fed to the synchronizing device 1 via the line 29-85, whereby the word query toggle circuit 46-59 in this synchronizing device is reset will. This word interrogation toggle originally generated the signal SlRF, which indicated that the synchronizer 1 requested access to the memory. The signal 5 IRF thus disappears after the clock time f _{0 of} the second priority period. It should be noted that the signal PIF disappears after the clock time t _{e of} the first period, since the priority flip-flop 30-10 is reset by the clock signal 2.6, if this signal is simultaneously with one at the input of the OR circuit 30-22 pending signal, such as B. the signal F2F occurs. This signal F2F was generated by the setting of the priority flip-flop circuit 31-10 at the beginning of the clock time i _{s of} the first period. In this way, the priority flip-flop circuit of the synchronization device 1 is reset in order to switch off the signal FIF during the clock time i _{7 of} the second short period.

As a result of this signal FlF being switched off, the AND circuit 31-16 is opened by the signal F2F. This AND circuit then generates the signal F 2 A during the clock time t _{7 of} the second period. This signal switches the delayed priority toggle circuit 31-20 to its setting state, since the AND circuit 31-18 is opened during the clock time I _{1 of} the second period and the signal F2D is generated at the start of the clock time t _{2 of} the second period . With the generation of this signal F 2 A , the synchronization device 2 is given priority. This award was made on the basis of the fact that no priority was granted in the previous time period of 2 microseconds and that other synchronization devices superordinate to this synchronization device do not require any priority.

As shown in FIGS. 30 and 31, the priority flip-flops 30-20 and 31-20 are reset, so that the signals FID and F2D disappear during the clock times t ₂ and t _{6 of} the second and third periods, respectively. In this way, both signals have a duration of 2 microseconds.

The signal F2F is only switched off when the priority flip-flop circuit 31-10 has been reset on the basis of an input signal S 2 MD applied to the OR circuit 31-22. In the present case, the signal F3F or F4F is not present because the synchronizing device 3 and 4 have not requested any priority. The signal S2MD is generated by the memory-ready flip-flop 33-30 when this flip-flop is set by the signals F 2 D, MNB and i0,4. As the timing diagram shown in FIG. 41 shows, the signal S2MD occurs at the beginning of the clock time f _{5 of} the third period. Since the memory-ready flip-flop 33-30 is reset by the clock signal 1 0.4, the signal S 2 MD disappears after the clock time t _{0 of} the fourth period.
Similar to the case of the synchronizing device 1, the signal S2RFR, which represents the output signal of the AND circuit 33-32, is fed to the synchronizing device 2 via the line 29-86. This signal resets word interrogation toggle 49-59 which initially generates signal 52 RF. In this way, the signal S 2 RF is switched off after the clock time t _{5 of} the third period.

By setting the memory-ready flip-flop 32-30, the signal SlMD is generated, which indicates that the synchronization device 1 has been given priority and that the corresponding memory address was sent to the memory control unit, which was generated by the generation of the memory-free signal MNB indicated that the selected memory location was not occupied. In this way, the signal SlMD can be used to generate the read signals through which the word stored in the corresponding buffer memory is extracted.

249 250

read and fed to the main memory via the main lines, the simultaneous coupling of the signals 51MD, gen. Assuming the 5ID and ti, 2, 5,6 is opened. This AND-switching line register 39-10 was last fully stored, the device then generates the signal SlAR, which is the signal 51MD as a result of the simultaneous on-OR circuit 32-10. This switching of the signal SlV from the synchronizing 5 signal SIAR is then coupled via the line 29-110 to device 1 and the clock signal 11,1, S, 6 of which the read control element 35-20, whereby AND-Schaltunig 32-18 transfer. The output the information signal contained in the cores 35-10 to 35-12 of this AND circuit 32-18 passes through the mation during the clock time t _{s of} the third short-OR circuit 32-22 and generates the signal period is read out. The address that is on 5Ii? V during the clock times t _t and t _{2 of} the second io the way in the form of the signals SAR 1 to SAR25 period. This signal SlRV is read out from the input, appears at the cycle time t _s in the buffer memory 39-10 of the memory 39-15 via the AND circuit 36-12. Since the function table line 29-28 is supplied, where it causes the read control element signal FT 819 to this AND circuit only while the signals SW1 to SW 60 on the line of cycle times t _x and t _{5 are} not present, this remains tion 29-30 at cycle time * ₃ . This 60 par-15 AND circuit is blocked, and the old address is lost, and all of the information units are consequently lost.

the equilateral coupling of the clock signal 1 3, 7 The write control element 35-21 then writes the

to the AND circuit 29-31 to the main line modified address at clock time i _{4 of} the third

are transmitted and appear there at clock time i _{4 of} the period.
third period. 20 As in F i g. 32 shows, the memory free signal becomes

If the memory control unit has not returned successful activation of the memory MNB , this must be derived from the address register if the address originally stored for the synchronization is changed. Normal device 1 controlled memory location is occupied. In this case, the AND circuit 32-32 would not have to open the address 25 and the memory-ready-toggle would have to be changed by adding the value 10000 to the upstream connection 32-30 would therefore also not be added to the outgoing address set so that on can be added. As a result, the signal of the drum in series arranged words in one SLMD would not be generated, and the two AND-other storage locations in the memory stored. Circuits 32-16 and 32-18 could not be opened. How to turn 30 elsewhere. Therefore, the content of the has not been described, the signals SMS1 to buffer memory 39-10 are read out, and the SMS 25 when reading out the address of the address during the clock times t _t and t _{2 of} the second period changing device supplied under the An appearing signal SIAR for reading out the flow of the address change control unit 29-54, the old address and writing in the new address would be changed in the desired manner, ie in 35 likewise not generated. As a result, the value 000001 would remain added to the address in this case - the old address would still be added in cores 35-10 to 35-12 of the. Address register stored to a second time

The signals SMS1 to SMS25 are considered to be able to be used when the synchronizing block in FIG. 29 and 37, the address changing device 1 shown is again given priority,
approximation device 29-52 by the control signal SNF 40 from F i g. 32 it can also be seen that the out of the OR circuit 37-14 is modified. This signal output signals of the AND circuits 32-16 and 32-18, SNF is generated when the signals PIA and 51Ml on and off at the same time on the AND circuit which, via the OR circuit 32-10, the read 37-16 5 Generate IAR , only then lie. The signal SNF thus appears during the occurrence when the synchronization device 1 generates the clock when the signals SMS1 to 5M525 at 45 signal 51 D or 51 V and thus indicates that the address changing device 29-52 is present. one of the registers is fully saved. To carry out an address change, the AND circuit 33-15 for the synchronizing device address changing device z. B. 2 microseconds 2 generated read and change signal depends on the need. It then generates the 25 information not from a read signal, because the output units of the changed address in the form of 50 buffer memories, the synchronization device 2 signals SAM1 to SAM2S. In the present case, these signals SAM1 to 5yiM25 are controlled by the output information during the signals of the memory. Therefore, only clock time i _{3 of} the third period is generated and it is necessary to use the signal 52MD to send address control 29-62 via line 29-72 to determine whether access to the memory has been granted. There these signals 5 ^ 4Ml to 55 are finally read out before the address and can be changed during the clock time t _{a of} the third period.

from the AND circuit 36-30 and then, as has already been mentioned elsewhere, the priority circuits are formed via the OR circuit 36-14 to the input so that the pulse shaping element 36-18 is switched on. Then synchronizing provide this input 2 priority nachgangs pulse shaping member 36-18 60 generates the synchronizer 1, a cycle time for the signals SMR1 to SMR 25. These signals SMR 1 transmission of information to the memory for up SMR 25 are then the address register 29 -50 was made available. The synchronizing device is fed via the line 29-64, where it controls the memory during device 2 for the purpose of access in approximately the clock time t ₄ by the write control element 35-21 in the same way as the synchronizing device 1, in the memory cores 35-10 to 35-12 written 65 except that the buffer controller will not read. As FIG. 32 shows, the signal SlAR signals as in the case of the synchronizing device 1, during the cycle times t _t and t _{2 of} the second short but write signals, such as. B. the signal 52 WV, period generated because the AND circuit 32-16 generated by. However, Fig. 33 shows that the write signals

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not by the signal S 2 MD, but z. B. generated by the AND circuit 33-22 , at whose inputs the signal S 2 MT, the clock signal 11,2,5,6 and the signal 52 V from the synchronizing device 2 are present. Since the signal S 2 MT represents the setting output signal of the memory transport trigger circuit 33-40 and is generated by the opening of the AND circuit 33-38 as a result of the signals S 2 MD and t0,4 , the signal S2MT corresponds to the signal S 2 MD, except that it is delayed by 2 microseconds. This delay is useful insofar as the synchronization device 2 represents an output synchronization device and the information taken from the selected memory location must first be stored in the output buffer memory of the synchronization device 2 before it can be read out and written into the drum.

In the example above, it was described how the address for the individual synchronization devices was first read out and then read out again and then changed and changed during the operation of the synchronization devices. Should z. If, for example, a synchronization device is switched on on the basis of a command 53 or 55, the address register assigned to this relevant synchronization device must first be cleared and then the start address must be written into this address register. The relevant address register is cleared by the function table signal FT 817 , which is generated on the basis of the commands 53 and 55. This function table signal is transmitted to the central processing system via the line 29-90 and is used to open the AND circuit 32-12 when the signal PS1 is present at the same time. This signal PS1 is transmitted from the command register IR-I of the central processing system via the line 29-61 and indicates that the synchronization device 1 is to be switched on.

The output signal of the AND circuit 32-12 is coupled to the OR circuit 32-10 , whereupon this generates the signal SAR. The signal SlAR appears in this case during the cycle times J ₀ and t ₇ , so that the output signal of the read control element 35-20 appears on the line 35-22 during the cycle time t _x and causes the in the cores 35-10 to 35-12 stored information is read out in the form of the signals SAR 1 to SAR 25. However, these signals SAR 1 to SAR2S are not transmitted by the AND circuit 36-12, since the instructions 53 and 55 generate the function table signal during all clock times with the exception of the clock times t _t and t _5. The address is therefore lost. On the basis of the commands 53 and 55, the function table signal FT 818 is also generated by the encryption device of the central processing system. This function table signal is sent together with the 25 information units of the start address, ie the signals PRA1 to PRA 25, to the inputs of the UDN circuits, such as. B. the AND circuit 36-28, coupled so that the new address PRA1 to PRA 25 transferred from the register RP-I via the line 29-30 passes through the OR circuits 36-14 and the input pulse shaping elements 36-18, in order to provide the signals SMR1 to SMR2S , which are then written into the memory cores 35-10 to 35-12 via the lines 35-17 to 35-19 by an output signal of the write control element 35-21 generated during the clock time t _%.

When connecting a synchronization device, it is necessary that not only that of the relevant Synchronizing device associated address register is cleared, but that also the corresponding Buffer storage, such as B. the buffers 39-10 and 39-12 are cleared. the

ίο The buffer memory is cleared by opening the AND circuits 32-24 and 32-26. The AND circuit 32-24 is opened when the function table signal FT 815 generated by the central processing system during the cycle times t ₇ and t ₀ , the clock signal ti, 0 and the signal PS1 are present at its inputs. The output signal of this AND circuit 32-24 is transmitted to the OR circuit 32-20, which then generates the read signal SIRD , whereby the information contained in the odd register 39-12 is read out.

In a similar way, the AND circuit 32-26 is opened when the function table signal FT 815, the signal PS1 and the clock signal i3,4 are present at its inputs at the same time. The output signal

This AND circuit is transmitted to the OR circuit 32-22, the signal SlRV of which causes the information contained in the cores of the register 39-10 to be read out.

Sometimes it is desired that information z. B. is to be read out under the influence of commands 41 and 42. This reading can be done either destructively (command 41) or non-destructive (command 42). Both commands 41 and 42 cause the generation of the function table signals FT811, FT820 ^{and i:} T821. As already described above, the function table signal FT 817 has the task of providing a flush signal so that the old address in the address register can be read out.

The AND circuit 30-16 is blocked by the function table signal / T 820, so that the synchronization device 1 cannot be given priority. This prevents the various controls which are carried out under the influence of the signal PIA from becoming effective while an address is being stored in the register P1. The actual transmission of the address read from the address register to the register P1 of the central processing system is caused by the function table signal FT 821, which opens the AND circuit 36-32 and the other, similar AND circuits for the other information units of the address, so that the signals SAR 1 to SAR 25 can be transmitted and lead to the generation of the signals SAD1 to SAD 25 , which are fed to the register P1 of the central processing system and stored there in the five least significant digits.

Magnetic drums and drive control

For the input and output devices operating at high speed, according to FIG present invention magnetic drums used, wherein up to 24 drums can be provided. Twelve magnetic drums were used in a computer system that was created and tested. Below Such a system comprising twelve drums will now be described.

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The drum itself is partially shown in FIG. This drum 42-1 is 27V2 inches long and 24 inches in diameter; their storage capacity is up to 250,000 words, each consisting of twelve decimal digits.

The magnetic drum is driven by a motor 42-2 at a speed of 880 rpm. Associated with the drum is a slidable magnetic head assembly 42-3. Arrange this magnetic head

50 positions to which the magnetic head can be adjusted step by step. Is the magnetic head ζ. B. has been set in its lower position by the abrupt shift, it will be at step-5 show increment from 00 to 01, 02, etc. incremented. The drum section 00 is located so on the extreme left and section 49 on the extreme right side of the drum. Should he Magnetic head set to sections 50 to 99

tion comprises six side by side arranged wall ₁₀ , so the rack 42-5 by means of the learner elements, which are attached to a common base magnet coil 42-15 by a "jump" along the. Five of these transducer elements are moved drum up or in the drawing for parallel recording and scanning of the five on the right so that the magnetic head uses a decimal digit for each information unit, by the motor 42-6, the drive pulley 42-18 during the sixth element is used to read the address information contained in Fig. 15 and the wire rope 42-16 controlled backward step sixth track. successively set to sections 50 to 99. This latter process will be discussed below in the. In other words: for each step, individually described. The magnetic head is with its the magnetic head is advanced, two six transducer elements are provided on a suitable support position. The movement arranged by the bracket attached to a slide. 20 Head when switching from one to the other This slide runs along the magnetic drum in these two positions, is referred to as a "jump" of a guide rail (not shown), or "jump-by-jump". The bar. This carriage 42-4 is set with the help of a drive pulley 42-18 and a switchable "jump" position, the sections 50 to 99 in the motor 42-6 driven wire rope 42-16 in the lower one via sections 00 to 49 are located . 25 upper "jump" position. The portion 00 is connected to the carriage 42-4 there is also a locking section 99 numerically interdigitated, the Abvorrichtung 42-17, the single cut in a rack 42-5 01 is latched with the numeric section 98, so that the Magnetic head on which combs on the drum, etc.

mel recorded tracks can be set. Arise on a section places that do not

The toothed rack 42-5 has 50 sawtooth-like openings 30 more permitting perfect recording, so it has recesses and can be appropriately identified in the longitudinal direction by means of this section and a bracket can be locked in two positions. This bracket 42-13 are two magnetic coils 42-14 and
42-15 assigned, which rest against the bracket and
control the locking of the rack 42-5 .

The recording density of the magnetic drums is 450 binary digits per inch, and each drum consists of 100 annular sections 00 to 99. These annular sections are in 25 sectors

divided into 100 words each. These sectors are 40 reel 42-14 and 42-15 controlled "jump" movements numbered continuously from 00 to 24, and passage through them requires 50 microseconds. A complete 2500-word section separated by a short space can be referred to as "sector space". about 90 microseconds can be restored.

As already mentioned, each ring conveyor contains the control circuitry for the drum drive

mige section six lanes. Five of these tracks 45 are shown in FIG. 44 shown. Each drum are made similar assigned to the parallel recording of the five information borrowed circuit arrangements, so that mation units of a decimal digit are used, while twelve such tax trends are used for a twelve-drum system the sixth track for a permanently stored circuit result. Fig. 44 can be divided into two down sector addresses, the section number and the sector cuts are subdivided: into a section, in weladressenmarke is provided, which is checked in series in the sector 50 chem the condition of the drum; this Intermediate space are stored. The at the beginning section contains circuits made by the program

The central processing plant is checked to see the state of the drum control circuits ascertain. The second section contains the drum control, by means of which the step-by-step switching, the incremental advancement and the direction of incremental advancement of the Drum associated head is controlled.

Like F i g. 42 shows, that is driven by the motor 42-6

is controlled, and secondly by step-by-step progression of the machine circuit, which is controlled by the magnetic coils 42-14 and gnetkopfes by two relays, which is controlled by a 42-15 and by the bracket 42-13 . With AC source from phase splitting via stepping, the head will connect to the motor 42-6 . In this case, the relay 42-11 controls neither the next higher nor the next lower connection, the coil of which is set to the rigere section number. As FIG. 43-65 is also shown in FIG. 44, the phase of the shows, the traces of one section with the motor switched on signal and thus also the traces of another section are numerically running in the direction of rotation of the motor 42-6 and thus the Riehkämt, so that there is a step-by-step progression for the 100 drum sections. The relay

no longer used in the program. Such a marked section is automatically carried out by the absence of a mark on the track of the sector address is detected.

It takes 70 microseconds to adjust the magnetic head from one section to the next by means of the motor 42-6, drive pulley 42-18 and wire rope 42-16. The ones from the magnet

Sector address stored in a sector always relates to the next following sector, ie the sector address N + 1 is at the beginning of sector N, etc.

The adjustment of the magnetic head is done in two ways: firstly, by means of step-by-step progression, which is achieved by the switchable motor 42-6, the wire cable 42-16 and the drive pulley 42-18.

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256

42-10, the coil of which is also shown in FIG , however, controls the actual step-by-step progression. This relay has a contact that when the relay is momentarily energized, the AC signal is sent to motor 42-6 for turns on a predetermined period of time, whereby the magnetic head carriage 42-4 together with the locking device 42-17 from one tooth of the rack 42-5 to the next tooth of this rack is set. In this way, the magnetic head moves to the next higher or next lower level Section of the drum set, depending on the direction in which the incremental progression is made. The contact of the jump relay also shown in Fig. 44 is designed in such a way that that it is in the upper contact position when the relay is not energized and thus the Solenoid 42-14 actuated, whereby the rack 42-5 automatically in the lower > Jump "position is held. When the relay 42-9 is actuated however, the solenoid 42-15 is energized, so that the rack 42-5 is set in the upper "jump" position will. In this way, the magnetic head on the top of the two is numerically linked intermingled sections set, which are assigned to the current switching step position.

Like F i g. 44 shows, the test circuits of the individual drums each contain a drum action toggle circuit 44-20 which is in the setting state when the drum to which this circuit belongs is or is to be used by the computer system. In addition, this toggle switch is also set when the drum has been advanced step by step or jump. As FIG. 44 shows, the setting input of this flip-flop 44-20 is connected to a first AND circuit 44-22 via the OR circuit 44-21. This AND circuit is controlled by the function table signal FT 832 of the central processing system generated by the encryption device 10-18 (FIG. 10) and the signal FDiV generated by the / IB encryption device 10-34 (FIG. 10A). The decryption device 10-34 also belongs to the central processing system. If a drum is to be put into operation, command 32 in the program of the central processing system is started. This command has the following format: 32XXXDDXXXXX. When it is stored in the command register / i? -L of the central processing system, this command generates the following signals via the encryption device 10-18: the function table signal FT 614, the function table signal FT 809 at the cycle time f ₇ and the function table signal FT 832 at the cycle time t _A. The signal FT 614 is coupled to the end pulse AND circuit 11-34 in order - as already described elsewhere - to initiate the end operation. This signal FT 614 is generated for all commands described in this chapter. The function table signal FT 809 is connected to the AND circuits 10-25 and 10-26 in order to store the sixth and seventh digits in the / 4 [beta] registers 10-27 and 10-28, thereby generating the signal PD1. The function table signal FT 832 causes the opening of the AND circuit 44-22 as well as any similar AND circuits in the various control arrangements of the drums. The two DD digits of the command are decrypted in the decryption device 10-34 of the v4.B register in order to generate one of the twelve signals PDN. This decryption device 10-34 generates a specific signal PDN (PD1 to PD 12), depending on the value of the DD digits. Should z. If, for example, command 32 is to drive drum 1, the DD digits would correspond to the value 01 which, after decoding by decoding device 10-34, would lead to the generation of signal PD 1.

ίο This signal PD 1 is then coupled to the AND circuit 44-22 of the drum 1. If, on the other hand, drum 2 is to be used, the DD digits would correspond to the value 02, and the signal provided by decryption device 10-34 would energize line PD 2, which is connected to AND circuit 44-22 associated with drum 2 is.

This is generated by coupling the two signals FT 832 and PD 1 to the AND circuit 44-22

ao a signal by which the flip-flop 44-20 is set. The setting output signal of the Flip circuit 44-20 is connected to one input of a program test AND circuit 44-25 and also directly to those shown in Fig. 28A

»5 AND circuits coupled for the main check in order - as described elsewhere - to cause conditional jumps to the main control loop (CL) of the central processing system. The same signal PD 1 from the / 4B register that is also applied to AND circuit 44-22 is applied to AND circuit 44-25 as a further input signal. At the last input of the AND circuit 44-25, the function table signal FT 831 is finally still present, which is switched on by the encryption device 10-18 of the central processing system at the cycle times i ₄ and i ₅ . This function table signal is generated when the command 31 is in the command register IR-I of the central processing system. The command 31, which has the format 31 XXXDDMMMMM , is a special command which has the task of checking the action toggle circuit 44-20 of the drum identified by the DD digits. In addition, the command 31 causes the encryption device to generate the function table signals FT 614 and FT 809, the tasks of which have already been described elsewhere. If the action toggle switch is in the setting state, the AND circuit 44-25 generates an output signal which is sent via the OR circuit 44-26 and a one-pulse delay device to the circuit arrangement provided for a conditional jump (Fig. 28). is coupled to the central processing system in order to transfer control to the address identified by the M-digits of the command 31. As will be described later, control of the central processing equipment is transferred through the M-digits to the control program for the drum movement; the command 31 thus forms part of the program of the central processing system. Its job is to check the status of a selected flip-flop 44-20. If this toggle switch is in its setting state as a result of the initial initiation of command 32 or as a result of the termination of a step or jump switching process, command 31 causes the central processing system to enter the control program of the corresponding drum

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258

occurs, where further instructions for the step-by-step or jump-wise advance of the selected drum be granted.

The drum movement is controlled by the following five commands:

1. Command 35, which is the format

35 XXXXXXXXXX

and causes the drum to be indexed step-by-step;

2. Command 36, which specifies the format

36 XXXXXMMMMM

has and causes the incremental indexing of the drum in the reverse direction;

3. Command 37, which specifies the format

37 XXXXXMMMMM

and causes the drum to be indexed in the forward direction;

4. Command 38, which specifies the format

38 XXXXXMMMMM

and causes the drum to be set to the upper "jump" position, and

5. Command 39, which specifies the format

39 XXXXXMMMMM

and caused the drum to be set to the lower "jump" position.

If the command 35 is stored in the command register / jR-1 of the central processing system and this command is evaluated by the encryption device 10-18, it generates the function times t _i and i ₅ ) when the command 37 in the command register, which determines the direction of the step-by-step forwarding IR-I of the central processing plant is stored. Command 37 also generates end pulse 614. The signal PD 1, which is generated by the decryption device 10-34 of the ΛΐΒ register of the central processing system, is applied to the AND circuit 44-34 as the second pass signal. In addition, is on

ίο input of AND circuit 44-34 still a locking signal. This locking signal is derived from the flip-flop 44-33 itself, from its setting output signal. There are also two pass signals at the inputs of the AND circuit 44-35. The first pass signal is the function table signal FT 836, which is generated by the encryption device 10-18 when an instruction 36 is in the instruction register IR-I of the central processing system. This

ao command 36 also generates the end pulse signal 614. The second pass signal is the signal PDl at the AND circuit 44-35, which this Circuit is supplied in the same manner as the AND circuit 44-34. This is also due to the AND circuit 44-35 outputs a locking signal, which is derived from the reset output signal the flip-flop 44-33 is derived. The output signals of the two AND circuits are also sent to the one provided for a conditional jump in FIG. 28 shown Circuit arrangement via the OR circuit 44-26 and the pulse delay device 44-60 coupled.

Is the step-by-step forwarding in operation in

Forward direction is set, command 37

table signal Fr 835 and the end pulse 614. The 35 the AND circuit 44-34 blocked before; the pro function table signal FT 835 is therefore continued with the command _{generated by clock times i 4} and t ₅ and the next count of the control counter (C + 1) PD 1 to the AND circuit 44-30 in addition to the signal turned on. That is marked. If, on the other hand, the step-by-step signal PD1 is previously set by the decryption device forwarding in the reverse direction 10-34 of the y4ß selection register under input 40, the AND circuit 44-34 allows the DD digits of a previous command 31 to flow failed 37 through to the direction flip-flop 44-33 or 32 generated. The output signal 44-30 is set, and at the same time generates a direct output to the setting input for the step-by-step signal at the OR circuit 44-26 in order to transfer the tilting gram provided to the command that is in the circuit 44-31 and also via a suitable delay device 44-32 identified by the M-digits of the instruction 37 at the reset in memory location. A similar chain of Ergang is coupled to the same flip-flop. By event occurs when an instruction 36 is initiated; In the command 35, the toggle circuit 44-31 is therefore in this case, however, the AND circuit 44-35 is locked in its setting state for a predetermined time when the step-by-step switching is activated, whereby the relay 44-10 closes, 50 already in Reverse direction is set.
the motor 44-6 started and the drum rotated. The outputs of the AND circuits 44-34

is taken one step further. and 44-35 are also used via the OR switch

The direction of incremental advancement 44-36 to the input of a restartable is coupled by another flip-flop 44-33 delay device 44-37, whose controls, whereby at the same time the excitation of the relay 55 output signal via the AND circuit 44-38 and 42-11 is controlled. If the flip-flop is the OR circuit 44-21 at the setting input 44-33 in the setting state, the relay 42-11 of the action toggle circuit 44-20 is switched on, energized, and the step-by-step switching takes place. This is also due to the OR circuit 44-36 in forward direction. The flip-flop is output signal 42-8 of the stepper motor 42-6 to -44-33 on the other hand, in the reset state, the relay 60 is connected to the tachometer 42-7. At the again 42-11 is not energized, and the delay device 44-37, which can be started step by step, is involved direction takes place in the reverse direction. To the tilting itself a monostable multivibrator known circuit 44-33 to be able to set or reset, type, the output generated by himself the AND circuits 44-34 and 44-35 advance signal by a certain amount compared to the see. At the first AND circuit are two 65 input signals received last. With Pass signals, one of which, the radio - in other words: As long as the input of the multition table signal Fr837, from the encryption vibrator a signal is present, the output signal device 10-18 is generated (while the clock is suppressed; in the present case, the

509 538/373

259 260

restartable delay device 44-37 are stored. A summary command for the 10 milliseconds thereafter generates an output signal. The drum movement has the format Q0BB0DDQ0000, This multivibrator has the task of controlling the drum device, in which the DD digits sufficiently identify the drum device to be used for the drum movement and thus form the basis for all the drum commands that are intended to carry out its mechanical action at a time which are to be entered before the drum action toggle circuit is stored in the same memory block, by means of which the AND circuit 44-38 is coupled and in which the BB digits the new drum abten clock pulse fl is set again. The section number to which the magnetic head output signal 42-8 of the tachometer is to be set.

OR circuit 44-38, the delay device. In connection with FIGS -20 of the drum 1 described. In these figures, there is always a function when the magnetic head has executed a step, special commands in certain blocks of the flow or jump movement. At the same time indicated in the diagram. First of all, it should be noted that the action toggle circuit 44-20 is also set when a summary drum command is executed if an command 32 AND circuits 44-34 or 44-35 is communicated by the output signal to one of the usually at the end of the program , is carried out in order to set the stepping movement in the opposite pull-drum action toggle circuit 44-20 shown in FIG. 44 to be performed. so that the program control loop from the pro-

As the last control element in the control arrangement 20 grams of the central processing system in again for the drum movement, the jump / toggle switch is provided, the control program for the drum movement unit 44-39 . The setting output signal can occur. In the following description, this jump toggle switch controls the excitation therefore assumed that the action toggle switch of the jump relay 42-9. If this relay is energized, 44-20 for the drum 1 by starting a, the rack 42-5 is adjusted to the right, that is, 35 such or another command (35, 38, 39, 36, it is then in the upper "jump" - 37) has been set and that the drum mile position. When the jump toggle switch is reset , the relay 42-9 is de-energized for the further execution of the summation device 44-39; thereby the command is available. the solenoid 42-14 is energized and the tooth- From Fig. 51 and the earlier description of

rod set in the lower "jump" position. ₃₀ central processing system shows that the flip-flop 44-39 is set by an output central processing system by the setting signal of the AND circuit 44-40 , the action flip-flop 44-20 a jump out through the function table signal FT 838 and the can lead when the processing system this signal PDl is opened. The function table flip-flop by executing a command 31 signal FT838 is checked when command 38 is initiated _{for 35.} This check is generated in block 51-1 shown cycle time t _t. The output signal of this AND- represents. If during this check it is found that the circuit is then connected to the setting input to which the flip-flop is set, then the next step-flip-flop is coupled. The reset step of the counters for the head movement at that of the toggle switch is compared with "0" by the output signal drum 1; this step is done in AND circuit 44-41. These _{40 are shown at} block 51-2. The counter itself is a single AND circuit is opened when a memory location in the main memory of the system is connected to the function table signal FT 839 and that, for example memory location 702, and counts the AnSignal PD1. The output signal of this number of switching steps, which the magnetic head from AND circuit must then lead to the reset input in order to be coupled to the correct one, through the BB-TXi of the flip-flop 44-39. 45 remote from the summary order

In Fig. 44 represents that to get back the waste. In the present case, I am attached Flip-flops used signal GC assume that the counter shows "0" and the Tromein general evacuation signal, which appears on the operating mel on the output of a new summary console of the system by means of a manual switch generates command waits. For step 2 of the subpro, so if the machine for some reason 50 grams it gives the same result what comes to a standstill. is indicated by the equal sign, the

_ ... j. ",, above the one on the right-hand side of the block

Program for the drum _{movement Ldtung is arranged after this} check must

The drum movement as the next summary command from the drum will now be described with reference to Figs. 55 memory block can be removed. This step is shown in These figures show a simplified flow diagram in block 51-3 . The one in the memory block that of a typical drum motion program. Drum 1 located summary command is so

Before the one shown in these drawings this block was taken and placed in one of the two

Flowchart is described in detail, is to register RP-I or RP-2 of the central processing

Note that the drum movement is stored by the 60 total system. The program continues with the

ric commands is controlled. Each drum has connection point C of the flowchart, where as

a separate memory block in which the relevant next step of the subroutine, block 51-7

summary commands are saved. A is shown. In this step you want to have one in one

typical memory block comprises e.g. B. three or four memory addresses (z. B. 703) included

memory locations allocated to a particular drum, 65 command 31, which indicates which

in what summary commands for related section currently on the drum in question

writing and setting to be carried out with this drum. The name for the present

Read operations and the section set for head movements is located in block 51-7

261

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and has the following format: 31BBXDD00176. In this command word, the ß5 digits designate the section that is currently set on the drum 1. The command word is then stored in a new memory location, e.g. B. the memory location 921 stored.

Next, the summary command taken from the drum memory block must be written to any memory address, such as e.g. B. the memory address 693 are stored. This step is indicated in block 51-8. The summary instruction is also located in one of the two registers RP-I and RP-2 and is randomly compared with a constant value in order to determine whether it is a data transfer instruction, ie a read or write operation. The summary read and write commands contain an “8” or “9” in their most significant digit, while the summary command for the movement control of the drum has a “0” in the most significant digit. The step in block 51-9 can therefore be used to determine whether the most significant digit of the summary command is greater or not. In the present case, where it is assumed that the number is less than 8, the step shown in block 51-10 can then be carried out. At this point, the β-digits of the command word located in memory location 703, which here designate the section to which the magnetic head is currently set, are corrected so that they contain the number of the tape section to be newly set, which is contained in the section in memory location 693 is included in the summary command. This is done by changing the Bβ digits of the word located in memory location 703 so that they correspond to the number of the new section. After this process, the action toggle 44-20 is checked again, as shown by block 51-11. This check can be carried out by means of the command word 31 stored in the memory location 703. Since the toggle switch has not yet been set in the program, it must not be set. However, if the toggle switch happens to be in the setting state, an error must be processed by the program in address 00176 of word 51. As a result of the check carried out at this point, the drum DD is to be set in the ylβ register (FIG. 10) for future commands relating to the head setting.

After the ßß-digits of the word in the memory positioner 703 have been corrected and set to the number of the new section, the next step must be to determine whether a "jump" is required or not. As is known, the memory location 921 contains the command word 31, the ES digits of which indicate the number of the section over which the magnetic head is currently set. During the "jump" test it is first determined whether the new section is in the lower jump position (section 49 and below) or in the upper jump position (section 50 and more). This check is carried out by comparing the number of the new section with the constant value 49 in step 51-12. It is assumed here that the new section has the number 80. In this case, the result of the comparison made in step 51-12 indicates that the number of the new section is greater than 49; the program therefore continues at connection point D of the flowchart shown in FIG.
After it has been determined that the number of the new section is greater than 49, you must next determine whether the number of the currently set section is greater than 49. This takes place in step 52-13, the number of the currently set section, which is represented by the BB-ZiR ern of the word stored in the memory location 921, being compared with the constant value 49. Again, it is assumed that the number of the currently

_1S section is greater than 49, e.g. B. 70. In this case, no jump is necessary.

In the next step of the program it must then be determined in which direction and how many steps the magnetic head must be indexed in order to be set from the current section to the new section. This is done in step 52-14 by subtracting the number of the new section from the number of the currently set section. The result of this subtraction indicates the number of steps the head must be advanced. In step 52-15 the result of this subtraction is compared with "0" to determine whether the head needs to be indexed at all. If this test yields an equality result, the number of the currently set section obviously matches the number of the new section, ie the head is set to the correct section. In this case, the program for adjusting the drum is ended. Before the program goes to the main control loop, another instruction 32 is executed in step 52-16. This command sets action toggle 44-20 and then the program returns to the control loop as indicated by the label CL in block 52-17.

In the present example, however, it was assumed that the number of the new section 80 and that of the old section was 70. The subtraction performed in step 52-14 therefore shows an unequal Result (-10) in step 52-15. In this case the program must start with that shown in block 52-18 Continue step. This step is a size comparison where the The result of the subtraction carried out in step 52-14 is compared with "0" to determine the direction to determine into which the head must be switched. In the present example it is assumed that that the number of the new section is 80 and that of the old or current section is 70. Of the Therefore, the size comparison performed in step 52-18 indicates that the result (-10) is less than zero. Next, the step illustrated in block 52-19 is performed; i.e., the settings for the

The directional flip-flop is set by a command 36 in the reverse direction. This setting results from the fact that in the upper jump position the section numbers move from right (above) to left (below). to take. The magnetic head must therefore be adjusted in the reverse direction.

Should the toggle switch provided for setting the direction already be in reverse direction

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be set, the command 36 would find the AND circuit 44-35 (Fig. 44) blocked by the direction flip-flop 44-33; in this case, no output signal would be generated by the AND circuit 44-35. No conditional jump signal PCT is thus generated. Since the direction toggle switch has already been set correctly, the switch command 35 could now be executed. This step is shown in block 52-20. After initiating the advance or step command and before the program goes to the control loop (block 52-22), the result of the subtraction carried out in step 52-14 must be decreased by one, since the first step command started and the result in the setting counter of the drum 1 (in the present case in memory location 702) has been stored. The steps shown in block 52-21 are therefore carried out before the program is passed on to the control loop.

Returning to block 52-19 and assuming that the direction toggle has previously been set in the forward direction, it can be seen that the relay 42-11 shown in FIG. 42 would be toggled by the execution of command 36. In addition, it would take a certain amount of time to close this relay, which is long compared to the time it would take to move from one command to another in the setting program. Therefore, it is possible to go into the control loop while the direction is being switched. Before this, however, the result of the subtraction carried out in step 52-14 must be stored in counter address 702 (block 52-23). In this case, the command 36 generates an output signal at the AND circuit 44-35, which sets the action toggle circuit 44 via the OR circuit 44-36 , so that under the influence of the next command 31 belonging to this drum again in the Setting program can be entered.

If, in the present case, the next loop test 99 is carried out and a command 31 is started for this drum - as indicated by block 1 in FIG. 51 - the program finds the action toggle circuit 44-20 for this drum set. If, during the check, it is found that the action toggle switch is in the setting state , the comparison shown in block 51-2 is carried out. This time, however, the setting counter of the magnetic head does not contain a "0". The comparison carried out in step 51-2 therefore produces an unequal result. For reasons described in more detail below, the program then continues with an exit command (block 51-4) and with a step command (block 51-5) . After the step instruction, a subtraction must be carried out in order to decrease the number contained in the setting counter by one (block 51-6) before the control loop is entered in step 51-24. In the illustrated embodiment the block 51-5 of the instruction step 35 the tachometer 42-7 produces an output signal, whereby the flip-flop action is 44-20 again set via the OR circuit 44-36, so that the possibility to re-enter the setting program consists. This process lasts until the number in the counter (memory address 702) has decreased to "0"; the head is then adjusted to the correct section. At this point, the operation carried out in block 51-2 of the flow chart yields an equality result, so that the next summary command located in the memory block of the drum 1 can be read out and executed. Of course, the next summary command must be a read or write command and not another command for adjusting the magnetic head.

In the description of the EirAtell program it is now assumed that the opposite relationships exist, ie that the currently set section has the number 80 and the new section has the number 70. In this case, steps 52-13, 52-14 and 52-15 are carried out again, with an unequal result in block 52-15. This time, however, the difference is +10 and not -10. The comparison performed in block 52-18 thus indicates that the result is greater than zero. Next, the step indicated in block 52-25 is carried out, that is, the magnetic head is adjusted in the forward direction. In other words, since the currently set section is numbered 80, it is to the left of the new section; the head must therefore be adjusted in the forward direction. If the command 37 provided for setting the forward direction determines that the relay 42-11 is already set in the forward direction, the step command shown in block 52-26 can be executed. The next instruction contained in the program therefore represents only one step. After the initiation of the step instruction represented in block 52-26, the step represented in block 52-27 is carried out next. That is, the result of the subtraction made in block 52-14 is decreased by one and then stored in the set counter (memory address 702). Thereafter, the program can proceed to the main control loop as shown in block 52-28.

As block 52-26 shows, step instruction 35 resets action flip-flop 44-20 by the output of tachometer 52-7 so that the next command (command 31) checking that flip-flop determines that the Flip-flop is in the set state so that the step shown in block 51-2 can be performed. In this step, the content of the counter (memory address 702) is compared with "0" again. If the content is not 0, the steps shown in blocks 51-4, 51-5 and 51-6 are carried out. This program continues until the content of the counter has reached the value 0; at this point the comparison carried out in block 51-2 gives an equality result, and the next summary command can now be taken from the memory block and executed.

For the further description of the program it is now assumed that the number of the new Tape section is less than 49; In this example, this new section should be number 30 to have. In the course of the individual operations, block 51-12 is reached, where the comparison test takes place, the result in this example is less than 49; the program runs in this case, continue at connection point F (FIG. 53). After the comparison made in block 51-12

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a comparison is therefore carried out again in the next step (block 53-29). It is assumed that that the current section has the number 50, the result of in step shows 53-29 shows a value that is greater than 49. In the next program step, must therefore the magnetic head can be set to the lower jump position by command 39 (block 53-30). As is known, the jump toggle 44-39 is reset by the command 39, whereby the relay 42-9 (Fig. 42) is de-energized. The tachometer 42-7 generates a setting signal 42-8, whereby the action toggle 44-20 is set again so that on the next command 31 a re-entry into the program can take place.

While the magnetic head is being set to the lower jump position, the number of steps which the magnetic head must be indexed under the influence of this summary command can be determined. The first step for this is carried out in block 53-31; That is, the sum resulting from the number of the new section and the number of the current section is subtracted from the value 99. In the present case, in which the new section is numbered 30 and the current section is numbered 50, this subtraction results in the difference -18. This number indicates the number of steps required to adjust the magnetic head to the new section. After this subtraction, the next step shown in block 53-33 is performed. Here the result of the operation carried out in block 53-31 is compared with "0". If this comparison yields an equality result, then the head is obviously set to the correct section and the program can thus go to the control loop (block 53-34). In the present case, however, the subtraction carried out in block 53-31 resulted in the difference -18. Next, in block 53-35, the result -18 is therefore compared with "0". The result of this comparison performed in block 53-35 indicates that the result is less than zero. The next step, therefore, is to perform the operation shown in block 53-36. At this point the exhaust command previously stored in block 51-4 is converted to command 36; the result of the operation carried out in block 31 is transmitted to the setting counter (memory address 702) of this drum. As is known, the command 36 is provided for advancing in the reverse direction. This downshift results from the fact that the new section is to the left of the current section. At the next entry into the setting program for the drum caused by a command 31 (block 51-1), the comparison carried out in block 51-2 gives an unequal result. However, this unequal result does not run through the outlet command, but instead reaches the command 36 provided for the reverse shift Exhaust command is converted. After the command 36 has been executed in block 36, a conditional jump signal is also generated via the OR circuit 44-26 by the switching of the relay 42-11 via the AND circuit 44-35. Associated with this conditional jump is a program which converts the reverse shift command stored in block 51-4 back into an exhaust command.
Alternatively, it is now assumed that the number of the new section in the operations described above is less than 49 and the number of the current section is greater than 49; so should z. B. the current section is the number

ίο have 70. Since, in the present case, the new section has the number 30 and the current section has the number 70, the result obtained in step 53-31 shows a value greater than 0. The result of the step carried out in block 53-35 is therefore also greater than 0; the program therefore continues at connection point G. In this case, the operations shown in block 53-37 are carried out, which essentially correspond to the operations of block 53-36, except that an instruction 37 is started instead of instruction 36.

It is now assumed that both the number of the new section and the number of the current section is less than 49.

In this case, after performing the step shown in block 53-29, the program displays that the current section number is less than 49; therefore, next becomes that in block 53-38 performed step. As an example, assume that the new section is number 30 and the current section is number 34. The result of the performed in block 53-38 Subtraction gives the difference -4. After doing this shown in block 53-38 Subtraction, the result of this operation is compared with "0" in block 35-39. Had in the present If both sections had a number below 49 and they both had the same number, the would be The comparison performed in block 53-39 yield an equality result, and that shown in block 53-40 Step would be carried out; i.e., an instruction 32 would be started by the the action toggle switch would be switched to its set state.

In the present example, however, it is assumed that the result of the in block 53-39 The comparison carried out is not equal to (-4). This result is now included again in block 53-41 "0" compared. As the result of this comparison

s ° is less than 0, the must now be in block 53-42 step shown.

From the operation shown in block 53-42, it follows that the indexing of the magnetic head must be done in the reverse direction, since the current section is four steps to the right from the new section. If the step relay 42-11 has already been set, a step can be carried out before the control loop is started. Are the step relay and the toggle switch that is, has already been postponed before the initiation of the command 36, a command is issued in step 53-43 35 executed. After the step command is initiated, the result is that carried out in block 53-38 Subtraction reduced by one because a step operation was initiated; this decreased by one The result is then transported to the counter located in memory location 702 in step 53-44. Then the program goes to the control

509 538/373

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loop over. When the next command 31 is initiated for this drum, the comparison carried out in step 51-2 again yields an unequal result; the program therefore continues with the steps shown in blocks 51-4, 51-5 and 51-6.

In the following it is again assumed that both the number of the new section and the number of the current section are less than 49. In this case, however, the new section should be numbered 34 and the current section numbered 30. The result of the operations performed in blocks 53-38, 53-39 and 53-41 then indicates that the results are greater than zero. Following the comparison carried out in block 53-41, the step shown in block 53-45 is therefore carried out, ie a command 37 is started in order to set the stepping in the forward direction. This results from the fact that the new section has the number 34 and is thus four switching steps to the right of the current section 30. If the toggle switch 44-33 off is set again this time, a step (block 53-43) can be carried out next. If, on the other hand, the relay has to be switched, the next step shown in block 53-46 must be carried out, ie the result obtained by the operation in block 53-38 is stored in the counter located in memory address 702. As block 53-47 shows, the control loop can then be started.

Assume that the number of the new section is greater than 49, e.g. B. 80, and it is also assumed that the number of the current section is less than 49, for example 8, the program is set to the connection point D on the basis of the result of the comparison carried out in block 51-12. It is also assumed that the result of the comparison carried out in block 52-13 has set the program to connection point 7 (FIG. 54). Taking into account that the current section 8 is in the lower jump position and the new section is in the upper jump position, the next step is to switch the jump relay to the upper position. This is done in block 54-48 by a command 38. When this command 38 is initiated, the relay 42-9 is energized and generates the setting signal on the tachometer 42-7 , as a result of which the action toggle circuit 44-20 is set again. If the action toggle switch of the relevant drum is in the setting state, then when command 31 is initiated, the setting program can be re-entered. While the jump relay is still energized, the next operation in the setup program is the step shown in block 54-49. Here the sum of the two section numbers, namely 80 + 8, is subtracted from the value 99. The result 11 obtained in this case can then be compared with “0” in block 54-50. If the numbers of the two sections were the same, the comparison carried out in block 54-50 would again result in an equality result, whereupon the program could go to the control loop. In the present case, however, there is a difference of 11. This difference (11) is now compared again with “0” in block 54-51.

The result of this comparison indicates a value that is greater than 0; the program therefore continues with the step shown in block 54-52. In this step, the outlet command shown in block 51-4 is converted into a command 37 which has the task of setting the stepping in the forward direction and storing the result of the subtraction carried out in block 54-49 in the setting counter (memory address 702) . at

A renewed entry into the program from block 51-1 then gives an unequal result in the comparison to be carried out in block 51-2. This time, however, there is no outlet command in block 51-4, but step command 37; thus this instruction 37 is executed in block 54-52. After instruction 37 has been executed, instruction 37 in block 51-4 is converted back into an outlet instruction so that the operations shown in blocks 51-5 and 51-6 are carried out.

ao deny if you re-enter the program at this point. If the result of the subtraction carried out in block 54-49 had been less than 0, the result of the comparison carried out in block 54-51 would cause the next operation in block 54-53 to be carried out. This operation is the same as that performed in block 54-49, except that an instruction 36 is temporarily stored in block 51-4.

As the above program shows, it must first be determined whether the magnetic head is through a jump has to be adjusted or not; if this is the case, the jump command must be issued will. While the jump setting is being made, the number of times to be performed is being made Switching steps and the direction in which switching must take place are determined. To this end the corresponding command for the switching direction as well as the corresponding further switching or Step commands left on. The program then carries out the necessary switching steps, until the magnetic head is adjusted to the new section. At this point is the task of the present summary command is ended and the next summary command from the for The memory block provided for the drum can be read out and executed.

Drum read synchronizer

The computer system according to the invention includes two drum read synchronization devices and a drum write synchronization device. The drum read synchronizer logic circuits are shown in FIG. 45 and 46 shown.
The synchronization devices have the task of establishing a connection between the magnetic drum, which is operated at a relatively low speed, and the remaining part of the computer system, which is operating at a high speed. In addition, these synchronizing devices have the task of controlling the flow of information between the magnetic drum and the computer system by means of various control circuits.

As shown in FIG. 45, the synchronization device includes an availability flip-flop 45-1. This availability toggle 45-1 is switched to its set state when the synchronizer can be used by the drum. For this purpose, the availability

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Flip circuit 45-1 is set by an output of AND circuit 45-2. This AND circuit is in turn prepared by the function table signal FT 854, which is generated by the command encryption device 10-18 at the clock time i _x due to the storage of a command 54 in the command register IR-I . The command 54 belongs to the program of the central processing system, in particular to the control programs which are provided for reading and writing on drums. This function table signal occurs at the end of such a program and causes the availability flip-flop to be switched to its set state, indicating that it is ready for further tasks. The command 54 has the following format: 54 XXSXXXXXXX. If this command is in the command register IR-I, then in addition to the function table signal FT 854 it also generates the end pulse 614, which is coupled to the AND circuit 11-34 in order to end the current operation. The number 5 of this command, which is the eighth number of the command word, designates the synchronization device to be used. For the sake of simplicity, only one read synchronizer will be described. If the number S corresponds to a "1", this means that it is a read synchronization device. The write synchronization device, on the other hand, is identified by a "2" in the, S digit. The "1" contained in the eighth digit of the command is decrypted in the decryption device 10-31 assigned to the command register 10-13 ( FIG. 10), whereupon the signal PS1 is generated, which is sent as the second control signal to the AND circuit 45 -2 is turned on. In this way, the command 54 with the corresponding S-digit causes the AND circuit 45-2 to be opened and the availability toggle circuit to be set in order to make the synchronizer ready for another drum read operation.

If a drum read command is to be carried out, it must first be determined whether the synchronization device is free to carry out the relevant command. This determination is made by instruction 56, which has the following format: 56 XXSXXMMMM. This command gives the following instructions: Check the availability flip-flop of the drum synchronizer identified by the 5-digit. If the drum is free, jump to the program beginning with the memory address MMMMM. (In the present case, the memory address MMMMM represents the beginning of the drum reading program.) If the availability toggle switch is in its reset state, continue with the current program, i.e. go to the memory address indicated by the next count of the control counter (C + 1 ) referred to as. If command 56 is started, the central processing system generates function table signals FT 614 and FT 856 at cycle time i ₄ . The test AND circuit 45-3 is prepared by the function table signal FT 856. In addition, the setting output signal of the availability flip-flop as well as the signal PS1 , which was generated by the decryption device 10-31 (FIG. 10), are also present at the inputs of this test AND circuit. If the synchronization device is available, the AND circuit 45-3 generates a signal. This signal is then coupled to the conditional jump circuit shown in Figure 28, thereby transferring control of the central processing system to the drum reading program. However, before this program can be carried out further, the magnetic head associated with the selected magnetic drum must be connected to the drum read synchronizer. This is done by initiating a connection command, in this case command 52. This command 52 has the following format: 52 XXSDDXXXXX; his instructions are as follows: Connect the drum synchronizer identified by the 5-digit to drum DD and reset the synchronizer's availability toggle switch. The AND circuit 45-4 is provided to perform this operation. The following signals are present at the inputs of this AND circuit: the setting output signal of the availability flip-flop, the signal PS1 of the decryption device 10-31 (FIG. 10) and the function table signal FTSS2B generated by the encryption device 10-18 shown in FIG . The command 52 itself generates two function table signals : the function table signal FT 852 A at clock time t _A. The generation of these time-delayed function table signals is described in connection with the encryption device 10-18. Command 52 also generates an end pulse 614 and a signal 809 at clock time I ₁ . This latter signal opens AND gates 10-25 and 10-26 so that the DD digits of the instruction can be stored in ^ S registers 10-27 and 10-28. When this command is carried out, the AND circuit 45-4 generates an output signal which is fed to the reset input of the availability flip-flop. As a result, the flip-flop is switched to its reset state and thus indicates that the synchronizing device is in operation. The signal labeled 51COiV from this AND circuit 45-4 is also coupled to the circuit arrangement shown in FIG. 47 in order to connect the magnetic head of the drum DD to the relevant synchronizing device. This process is described in detail below.

After the drum in question is now in communication with the read synchronization device is, it must next be determined to initiate the read operation whether the magnetic head is on the corresponding track is set. For this purpose, the must on the drum in the sector gap section sector address recorded in series with that by the drum read command marked section sector address are compared. This process is also described below described in more detail.

The circuitry described below is used to select the section sector address to read out the drum and to forward this address to the central processing plant for there to be able to carry out the comparison process. For this purpose, the output of the AND circuit 45-4 of a suitable one-pulse delay device 45-5, whose signal is on

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the OR circuits 45-6, 45-25 α and 45-30 is coupled. The output signal of the OR circuit 45-6 is connected to the setting input of a sector address toggle circuit 45-8 and the output signal of the OR circuit 45-30 to the setting input of a toggle circuit 45-23, while the output signal of the OR Circuit 45-25 α is coupled to the reset input of this flip-flop. The setting input signal of the flip-flop 45-23 makes the reset input signal of this flip-flop ineffective, so that this circuit is therefore switched to its setting state in any case. In this way the AND circuit 25-24 is disabled. At the same time, the output of the OR circuit 45-25 α causes the address register 45-26 to be reset to 1, whereby the previous information in this register is removed. The set output of the flip-flop 45-8 is applied as a pass to AND gates 45-10 and 45-11 which are connected to the input and shift lines, respectively, of the 18-stage address shift register 45-26. The signal from the sixth track of the drum is present at the other input of the AND circuit 45-10. This track is known to contain the section sector address. The signal provided by this track is coupled to the input of the AND circuit 45-10 via an amplifier 45-9, for example. The signal of the track-dependent sector selection or the signal of the automatic sector selection circuit 45-12 is present at the other input of the AND circuit 45-11. This automatic sector selection circuit is already known in the art. In both cases, a sector selection signal is generated in synchronism with each information unit recorded in the track 6. Thus, the sector address toggle 45-8 causes the section and sector addresses in the sixth track of the drum in question and the sector address mark to be stored in the 18-stage shift register 45-26 via AND circuits 45-10 and 45-11 will. The delay device 45-5 provided in the circuit arrangement is intended to ensure that the in FIG. 47 connect to the selected magnetic head prior to opening AND gates 45-10 and 45-11.

As is known, the sixth track contains both the section and the sector address of the section, which is scanned by the magnetic head of the drum concerned. It also became known Assume that prior to connecting the synchronizer to the drum, the control program for the drum movement has been performed and the head of the selected drum was set to the correct or supposedly correct section. Track 6 contains im Sector gap first the sector address mark, then the sector address and finally the Section number. So shortly before the sector and section addresses are stored in register 45-26 the sector address mark is first written into this register. These The sector address mark has the following code combination: 1010101100. This sector mark is used by a decryption matrix 45-25, those with the first ten stages of the sector address shift register 45-26 is connected. As soon as the sector mark is in these stages, the decryption matrix is set 45-25 detects the presence of this mark and generates an output signal. This output signal is fed to the shift register via the OR circuit 45-25 a, whereby the register is set to 1 is postponed. At the same time, the output signal of the decryption matrix 45-25 is sent to the Reset input of the flip-flop 45-23 coupled to reset this flip-flop and thus to prepare the AND circuit 45-24. Through the in the section as well as in the sector address contained information and the shift pulses transmitted by the AND circuit 45-11 becomes the "1" that is generated as a result of the detection of the Sector mark was inserted into the shift register, causes the register to be in its final stage

ao or eighteenth stage to switch. The output of the eighteenth stage and the output of the shift AND circuit 45-11 are supplied to the AND circuit 45-24. If the "1" is shifted to the eighteenth stage and detected by the AND circuit 45-24, an output signal is generated by this AND circuit which is sent to the reset input of the sector address via the OR circuit 45-7. Toggle circuit 45-8 is coupled. By resetting this flip-flop, the two AND circuits 45-10 and 45-11 are blocked, so that the flow of information or the flow of shift pulses to the shift register 45-26 is interrupted. In this way, the sector and section addresses remain in the shift register 45-26. The output signal of the AND circuit 45-24 is also coupled via the OR circuit 45-30 to the setting input of the flip-flop 45-23, whereby the pass signal for the AND circuit 45-24 is switched off.

Since the section number can range from 00 to 99, ten pieces of information are required to represent the various section numbers. These ten information units, which are stored in the first ten stages of the shift register 45-26, are supplied to ten AND circuits, the first of which is denoted 45-29 and the last 45-30. The outputs of these ten AND circuits are supplied to the ninth and tenth stages of the register RP-I shown in Fig. 14A. Since the sector address can only have a value between 00 and 24, only eight information units are required to represent it. Five of these information units are used to represent the least significant digit of the sector address and the remaining three information units are used to represent the most significant digit 0, 1 or 2 of the sector address. These information units are stored in the last eight stages of the shift register 45-26 and fed from there to eight AND circuits, the first of which is designated 45-28 and the last 45-27. The outputs of these AND circuits are supplied to stages 3 and 4 of the register RP-I shown in Fig. 14A. After the section and sector address numbers are stored in the shift register, they can

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can now be re-stored in the register RP-I of the central processing system via the AND circuits 45-27, 45-28, 45-29 and 45-30. This relocation is initiated by instruction 58, which has the following format: 58XXSXXXXXXX. If this command is in the command register IR-I of the central processing layer, it generates the usual end pulse signal 614. In addition, this command generates the function table signal FT 704 _{at clock time i 0} to clear the register RP-I , and also the function table signal FT 858 at clock time ^. This function table signal FT 858 is coupled to the aforementioned AND circuits so that the sector address can be stored in digit parts 3 and 4 and the section number in digits 9 and 10 of the register RP-I (FIG. 14A). At the same time, function table signal F 858 shifts decimal zeros into digit positions 1, 2, 5, 6, 7, 8, 11 and 12 of register RP-I . This is done by coupling the function table signal FT 858 to the appropriate input lines 14A-IaS, 14A-2aS , etc. of the register RP-I (FIG. 14A). In this way the following word is stored in the register RP-I : 00SS00005500. The function table signal FT 858 is also applied to the OR circuit 45-6 to switch the sector address toggle circuit 45-8 to the set state, whereby the AND circuits 45-10 and 45-11 are opened and thus the next section and Sector address can be stored in the address register 45-26. Before this command can be started, however, it must be indicated to the central processing system that the synchronizer has finished storing the sector and tape addresses in the shift register 45-26 . The flip-flops 45-15 and 45-13 and the AND circuits 45-14 and 45-16 assigned to them are provided for this purpose.

The flip-flop 45-13 is set at the start of the reading operation by the output of the single pulse generator 45-5 and also by the output of the AND circuit 45-24 . The output of this AND circuit is designated SlSAF and is generated after the section and sector addresses have been stored in the shift register 45-26. The AND circuit 45-14 is opened by the output signal of the flip-flop 45-13 and the clock signals ti and t5. The flip-flop 45-13 is reset by the same clock signals. Since these clock signals are also applied to the AND circuit 45-14 , the flip-flop 45-15 is switched to the setting state. The set output of this flip-flop 45-15 is then applied to the main test circuitry shown in Fig. 28A to indicate to the central processing system that a particular operation has been completed by the synchronizer and that the next operation can be initiated. The AND circuits shown in FIG. 28A are checked at certain intervals by the main control loop or loop 99 of the central processing system. This inspection has already been described elsewhere. The setting output signal of the flip-flop 45-15 is also coupled to the test AND circuit 45-16 , at the other input of which the signal PS1 from the decryption device 10-31 shown in FIG. 10 is present. In addition, the function table signal FT 850 , which is generated by the encryption device 10-18 when an instruction 50 is in the instruction register IR-I, is also present at this AND circuit. The command 50 has the following format: 50 XXSXXMMMMM; he issued the following

ίο Instructions: Check toggle switch 45-15 of the drum synchronizer identified by the number S. If this toggle switch is set, go to the program which begins with the memory address MMMMM. On the other hand, if the toggle switch is reset, continue with the program indicated by the count 10 + 1 of the control counter. In summary, it can be stated that the command 50 is in a certain sense a test command that the

ao has the task of returning the program of the central processing system to the control program for the synchronization device , since the flip-flop 45-15 is set by the signal SlSAF when the information contained in a sector is to be read from the drum. By checking the AND circuit 45-16 , the command causes a signal CT to be generated when the flip-flop 45-15 is in the set state; this signal is coupled to the switching system provided in the central processing system for conditional jumps in order to incorporate the program of the central processing system into the next phase of the control program for the synchronizing device. The signal CT generated by the AND circuit 45-16 also resets the flip-flop 45-15, so that the flip-flop is always reset when a conditional jump occurs as a result of this check.

As the final circuit arrangement of FIG. 45, the sector 00 decryption device 45-22, the sector 0 flip-flop 45-17 for subtracting the value 2499 and the associated circuitry will now be described. This circuit arrangement

4.5 has the task of changing the address circuits to control in the distributor when a whole section or 25 sectors of the magnetic drum in the Main memory are to be stored.

The sector 00 deciphering device 45-22 is connected to the last eight stages of the shift register 45-26 and indicates when the sector number read into the shift register 45-26 corresponds to the sector number 00 of the drum. If the sector 00 has been stored in the shift register 45-26, an output signal is generated by the decryption device 45-22. This output signal from the decryption device 45-22 is coupled as a pass signal to the AND circuit 45-20. The signal SlSAF generated by the AND circuit 45-25 is present at the second input of this AND circuit. The output of AND circuit 45-20 is coupled to the setting input of sector 0 flip-flop 45-19 to indicate that sector 00 of the

The section just stored represents the next sector that is read out of the drum shall be. The setting output of the sector 0 flip-flop is sent as a pass signal to the

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AND circuit 45-18 turned on. In addition, two further pass signals are present at this AND circuit, namely the output signal of the number counter 46-47 (Fig. 46) corresponding to the eleventh digit and the 99-word output signal of the 100-word counter 46-48, 46. The output of AND circuit 45-18 therefore indicates that the last digit of the last word from sector 24 has been read. This output signal switches the flip-flop 45-17 provided for subtracting the value 2499 into the setting state. This flip-flop then generates the signal Sl S 24, which is connected to the address change circuit shown in FIG. 37 of the distributor.

The sector O flip-flop 45-19 is reset by the output of the decryption device 45-25 or by the output of the AND circuit 45-4 transmitted from the OR circuit 45-25 α.

For a general description of this circuit arrangement, it is assumed that in the case of restoring of a complete section, the synchronization device is to be operated in mode 2. Around describe the automatic address change that occurs when the synchronizer is operated in mode 2, it is assumed that the summary read command requires that the entire Information of a section (25 sectors) is stored in memory locations 4000 to 6499 shall be; It is also assumed that sector 10 is the first sector to reach the magnetic head. There each sector contains 100 words, the program of the central processing system does the multiplication 100 x 10 (i.e. the number of the starting sector) to get to the value 1000. This number 100 can then be added to the starting address 4000 identified by the summary command must be added and thus results in the new start address 5000. So if the When the end of sector 24 is reached, the address number 6499 should be included. In order to now read out the other data stipulated by the summary command to be able to d. H. the information located in sectors 00 to 09 is processed by the address changing device the required correction is automatically made in the distribution list by subtracting the value 2499 from the value 6499. on in this way the information read out from sectors 00 to 09 is put into the correct memory locations 4000 to 4999 stored.

46 shows in a simplified representation the circuit arrangement for the read synchronization device in order to transmit the information contained in the drum to the two input buffer memories assigned to the synchronization device and from there to be finally stored in the main memory of the computer system. For this purpose five information channels 1 to 5 are provided, each of which is assigned an amplifier 46-54 or 46-53. The output signals of these amplifiers are fed to the respective storage AND circuits, which in the present case are represented by AND circuits 46-55 and 46-56. The output signals of these AND circuits are coupled to the information input lines of two one-word buffer memories, which are assigned to this synchronization device and are shown in FIG. 39 are shown. For transmitting the information through the AND circuit 46-55 and 46-56 in addition to the information input lines still situated on a sector selection pulse SP, which is provided by the automatic sector selection circuit 46-72. The final input signal to these storage AND circuits is the setting output signal of an information flip-flop circuit 46-51. This information toggle 46-51 is in its set state when a reading operation is to begin, this setting being made on the assumption that the correct section and sector on the drum has been selected. To control the setting of the information flip-flop circuit 46-51, the read commands 53 or 55 or a command 57 are issued by the central processing system. Command 53 has the following format:

53 XXSXXXXXXX. It gives the following instructions: Switch on the drum synchronizing device 5 in mode 1, and transport the starting address located in the five least significant digits of the register RP-I to the memory address register 29-50 in the distributor. When the command 53 is stored in the command register IR-I of the central processing system, the following signals are generated:

1. The ordinary end pulse signal 614 for the AND circuit 11-34,

2. the function table signal FT 815 for the AND circuit 32-24 to clear the input buffers of the distributor,

3. the function table signal FT 820 during the cycle times t ₇ , t ₀ , t _± and t ₂ for the AND circuit 30-16 in order to prevent the priority instructions in the distributor,

4. the function table signal FT 817 during the clock times t ₇ and i ₀ for the AND circuit 32-12 to initiate the read-write cycle for the address registers of the drum read synchronization device,

5. the function table signal FT 819 at the clock times t ₀ , t ₂ , t _z , t _v, t ₆ , t ₇ for the AND circuits

36-12 etc. to prevent the output signals of the address register from being fed to the pulse shapers of the address register,

6. the function table signal FT 818 during the clock time t _x for the AND circuit 36-28 etc. in order to store the information contained in the five least significant digits of the register RP-I in the address register, and 7. the function table signal FT 853, the is generated during the cycle time t _s.

The flip-flop circuit 46-40 provided for operating mode 1 is set by the function table signal FT 853 and the simultaneous coupling of the signal PS1 to the AND circuit 46-42. At the same time, the output signal of this AND circuit 46-42 is coupled via the OR circuit 46-45 to the flip-flop circuit 46-41 «in order to switch it over to its setting state. The setting output signal of this flip-flop circuit 46-41 'is coupled to the AND circuit 46-49. At the other input of this AND circuit 46-49 is the Si

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signal SlSAF generated by the AND circuit 45-24 shown in FIG. If the correct sector is found and there is a command 53, the flip-flop 46-41 α is set. Next, the signal 5 ISAF is generated, which is coupled to the setting input of the information flip-flop circuit 46-51 via the AND circuit 46-49 and the delay device 46-50. The store AND circuits 46-55 and so on through 46-56 are prepared by the set output of this flip-flop. The signal SlSAF is also used to reset the flip-flop 46-41 a. Before this flip-flop is reset, however, this signal SlSAF is connected from the AND circuit 46-49 to the setting input of the information flip-flop 46-51. The information then read out from the five channels is coupled by the AND circuits 46-55 to 46-56 to the input of the odd or even word memories provided in the distributor. The information toggle circuit 46-51 can also be set by initiating a command 55. This command essentially corresponds to command 53; however, it is only used when a complete section is to be relocated. This command 55 has the following format: 55 XXSXXXXXXX; it generates the same function table signals as instruction 53, except that signal FT 855 is generated in place of signal FT 853. This command issues the following instructions: Switch on the drum synchronization device identified by the S digits in mode 2 and transport the start address contained in the five least significant digits of the register RP-I to the memory address register of the synchronization device S in the distributor. When command 55 is initiated, function table signal FT 855 is coupled to AND circuit 46-43. At the same time, the signal PS1 , which was generated by the decryption device 10-31 (FIG. 10), is connected to this AND circuit. The AND circuit 46-43 then generates an output signal which switches the flip-flop circuit 46-41 provided for mode 2 into the setting state. The output signal of the AND circuit 46-43 is also coupled via the OR circuit 46-45 to the setting input of the flip-flop 46-41 α , whereby the AND circuit 46-49 is opened under the influence of the signal SlSAF and the information Toggle switch 46-51 is set.

Finally, this information flip-flop 46-51 can also be set by the AND circuit 46-44. This AND circuit is prepared by a continuation instruction 57, which has the following format: 57 XXSXXXXXXX. This command 57 issues the following instructions: If a sector has been read out of or written into the drum via the synchronization device S , then store the next information sector in accordance with the previously set operating mode and in accordance with the memory address sequence. By storing the command 57 in the command register IR-I , the usual end pulse signal 614 and the function table signal fT857 are generated at the cycle time t ₃ . This function table signal FT 857 is applied to AND circuit 46-44. Since the signal PS1 generated by the S digit of this command is present at the same time at this AND circuit, an output signal is generated which is connected to the setting input of the flip-flop circuit 46-41 α via the OR circuit 46-45. As can be seen from the drawing, the settings of the flip-flops 46-40 and 46-41 are mutually exclusive, since the flip-flop circuit 46-41 is switched to the setting state by the output signal of the AND circuit 46-43, while the flip-flop circuit 46- 40 is switched to the reset state by the same output signal. In the same way, the flip-flop 46-40 is set by the signal generated by the AND circuit 46-42, while the flip-flop 46-41 is reset by the same signal.

The sector mark 10111 is recorded on the information tracks at the end of each sector. This signal, which indicates the end of a sector, is processed by a special decryption device 46-52 is detected, which then generates the sector end signal (ESS). This signal is used to to reset the information toggle 46-51 at the end of the currently read sector. The flip-flop circuit 46-51 is thus at the beginning of a sector by a corresponding one Command 53, 55 or 57 set and automatically reset by the sector end signal. If several sectors are to be re-stored, both command 57 and command 58 be started before the completion of the reading of the current sector.

The circuit arrangement shown in FIG. 46 also includes a number counter 46-47 of a known type which can count up to twelve. A word counter 46-48, which can count up to 100, is also provided. The digit counter counts the twelve digits contained in a word, and the word counter counts the words contained in the sector. Both counters are reset at the beginning of the read operation by the signal SlSAF and furthermore at the beginning of each sector, since this signal is generated once for each sector. In order to increment the digit counter, the circuit arrangement 46-72 generates a pulse SP for each character read out of the drum, which pulse is coupled to the AND circuit 46-46 in order to increment the counter. The AND circuit 46-46 is opened by the output of the information flip-flop 46-51, so that the digit counter is operated in synchronism with the reading of the digits through the AND circuits 46-55 and 46-56.

In order to advance the word counter 46-48, the eleventh digit of each word detected by the digit counter 46-47 is coupled to the AND circuit 46-58 and fed from there to the advance input of the word counter with a simultaneous activation of a pulse SP. It can be seen from the connections that the digit counter is reset after each word, while the word counter is incremented by one after each cycle carried out by the digit counter. In order to be able to control the storage of the information read from the drum in the input buffer memory of the distributor, the output signals SlWDl to SIWD 12 of a first group of twelve AND circuits are connected to the twelve write input stages of the odd word input buffer memory 39-12 . The first and last AND

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The circuit of this first group of AND circuits is denoted by 46-60 and 46-61. Similarly, the output signals 51 WV1 through 51 WV12 of a second group of twelve AND circuits, represented by AND circuits 46-62 and 46-63, are applied to the twelve write input lines of the even word input buffer 39-10 of the distributor turned on. At one input of these twelve AND circuits 46-60 to 46-61 and 46-62 to 46-63, the output signal of the digit counter 46-47 is present. In other words: the first AND circuit 46-60 of the first group of twelve AND circuits and the AND circuit 46-62 of the second group of twelve AND circuits are connected to stage 0 of the digit counter 46-47. The second AND circuit of each group of twelve AND circuits is connected to the second stage of the digit counter 46-47 and so on at the inputs of the twelve AND circuits 46-60 to 46-61 and 46-62 to 46-63 the setting output signal of the flip-flop circuit 46-57 provided for the control of the buffer memory, which is set by the delayed output signal of the AND ¹ circuit 46-49. In this way, the flip-flop 46-57 is set whenever the store AND circuits 46-55 to 46-56 are opened by the output of the flip-flop 46-51. The two groups 46-60 to 46-61 and 46-62 to 46-63 each consisting of twelve AND circuits are opened by the output signal of the flip-flop circuit 46-57. In order to be able to supply the words first to one buffer memory and then to the other, the odd numbers registered by the word counter 46-18 are combined and supplied via the line 51Z> to all even AND circuits 46-62 to 46-63. Similarly, the registered by the word counter 46-48 even numbers are combined and fed via conduit 51 V all odd write-AND circuits 46-60 to 46-61. In this way, the first word read out of the drum can be fed digit by digit to the twelve stages of the odd word memory via the AND circuits 46-60 to 46-61. At the same time , the signal SlRV is generated by the signal appearing on the line 51 V , which runs through the circuit shown in FIG. 32, so that the content of the even word register can be stored in the main memory. During the next word the word counter is set to an odd number; therefore the second group of AND circuits 46-62 to 46-63 is opened one after the other, so that the second word transmitted by the AND circuits 46-55 to 46-56 is stored digit by digit in the twelve stages of the even word register can. During this time, the in F i g. 32, the signal 51 D occurring in the circuit shown in FIG. 32 is generated so that the content of the odd word register can be re-stored in the main memory. While information from the drum is stored in one word register, the information contained in the other word register is fed to the main memory.

As the last circuit in FIG. 46, word query toggle 46-59 will now be described. This flip-flop is set by the output signal 11 of the digit selector 46-47 and thus indicates that one of the two word registers is full. The setting of the word interrogation toggle circuit 46-59 generates the signal 5 IRF . This signal is the one shown in FIG. 30 shown priority circuits of the distributor to indicate to the distributor that the one word register is full and the content of this register can be stored in the main memory. If the distributor has been given access to the memory, the circuit arrangement shown in FIG. 32 generates the signal SlRFR, whereby the word query toggle circuit 46-59 is reset. This indicates to the synchronizing device that the path to the memory is free and that the contents of the full word register can be stored in the main memory.

The delay device shown in FIG 46-50 between the output of the AND circuit 46-49 and the information flip-flop 46-51, has the task of delaying the opening of the AND circuits 46-55 to 46-56 until until the sector automatic selection circuit 46-72 operates. This is done in the beginning Each sector has a label associated with this circuit in the in connection with the write synchronization device described type recorded.

After completion of a complete sector relocation, the flip-flop 46-97 must be turned off in order to disable the AND circuits 46-60 to 46-63. This blocking is carried out by the AND circuit 46-64, at the inputs of which the output signal 11 of the digit counter 46-47, a signal from the circuit 46-72 and the signal 99 of the word counter 46-48 are present. These three signals together indicate that the last digit of a total of 100 words has been stored and the end of the sector has been reached. The flip-flop 46-57 is then reset and waits for the next signal SlSAF transmitted by the AND circuit 46-49, which sets the flip-flop 46-57 again and thus relocates the next sector.

Before describing a typical cycle of operation for the drum read synchronizer the write synchronization device and the circuit arrangements are described first, soft establish the connection between the drums and the synchronizing devices. Fig. 47 shows a typical circuit arrangement by means of which the drums and synchronizers be connected to each other. As this figure shows, the drums are connected to the individual synchronization devices a special bistable circuit arrangement or a through a thyratron controlled relay is used. In the simplified example where twelve drums and If a read and write synchronization device are provided, 24 such switches would be result. A typical switch is shown in Figure 47 at 47-1. This switch has an input ON and an input OFF, which are arranged so that the switch when the input is energized OFF is opened and closed when the ON input is excited. Around twelve drums with the To interconnect synchronizing device 1, twelve of these switches are provided. Another twelve Switches are provided around the twelve drums

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to be able to interconnect with the synchronization device 2.

The order in which the drums are interconnected with the synchronizing devices has already been described earlier. First the function table signal FT 852A and then the function table signal FT8S2B are generated by command 52. The function table signal FT852; 4 is applied to the AND circuits 47-26 and 47-27 in parallel in order to switch off the relevant synchronizer from all of the drums. For this purpose, the AND circuits 47-26 and 47-27 each receive a corresponding signal PS, which is derived from the 5-digit of the command 52. The AND circuit 47-26 controls the disconnection of all drums 1 to 12 from the synchronizing device 1, while the AND circuit 47-27 controls the disconnection of all drums from the synchronizing device 2. The output signal of the AND circuits 47-26 and 47- 27 is coupled to the input terminal OUT of all twelve bistable switches which connect the synchronizing device belonging to them to each drum. So z. B. in the case of the drum synchronization device 1, the signal PS1 generated by the decryption device 10-31 is coupled to the input terminal OUT of all twelve bistable switches of the synchronization device 1 via the AND circuit 47-26. The first and last of these bistable switches are designated 47-1 and 47-12 in FIG. 47, respectively. If the function table signal FT 852 A is generated on the basis of the command 52, the 5-digit of this command is decoded and in this case the signal PS1 is generated, which opens the AND circuit 47-26. The output signal of this AND circuit is then fed to all twelve switches 47-1 to 47-12 in parallel in order to first switch off the synchronizing device 1 from all twelve drums. The selected drum must then be connected to the selected synchronizer. This process also takes place under the influence of command 52. The function table signal FT 852 B is generated for this purpose. Like Fi g. 45 shows, the simultaneous coupling of the function table signal FT 852 B and the signal PS1 to the AND circuit 45-4 generates an output signal which is denoted by 51CON. This signal is used to select the read synchronizer. The signal 51 COiV is fed in parallel to the twelve AND circuits 47-13 to 47-25, the output signals of which are coupled to the corresponding terminals IN of the twelve switches which are assigned to the synchronizing device 1. A similar signal 52COiV is applied to the twelve AND circuits 47-29 to 47-41 in parallel in order to establish the connection between one of the drums and the synchronizer 2. All AND circuits 47-13 to 47-25 are prepared by the signal SlCON. The final selection of the drum to be switched on is made using the DD digits of command 52. These DD digits are decrypted by the decryption device 10-34 shown in FIG. 10A, as a result of which one of the twelve signals PD1 to PD 12 is generated. Each of the signals PD is supplied to the corresponding AND circuits from the two groups 47-13 to 47-25 and 47-29 to 47-41. So z. B. the signal PD1 is connected to the AND circuits 47-13 and 47-29, which control the bistable switch that connects the drum 1 to the synchronizing device 1 or 2. All twelve AND circuits 47-13 to 47-25 or 47-29 to 47-41 are prepared by the signal 51 CON or 5 2 CO N. These AND circuits are then opened by the signal PD, whereby the selected drum is connected to the selected synchronizing device.

Should z. If, for example, the drum 1 is connected to the synchronizing device 1, both the signal 51COiV and the signal PDl would be present. These two signals would be derived from the format of instruction 52, namely the 5 and DD digits. As a result, the AND circuit 47-13 would generate an output signal which would actuate the switch 47-1 and connect the drum 1 to the synchronizing device 1. If, on the other hand, the drum 1 is to be connected to the synchronizing device 2, the command 52 would generate the signal 52COiV and the signal PD 1 based on its 5-digit.

Command 52 and the function table signals FT 852 A and FT 852 B generated by it at different times therefore cause all drums to be switched off from a specific synchronization device and shortly thereafter a connection is established between this synchronization device and a selected drum, with all operations required for this can be controlled by the 5 and DD digits contained in command 52.

Drum write synchronizer

48, 49 and 50 show in simplified form the drum write synchronizer. Quite a few of the components shown in these figures are the corresponding components of the drum read synchronization device shown in FIGS similar. They also have to fulfill essentially the same functions as those in Fig. 45 and 46 components shown.

As shown in Figs. 48, 49 and 50, the drum type write synchronizer is included also an availability toggle 48-1. As in the case of the read synchronizer, this flip-flop set by an instruction 54 before a program to execute the synchronizer was required comes to an end. As already described elsewhere, generated the command 54 the function code HensignalPT854, thereby preparing the AND circuit 48-2.

The eighth or 5-digit of this command generates the signal PS 2 , which is also coupled to the AND circuit 48-2. The output signal of this AND circuit 48-2 is also connected via the OR circuit 48-7 to the reset input of the sector address toggle circuit 48-8 in order to ensure that this toggle circuit is reset before exiting the relevant program. Before using the synchronization device, it must first be determined whether this synchronization device is free. This is in turn done by an instruction 56 which generates the function table signal FT 856, whereby the AND circuit 48-3 is prepared.

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The eighth digit of this command 56 generates the signal at the beginning of command 52 in the setting state.

PS2, which is also found at the input of this AND-. The signal Sl CP is also on the

Circuit 48-3 is coupled. Since an OR circuit 49-49 is also added to the digit counter 49-47

the output signal of the availability toggle switch to reset it. In addition, the device is applied, the AND circuit 48-3 generates a 5 the signal S 2 CP via the OR circuit 49-48 α

Signal which is connected to the circuit shown in FIG

arrangement for conditional jumps is supplied, which is also to be postponed.

by the control of the central processing After the sector address toggle circuit 48-8 is sent to the program of the drum-write sync by the signal S 2 CP in the setting state chronizing device. This control has been switched, the setting signal causes this transfer of information takes place in the same way as in the case of the flip-flop circuit, the opening of the input and read synchronization device. shift AND circuits 48-10 or 48-11 of the from From the drawing it can be seen that the one 18 stages existing address shift register output signal S2AV of the availability 48-26, so that the flip-flop 48 contained in the sixth track -1 also at the reset input 15 section and sector address and the sector mark of the flip-flops 49-50 and 49-41 for which can be stored in the register 48-26. Operating mode 1 or 2 is switched on in order to ensure that the output signals of this sixth track are supplied so that these flip-flops are reset via an amplifier 48-9 and via the AND. After it has been adjusted on the basis of a command 56 fixed circuit 48-10 at the input of the address that the write synchronization device 20 shift registers 48-26 are switched on. When the output is free, the next command 52 must be signaled the sixth track will also be sent to one in order to connect the selected drum to the automatic sector selection circuit 48-12 of the other write synchronization device. It is known that command 52 first generates the address mark signals as long as the function table signal FT852A and at a sector address mark as well as the sector and later point in time the function table signal intersection address are in the sixth track. The FT 852 B. By means of the function table signal output signal of this circuit 48-12, the write synchronization device , the AND circuit 48-11 on all the shifting drums is switched off via FTSS2A. This operation of the address shift register 48-16 was already performed in connection with FIG. 47 described- 30 links.

ben. The function table signal FT 852 B as well as the sector mark consisting of ten information units on the basis of the eighth digit of the instruction 52 is stored in the first ten stages of the signal PS 2 at the input of the AND switch shift register 48-26, where their direction 48-37 coupled. This AND circuit, the presence of the decryption device, then produces an output signal which is detected by the return 35 48-25. This decryption device input is fed to the flip-flop 48-1, device 48-25 thereupon generates an output signal, which indicates that the synchronizing one- the OR circuit 48-25 α, whereby the operation is now used. Before the available shift register 48-26 is reset to 1 and the keits flip-flop is reset, the sector mark is removed from the shift register. The output signal of the AND circuit 48-37 still becomes 40. In this way, the shift register is transferred from AND circuit 48-4 to evacuate so that it will next generate the one in the sixth signal S2C0N. With the aid of this signal, the sector and section addresses contained in the track are used by the synchronizing device with which the exception can be made. The output of the OR-select drum is connected. As is known, circuit 48-25 α is also coupled to the reset the DD digits of command 52, the drum and 45 input of flip-flop circuit 48-23, whereby the 5-digit of this command prepares the synchronization by AND circuit 48-24 will. The device selected from the output of the sector mark at the end of the 18 shift pulses that follow the signal 52COiV derived from the ErUND circuit 48-4 are also completely supplied to a suitable delay in, sector and section addresses in the device 48-5, the z. B. a delay 50 shift register 48-26 stored. Can have to this of 8 milliseconds. The starting point in time is "1", to which the delay signal from this delay device 48-5 is coupled to the shift register by the decryption device on the line S 2 CP. This delay line 48-25 had been reset, in the last device 48-5 it has the task of the stage of the shift register 48-26 in FIG. 47. This "1" is shown as the switching relay for the magnetic head. 55 The second input signal to the AND circuit is to give sufficient time to close. The output 48-24 coupled, which thereupon an output signal of the delay device 48-5 is generated via signal that the OR circuit 48-6 to the setting input again to the setting input of the flip-flop circuit via the OR circuit 48-23 α the sector address toggle circuit 48-8 is coupled 48-23. At the same time the Auspelt and also the register 48-26 via the 60 output signal of the AND circuit 48-24 via the OR circuit 48-25 α in order to set this Re-OR circuit 48-7 to the reset input of the register to 1 postpone. In addition, the sector address toggle circuit 48-8 is switched on, where the output signal of this delay device 48-5 is blocked by the AND circuits 48-10 and 48-11 to the reset input of the sector address toggle and the sector and section address circuit 48 -23 switched on. This flip-flop 65 sensor information in the shift register 48-26 verist so that the reset signal remains through the.

Setting signal is suppressed. The signal 52CP The sector and section address can now

thus ensures that the flip-flop 48-23 is reversed by an instruction 58 in the register RP-I

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be saved. The command 58 generates the radio 48-33 are the clock signals rl, ί3, / 5 and Π of the tion table signal FT 858 and the signal PS2, clock generator of the central processing system. whereby the address via the AND circuits 18 These clock signals via the AND circuit 48-27 to 48-30 are in the register RPL is restored 48-33 and the OR circuit 48-34 can be connected to the Weiwerden. The function table signal FT 858 5 switch input 52ClC of the digit counter 49-47 and the signal PS 2 are also switched on by the. The reason for this connection is, AND circuit 48-35 transmit and open the output buffer located in the distributor normally the AND circuit 48-36, so that the memories during the storage of the sector flip-flop 48-8 via the OR circuit and section address information in the register can be set again. In this way io 26 should be evacuated. The clock signals ti, t3, the next sector and section address in the tS and ti, which are stored as output signal S2C1C of the registers 48-26. OR circuit 48-34 appear, switch the

Like the read synchronization device, the write synchronization device also contains a digit counter for at least two cycles during the time it needs to complete the device for subtracting the value 2499. This 15 registers 48-26 are filled. At the same time, the circuit arrangement includes the toggle switch signal S 2 GSAF as a pass signal to the AND-48-17, a decryption device 48-22 and circuit 49-65 of the step-by-step forwarding of a checking circuit which is coupled from the toggle switch control of the word counter. At lines 48-11 and 48-15 and from the Aufprüf-Kipp- other inputs of this AND circuit 49-65 circuit 48-16 consists. The flip-flop 48-13 ₂ o are the signal corresponding to the last digit is set by the signal S2SAF , which occurs at the digit counter 49-47 and the clock pulses tO, output of the AND circuit 48-24. The t2, t4 and t6 of the clock on. If the output signal of this AND circuit 48-24 is fed to the digit counter in the individual pulse generator 48-24 «corresponding to the number 11, which state is switched, the AND circuit is caused to generate the signal S2SAF at the clock time i ₂ 25 49- 65 under the influence of one of the clock signals iO occurs. The trigger circuit t2, t4 or t6 is opened by this signal. The output signal of this 48-13 is set and the AND circuit 48-14 before AND circuit is then prepared via the OR circuit. This flip-flop 48-13 is also set 49-63 and the pulse delay device at the beginning of a write operation by the signal 49-62 to the stepping input of the word counter S2CP . Coupled by coupling a clock ₃₀ 49-48. In this way, the word signal il or t5 , the AND circuit 48-14 · counter is incremented by one when the is opened, so that the toggle circuit 48-15 set digit counter has ended one cycle. Which can not become. The output signal of these toggle gears and even numbers of the word counter evaluation 48-15 causes the opening of the AND circuit of the combined, so that all even numbers 48-16, whereby the command 50, which generates ₃₅ the output line 52 V and all odd Numgung of the function table signal FT 850 causes mern the output line S 2 D of the word counter causes that a conditional jump signal is generated. The corresponding output signals are supplied to the circuit shown in FIG. 28 in a first group of twelve read AND circuit arrangements. So if a sector address and gen 50-70 to 50-71 and a second group of section addresses are written into the register 48-26, ₄₀ twelve read AND circuits 50-72 to 50-73, the toggle circuit 48- 15 always fed in parallel, which in turn provides the read lines. If this flip-flop is then in the odd and even word output buffer storage in its setting state, then it is more likely to control the synchronizing device 2 by the command. So 50 always put back. The for subtracting is z. B. the straight line 52 V in parallel to the toggle circuit provided for the value 2499, which ₄₅ twelve digit AND circuits 50-70 to 50-71 are coupled to the signal 52524 for controlling the address, in order to activate these AND circuits during change device ( Fig. 37), the output signal of the AND circuit 48-18 is prepared by an even count of the word counter. The output signal S2D of the word counter is set and, by contrast, the twelve AND circuits 50-72 to circuit 48-25 α are reset by the output signal of the OR. The following input signals are applied to the AND 50 50-73 in parallel to this AND circuit 48-18: gen to prepare the signal corresponding to the counter 98 during an odd count. At the second input of the odd AND word counter 49-48, the one corresponding to the tenth digit, the corresponding speaking signal from the digit counter 49-47 and digit signal from the digit counter 49-47 is present. This output signal of the sector-O-decryption signal ₅₅ is likewise also on the straight AND device 48-22. The trigger circuit 48-17 will turn on circuits 50-72 through 50-73. At the third input, that is, while the sector number of these AND circuits is being stored, the 24 is finally set in order to correct the address in the manner already written by the OR circuit 50-74. S2GSAF on. The twelve even AND circuits

From the description it follows that the toggle 60 are so consecutively by the number counter

circuit 48-23 in the time segment between the open during an odd word count

Capture the sector address mark and the captured while the twelve odd AND circuits

sung of the overflow pulse at the eighteenth stage in succession by the digit counter during one

of the shift register 48-26 was reset and the even counter registered by the word counter 49-48

therefore generated the signal 5 2 GSAF. 65 stand to be opened.

This signal is sent as a pass signal to the As Fig. 48 shows, through the signal AND circuit 48-33 of the digit counter connected to S2SAF, the flip-flop circuit 48-35 for the sector. At the other input of this AND circuit address register and the trigger circuit 48-31 for

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the step-by-step advancement of the digit counter is postponed. By resetting the toggle circuit 48-31 , the AND circuit 48-32 in the control circuit of the digit counter is blocked. As is known, the AND circuit 48-33 was blocked by switching off the signal S 2 GSAF. After the two AND circuits 48-33 and 48-32 are blocked, there are no more signals at the incremental inputs of the digit counter 49-47 and the word counter 49-48. The digit counter 49-47 and the word counter are reset to 0 by the signal S2 & 4F transmitted from the OR circuits 49-49 and 49-47.

The signal S2SAF, which is generated when the sector and section addresses are in the address shift register, thus interrupts the operation of the digit and word counter, so that the sector and section address information remains stored. At this point, command 58 can now be started to determine whether the correct sector and tape address has been set on the drum. As a result of the initiation of this command, the read-out AND circuits 48-27 to 48-30 assigned to the address register 48-26 are opened by the function table signal FT 858 and the signal PS1 generated by the 5-digit of the command 58. Command 58 also opens AND circuit 48-35, as a result of which flip-flop circuit 48-35 α is set for the sector address register. The output signal of this trigger circuit 48-35 α is normally coupled by the AND circuit 48-36 to the setting input of the trigger circuit 48-8. In this manner, the next sector and section address information can be shifted into shift register 48-26. The AND circuit 48-36 α is opened by the output signal of the multivibrator 48-35 α. This AND circuit then represents the current path via which the flip-flop 48-8 is set during the actual writing process.

If the comparison carried out after the initiation of command 58 shows that the sector on the drum is correctly set, the program can initiate a start command 53 or 55, depending on the operating mode in which the synchronizing device is to be operated on the basis of the summary command . The AND circuits 49-42 and 49-43 are opened by the command 53 or 55, so that either the toggle circuit 49-40 for operating mode 1 or the toggle circuit 49-41 for operating mode 2 is set. In addition, the command 53 or 55 causes the setting of the start trigger circuit 49-41 α via the OR circuit 49-45. The AND circuit 49-90 is opened by the setting output signal of this start trigger circuit 49-41 α, so that its output signal 49-90 when the next signal S2SAF is generated sets the trigger circuits 49-52 and 49-53 and at the same time the word query Toggle switch 49-59 resets. These settings or resets are required in order to be able to initiate a write process.

The setting of the flip-flop 49-52 generates the signal S 2 WSS ¹ which is used to generate a sector selection start signal before the information is recorded. For this purpose, the signal generator 50-80 is switched on by the signal S 2 WSS . The output signal of this generator is via suitable OR circuits, such as. B. the OR circuits 50-78 and 50-79, coupled to the five intended for the write control AND circuits 50-76 and 50-77, which energize the five heads associated with the drum. In addition, the signal S 2 WC , which is generated by the setting output of the flip-flop circuit 49-53 provided for the write control, is present at these AND circuits. As from the

ίο the drawing can be seen, this flip-flop is also set by the signal S2SAF due to the initiation of a command 53 or 55. The AND circuit 48-36 is also blocked by the signal S2 WC in order to prevent the flip-flop circuit 48-8 from being further set via this current path. After a period of 54 microseconds, the pulse generated by the generator 50-80 can be switched off and the system can be prepared to receive the information received from the output buffers of the distributor.

enroll ao mation. For this purpose, the signal S2SAF is delayed by a delay device 49-50 by 54 microseconds and then coupled via the individual pulse generator 49-51 to the reset input of the flip-flop circuit 49-52 in order to switch off the signal S 2 JFSS and thus the generation of the signal from the generator 50-80. The individual pulse generator 49-51 causes the delayed output signal to appear at the cycle time t _2. While the start signal is being generated by the generator 50-80, the two output buffer memories connected to the synchronization device can be filled with information from the main memory, so that these buffer memories are ready for operation at the beginning of the actual writing process. For this purpose, the output signal S2SAF of the AND circuit 49-90 is coupled via the OR circuit 49-55 to the reset input of the word query toggle circuit 49-59. The reset output signal of this flip-flop circuit and the output signal S 2 WC of the flip-flop circuit provided for the write control open the AND circuit 49-68 and generate the signal 52i? F which informs the distributor (FIG. 31) that a word is from main memory can be transferred to the output buffer. If the distributor receives access to the main memory and a word is transferred from the main memory to the output buffer memory, then the in FIG. 33 generates the signal S 2 RFR , whereby the word query circuit 49-59 is set again. The signal S2SAF generated by the AND circuit 49-50 is also fed to a delay device 49-54, where it is delayed by 30 microseconds.

The output signal of this delay device is then coupled again to the reset input of the word interrogation toggle circuit 49-59 via the OR circuit 49-55 so that the second word can be interrogated and stored in the second output buffer memory. The signal S2WCSD generated by the delay device 49-54 is connected via the OR circuit 49-63 and the pulse delay device 49-62 to the stepping input of the word counter 49-48 in order to step the word counter from 0 to 1 in order to output from turn off the line 52 V and couple it to the line S 2 D so that the second word in the two

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th output buffer memory can be stored.

After the write heads have been energized via the toggle circuit 49-53 , the signal for the address mark has been generated and the two buffer memories have been fully stored, the information in these memories can now be written into the drum and further words can be queried in order to continuously fill the two memories. For this purpose, the multivibrator 48-31 provided for controlling the counter is set by the output signal S 2 WSSR of the pulse delay device 49-51 . The setting output signal of this flip-flop and the clock signals 1 1 and tS are coupled to the AND circuit 48-32. The output signal of this AND circuit then advances the digit counter 49-47 , which in turn advances the word counter via the AND circuit 49-64 . While the digit counter is being advanced, the two groups, each consisting of twelve read AND circuits 50-70 to 50-71 and 50-72 to 50-73, are passed through the digit counter 49-47 and through the lines 52 V and SID of the word counter 49 -48 alternately prepared. These AND circuits 50-70 to 50-73 are then opened by the coupling of the clock signals t0, ti, t4 and tS, which are transmitted by the AND circuit 50-75. This AND circuit is opened by the signal Sl WC and blocked by the signal 52 WSS.

If the digit counter reaches the counter reading 9, the next word is queried in order to be stored in the buffer memory from which the information is currently being read. This word query is caused by the OR circuit 49-61 via the AND circuit 49-60 . The ninth and tenth digits of the content of the digit counter 49-47 are applied to this OR circuit. The AND circuit 49-60 is prepared by the output signal Sl WC of the flip-flop circuit 49-53 provided for the write control and blocked by the signals 99 and 100 of the word counter 49-48. The output signal of the AND circuit 49-60 is connected via the OR circuit 49-55 to the word query toggle circuit 49-49 in order to reset this toggle circuit at each cycle of the digit counter. In this way, an output memory is filled with information from the main memory, while the information located in the other memory is output digit by digit to the writing head of the drum. Since both buffers were filled at the beginning, the further word queries can be stopped when the word counter reaches the counter reading 99, since the word counter is one counter ahead of the word just written into the drum. For this purpose, the counter positions 99 and 100 of the word counter 49-48 can be used to block the AND circuit 49-60 in order to prevent further words from being interrogated when the word counter has reached this count. Next, the end mark must be written into the information section of the drum and then the write control current flowing into the head must be switched off. For this purpose, the word count AND circuit 49-67 receives a signal when the word counter reaches the count 101. The signal of the number counter 49-47 corresponding to the number 1 and the clock signals ti and t6 of the clock generator are also applied to this AND circuit. The output signal 52 WESS generated by this AND circuit 49-67 is fed to a generator 50-81 which generates the signal for the end mark of the sector. The signal of this generator 50-81 is connected via the OR circuits 50-78 to 50-79 provided for the five tracks to the AND circuits 50-76 to 50-77 provided for the write control in order to set the end mark of the sector in the Inscribe information section. As is known, this end mark is used by the read synchronization device to end the read process at the end of a sector. After this end mark has been generated, the toggle switch 49-53 provided for the write control can be reset. This reset is carried out by the output signal of the AND circuit 49-66, at the inputs of which the SignalOl of the word counter 49-48, the signal D 3 of the digit counter 49-47 and the clock signals ti and t6 of the clock generator are present. Due to the coupling of these signals, the AND circuit 49-66 generates the signal 52 WCR. This signal resets the toggle switch 48-31, which is provided for the step-by-step advancement of the counter, in order to prevent further activity of the digit and word counters. This signal is also coupled to the reset input of the flip-flop circuit 49-53 provided for the write control in order to switch off the write control current and the signal 5 2 WC from the AND circuits 50-76 to 50-77 and the AND circuit 50 -75 to lock. If several sectors are to be written into the drum, a command 57 is started while the first sector is being written, as a result of which the start toggle circuit 49-41 α is set again.
The instruction 58, which would occur in this connection, sets the flip-flop 48-35 α , so that the AND circuit 48-36 α generates an output signal when the signal 52 WCR is generated at the end of the sector, whereby the flip-flop 48-8 is set again so that the next sector and address information can be stored in register 48-26. As a result, a further signal SlSAF is generated, which is transmitted by the AND circuit 49-90 and initiates the write process described above again.

Drum reading program

Figs. 55 through 58 show a simplified flow chart a summary drum read command.

This drum summary read command has the format 8SSNNDDMMMMM, while the drum summary write command has the format 9 SSNNDDMMMMM. The summary read command issues the following instructions: Read iViV 100 word sectors continuously from the drum DD , starting with the sector SS. Store the words in successive memory locations in ascending order, starting with the memory location MMMMM. When changing

storage of a complete drum section is 55 equals 00 and NN equals 25. The write command gives the same instructions, but refers to a write operation. Since both commands

509 538ß73

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the current summary command is a read command. After it has been determined that there is a read command, the next step is to determine whether the read synchronizer is free. This check is made by an instruction 56 and is indicated by block 55-4 . As already mentioned, the instruction 56 generates the function table signal FT 856, which the AND circuit 45-3 shown in FIG. 45 checks.

is not free so that this summary command can be executed as soon as the read synchronizer is not busy.

In the present case, however, it is assumed that the test shown in block 55-4 has determined that the read synchronizer is free. As the next program step, the read synchronization device must now be connected to the drum.

that are similar to each other, will only be discussed below the read command is described.

As already mentioned, each drum has its own memory block in which the assigned ones are located summary orders are located. This memory block contains both the read and write commands as well as the commands for motion control. As already ii * connection with the in Figs. 51 through 54 for the flow chart shown in Figs

Control of the drum movement has been described, io If the synchronization device is not occupied, the command 31 causes the control of the zen to generate a conditional jump signal, whereby the central processing system goes to the program via the program of the central processing system to which the summary command processed. Reference is made to the program which begins with the ejection of the drum action toggle switch at the end of the summary command. If the synchronization device of the control program for the drum movement 15 is occupied, the z. B. set by a command 32. Return to the control loop through the program; This pre-setting of this flip-flop is the central gear is shown in block 55-5. At this point, the processing system again causes the program to mention that the summary command should be entered into a program which processes the next summary command, the table command with the memory block, which is designated in the memory read synchronization device, a block of the drum in question is located (Fig. 51). is stored when the synchronizer. In the following description it is assumed that
that the previous summary command for the
drum described here was a setting command
and that the movement counter during the 25
execution of this command was reset to 0.
The comparison shown in block 51-2 would be shown in
in this case indicate that the results are the same.
This would mean that the next in the block

51-3 could be executed. 30 be bound. This is done in the manner shown in block 55-6 Corresponding to this instruction is the next shown. To this end, each contains

Program for the synchronization device an instruction 52 with a corresponding 5-digit. the The number of the drum which is to be connected to the relevant synchronizing device results from the sixth and seventh digits of the summary command to be processed. The DD digits this command is included in command 52 contained in the program for the read synchronizer

Register RP-I must be checked whether this instruction 40 is combined (block 55-6). This command 52, which represents a data transfer or a further program, now the relevant synchronization device program for the drum control. This, as well as the corresponding DD digits, is checked is indicated by block 55-2 and then, in the manner shown in block 55-7, the execution of command 19 (size or guided. As from the read synchronization device equality check ). The summary commands 45 direction showing F i g. 45 to 47 can be seen, for the drum movement, all drums with the highest value due to command 52 contain a "0", while the read and write commands from the relevant synchronization device are switched to their highest and then the selected drum-valued digits an »8« or a »9« corresponding to the selected synchronizing device. Tied instruction 50 given in block 55-2. At the same time, this command causes the would mean that the summary command AND circuit 45-4 is to compare the setting of the sector with a constant value, e.g. B. address flip-flop 45-8 to switch the sector and Ab with a value that, with the exception of an "8" in the interface address, is read out of the drum and the most significant digit in all other digits in the address shifting unit consisting of 18 levels. The numerical value of a 55 register 45-26 to be stored . After the initiation of the read or write command is greater than this, the command 52 and the value constant during the selected drum, and the program would therefore proceed to the instruction given in block 55-3 with the relevant synchronizing device. is bound, the program executes the step shown in block 55-8, a size comparison is to be carried out here too, ie it sets the step shown in and the summary command is shown here with a variable program shown in FIG. 55

summary command to be taken from the drum memory block. In the description that follows, let Assume that this summary command is a read command for drum 1.

The removal of the summary command from the memory block assigned to drum 1 is shown in FIG 55 indicated by block 55-1. After saving the summary command in the

second constant value, such as B. 90 ..., compared, to indicate whether the current summary command is a read or a is a write command. The format of the read and write commands shows that im In the case of a read command, its size value is less than 90 ... The result of the performed in block 55-3 Examination therefore indicates that it is

connection X in such a way that the program designated by connection A is entered. The program can then return to the control loop (55-9).

Command 52 shown in block 55-7 also sets flip-flop 45-16 so that the summary command program can be re-entered from the control loop

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(55-10); that is, the control loop finds the toggle. First it is assumed that the sum-

circuit 45-15 is pre- set if the program encompasses a complete section of some command.

enters the control loop and the next loop is to be saved and that as the next step

test 99 is performed (55-10). The program is executed in the subroutine of step 56-6, the program then enters through port A 5. This step is the starting memory address

(Fig. 56) a designated subroutine. calculated for the transfer. This initial

After the drum with the synchronization address is - as already described

device has been connected, must next is - calculated, d. that is, those with the M-digits of the

the accuracy of the setting command must be checked, summary command marked initial d. that is, it must be determined whether the solenoid address is changed to take into account that

head is set to the correct drum section, the first sector to be read out is not sector 00

is. For this purpose an instruction 58 is executed. As mentioned earlier, supposed to be adopted

(56-1). With this command, the sector and will become that with the summary command

Section address from register 45-26 relocated to the Re-identified start address of the entire register RP-I ; in addition, through 15 the average is 5000 and that sector 10 is the first

this command causes the next sector and sector to be read out. The program

Section address written in register 45-26 then multiplies the number of the first sector (in

will. After the sector and section address this case 10) with 100 and added the product

has been transported to the register RP-I , it can (1000) to the

into main memory, e.g. B. in the memory location 1162, 20 marked start address. Those in the sectors

can be saved. Thereafter, the information contained by the 10 to 24 can then from the

Command 58 (block 56-1) read out actual read-out drum and successively in the

section number compared to the section number are stored in the memory, whereby the

which starts with the address 6000 due to the previously executed total storage and at

ric command for the motion control designates 25 of the address 7499 ends. After the sector 24

became. For this purpose, the section can be read out, then the sec-

Numbers that were entered into addresses 5000 to 5999 by the previously executed totalizers 0 to 9

ric command for motion control received can be saved.

were, in the main memory, z. B. in the memory After the above arithmetic operation, the toggle point 857 will be stored. This comparison 30 circuit 45-15 by an instruction 50 again is shown in block 56-2 . If this is checked (block 56-7). This is to ensure that the comparison is made by the summary command that after step 56-1 no new section, sector and section address marked for the motion control has not been written into register 45-26 with the one read out of the drum . If a new address matches a section, then 35 is written in, so a program, a subroutine for the new start address must be computed by means of step 56-6 second instruction 58 (block is set (56-4). If, on the other hand, the comparison 56-9) is carried out and the program to step indicates that the will be returned by the summary instruction for 56-6 . In the present operation, it is assumed, however, that no new section has been written with the sector address read from the drum. Therefore, if a section matches, the program executes the start command, in this case command 55, left on in the step shown in block 56-3. In this (block 56-8). As is known, the step causes the initial sector number SS 45 drum obtained from the current sum command 55 to start flowing into the buffer memories. At the same time as the number of sectors NN , the start address is stored in the register storage location (1141) , whereupon the program RP-I continues in the storage address register of the distribution program at connection E. relocated. For this purpose, after it has been determined that the starting address calculated in step 56-6 is already set in the correct drum section, 50 register RP-I, so that the starting address is next to be determined whether the address is correct of command 55 is automatically stored in the memory synchronization device in mode 1 or 2 when the address register of the distributor is stored. As is well known, the synchronization device works. After the start command has been initiated and before a complete copy is saved before it is executed, certain accounting cuts (25 sectors, starting with sector 00) can be carried out in 55 steps. So z. B. the actual operating mode 2; on the other hand, if a predetermined number of borrowed initial sectors are to be stored, e.g. B. in sectors that are not a full section of storage location 1030 (block 56-10). If the beginning corresponds to being re-stored, then the syn- sector works from the previously in the memory location chronising device in operating mode 1. The sector and section of the memory location 1141 now stored in 1162 is the starting sector 55 60 address as a result of steps 56-1 and / or. 56-9. and then, which is also located in this memory location, the end address in the number NN of sectors is therefore calculated with the step 56-11 and compared to the value 0025 (56-5) in the main memory for test purposes. If this comparison results in the same result (e.g. stored in memory address 1167) , this means that this end address is indicated in the case of a complete section that an entire section should be relocated 65 Section relocation should be one less than that (operating mode 2 ); in this case the start address is used. Next, in step 56-12 , the variable port X is set with that shown in block 56-6 to continue that step. Transfer the control program to connection B. At-

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then the program goes to the control loop z. B. in the memory address 1030, stored over, so that the program will be loaded with a next. This process is carried out in step 56-19 failure 50 (step 55-10) that shown in FIG. Then the end address can be calculated and the subroutine follows. also in an allocated memory location

Before describing the 5 shown in Fig. 57, these must be stored (blocks 56-20). It is assumed for these end program steps that the comparison carried out in the address can be used for test purposes at the end of the pro step 56-5 of an unequal program. Then the result would have been, indicating that changeable port X (Fig. 55) is set to perform a read or write operation in mode 1 so that the program at port B is performed. In this case the anio could continue.

catch sector SS of the summary command in the main As F i g. 57 now shows, if the

memory, e.g. B. in memory location 1167, a program at connection point B can be stored by the (block 56-22). The next step shown in block 57-1 would be carried out, an instruction 58 would be carried out to read out the actual if the program was to read out again by executing the borrowed sector address, step 55-10 from the control loop back to the (block 56- 13). This actual sector and section address provided for the execution of the read command would again be returned to the main memory when the program has returned, that is to say when the for example are stored in memory location 1162. Subsequently, the changeable connection X would be set in the address register 45-26 in such a way that the program was set at the sector address storing the anao. To end point D (Fig. 55) can continue (block this purpose is from the number representing the number 56-14). After the setting of the changeable other represents the sectors to be processed, and which conclusion X is stored in memory location 1141 by the summary data, the incorrectly provided and now value 1 in memory location 1167 is deducted. The remaining start sector address stored in can then be compared with the actual number contained in memory location 1141 with "0" contemptuous sector address, which are equalized by the (step 57-2). In this case, first command 58 was provided and it is assumed that the memory address 1162 carried out in step 57-2 is located. This comparison will result in an unequal result and thus indicates, by means of the step shown in block 56-15, that command 18 is still being read out further sectors. If an unequal result arises from this comparison before the end program can be started, then the problem would be possible. In this case, the control loop will be switched to after the scan. If step 57-2 were carried out, steps 57-6 (command control loop then by a test command 50 that 58) and 57-7 (command 57) would be carried out. This starts the program again (block 55-10), so the next sector would be read out. After executing the program at connection point D (Fig. 55), step 57-7 will continue to the current sector number; That is to say, the sector and section address that was previously stored in the memory location 1030 in step 57-8 would be stored out by a series of commands 58, with the value 1 added. Are read there, and after each of these commands 58 by the current sector address is corrected and a comparison (block 56-15) would be carried out can be used for test purposes. After passing through, until an identical result 40 execution of step 57-8 is obtained in the memory, which then indicates that the address 1030 located sector address with the actual desired starting sector is correctly set. Has compared the actual sector provided by instruction 58 with the test number shown in block 56-15. This comparison will give the same result in step, so that is carried out by 57-9. If the actual sector M digits of the summary command marked 45 corresponds to the start address of the register RP-I (block 56-16) sector number in memory location 1030, then the control loop can be transported left in order to carry out the start . However, if this comparison results in a command to be available. Subsequent difference, this could be due to the tilting provided for a sector change, that sector 00 was exceeded. In a circuit again checked by an instruction 50 50 such a case will be subtracted from the memory location 1030 (block 56-17) to ensure that the contained sector address has the value 25 ). Then in step 57-11 the memory address register 45-26 is to be stored - the calculated sector address with which the sector was not set again. Would this be compared to the actual sector address. If the case is true, the program would give the same result to this comparison in steps 55, then repeats 56-13, 56-14 and 56-15 until the program returns to the control loop; by the prospect in step 56-15 gives the same result. If step 55-10 has been carried out, the sector is not changed again, however, the reading program is entered after. If the comparison carried out in the test carried out in step 56-17 in step 57-11 results in an unequal start command, in this case command 53, left on. 60 Result, an error program must be started As already mentioned above, this will, under certain circumstances, make a message to the command that is now contained in the register RP-I and the summary command again address in the memory address register of the Execute.

divider. At the same time, the read After the program connects point B

Synchronizing device switched on in operating mode. 65 has run through several times, the after the initiation of the command 53, the actual storage location 1141 stored sector number is reduced to 0 by the command 58 (block 56-13), and the comparison carried out in step 57-2 Start sector address in main memory, gives the same result, which indicates

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that all sectors identified by the summary instruction have been processed and the program can thus be terminated. Finally, assuming that the sector number currently in memory address 1141 has decreased to 0, the accuracy of the program can be checked as follows: In step 57-3 an instruction 58 is started and the current sector and section address becomes read out and stored in the register RP-I. The expected last sector located in storage location 1030 is compared with the sector actually read from the drum in step 57-4. If this comparison yields an unequal result, an error has occurred and an error program must therefore be carried out. If, on the other hand, the comparison shows the same result, then no error has occurred in the reading program, and the changeable connection X can be set so that the end program can be started at connection point C. This setting of the changeable connection X to the connection point C is carried out in step 57-5.

The execution of the end program is shown in detail in FIG. 58 and consists in reading out the memory address contained in the memory address register RP-I of the distributor by executing instruction 41. This process occurs in step 58-1. This address is then compared with the calculated end address, which is located in memory location 1167, by command 18 (step 58-2). If the result is not the same, an error has occurred and an error program must be carried out. If, on the other hand, the result is the same, then the next summary command located in the memory block of the read synchronization device can be carried out. The action toggle of the drum for which a summary command has just been executed is set in step 58-3 so that the next summary command contained in the drum memory block can be executed. A command 54 can turn off the drum from the synchronizer in step 58-4. In this way, the synchronization device is available for further tasks and the program is transferred to the control loop. As shown in steps 55-1 through 55-8 of the flow chart in FIG. 55 can be seen, however, the next summary command located in the memory block of the read synchronization device can be read out beforehand and the drum can be connected to the synchronization device.

Magnetic tape storage

The input and output devices 12 contain devices for storing information on magnetic tape. For this purpose, band devices arranged in groups can be provided, these groups each being controlled by a synchronizing device. However, it is sufficient at this point to describe only one of these groups and the synchronization device S3 assigned to it. For this purpose, reference is made to FIG. 59 to 73 referenced.

The description is limited to the use of digital data for magnetic tape storage; however, alphabetical data can also be used for this purpose. The digits 0 through 9 will be each represented by five magnetic signals arranged in a line, which runs transversely to the magnetic tape. An additional magnetic signal is also provided for each digit, but not for the encrypted representation of the digits, but for the forwarding of the respective line of digits is used; this signal is referred to as the synchronization signal. Reading or writing information takes place at high belt speed,

ίο at a speed of 100 inches / sec. The lines can be recorded with different densities; in the present case, however, only the most common density of 200 lines per inch taken into account. The minimum length of a series of basic data on a magnetic tape consists of ten words, each containing twelve digits, for a total of from 120 lines of digits. A data block can contain any number of ten-word series. While When writing the data, a space of 1 inch can be provided between the data blocks will.

Ten tape devices are combined into a group to which a synchronization device is assigned. The essential components of a tape deck are shown in diagrams in FIGS. 72 and 73. As the block 73 α shows, the magnetic tape is guided in loops between two reels 73 b and 73 c and a central drive wheel. Is associated with the tape an assembly 73e magnetic read-write heads which is located in the vicinity of the central drive wheel, wherein (Ziffernbitsteilen and Synchronisierbitstelle) is provided a magnetic head for each bit position of a line. The coils 73 b and 73 c each have their own (not shown) motor by which they are driven directly. Braking takes place by means (not shown) that act on the motor shaft. The middle drive wheel 73 d is driven by a switchable motor 73 CDM via a fast-acting magnetic coupling, the coupling magnet 73 / of which is shown in the drawing. The braking forces act on a part driven by the clutch when a brake magnet coil is excited. In the forward direction, the tape is fed from the reel 73 b to the reel 73 c; it is in this direction that the read and write operations are normally performed. But reading operations may be on command, carried out in the reverse direction, ie when the tape from the reel 73 c is transported to the coil 73b; this direction also represents the rewinding direction. The magnetic tape loops provided between the reels and the central drive wheel make it possible to accelerate and decelerate the central drive wheel faster than the reels. Means are provided to automatically adjust the size of the tape loops in accordance with the intended tape feed direction, a larger loop initially being formed between the supply reel and the central drive wheel.

The tape device includes six power ports (thyratron tubes), which are shown in FIG. 72 as a block diagram. These power gates have the following designations: main interlocking power gate 72M / G, backward - power gate 72BG, forward - power gate 72FG, rewinding power gate 72 R WG, read power gate 72RG and write power gate 72 WG. The main interlocking gate 72 MIG is switched on by hand.

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while the remaining five power gates are controlled by the synchronizer.

The connection terminals of the current gates can be found in the main intermediate barrier current gate shown in the drawing and have the following designations: anode terminal A, extinguishing terminal £ and first and second grid ignition voltage terminal gl and g2. By connecting the erase terminal to earth, negative pulses are applied to the anode, which initiates the erase process. The terminal gl of the main partition inhibit current gate is grounded above the blocking voltage, while the remaining grid terminals of all current gates are normally below the barrier potential.

In order to be able to work with a tape device, its main interrupter current gate 72 MIG must first be ignited. For this purpose, a switch 72 a is actuated by the operator, whereby a connection to a positive 246 V line is established and the relay 12RM is actuated. As a result, contacts 1 and 2 of the relay close, with contact 1 providing a current path that bypasses the on / off switch, while contact 2 closes the voltage transmitted via the 246 V line via known safety contacts 72 AT shown by a dashed line a point 72 D and via a capacitor 72 C to the second lattice clamp, the point 72 D leading via the main interlock relay to the anode of the main interlock current gate. This will fire the main interlock gate and energize the main interlock relay. The contacts 2 of this relay close while its contacts 2 open, so that the relay HRM drops out.

The main interposer gate can be switched off by pressing a switch 72 b. It also goes out automatically when firstly the power supply is interrupted, secondly one of the safety contacts 72 X opens, thirdly the limit switch 72.FL provided for feeding the tape in the forward direction closes during the forward movement or fourthly the limit switch provided for feeding the tape in the reverse direction BL closes during the rewind, which is indicated by the closure of the contacts 12BRl of the rewind relay, provided, however, that no rewinding process takes place and the contacts 72 RWRl of the rewind relay have not opened.

The current gates controlled by the synchronization device are ignited with simultaneous grid control. Their anode terminals are connected to the positive voltage source 246 V via relays. Their first grids are on a common line 72c on which the selection signal 61 SXT for the tape device is transmitted. This signal raises the potential of the first grid above the reverse voltage, and prepares the current gates to fire as soon as a selectively generated selection signal is connected to their second grid. If a read operation is to take place in the forward direction, the selection signals 60FP and 60 RP are switched on during the selection interval. The signal 60FP ignites the flow gate 72FG (if this has not yet ignited) and actuates the relay 72 FR (flow relay), while the signal 60 RP ignites the read current gate 12RG and thus energizes the read relay 12RR. If a read operation is to take place in the reverse direction, the signal 60 BP is switched on in addition to the signal 60 RP , which ignites the return current gate 12BG (if it has not already ignited) and thus energizes the return relay 72 BR. If a write operation is to be carried out, the signals 60 WP and 60FP are given. The effect of the last-mentioned signal has already been described. The signal WP ignites the write current gate 72 WG and thus excites the write relay 72Wi ?. During a rewinding operation, the tape synchronizing device generates the signals 60 BP and 60RWP. The effect of the signal 60 BP has already been described. The signal 6Oi? WP ignites the Umspul-Stromtor72i? * FG and thus energizes the Umspul relay 12RWR.

The read current gate 12RG is cleared at the end of a read operation by a read shutdown signal generated by the synchronization device, while the write current gate 72 WG is cleared at the end of a write operation by a write shutdown signal.

If the return flow gate has ignited and the flow flow gate is then ignited, it goes out the return current gate, as the contacts 1 of the flow relay close and the extinguishing terminal of the return current gate to earth. On the other hand, it has the flow gate based on an earlier selection ignited and the return current gate is ignited during an occurring selection process, the flow relay goes out as a result of the closure of contacts 2 of the return relay 72Si ?.

The purpose of rewinding the magnetic tape is to rewind the tape to the first data block so that the read / write position can be read during the subsequent advance. If the tape has reached the first block position, this is indicated by closing the reverse limit switch 12BL . As a result, the extinguishing terminal of the return current gate via contacts 72 i? WR 2 of the rewind relay connected to earth. The return current gate extinguishes, and the contacts 3 of the relay 12BR close again, whereby the clearing terminal of the rewinding current gate 12RWG is connected to earth and this current gate is extinguished.

When the main interlock relay 72 MIR is excited, its contacts 72 MIR 1 (FIG. 73) close and thus form a circuit for the central drive motor 73 CDM. The circuit for the drive in the forward direction extends from the live side of an AC line via contacts 72 MIR 1, contacts 1 of relay 13 RCR, through motor 13 CDM and via contacts 2 of relay 13RCR to the neutral side ACN of the line. At the same time, a circuit is formed via the relay 13 RMF . If the return relay 72 BR is energized, its contacts close

72 Bi? 4 (Fig. 73) the circuit of the relay 73 RCR, whose contacts interrupt the flow circuit and the circuit of the relay 13 RMF. Instead, a return circuit for the motor is formed via contacts 3 and 4 of the energized relay 13 RCR .

The middle belt feed wheel is independent of the setting of the drive direction of the motor

73 d is only driven when the clutch solenoid 73 / is excited and the brake solenoid 73 g is deactivated.

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^{1 is} excited. The solenoids 73 g and 73 / are connected to the “reset” or “adjusting circuits” of a flip-flop drive circuit 73 h , while at the other end they are connected to a positive voltage source when the contacts a of the relay 73 RCB are closed. After ignition of the main interposer gate 72 MIG , the relay 73 RCB is excited via the point 72 D, whereby its contacts close and the positive potential

kers73 / is connected to the flip-flop 73 k , the amplifier supplies the inverter 73 / with a potential. The loop and coil motor control 73 α is supplied with a signal of one or the other polarity 5, which is generated by the central drive. If the tape recorder is in the forward position, this signal is fed to the controller 73 α via the reversing element 73 / and the rear contacts 6 of the relay 72 BR , whereby the reel motors of the forward

turn on the solenoids 73 / and 73 g, so that current flows to the flip-flop circuit 73 h . Will be in operation. If the device is in the return position, a door switch 73ASW is closed, whereby the signal from the middle drive is formed directly by the circuit for the relay 73 DSR and the output of the amplifier 73 / via the front relay 73 i? CD is prepared, so that at the closing contacts 7 of the energized relay 12BR to the control of the contacts 3 of the rewinding relay i? WR the re-15 tion 73 α switched on, whereby the coil motor lais 73 RCD is excited. In this way, a control current is fed to the now in accordance with the reverse flip-flop circuit 73 h , the tape device is driven, rend the loop and reel motor control As soon as the control potential is switched off,

Signals of the middle drive are fed, the voltage of the reversing element 73 / returns to norwhen the tape device is to perform a read or write 20 times and provides a control signal for the reverse operation or a rewinding process. Control input of the flip-flop 73 h ready. This is intended to be rewound, so ignites the stream gate this flip-flop is reset, the couplings 72 RWG after the return stream gate is lung ignited solenoid deenergized and the Bremshat. Contacts 72 RWR 3 close, the solenoid relay energized again. At the same time the 73 RCD is energized, and its contacts α no longer provide signals to the controller 73 α from the middle connection between the required negative drive, so that the coil motors switch off. Potential and the input of the amplifier 73 / forth. If a tape device is assigned to it by the

If a write operation in the forward direction is to be selected, the selection signal 61 SXT will split its moves, the write current gate 72 WG will ignite and the magnetic tape synchronizing device will be informed of this. Flow gate 72FG. After ignition of the write 30 Normally, a current gate is applied to the selection line 72 c at the input 72 W of the AND switch voltage, which is a control potential opposite the anode of a diode 73 £. The corresponding 72Fl is small enough to make it conductive. The time is a selection signal from the tape synchronizer pushes the potential between Ka signal 59 WCDG to the individual AND circuits method and anode of this diode down so far that 73 & all tape devices output; the diode is then blocked. If one assumes that the contacts 3, however, only the AND circuit is open, at the input of which the main interposer relay 72 MIR is closed, the signal 72 W is applied at the same time. In the- are, one or both diodes 72 V2 and 72 F3 conducts. In this context it may be pointed out, If the return current gate is still ignited from an earlier issue during the magnetic tape storage cycle, the return relays are only one tape device of a group open in the 40 contacts 72BR5 and the forward relay read or write position is located. Is there a contact 72 Fi? 2 closed. The diode 72 F 2 conducts tape recorder in the reading position, so its current ignites therefore; characterized the gate 72 RG (read stream gate) and also either all tape drives a group appears on line 72 d, is common to a, the return-current gate 72 BG or the disengagement signal preprocessing run 72 l / Z //? the return intermediate flow gate 72FG. After ignition of the power gate 45 blocking. If, however, before the selection 72RG is generated, the lead current gate is triggered at the input 72 R of the AND circuit signal and the 73 m is a control potential. When the synchronizing flyback current gate is extinguished, the reversing device is then switched to the state of contacts 72 BR 5 and 72FR 2 during the read operation; a suitable time the signal 59 RCDG on in this case, current flows from the diode 72 F1 to the AND circuits 73 m of all tape devices 50 diode 72 F 3, and it appears on the line 72 e, switched on; In this case, however, only the AND switch, which is common to all tape devices in a group, is opened, at whose input 72 R the one decoupling signal 72 UFIR of the return intermediate control potential is also applied. After opening the AND lock. During the subsequent on-Schaltung73m and 73 k of a tape recorder is supplied to the switching period in the selection interval can then entEingang of amplifier 73 / via the OR formwork 55, neither the write stream gate 72 WG, the sense current Tung 73 η the required control potential supplied; tor 72 RG or the Umspul-Stromtor72 /? WG is to be noted here that it is assumed that the Konigns are. If the power gate 72 WG has ignited, clocks α of the door switch relay 73 DSR have dropped at point 72 W in the anode circuit so far that one or both of the output signal of the amplifier 73 / is at 60 diodes 72 F 2 and 72 F 3 current flows to the diode 72 F 6, the setting input of the drive flip-flop 73 h , with either one or the other of the coupled, whereby this is switched into the setting state with both signals 72 UFIR and 72 UBIR or both and thereby the clutch solenoid will end. If the reading current gate is ignited, 73 / is excited and the brake magnet coil 73 g is de-excited. If the voltage at point 72 R in the anode circuit falls, the middle belt feed wheel 73 d is located so that current from one or both diodes is engaged with the clutch and can go from 72 F 2 and 72 F 3 to diode 72 F 5 flows and thus the middle drive motor 73 CDM is driven either the decoupling signal of the advance. While the output signal of the amplifier interlocking or the decoupling signal of the

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Intermediate return block or both signals at the same time be terminated.

Will the Umspul-Stromtor 72 i? FFG ignited during the switch-on period in the selection interval, the contacts 2 of the rewind relay 72 RWR open and thus switch off the anode potential at the diodes 72 V 2 and 72 V 3, whereby the two decoupling signals 72 UFIR and 72 UBIR are terminated. As is known, the return flow gate 72BG goes out at the end of the rewinding process, which also extinguishes the rewinding current gate. Since the flow gate is also switched off, all relay contacts 72 BR4, 72FR2 and 72 RWR2 are closed at the end of the rewinding process. When the next tape recorder is activated, both signals 72 UFIR and 72 UBIR are therefore coupled to the tape synchronization device and thus indicate that the device is in the first block position.

If the main intermediate barrier current gate 72 MIG of this device is in operation when a tape device is activated, a decoupling signal 72 UMIR is generated. The selection signal 61 SXT raises the anode potential of the diode 72 V 4 to such an extent that the diode conducts and thus the uncoupling signal 72 UMIR is sent to the belt synchronization device via the closed contacts 4 of the main interlock relay 72M //? turns on.

If the middle drive motor 73 CDM is set to advance, the relay 73 RMF is energized and its front contacts 1 and 3 (Fig. 72) close. If the write current gate is to be ignited, the contacts α of the write relay 72 WR close and transmit a signal "write in forward direction" 72 UWF to the synchronization device via the front contacts 1 of the relay 73 RMF. If the middle drive motor is set to reverse, the relay TiRMF is in the de-energized state, and its rear contacts 2 close, so that the contacts α of the read relay 72RR are also closed and a signal 72 URB (read in reverse direction) to the Transfer synchronizer.

Briefly summarized, it can be stated that the magnetic tape devices are controlled by control signals of the magnetic tape synchronizing device and that each device, after its selection, informs the synchronizing device by appropriate signals of the state in which it is. The control signals include the selection signals 61 SXT, which are individually connected to the respective devices, as well as the activation signals 60 BP to 60WP and the write and read deactivation signals 59WC and 59 RC, which are coupled to all devices, but only to that device take effect that has been selected. The control signals also include the central drive signals 59 RCDG and 59 WCDG, which are also coupled to all tape devices, but again only take effect on the device whose read or write current gate is in operation. If a device is activated, it transmits the uncoupling signal 72 UMIR to the synchronizing device when its main interlocking current gate is in operation; and when the main intermediate lock-stream gate is in operation and the rewinder-stream gate not, it generates the disengagement signal 72 UFIR when the return-current gate is turned on, and the signal 72 UBIR when the flow-stream gate is in operation. The last two signals mentioned are also generated when neither of the two power gates is in operation, which indicates that the device is in the first block position. After the device has been selected and has responded accordingly to the switch-on signals 60RWP, 60RP and 60 WP , it switches off the forward or reverse uncoupling signal or both signals. If the reading current gate is selected or ignited, either a signal 72 URF (reading in the forward direction) or a signal 72 URB (reading in the reverse direction) is transmitted to the synchronizing device, depending on whether the middle drive motor is in the forward direction or in the opposite direction running around. If the write current gate 72 WG is selected, a signal 72UWF (write in the forward direction) is transmitted to the synchronizing device, provided that the middle drive motor is running in the forward direction.

The operation of the tape devices will be discussed in conjunction with the following description of the tape synchronizer described.

Belt synchronizer program

F i g. 74-86 are flow charts showing the general program steps required to perform the functions provided by the tape synchronizer described above. In these drawings, the symbol CL surrounded by a circle represents the control loop or the series of commands described above. The other symbols surrounded by a circle, such as Sn, Cn, Fn and Dn, represent changeable connection points in the program Symbols T, NI and E surrounded by a circle represent fixed connection points in the program. The various functions of the individual program steps are listed in the blocks.

At the top of each block is the number of the command from the program of the central processing system, which initiates the function specified in the block.

The computing system described in the present invention includes only one belt synchronizer. However, several of these synchronizers can be used, including certain Parts of the program would have to be changed somewhat.

As already mentioned elsewhere, the functions which are initiated by the Computing system through the input and output devices, such as. B. tape devices, run as Pseudo or summary commands shown. These commands are the central processing facility supplied and interpreted by it. Under the influence of control signals sent to the input and output devices are turned on, these commands are then applied in accordance with the program the central processing facility and in accordance with those listed below Steps performed by the relevant synchronizer.

Like F i g. 74 shows, the tape program begins first with the next one for the tape synchronizer provided summary command taken from the memory location provided for it will. This summary order, which one

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the instructions for the functions to be performed are then stored in the register P 1 of the central processing system. This summary command is also temporarily stored in a memory location in the main memory in order to be available for future tasks.

Like F i g. 74 shows, it must then be determined in the next step whether the tape synchronizer in question is busy or not. This is done by checking a specific memory location, which contains information which indicates whether the synchronization device in question is busy or not.

If it is determined that the synchronizer is busy, the program follows the horizontal path and returns to the control loop. In this case, the series of commands 99 can be used to check again at which point the program provided for this synchronization device can be entered again. If, on the other hand, it was found that the synchronizing device is free, the next step in the program is to execute an instruction 60 which checks the flip-flop 60 α provided for the control circuit of the synchronizing device. This can be seen from FIG. 62, in which the function table signal FT 860 is shown, which is generated by the command 60 and coupled to one of the inputs of the AND circuit 62 a. If the tested multivibrator is in the reset state and thus indicates that the control circuit of the synchronizing device is not free, then an error would be indicated because an earlier program step determined that the synchronizing device was not occupied. In this case, an error would be displayed. If, on the other hand, the multivibrator provided for the control circuit of the synchronizing device is in the setting state, the function table signal FT 860 does not cause a jump; an instruction 63 is then executed as the next program step (FIG. 74). This command 63 has the task of selecting the tape device which is designated by the summary command. This selection is made by the function table signal FT 863, which opens the AND circuit 59 a and thus energizes the corresponding selection lines 61 SZT1 to 61SXT10 of the tape recorder. If the selection process is completed, the selection flip-flop is set 62 e. As already mentioned elsewhere, this setting takes place 200 microseconds after command 63 has been initiated.

Like F i g. 74 shows, in the next program step the changeable connection Sn is set to Sl; then the control loop is started.

As can be seen from the flow chart in FIG. 74 as can be seen, have the program steps shown there the task of determining the password of the tape device and checking that the control circuits of the tape device in question are free; If so, the correct tape device is selected.

F i g. 75 shows how the program is started from the control loop. To the Control loop, which consists of a series of commands 99, also includes command 99-2, which is shown in FIG. 75 is shown as one of the horizontal paths. This command checks for one of the ten-word flip-flops of the belt synchronizing devices, if there are several of these synchronizing devices are provided, is set. The other commands in the control loop are commands 99-6 and 99-3. The command 99-6 checks whether one of the selection flip-flops is set, while the command 99-3 determines whether the clock trigger circuit provided for reading is set. Set the commands 99

ίο notes that the flip-flops in question are not set are, the program goes over to further commands 99 of the control loop, as can be seen from FIG is.

If instruction 99-2 has determined that a ten-word toggle switch is set, the program follows the horizontal line shown in FIG Path; in this case an instruction 69 would be started to trigger that ten word toggle (e.g. 63 a) that is assigned to the synchronization device used. Was If this ten-word toggle switch is in the reset state, an error message is issued because the command 99-2 has already determined that one of the flip-flops was set. On the other hand, is that If the ten-word toggle switch is set, the program goes to the fixed connection or transfer point T over.

If the command 99-3 determines that the clock trigger circuit provided for reading is set, the program goes over to the fixed connection point JV. If the command 99-6 determines that one of the selection flip-flops is set, if several such flip-flops are provided, the command 64 is given (horizontal course of the flowchart), which checks that selection flip-flop 62 e that of the relevant synchronization device assigned. If this test determines that this flip-flop has been set, the program goes over to the changeable connection Sn . If, on the other hand, the selection toggle has been reset, an error display is given to indicate that an error has occurred as a result of the previously carried out test 99-6.

The program can be restarted using commands 99-2, 99-3 and 99-6 of the control loop. Like F i g. 75 shows, this is achieved either when the selection of a tape device is completed while ten words are written out of the tape, or when the clock toggle circuit provided for reading is set. Assuming that the program has passed through the various steps shown in Fig. 74 in that the alterable terminal Sn was adjusted to Sl and the control loop has started to operate, and one proceeds from the assumption that the control loop after performing the examination 99 -9 determines that the tape device in question has been selected on the basis of command 63, command 94 is started and the program changes to S1 on the basis of the setting of the changeable connection Sn.

F i g. 76 shows that when the program is entered at connection point S1, instruction 72 is started, which generates the function table signal FT 872. This function table signal FT 872 tests the AND circuit 62 / to determine whether the flip-flop 62 /, which the availability of the

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Tape device indicates whether it is reset or not. the device revolve in the required direction If the command 72 determines that the relevant tape can. After the delay of 0.8 seconds, the device is not free, ie the toggle switch, which then indicates the availability of the changeable connection points Fn of the tape recorder, is set back and Sn is set to F1 or 53, whereupon the Pro is set the command 76 is entered into the control loop.
to check whether the tape device is between- Command 66 determined that the is locked. By the command 76, the radio direction of rotation is advertising not changed the tape recorder tion table signal FT generated 876, which has the to and that the terminal point of Sn provided multivibrator intermediate lock-on 52 once reset output of and the program on the control loop 62 d checks and thereby determines whether the power supply was switched to io, the re-entry into the tape device in question would be interrupted or the program from the control loop in the in is not. If during this test it is found that the F i g. 75 takes place, ie is interrupted by the power supply , the operator receives the command 99-9 when the selection person receives a corresponding message and that the course has been terminated. Via command 64, the program is transferred to the control loop. If the selection flip-flop is then checked, but if it is found that the power supply has not broken if this flip-flop is set, then the program follows that in FIG. 76 the program would go to connection point 52. illustrated horizontal course and goes directly This connection point is illustrated in Fig. 80th to the control loop. As this figure shows, in the first step of the

If the command 72 has determined that the program in question is executing a command 67 which tape device is available , this causes the tape device to be switched on sooner; That is, this command program that the password of the tape device in sets the tape in motion and at the same time checks another memory location temporarily off the AND circuit 62 o to determine whether this is stored. At the same time the program continues with the tape rewound. Command 67 generates the function table signal FT 867 from the analysis of the currently executed command, by means of which it is possible to determine whether it is a read or write command for switching on the tape recorder or a rewind command Toggle switch 59 e in the setting state delt. If one assumes that the analysis of the sum is switched over and the WCDG signal thus indicates a write command at the ric command, the tape recorder is coupled. The fixed transfer point 1 is set by this signal, and the program presses the clutch against the drive roller and the program moves with the in Fi g. 77 thus sets the belt in motion.
th away. As FIG. 77 shows, if it is assumed that the tape was rewound, control data for the tape device and an initial run, the program follows the address shown in FIG. 80 in the register RP-I of the central processing upper horizontal run . In this case, the management system must be put together. These data result in 35 for the clock program 1.8 seconds to the eye from the password of the tape device, which is added to the glancing time beforehand. By this pro- of another command was saved. After this information has been provided in the register RP-I , the time required for the clock program to be stored for the central processing system will be delayed by 1.8 seconds. Im is, the starting address is transferred by an instruction 74 40 next step the changeable connection would be relocated to the address register of the distributor. point Fn can be set to FI and then the command 74 is followed by a command 66, which ßend the transfer to the control loop. has the task of the control data is rewinds in the If it is determined, however, for the loading that the belt did not drive vice of the tape recorder provided registers 60 ft, then the command is started 68, einzuspeichern which and to check whether the Umlaufrich- 45 initiates the write process and at the same time the tion of the tape device must be switched. Ten-word toggle switch sets.
If the direction does not need to be switched, the function table is generated by command 68, the program follows the horizontal course, signal FT 868 is generated, which is sent to device 64 e for the via the AND switch and the changeable connection point 5 η Initiation of reading or 52 set. Must, however, the direction of the belt turn 50 write operation provided flip-flop in circulation are switched, as is indicated by the sets and at the same time on the basis of the AND of the program contained in the password of the tape recorder circuit 64 e signal generated 6453.Κ5Γ the tene direction indicator changed. It should be noted that the ten-word group toggle 63 / sets the direction in which the 55 is set to the ten-word toggle 63 ή direction indicator contained in the password of the tape recorder. The ten word toggle is the tape recorder that was last used ; the directional flip-flop which is indicated by the command does not indicate the direction in which the 69 generated function table signal FT 869 checked tape device is now to be used. This means that the direction indicator must be in the characteristic at the input of the AND circuit 63 / an. After the write process has been initiated and the word changed, if a toggle 60 has been set to the ten-word toggle switch, the circulation direction is required . is, the changeable connection point Cn is on

In the next step , Cl must be set by the, followed by the transition

Another point to be described clock program for the control loop takes place.

0.8 seconds can be added to the instantaneous time. As can be seen from the description of the FIG. 85

the. This delay of 0.8 seconds is necessary and can result in the flow charts shown in FIG

that is, to give the tape recorder enough time for the control loop over the connection point

Change of direction of the belt loops as well as for the Fl after the required delay of

Changeover of the drive motor so that the program re-entered for 1.8 seconds

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are when the command 67 has determined that the signal FT 870 generated, which the flip-flop band is rewound and when the connection point F η 64 c / switches to the setting state, whereby the and Fl has been set. If, on the other hand, the pro-tape device writes another ten words,
gram the in F i g. 80 shown lower horizon- As F i g. 82 shows, lead from connection point 3 valley path taken and connection point Cn 5 is all paths to the control loop. The other im has been set to C1, so the path entered by the command 99-2 (Fig. 75) could be entered into the pro-upper horizontal part of the connection C2 ready can be entered by the control loop via the. This would mean that one of the ten connection points T would be entered if the word flip-flop was set. Subse- circuit point Cn on Cl is set and when in ßend a command would be started 69, the io present program, the first instruction is an instruction the ten-word flip-flop in question checks whether 73, which checks whether one of them between the blocks is in the setting state; if so, then there would be clearance, ie, whether the blocks would transition the program to the T terminal. space toggle switch is set. Located

Like F i g. 79 shows, the connection point T that this flip-flop is in its set state, so

Program for the changeable connection Cn. In the 15 is the one in the password of the tape device

In the present example, it can be assumed that the block number is incremented to indicate that a

that this connection has been written by a further block in FIG. 80; then-

step shown has been set to Cl. ßend the connection point Dl is set. Be-

In this case, on the other hand, the program would use the inter-block toggle switch.

81 continue connection point Cl shown. If the device is not in its setting state, the pro-

In the first step of the flow chart shown in FIG

diagram will enter the tape device's password history to determine if the read

analyzed and determined whether the format must be continued at a fixed rate; this is done by

Requires block length. If no fixed block length is set, whether all blocks have already been

is required, the program goes to which has been assigned for.

changeable block provided subroutine via; Like F i g. 83 shows, the program goes from the

this subroutine is for the sake of simplicity changeable connection Dl to an instruction 61 about,

not described here. The result of which determines whether the read and write control

Analysis of the password of the tape device that a circuits are free. (The changeable connection

if a fixed block format is desired, the one for 30 D 1 can e.g. B. have been previously set if

the conversion of the information provided by the command 73 was determined that the

Control digit set, whereby the conversion inter-inter-block toggle circuit is set.)

device 68 ί one consisting of ten words The command 61 checks the flip-flop 64 a in order to

Group converts and thus the numerical information see whether this toggle switch is reset. Are

mation in the right form. 35 those intended for reading and writing

In the next step, the start address for control circuits is free, so an error message is displayed together with the direction indicator of the tape recorder. If the control circuits are not free, so temporarily stored in a memory location, the program causes the current in order to be available for future tasks to address the number of each arising in a block. 40 held words is added to the address

In the next program step, that of the end of the block is then obtained. Then the ProAdresse at the end of a block is temporarily transferred to the control loop for test purposes,
going stored, this address being the memory As F i g. 84 shows, after the entry into the cherstelle is designated, from which the last in the block connection point D 2 first determines whether the information to be written in has been taken. The address in the address register is the same. Next, the final address for test purposes is the final address, which is previously temporarily stored in a memory location for execution. this comparison is temporarily saved. After these accounting commands, the arrival. If (the connection point D1 z. B., by the circuit point Cn on C2 and the terminal point Dn in Fig. Program steps shown 82 is set is set to Dl, and the program have been for turning 50, when all blocks are completed.) The circuit point 3 passes. This connection point 3 addresses the same, then the password leads to the program of the tape recorder shown in FIG. 82 in the one for the tape recorder. The memory block seen in the first step of this flowchart is restored, from which ten words are originally taken for the current address. The program adds up. The next step is then done and goes to the control loop, checks whether all blocks have been written since all the blocks to be written have been written. If so, the connection point will have been D1 .

is set and the program «returns to the control F i g. 85 shows how the delays

loop back. If, on the other hand, not all blocks can be provided in the program yet. Of the

is set, the program determines whether the part of the program shown here shows the steps

the current block is already enrolled; if so, by which the delays are provided

the program can create a space between. Like F i g. 85 shows the control loop enters

see the blocks inserted, whereupon this part of the program is shown by means of a test 99-3,

the transfer to the control loop takes place. Is there if the clock trigger circuit and the connection N

against the current block are not yet fully set. If the clock toggle switch is

is written, a command 70 is started, whereupon the connection N directs the program to

be inscribed by another ten words. Command 95, which is generated to set the clock toggle

This command 70 is used to check the function table circuit again. Is this tilting

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312

circuit is set, which is normally the case, the program causes that 8.33 milliseconds are added to the counter. The counter is accommodated in a memory location provided for this purpose and is incremented according to the real time. In the next program it must be determined whether the time stored in the memory is equal to 100 milliseconds. If so, 100 milliseconds are added to the instantaneous time that is in another memory location. If not, the program goes over to the control loop in order to then check again the flip-flop circuit provided for the real time. Assuming that, at the instantaneous time 100 milliseconds were added, then in the next program step stored in a memory location instantaneous time with the ver in a stored at the memory location storage time adjusted in order to check whether the instantaneous time is greater than the storage time. If so, the program goes to connection point E ; if not, it returns to the control loop in order to then check again the flip-flop provided for the real time. Like F i g. 86 shows, for the connection point E, the program to the changeable connection point Fn, whereby the program can enter that part of the program which follows the program part in which the delay took place.

The above description is a general description of the program required to operate the tape synchronizer in the event of a write operation. A similar program is provided for reading information from the tape ; while a simplified sequence of commands can be used for the rewinding process. These other programs and the individual steps required to control a tape recorder in conjunction with the synchronization device described are known to the technician and are therefore not described in detail.

Computer system

If necessary, a computer of known type can be used as the computer system in the present system, which computer can be used in connection with a memory described in the present invention with any access . Of course, it must be a parallel computer that is able to process words that consist of 60 parallel information units.

Both computing systems are similar to one another, so that for the sake of simplicity only one system is described in somewhat more detail here. The computer system includes a display or D flip-flop circuit that is set by the computer system and checked by the central processing system. These operations are described in more detail below.

General description of the computer system

The computer system described here works according to the so-called overlap principle. In other words, the computer is capable of executing a number of different instructions during one and the same short period. In a nutshell, the computer system performs the following operations in a short period:

1. Activation of the memory for the purpose of extracting a first command;

2. Storage of a second command taken during the previous short period in the command register IR-I and control of the memory due to the removal of the operand required for this second command or control of the memory for the purpose of storing information contained in the registers of the computer system;

3. Execution of a third instruction, the operands of which have already been carried out at an earlier point in time from Memory has been transferred to the computer system, and

4. Transferring the previously calculated result of a fourth command to an addressable one Computer register.

Each of the two computer systems of the machine is able to control the memory twice in a short period, namely once to remove an instruction and the second time to remove an operand. As has already been described in connection with FIG. 1, each of the two computing systems controls the memory for the purpose of extracting a command during a time segment reserved for this purpose within a short period; in addition, they control the memory for the purpose of removing an operand in a different time segment, which is also reserved for this purpose. The activation of the memory by the first computer system via the address decryption device 10-74 for the purpose of extracting commands and operands does not take place in the time segments in which the second computer system fulfills the same functions. As has already been mentioned elsewhere, the first computer system controls the memory during the cycle times i ₀ and t ₅ for the purpose of extracting commands or operands. The memory receives these address signals at the cycle times t _x and i ₆ . On the basis of such a control, the first computer system can send a memory-free signal MNB at the cycle times t. ₂ and I ₁ obtained. The control of the memory by the second computer system via the address decryption device 10-64 for the purpose of removing instructions and operands, however, takes place during the cycle times i ₄ or t _v . The memory receives these address signals at the cycle times t ₅ or t ₂ , while the second Computing system can receive a memory-free signal MNB due to the aforementioned activation at the cycle times i ₆ and t _z.

For the sake of simplicity, the clock pulses that are sent to the FIG. 95, 96 and 97 shown computer system are generated by the clock * shown in FIG.

Referring now to FIGS. 95A, 95B and 95C, the control circuits for describes a computing system that can be used in the present invention. Because the operating cycle as well as the operation of a computer system largely depends on the arrangement of the Control circuits or the control unit is determined, relates to the following description of the Computer system primarily whose control arrangement

313 314

tion. For the sake of simplicity, the control unit used in conjunction with a parallel line eleven of the twelve is used in contrast to a command word which assumes that what is shown in FIGS. 95A, 95B and 95C denotes that is to be executed Digits represent numbers, while the computer and a memory with any twelfth digit represent a sign. Represents the handle being used. In addition, it is assumed that 5 machine words, on the other hand, represent a command, so a machine word consists of twelve digits (60 information - the digits of this command word to form groups together). summed up, with each group having a certain _T. , Represents part of a control information. A command word used in the symbols calculator used in the drawings has the following

In the in connection with the description of the io format:

Computer drawings used are certain 12 11 10 987654321

Symbols used. For example, a coincidence-. «» R »« * »* ·«. * »*» * ·

Circuit through a crescent moon with a point ^{T 1 l} AABBMMMMM

shown in the middle. In every coincidence or in this format, the two / digits represent the

AND circuit also contains a number, 15 represents the command to be carried out. Thus he

which corresponds to the number of AND circuits that results in this word structure as a whole

100 different commands are possible through this single AND circuit,

the. An OR circuit is also characterized by The two A digits denote the address of a

depicted a crescent; in this case there is an addressable register in which one of the

however, in the middle of this crescent there is a plus operand to be processed

sign. Also the OR circuits are included; in addition, these two designate digits

Numbers which correspond to the number of OR circuits, the address of an accumulator in which the result

that are stored by a single OR switch of an arithmetic operation

tion can be represented. The terms AND circuit can.

and OR circuit are described in 25 The five M digits denote the address of a

used as they are normally located in the electrical operands in main memory, the

nik can be used. So represents an AND circuit to be working, or they designate one

z. B. represent a circuit that has a single output address to which the controller is transferred

gang, on the other hand, has two or more inputs, whereby should. The two 5 digits represent the address of one

This circuit is designed so that only 30 further addressable registers are in which a

an output signal is generated if a value is stored at the same time that is used to change the M-digit

signals are present at all of its inputs. Serving too remote a command. The twelfth digit, i.e. H. the

Note, however, in this context that the Γ-digit can be used for other purposes or

an AND circuit cannot be used at all by coupling one,

or several so-called blocking signals blocked 35 A command with the format 70253502500 would

can be. If this is the case, then these are interpreted by the computer system as follows

Blocking signals at the input of the AND circuit are:
Marked dots or small circles. One

OR circuit is a circuit that creates an 1 · * ψ * & an addition (where assumed

zig output and has two or more inputs, ₄ o ^will ' ^{that 70 represents an add} command);

this circuit is designed so that a 2nd one of the operands is in the addressing

Output signal is generated when at any bar register 25;

a signal is present at the inputs. In the drawings 3. the other operand is in the memory, as well as in the description its address is also determined by the fact that for the mentioned decoding and encoding device 45 value 02500 a part of the content of the addressing is written. Both facilities are added to the techable register 35; nik known and consist among other things of OR 4. Save the result of this arithmetic operation circuits or AND circuits. The addressable register 25 in this \ _n. The term "encryption device" used in the description refers to a circuit which consists of a 50 The number of input and output lines required in the format just described are available to the control unit (FIG Memory via 60 signal lines HSB-R fed in parallel to the input lines for generating a signal, with five signal lines leading to one or more output lines. Use the transmission of a digit of the command word. The term "decryption device" refers to it. The first five lines are transferred to a circuit that also consists of several the first digit (an M digit), the last five Lei input and output lines, with lines such. B. the lines 55-60, however, transmit the simultaneous presence of signals twelfth digit. All of the input lines on it in the drawings for generating a set line or main lines have the same meaning as the signals on one or more output lines. One in the drawing leads as a single gang line. The main line shown in the line can, however, in principle, an information word used by the computer system consists of a number of signal lines and consists of twelve decimal points. Is also a main digit in the drawings. Each of these digits can represent five binary information lines which, when connected to the input of a coincidence unit, represent the value of the connected or AND circuit, so significant digits; The fifth information indicates that the individual to this main line unit is used for testing purposes. Contains the associated signal lines each with their own word of information that is to be processed (in the AND circuit (not shown in the figures)

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316

are connected. The representation of 60 signal lines, which are connected with 60 AND circuits, would only make the drawings confusing. As shown in the lower part of FIG. 95A, a command word is transmitted to the control unit via a main read line HSB-R consisting of 60 lines. This main line thus comprises 60 lines, one line each being provided for an information unit of a digit. In Fig. 95A is

are connected, both are controlled by the function table signal FT 312 generated by the function control unit 95-148. These AND circuits have the task of transporting the / - and / 4 digits from the command register IR-I to the parts of the second command register IR-2 labeled 95-107 and 95-107 α. The / and /! Digits are simultaneously transferred from the command register 95-101 to the command register 95-107 and 95-107 α, if

this main line with the reference number 1-60 ver io to the AND circuits 95-102

see, indicating that the main line consists of a number of lines. These lines HSB-R are each connected to a coincidence circuit 95-100 . These AND shades 95-100

and 95-103

turned on

the function table signal FT 312
will.

As will be described in more detail below, those in command register 95-101 are

become 15 M digits during a different time period by a function table signal FT 320

prepared, which is generated by the function control unit 95-148. This function control unit 95-148 is shown in the form of a block in FIG. 95C and will be discussed later in connection with

fed to a further register part 95-108 of the second instruction register. These M-digits of the register 95-101 are transferred to a five-digit F i g via the AND circuits 95-136 shown in FIG. 95B. 96 described in more detail. The AND circuits 20 connected parallel adders. (The AND circuits 95-100 are connected to a twelve-digit register. 95-136 are linked by the function table signal that is prepared with "first command register IR-1" FT 400.) This five-digit parallel is drawn and has the reference number 95-101. The adder is shown in FIG. 95B as B adder 95-139, instruction register 95-101 contains 60 storage locations, and. The B adder 95-139 is in each case one memory location for an information output with the AND unit of the command word shown in FIG. 95A. Since in the present circuit 95-105 are connected, which the most significant digit T but not function table signal FT 311 are prepared by the invention. is used, this number is also in the register. The inputs of these AND circuits 95-105 are not included. 25 of these are connected to the five-digit register 95-108 in the command register 95-101. 30 From the arrangement it follows that the registration units of the five M digits, while three 95-107, 95-107 α and 95-108 the / digits and A-Zii- groups of ten each Store the B-, A- and fern or the modified M-digits / digits of the command word. The ten memory locations that were previously located in the instruction register 95-101, which contain the information units for the. The B adder 95-139 will also receive the two Λ digits, are connected to the one 35 part of the content of a selected addressable of ten AND circuits 95-102 or registers 95-121 via the AND circuits 95 -133 ten AND circuits 95-103 connected, their output, these AND circuits are prepared by the passage with the storage registers 95-107 and 95-107 α function table signal FT 410. The block, which is a part of the second instruction 95-121, can form up to 100 addressable registers, REregisters IR-2 . The command register 95-101 has a capacity of 40, these registers each storing one of twelve, the first of a number of registers which are used for storing digits.
The AND circuit 95-133, as well as those missing with it, are used to secure various parts of various loads. So z. B. the connected signal lines represent 95 signal lines error registers 95-101 stored command or a part as well as 95 AND circuits, so that by these in a second command register, ₄₅ arrangement of the AND circuits 95-133 the first which consists of the register parts 95-107, 95-107 α and five digits (ie the five least significant digits), 95-108 . After this relocation, a new command is located in a specific addressable register in the command register 95-101, with the content of the stored in the register 95-101. In addition, another sensitive M-digits will be added. The register (not shown) of the arithmetic unit 50 sum of this arithmetic operation is stored in the register 95-131 (Fig. 95C) information; this 95-108 saved. In this way, the information comes from register 95-107 and the entire instruction in register 101 is used to control arithmetic unit 95-131. In a changed form, a second command register is added to the command register of the arithmetic unit, which stores the command from the register elements 95-107, 95-107 α, so other commands can exist in 55 and 95-108. As will be described below, the command register 95-101 (IR-I) as well as into the off is taken from the memory and stored in a new command in the register parts 95-107, 95-107 α and 95-108 after the end of this relocation Command register can be saved. Except- the command register 95-101 is stored. At this point there is a further location with selection register 59-113, it is not described in more detail why the register designated (FIG. 95B) is provided, which is incorrectly modified in the present manner. Likewise, for the purpose of storing a command part Ver, it should only be ascertained that it is used through this. The part of the command which is stored in the register gang makes it easier to program the computer 95-113 represents the address, ie is tert. It should be noted that the five least significant digits in the instruction one of the 100 addressable registers 95-121 in the register / RI denote the result of the 65 of the instruction before it was changed with M '

Arithmetic operation can be saved.

The AND circuits 95-102 and 95-103 that start with
the inputs of registers 95-107 or 95-107 α

will. As soon as it is in the memory section 95-108 of the
Command register IR-2 are located, they are denoted by M.

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318

The relevant accumulator used in this last-described operation is selected by the register selection decryption device 95-120 (Fig. 95C). This register selection decryption device 95-120 comprises a decryption matrix which, upon receipt of an input signal, selects one of 100 addressable registers.

The input of the register selection decryption device 95-120 is connected to the selection register 95-118 which stores two digits. The two digits that are stored in this selection register 95-118 can be sent to this register via the AND circuits 95-114 to 95-117 and 95-180 to 95-181 .

As can be seen from Fig. 95B, each of AND circuits 95-114 to 95-117 and 95-180 to 95-181 represent ten AND circuits so that each of these AND circuits can transfer two digits to be entered into the Register 95-118 should be saved. The AND circuits 95-117 are controlled by the function table signals FT 432 and FT 320 and receive selected information from the main read line HSB-R. These AND circuits are supplied with the B digits of a command, which are stored in the command register 95-101 of the control unit shown in FIG. 95A. While the AND circuits 95-100 receive the entire command word to be stored in the command register 95-101 , only the B-digits of this command word are fed to the AND circuits 95-117 at the same time. These B digits are then transported to the selection register 95-118 . Simultaneously with the storage of the command in the first command register 95-101 , one of the various addressable registers 95-121 is selected. The five least significant digits that are in this selected addressable register are - as previously mentioned - fed to the B adder 95-139 via the AND circuits 95-133 , so that five digits of the selected addressable register 95-121 and the five M 'digits of a command located in register 95-101 can be combined with one another and stored as M digits in register part 95-108 of the second command register.

As can be seen from the drawing, the output information of the command register 95-101 can also be fed to the selection register 95-118 via the AND circuits 95-116. Here, too, the AND circuit 95-116 represents a number of AND circuits which transmit ten information units, ie two digits. These two digits, which are transmitted by the AND circuits 95-116 , are the B digits of the command word which is located in the command register 95-101 . Under normal circumstances, the B digits of an instruction stored in the instruction register IR-I (95-101) are fed directly to the selection register 95-118 from the main line via the AND circuits 95-117. However, there may be cases where the overlapping operation must be temporarily prevented so that the B digits cannot be transmitted from the main line. In these cases, the B digits of the command are stored in the command register IR-I in order to be subsequently transported to the selection register 95-118 via the AND circuits 95-110. One such eventuality is the activation of an addressable register by the B-digits, if the previous instruction, through which this register was designated as result memory, has not yet ended. Until the command is completed, the data stored in the register identified by the B digits does not yet represent the latest information; the B amendment must therefore be delayed. Further examples of such a contingency arise in connection with the execution of a duplication instruction as well as other instructions which require a longer storage in the instruction register IR-2 (95-107) for their execution. In such cases, the command immediately following remains stored in command register IR-I (95-101) until the long command can be removed from command register i7? -2. The command only receives its B modification when it can be re-stored in the command register IR-2.

The selection register 95-118 can also be supplied with two digits via the AND circuits 95-114 and 95-115; these AND circuits are prepared by the function table signals FT 434 and FT 431 , respectively. The AND circuits 95-115 transmit the output signals of the B adder 95-139 (two digits) to the register 95-118, and the AND circuits 95-114 transmit the output signals of the selection register 95-113, which also holds two digits. Finally, the AND circuits 95-180 prepared by the function table signal FT 430 also transmit the Λ digits of the command register IR-2 (95-107 α) to the register 95-118, and the AND circuits 181, which are generated by the function table signal FT 433 can transport the two least significant M digits of the instruction register / R-2 (95-108) to register 95-118 . The. ^ Digits are transferred directly from the instruction register IR-2 (95-107 α) via the AND circuits 180 when jump instructions are carried out and when data are to be relocated between the main memory and the addressable registers. The use of AND circuits 180 in these cases is a result of timing considerations. The two least significant M digits from the memory section 95-108 of the instruction register IR-2 are fed to the selection register 95-118 if both operands are to be removed from the addressable registers on the basis of instructions. Such commands are characterized in that their M-digits appear in the form 999ZX and have no corresponding memory location. The digits 999 are recorded in the B adder; the signals generated during this detection ultimately lead to the generation of the function table signal FT 433, which opens the AND circuits 95-181. Of the six inputs to register 118 , only AND circuits 95-116 and 95-117 are open at the same time, while generally only one group of AND circuits 95-114 to 95-117 and 95-180 and 95-181 to any one Time transmits signals.

It can be seen from the drawing that the input of the selection register 95-113 is connected to the output of the B adder 95-139 via the AND circuit 95-112 . This AND circuit is prepared by the function table signal FT 421. As will be explained below,

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320

the selection register 95-113 holds the two ΛΙ digits of the command word stored in the register 95-107 α via the AND circuits 95-134, the B adder 95-139 and the AND circuits 95-112. The two A digits stored in this way in register 95-113 are used to determine the address into which the result of an instruction just executed by arithmetic unit 95-131 is stored. The Λ digits stored in the second instruction register 95-107 α are fed to the B adder via the AND circuits 95-134. These AND circuits 95-134 are controlled by the function table signal FT 403. The Λ digits in the register 95-107 α are fed to the B adder 95-139 via the AND circuits 95-134 at two different times in a normal operating cycle. Under normal circumstances, they are not changed when passing through the B adder 139 , since this adder in this case only serves as a transmission path. If the B adder 95-139 generates for the first time an output signal which corresponds to the Λ digits in the register 95-107 α, this output signal is fed to the selection register 95-118 via the AND circuits 95-115. The / 4-digits stored in this way in the register 95-118 are used to identify the address of one of the addressable registers 95-121 from which an operand to be processed by the arithmetic unit 95-131 is taken. If the B adder 95-139 generates an output signal for the second time which corresponds to the ^ digits in register 95-107 α, this output signal is fed to the selection register 95-113 via the AND circuits 95-112. As mentioned earlier, register 95-113 transports data to selection register 95-118; the data in register 95-113 ultimately determine which of the addressable registers 95-121 receives the result determined by the arithmetic logic unit.

The Af digits in the second instruction register 95-108 are fed to the B adder 95-139 via the AND circuits 95-135 ; these AND circuits are controlled by the function table signal FT 402. These M-digits finally reach the address decryption device 10-64 or the control counter CC 2 (95-106). If an instruction controls the memory after its B-conversion for the purpose of removing an operand and the memory is occupied at this point in time, this control process must be repeated until the operand can be removed from the memory. This repeated activation is carried out by the memory section 95-108 of the command register IR-2 via the AND circuits 95-135 and the B adder 95-139 . If there are jumps in the program, the M digits are stored in the control counter CC 2 from the command register IR-2 via the AND circuits 95-135 and the B adder 95-139.

As already stated, the output information from the B adder 95-139 is information consisting of five digits; these digits are sent to various parts of the control unit already described and also to the address decryption device 10-64 (FIG. 10) via the. AND circuits 95-140 and OR circuits 3-31 turned on; these AND circuits 95-140 are controlled by the function table signal FT 363. The output of the address decryption device 10-64 is connected to the selection circuit of the main memory, not shown in this drawing. The AND circuits 95-140 are controlled by the function table signal FT 363 and can be blocked by a jump signal generated by the function control unit. If the output information of the B adder 95-139 has been decrypted in the address decryption device 10-64 , a specific address in the main memory is selected and the content of this address is sent to the memory via the main read line HSB-R . The output information from the β-adder 95-139 is used in this context to select the commands contained in the memory so that they can be fed to the control unit via the AND circuits 95-100; In addition, the address of the operands in the memory is selected by the output information of the B adder, so that these operands can be fed to the arithmetic unit 95-131 via the AND circuits 95-146 for processing.

As can be seen from the drawing, the output of the control counter 95-104 is connected to the input of the B adder 95-139 via the AND circuits 97-137; these AND circuits 95-137 are controlled by the function table signal FT 401. In the control counter 95-104 the address is stored which indicates the memory location of the last command removed from the memory. The B adder 95-139 is used to modify the output of the control counter 95-104 ; this output signal is then fed to the selection circuits of the main memory via the AND circuits 95-140, the OR circuits 3-31 and the address decryption device 10-64 , so that a command word can be taken from the main memory and connected to the main read line.

The control counter 95-104 is connected at its input via the AND circuits 95-143 to the output of the B-adder 95-139, so that at selected times, ie when the output signal of the control counter to the B-adder 95-139 and from there is fed to the address decryption device, the output signal of the B adder 95-139 can be fed back simultaneously to the control counter 95-104 via the AND circuits 95-143; these AND circuits 95-143 are controlled by the function table signal FT 345. The function table signal FT-UA from the function control unit 95-148 can be coupled to the B adder 95-139; This signal inserts a carry into the least significant digit and adds a "1" to each value transmitted by the B adder. If the function table signal FT-UA is generated and the output signal of the control counter CCl (95-104) is passed through the B adder 95-139 via the AND circuits 95-137, the content returned to the control counter 95-104 is increased by one . This enlargement of the content in the control counter 95-104 by one enables new commands to be taken from successive storage locations in the main memory.

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The control counter CC 2 (95-106) can also receive its input signals from the β-adder 95-139. The input AND circuits 95-144 to the control counter CC 2 (95-106) are controlled by the function table signal FT 346. The output signal of this control counter CC 2 can also be fed to the address decryption device 10-64 via the AND circuits 95-151 and the OR circuits 3-31. The AND circuits 95-151 are controlled by the function table signal FT 364 in conjunction with a jump signal from the function control unit 95-148. The control counter CC 2 (95-106) is used during a jump instruction.

The two / digits (ten information units) in the command register 95-107, which determine the operation to be carried out, are transported to the command decryption device 95-109 and from there to the command control unit 95-148. The command decryption device 95-109 consists of two parts: the most significant command digit is decrypted in the first part and the least significant command digit is decrypted in the second part. The command decryption device 95-109 also controls the command encryption device 95-110 provided for the arithmetic logic unit, which in turn is connected to the input of the arithmetic control unit 95-130 via a number of AND circuits 95-132. These AND circuits 95-132 are controlled by the function table signal FT 300. The command decryption device 95-109 consists of a number of AND circuits, each of which has a plurality of inputs and an output. Like the other decrypters, the command decryptor 95-109 receives a number of inputs, but only excites a single output line. The ten information units of the two / digits are thus fed to the command decryption device 95-109, and this only generates an output signal on the basis of these input signals. The command decryption device 95-109 can have up to 100 output lines and is designed in such a way that, under the influence of the two / digits, it selects one of these 100 output lines in order to identify the command to be executed. The command encryption device 95-110 of the arithmetic unit, which is connected to a number of lines of the decryption device 95-109, is a matrix consisting of a number of OR circuits. If one of the input lines of this encryption device is energized, the command encryption device 95-110 of the arithmetic unit generates a number of signals which are fed to the arithmetic control unit 95-130 of the arithmetic unit 95-131 via the AND circuits 95-132 . The arithmetic logic controller 95-130 generally consists of a decryption and an encryption function table of known types; these function tables are supplied with the / digits or the command digits of a command word; in accordance with these digits, the function table signals then control the individual switching elements of the arithmetic unit.

The output signals of the command decryption device 95-109 are also fed to the function control unit 95-148; the function control unit 95-148 also includes an encryption function table and other elements which generate the function table signals labeled FTNNN, as will be described later.

The command numbers in the register 95-107 are thus fed to two separate control circuits, ie the arithmetic control unit 95-130 and the function control unit 95-148. In terms of time, the / digits are first passed to the function control unit 95-148, which generates the control signals which are required for the operation of the circuit arrangement shown in FIGS. 95A, 95B and 95C. After a short period, the function control unit can generate a function table signal FT 300, which is coupled to the AND circuits 95-132, whereby the encrypted command is passed from the decryption device 95-110 to the arithmetic control unit 95-130. During this process, further control signals are generated by the function control unit 95-148, whereby another command contained in the command register IR-I (95-101) is re -stored in the command register IR-2 (95-107, 95-107a and 95-108) will.

The register selection comparison unit 95-142 (FIG. 95 C) receives information on one of its two input lines from two sources. One of these input lines is connected to the OR circuits 95-149, which in turn are connected to the outputs of the AND circuits 95-145 and 95-119. One input of the AND circuits 95-119 is connected to the selection register 95-118. These AND circuits 95-119 transfer the two digits stored in register 95-118 to register selection comparison unit 95-142. The other input of the register selection comparator 95-142 is connected to the AND circuits 95-145 via the OR circuit 95-149; The .B digits stored in the first command register 95-101 are transmitted on this line. As can be seen from the drawing, the two AND circuits 95-145 and 95-119 each represent ten AND circuits, and thus transmit the ten information units of these two digits to the register selection comparator 95-142. The AND circuits 95-145 are opened at a certain clock time of a short period, namely at the clock time t ₅ , while the AND circuits 95-119 are blocked at the same time. The data, ie the two digits which are fed to the register selection comparison unit 95-142 via the OR circuit 95-149, are compared with the two digits in the selection register 95-113, which are also fed to this comparison unit 95-142. If the digits of these two sources are the same, an equality signal CAAM is generated. If, on the other hand, the digits are not the same, an inequality signal CAAL is generated. The signal CAAM or CAAL is fed to the function control unit 95-148. If the signal CAAM is generated, this means that either the S digits or the A digits of a command to be executed match the result address of a previous command. If a specific register were to be selected in the usual way by the selection register 95-118 before the previous command was terminated, the computer would not receive the latest data. To avoid this, the function control unit 95-148 is provided with test AND circuits which respond to the signals CAAL and CAAM

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speak to. When the CAAL signal is generated, the overlapping operation of the computer system is not disturbed; on the other hand, when the CAAM signal is generated, the overlapping operation is temporarily prevented until the previous command has been executed or until the data of this previous command have been circulated again.

The register selection comparison unit 95-142 is not described in detail, since devices for comparing of decimal values, which are represented in binary encrypted form, in technology are already known. The only task of the comparative work is to generate a first signal, if the compared data are the same and provide a second signal, when the data being compared are not equal.

The arithmetic unit 95-131 shown in Fig. 95C receives the data to be processed from two sources. The first source is the memory, which is connected to the arithmetic unit 95-131 via the main reading line HSB-R and the AND circuits 95-146. All AND circuits 95-146 are controlled by the function table signal FT 370. As can be seen from Fig. 95C, these AND circuits 95-146 represent 60 AND circuits all of which are connected to the M input register 95-150. The M input register 95-150 is in turn connected to the arithmetic unit 95-131. Another input to the arithmetic unit 95-131 can be connected to one of the addressable registers 95-121, which outputs its content to the AND circuits 95-128 when it has been selected by the register selection decryption device 95-120. The AND circuits 95-128 are controlled by the function table signal FT 380. These AND circuits also represent 60 AND circuits, so that all twelve digits contained in a specific addressable register can be transmitted. The output signals of the AND circuits 95-128 are coupled to the input of the arithmetic unit 95-131 via the OR circuits 95-129 and input pulse shaping elements 95-129 a.

For certain operations, the content of an addressable register must be sent to the arithmetic unit 95-131 via the M input register 95-150. In such a case, the contents of the selected register are passed through the AND circuits 95-122 controlled by the function table signal FT 425 and the OR circuits 95-123 to the regeneration pulse shaping elements 95-124 ; From here, the content of the selected register then reaches the M input register via the AND circuits 95-171 controlled by the function table signal FT 373.

The output of the arithmetic unit 95-131 is connected via the AND circuits 95-126 and the OR circuits 95-123 to the input of the addressable registers 95-121 , so that the results determined by the arithmetic unit 95-131 are converted into a selected addressable Register 95-121 can be saved. The selection of the addressable register is determined by the digits in the selection register 95-113, this selection being made via the register 95-118 and the selection decryption device 95-120 .

The result determined by the arithmetic unit 95-131 is fed back to this work under certain circumstances, namely via the AND circuits 95-127 and the OR circuits 95-129 or via the AND circuits 95-170 and the M input register 95 -150. As can be seen from the drawing, AND circuits 95-126 and 95-127 are controlled by function table signals FT 426 and FT381, respectively; the AND circuits 170 become

ίο on the other hand controlled by the function table signal FT371. If the function table signal FT 426 is present, the result generated by the arithmetic unit 95-131 is sent to one of the addressable registers 95-121. If, on the other hand, the function table signal FT 381 or FT 371 is present, the result is directly fed again to the arithmetic unit 95-131 in order to be further processed. The reason for this possibility arises from the overlap principle, since the instructions to be executed next sometimes require data that is currently being processed. In such a case, the result determined by the arithmetic unit is passed via the AND circuits 95-126 and the OR circuits 95-123 to a specially selected accumulator 95-121; in addition, the result is fed back to the arithmetic unit via the AND circuits 95-127 or 95-170.

The addressable registers 95-121, which supply the arithmetic unit 95-131 information via the AND circuits 95-128 and which supply the five least significant digits of a machine word to the ^ -adding unit 95-139 via the AND circuits 95-133, can be theirs Also store the content in the main memory via the arithmetic unit and the main writing line HSB-W . The addressable registers 95-121 are at their outputs with the M input register 95-150, the AND circuits 95-122, the OR circuits 95-123, the regeneration pulse shaping elements 95-124 and the AND circuits 95-171 tied together. In this operation, the content of an addressable register is not changed when it passes through the arithmetic unit 95-131; this arithmetic unit only works as a transmission path in this case. The output signals of the arithmetic unit are coupled to the AND circuits 95-125 via the AND circuits 95-126, the OR circuits 95-123 and the regeneration pulse shaping elements 95-124. The AND circuits 95-125 are controlled by the function table signal FT3S2 and thus route the contents of a selected addressable register to the main memory via the main write line HSB-W.

From the drawing it can be seen that the output of the regeneration pulse shapers 95-124 is returned to the addressable registers 121 again. This return is necessary if - as in the present case - the information from an addressable register 95-121 is read out destructively will. In this way, the information read out from an addressable register fed to the same register again.

Computer operating cycle

For a better understanding of the functions and mode of operation of the various switching elements now in connection with FIG. 95 of the operating cycle of the computer system.

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In the first step of the sequence of operations, the can be taken out and an operand

five in the control counter 95-104 with JV, which corresponds to the / digits of the

signed digits which one input of the B-add instruction JV can be processed.

Works 95-139 via the AND circuits 95-137 After the JV command has been re-stored and re-

fed. The add-1 signal FT-UA at the transfer 5 has been changed, the command register 95-101

input 95-154 to B-adder 95-139 is activated by connecting the function table signal

normally turned on at the same time so that FT 321s are evacuated. In the short period, ie

the B adder 95-139 the content of the control in state 1 for the command JV, in which the digits of the

Counter 95-104 increased by one. If, on the other hand, the command JV is transported to the B adder 95-139

The computer system is switched on for the first time, so the OK and have been changed, the content is changed at the same time

Signal FT-UA is not generated, so that the first from the control counter CCl (now JV) to the B adder

called command is command JV. The output signal 95-139 is supplied and increased by one. Of the

of the B adder 95-139 (now JV) the control counter now contains the new address JV + 1,

Address decryption device 10-64 supplied; via the decryption device 10-64 and

this address decryption device selects the AND circuits 95-140 to be transmitted, so

on the content of the memory location JV. In this, that the second command JV4-1 from the memory

Storage location JV is the first from the taken and entered in the command register 95-101.

Command to be taken from memory; all of this can be saved. The B adder 95-139

Missing word is read from the memory via the main reading, so it carries out several operations at the same time, because

line HSB-R and the AND circuits 95-100 20 die during one and the same short period

transported to the first command register 95-101. The M 'digits of the contained in the command register 101

specific time span between the coupling command to a part of the content of an addressing

added to the address by the decryption device free register 95-121 and also

10-64 and the coupling of the content of these the number stored in the control counter CCl by one

Memory address on the main read lines HSB-R 25 increased. These two operations take place in

is referred to as a short period. one and the same short period will take place, however

While the entire command word JV in the loading ^at different clock times of this short period.

error registers 95-101 are stored are kept.

simultaneously, the two B-number of the instruction word JV JV After the command in the second, from right above the main read line HSB-R 30 and the memory parts 95-107, 95-107 and 95-108 loading and α circuits 95-117 in the The command register and the subsequent Be-95-118 are stored in order to then read the contents of an addressing marked in this way JV + 1 into the command register95-101, the computer is located in the Zubaren register. The state in which ^{was 2 with reference to the command N and in} state 1 the computer is at that moment, 35 ^with reference to the command JV + 1.
is referred to as "state 1". At the beginning of state 2 a new one is created in the

State 1 lasts for each command a short memory location JV + 2 command contained in the previous one

period. During state 1, this is called up in the first described manner; d. i.e., the B adder

The command word JV in the command register, converted 95-139, becomes the content of the control counter 95-104

saved and modified. For this purpose 40 are supplied, whereupon this B-adder the content

the / digits and ^ [digits of the command JV the Re- ^de s control counter increased by one and a de-

registers 95-107 or 95-107 α supplied. The output signal generated in the discussion that the

error register 95-101 located five M 'digits of the address decryption device 10-64 of the memory

Command JV are fed via the AND circuits 95-136, so that the next command is

to which one input of the B adder 95-139 45 can be taken. This next command will

coupled. At the same time the effect is stored in the command register 95-101 via the, if

AND circuits 95-117 ^com in the selection register r JV command +1 in the memory of the parts

95-118 stored B-digits of the command JV 95-107, 95-107 «and 95-108 existing command

by the decryption device 120 that a register IR-2 is stored and the command JV

addressable register 95-121 is selected so that 50 is nearly executed.

part of the registers that can be addressed in this -109 forwarded. These resolutions can be passed. In this case, however, only need the processing device checks the five least significant digits of the two / digits consisting of the 55 units and energizes B digits of the command JV, one of its 100 output registers the B adder 95-139 selected on the basis of this check fed to lines. The outputs excited in this way. The sum of the five M 'digits of the instruction of the decryption device 95-109 miss JV and the five least significant digits of the causes the circuits of the function control unit 60 95-148 selected by the B digits of the command JV to generate the corresponding function addressable Register is given table signals from the B adder so that 95-139 shown in Fig. 95 is applied to instruction register IR-2 (95-108) through the controller in accordance with the given AND circuits 95-105. While the down command is working.

changed M-digits of the JV instruction to the register It is now assumed that the

95-108 are supplied, these digits are 65 arithmetic unit 131 on the basis of the in the registers

at the same time also the address decryption pre- 95-107 and 95-107 α located command JV one

Direction 10-64 so that he should perform this simple operation, including two

Numbers marked content of a memory location operands are required. The first operand should

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from memory and the second operand from a selected addressable register 95-121. During state 2, these two operands must be supplied to instruction N or otherwise made accessible. As is known, the operand that was located in the memory location identified by the instruction N was called up by the B adder 95-139 during state 1, that is, while the M digits of the instruction N were in the instruction register 95-101 and by the. B-adder 95-139 were modified. This operand taken from the memory is connected to the main line during the third short period, ie at the clock time t _{s of} this period (state 2).

State 2 lasts indefinitely, since the time it takes to perform the operations is required in state 2, depends on the command to be executed. State 2 can thus require several short periods.

In order to be able to read out the content of the addressable register identified by the command N , the two ^ digits of this command are transferred from the register 95-107 α via the AND circuits 95-134 and the B adder 95-139 to the AND Circuits 95-115 coupled. These AND circuits are connected at their outputs to the selection register 95-118. While the A digits are coupled to one input of the .B adder 95-139, a decimal zero is connected to the other input of this adder from the zero register 95-147 , so that the addressable register 95-121 to be selected from the two A-ZiSem of the command in register 95-107 α {IR-2) is selected. The two A digits are stored in the selection register 95-118, from where they can be forwarded to the register selection decryption device 95-120. This decryption device 95-120 selects the relevant register 95-121 identified by the digits in the register 95-118. The operand located in this selected addressable register is fed to the arithmetic unit 95-131 via the AND circuits 95-128, the OR circuits 95-129 and the pulse shaping elements 95-129.

Two pulse times after the aforementioned restoring of the A digits of the command N in the command register 95-107, these digits are again fed to the B adder 95-139 , with a decimal “0” or “1” being sent to the other input of the B adder is coupled. The result of this arithmetic operation is then fed to the selection register 95-113 via the AND circuits 95-112. The two Λ digits of the command N are stored in this selection register 95-113 until the arithmetic unit 95-131 has determined a result on the basis of this command. The present invention does not describe in detail why the two A digits are stored in this way; it should only be mentioned that the instruction iV located in the storage elements 95-107, 95-107 α and 95-108 of the instruction register IR 2 is no longer available after the result relating to it has been received.

As already mentioned above, one of its 100 output lines is energized by the command decryption device 95-109 in order to indicate the command to be executed on the basis of the / -cipherals located in the command register 95-107. These output lines are also connected to the command encryption device 95-110 of the arithmetic unit; this encryption device generates at its output a number of signals which are different for each energized line of the 100 lines. The command signals generated in this way are coupled by the encryption device 95-110 via the AND circuits 95-132 to the computer control unit 95-130. There these signals are stored in a static register so that they can control the operations of the various switching elements of the arithmetic unit 95-131 in accordance with the N instruction. Since the AND circuits 95-132 are controlled by the function table signal FT 300, it follows that the command N in the command register IR-2 (95-107) must first cause the function control unit 95-148 to generate signals, before an output signal of the encryption device 95-110 can be connected to the arithmetic control unit 95-130.

As in connection with FIG. 96, the control unit 95-148 contains a device known under the name "program counter" which is controlled by the command iV stored in the second command register 95-107. This program counter is known in the art and is used to generate a signal when a given instruction is terminated or is about to terminate. In other words: a short period before the end of the command to be executed by the arithmetic unit 131, the program counter generates an end signal CHJP (EP), as a result of which the function table signals of the function control unit 95-148 are changed.

As a result of these new signals, the command N + 1 in command register IR-I (95-101) is relocated to command register IR-2. The instruction N + 1 is modified in the manner described above and appears in the second instruction register, which consists of the register parts 95-107, 95-107 α and 95-108. In addition, function table signals are generated by the function control unit 95-148 so that the numbers in the control counter CCl (95-104) can be incremented by one by the B adder 95-139 and fed to the address decryption device 10-64, so that a new instruction N. +2 can be stored in the command register IR-I (95-101). So if the first command N has almost been executed by the arithmetic unit 95-131, the second command N + 1 is in the second command register, and the third command N + 2 is in the register 95-101; this state of the computer system is denoted by state 3 with respect to the command N, state 2 with respect to the command iV + 1 and state 1 with respect to the command N + 2 .
State 3 lasts for a given command

(N) a short period; At the end of this short period, the result of this command is available in the result register 95-130a of the arithmetic unit. At the beginning of state 3, a new command (N + 3) is again called up by the control counter CCl.

Assuming that the command N + 1 now in the command register IR-2 only requires a short period to be executed in the arithmetic unit 95-131, then during state 3, reference is made to

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In response to command TV + 1, command JV + 2 contained in command register 95-101 is relocated and modified in command register IR-2. The / digits of the command JV + 1 located in the command register IR-2 are also fed to the decryption device 95-109, while the ^ 4 digits of this command are fed to the selection register 95-113. At the same time, the two ^ digits of the JV instruction, which are located in the selection register 95-113, are fed to the selection register 95-118 via the AND circuits 95-114. At this point the computer is in state 4. With respect to the JV instruction, the result determined during state 3 is sent to the addressable register 95-121 selected by the ^ 4 digits of the JV instruction; These ^ (- digits were in register 95-118 and were transported to the register selection decryption device 95-120 at the end of state 3 applicable to instruction N. During state 4, the result of instruction JV is transferred from result register 95-130 a des Arithmetic unit 95-131 passed through the AND circuits 95-126, the OR circuits 95-123 and the regeneration pulse shaping elements 95-124 to the addressable register 95-121.

In summary, the following can be determined for the four states: The Zutsand 1 indicates that the request made by the control counter for the purpose of removing the command JV was successful, ie that the memory-free signal MNB was received. At the same time, this status indicates that the command called has been stored in the command register IR-I (95-101).

In state 2 the command JV was re-stored in the command register IR-2; it is now carried out by the arithmetic unit 95-131.

In state 3, the JV command continues to be executed by the arithmetic logic unit, but only a short period is required for its execution. In addition, the command JV + 1 is in this state in the command register IR-2 and the command JV + 2 in the command register IR-I.

In state 4, instruction JV is executed and the result of the arithmetic operation is fed to an addressable register by the arithmetic unit. At the same time, the command JV + 1 is still being executed by the arithmetic unit, but only a short period is required for its execution. During the same state, the command JV + 2 is also in the command register IR-2 and the command JV + 3 in the command register IR-I. In full overlap mode, the computer system executes four different commands at the same time during state 4. However, only one of these four commands controls the arithmetic unit.

If the computer works in the case of a given command in full overlap mode, the transition from state 3 to state 4 occurs after a predetermined time. This means that after the short period in which the arithmetic unit last carried out an operation on the basis of this command, the result is automatically fed to one of the addressable registers 95-121. However, with respect to the instructions contained in instruction registers IR-I and IR-2 , as well as the instruction currently being fetched from control counter 95-104, the transition from one overlap state to the other is primarily generation dependent an end signal by the control unit 95-148 when the program counter has reached a predetermined state, ie when it indicates that the instruction currently stored in the instruction register IR-2 has almost been executed.

As is known, the addressable registers 95-121 are used to provide operands, To receive results as well as a change value for the M 'digits in the command register 95-101 ίο to provide. If the computer is working in full overlapping mode, the following states can occur appear:

1. The result that has just been determined and to be stored using the JV command is the operand

represented by the ^ digits of the command JV + 1 was retrieved.

2. The result just determined and to be stored by the command JV contains a change value to be stored in an addressable register for the M-digits of the command JV + 2 located in the command register IR-I.

3. The result which is determined for the command JV + 1 currently in the command register IR-2 contains the change value for the M 'digits of the command JV + 2.

The register selection comparison unit 95-142 is used to compare the address of the result in the selection register 95-113 with the address of the operands identified by the command JV + 1 and with the J5 digits of the commands JV + 1 and JV + 2, if these are located in the command register IR-I . If such a comparison indicates that the address of the result does not match the address of the operands or the 5-digit number, the overlap operation is continued without interruption. On the other hand, if the comparison reveals that the addresses of the result and the B digits of the command JV + 1 or JV + 2 are the same, then the overlapping mode is changed. However, if the address of the result corresponds to the address of the addressable register from which an operand is to be taken for the next instruction to be executed, the overlap mode is not changed and the result determined is returned directly to the arithmetic unit 131 for further processing.

Function control unit

The description of the FIG. 96 shown function control unit 95-148 and associated facilities.

As is known, the instruction decryption device 95-109 is controlled by the register element 95-107 of the second command register, in which the / digits of a command word are located. In Fig. 96 this register element 95-107 consists of two parts: a register 96-200 for the most significant Instruction number and a register 96-201 for the least significant instruction number. Like this marking states, the most significant / digit is in register 96-200 and the least significant in register 96-201 / Digit of a command word is saved. Each of the two registers 96-200 and 96-201 consists of five Switching elements that can be designed as bistable circuits and each have two outputs own. These five switching elements are used to

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tion of the decimal digits consisting of five information units is provided. The output signals of the two registers 96-200 and 96-201 control the instruction decryption device 95-109, which in turn consists of two separate decryption devices 96-202 and 96-203 , which are assigned to registers 96-200 and 96-201, respectively. The decoding devices 96-202 and 96-203 are designed as AND circuit matrices and generate a signal on one of their output lines which corresponds to the decimal value stored in the registers mentioned. Since the registers 96-200 and 96-201 each store five units of information corresponding to a decimal digit, the decoding devices 96-202 and 96-203 each have ten output lines corresponding to the values 0 to 9.

The ten output lines of the decryption device 96-202 and the ten output lines of the decryption device 96-203 are connected to a further decryption device 96-204, which consists of a number of AND circuits, e.g. B. from AND circuits 96-205 and 96-206. Each output line of the decryption devices 96-202 and 96-203 controls ten such AND circuits, so that the decryption device 96-204 comprises a total of 100 AND circuits and 100 output lines, which are represented by lines 00-99. So z. B. the line 00 represents the output line of the AND circuit 96-205 of the decryption device 96-204. The inputs to this AND circuit 96-205 are derived from the lines which the decimal digits 0 of the decryption device 96-202 and 96-203 transfer. The lines 01 to, not shown

98 would be derived in a similar manner from further AND circuits not shown. So z. B. the line 25 be connected to the output of an AND circuit the decryption device 96-204 is not shown, the two output signal corresponding to the decryption device is formed by a decimal number of 96 to 202 and controlled by the decimal number 5 output signal corresponding to the decryption device 96-203 .

The 100 output lines of the decryption device 96-204 are connected to the encryption device 95-110. If one of the lines 00 to 99 is energized, the encryption device 95-110 of the arithmetic unit, which consists of an arrangement of OR circuits, generates signals on a number of output lines. Each of the lines 00 to 99 generates a different number of signals at the output of the encryption device 95-110 of the arithmetic unit. Like F i g. 95 shows, the outputs of the encryption device 95-110 are connected to the control circuits 95-130 of the arithmetic unit 131 via the AND circuits 95-132 . Lines 00 to

99 of the decryption device 96-204 also control the decryption device 96-207 of the program counter, which is also a matrix consisting of AND circuits. As shown in FIG. 96, the lines 00 to 99 are each connected to different AND circuits of the program counter decryption device 96-207. So is z. B. the line 00 is connected to four AND circuits, while the line 99 is connected to two AND circuits and the line 50 is connected to five AND circuits of the decryption device 96-207. The output signal of the program counter 96-215 is also applied to each AND circuit of the decryption matrix 96-207.

The program counter 96-215 can consist of a number of bistable devices which are connected in series are so that when connected

ίο of pulses at the input of the first bistable device, other bistable elements of the program counter change their state. Such devices are known in the art and can e.g. B. consist of a decimal counter or a binary counter controlling a matrix. In any case, the program counter used is supplied with step pulses from the control unit of the computer system and from the switching elements 96-214, whereupon this program counter is incremented once each time and a single output signal is generated in the process. According to the present invention, the program counter generates output signals which correspond to the counts 0 to 45. If the program counter receives z. B. 45 input pulses (CPCS) from

As control unit 96-214, it generates an output signal on its output line PC 45; If, on the other hand, the program counter receives 23 input pulses, it generates an output signal on the output line PC 23. The step pulses coupled to the program counter 96-215 are generated under the influence of other signals which are generated by other parts of the function control unit 95-148. The output lines of the decryption device 96-207 of the program counter control a matrix 96-210 consisting of OR circuits in such a way that this matrix or encryption device consisting of OR circuits receives a number of intermediate signals CHJP-I to CHJP-N when one of the output lines is energized generated by decryption device 96-207. In addition, the decryption device 96-207 of the program counter generates the signals PYMR and the write signal CU on certain output lines. These signals are required for commands that require access to the main memory. Thus, the decryption device 96-207 generates the CI / write signal for each instruction contained in registers 96-200 and 96-201, since this instruction requires information to be stored in the memory. Conversely, the decryption device 96-207 generates the read signal PYMR for all commands which require information to be read out of the memory, e.g. B. from the memory to the arithmetic unit 95-131 require. The read signal PYMR is also generated when commands are taken from the memory by the control counter CCl or CC2. Although not shown in the drawing, the output signals of the AND circuits 95-140 and 95-151 (FIG. 95B) can be input to the inputs thereof

6o- the output signal of the control counter is, are combined and generate the read signal PYMR when the memory is activated for the purpose of taking a command provided for the computer system.

All output lines CHJP of the encryption device 96-210 are connected to the clock decryption device 96-211, which also consists of a matrix of AND circuits,

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such as AND circuit 96-212. The lines CHJP are each connected to a different number of AND circuits, the line CHJP-I e.g. B. is connected to the inputs of four or five (not shown) AND circuits. Further input signals are present at the AND circuits of the clock decoding device 96-211, one of these other input signals being derived from the clock generator (FIG. 15), which has eight output lines t _? to t ₇ . As can be seen from the drawing, the AND circuits of the decryption device 96-211 are also controlled by the output signal of the block 96-214, which is referred to as "cycle control and switching elements of the computer system". Under the influence of various signals, e.g. B. the signals CHJP and PYMR and the write signal CU, the block 96-214 also controls some AND circuits of the decryption device 96-211. The memory-free signal MNB is generated by the memory and indicates that the data required by the computer system are being read from the memory. This block 96-214 consists of a number of AND circuits and other switching elements. The AND circuits of the decryption device 96-211 and each connected to the last decryption device 96-211 α ; this device represents a matrix consisting of OR circuits. From the previously described mode of operation of the encryption and decryption devices, it follows that each output line of the decryption device 96-211 excites a different number of output lines of the encryption device 96-211 α. The output signals of this encryption device 96-211 α are referred to as function table signals FT1 to FTN . These signals control the switching elements of the computer system shown in FIG. 95 with the exception of the internal circuits of the arithmetic unit 95-131, for which further control circuits 95-130 are provided.

The program counter 96-215 is controlled by the step signal CPCS and the flush signal CPCL , both of which are generated by the cycle controller 96-14. If there is an instruction in registers 96-200 and 96-201 which keeps arithmetic unit 95-131 occupied for a number of short periods, then encryption device 96-210 generates the signals CHJP which are required to switch program counter 96-215 over to advance the control unit 96-214. The processes that occur can be briefly summarized as follows: It is assumed that the two digits contained in registers 96-200 and 96-201 of the second instruction register indicate an instruction, e.g. B. a multiplication command, for the execution of which the arithmetic unit 95-131 must be used for several short periods. The instruction located in registers 200 and 201 is decrypted by decryption devices 96-202, 96-203 and 96-204, whereby one of the AND circuits located in decryption device 96-204 has an output signal on one of lines 00 to 99, e.g. B. to line 75, is coupled. The signal appearing on this output line 75 is fed to the encryption device 96-110 of the arithmetic unit and is also connected to certain AND circuits of the decryption device 96-207 of the program counter. At one of these controlled AND circuits, for example the AND circuit 96-221, the output signal FCO of the program counter 96-215 is present at the same time. This output signal PCO indicates that the program counter 96-215 has been cleared. A signal is transmitted via the AND circuit 26-221 to the encryption device 96-210, whereby the latter generates signals on a selected number of lines CHJP. The number as well as the grouping of these energized lines CHJP depends of course on which AND circuit of the decryption device 96-207 generates an output signal. In any case, the signals which were generated on lines CHJP under the influence of the command located in command register / jR-2 are fed to further switching elements of block 96-214. The signal CPCS of this block 96-214 switches the program counter 215 from FCO to FC1.

If the instruction stored in registers 96-200 and 96-201 cannot be executed within a program step, the signals CHJP generated by this instruction cause the cycle control unit 96-214 to repeat the step signal CPCS until a End signal CHJP (EP) is generated. Following the generation of this CHJP (EP) signal, the CPCL signal is generated, whereby the program counter 96-215 is cleared and reset to zero.

In the case of commands that cannot be executed within a short period, the program counter generates a new output signal for each short period, whereby the content of this counter is incremented from 0 to 45 (for the longest command to be executed). Each time the program counter is advanced, the decryption device 96-207 generates new signals, which in turn lead to the generation of new signals CHJP by the encryption device 96-210.

As already mentioned elsewhere, the output lines FCO to PC 45 of the program counter are connected to various AND circuits of the decryption device 96-207.

Depending on which instruction is in the instruction register IR-2 , one of the AND circuits of the decryption device 96-207 generates an end pulse signal CHJP (EF) when the program counter 96-215 reaches a predetermined count. Is z. B. the output line 75 of the decryption device 96-204 energized under the influence of a given instruction, the AND circuit 96-225 generates a signal in the decryption device 96 to 207, when the program counter reaches the count 96-215 PC 23rd The output of AND circuit 96-225 is applied to encryption device 96-210, thereby energizing line CHJP (EP) . The CPCL signal is then generated by the cycle control unit. The signal CHJP (EP) is therefore also passed to the arithmetic unit 95-131 after a short period in order to clear its register so that it can accept a new operand and a new instruction.

The two / digits are stored in the registers 96-200 and 96-210 in static form; d. H., the content of these registers will not be changed until they are cleared and the two

ί 190

335

Missing digits of the next command are stored
the. So while registers 9J-20
96-201 two given command digits are located, I
the line reached by decoder 96-204 continues to be energized. On the other hand, the ^{8 is changed} by the decryption device 9 ^ 207 on the basis of the selected line of the encryption device 96-204 «""f * ^" * 336

Srd ^ ÄrSSr command then in the command register jR * ™ **** ^.

dem, whereby other line CHJP are energized at the same time in each short period.

Since the AND circuits of the decryption device 96-211 are controlled by both the CHJP signals and the clock pulses of the clock generator (FIG. 15), the various output pulses of this decryption device 96-211 have a duration of only one pulse. Likewise, the signals of the encryption device 95-148, which are generated under the influence of the signals of the clock decryption device 96-211, have a duration of only one pulse.

The control circuits described here are already known in the art. A detailed description of the switching elements 96-200 to 96-210 is therefore not given. It should be readily understood by those skilled in the art that the encryption device 96-210 can generate any group of signals CHJP under the influence of the instruction digits in registers 96-200 and 96-201. Show z. For example, if the digits in registers 96-201 and 96-200 give an instruction to check the output of a particular flip-flop or the setting of a particular flip-flop, the corresponding CHJP signals are generated in accordance with this command.

97 shows certain details of the cycle controller 96-214 used in connection with the setting and testing of the D flip-flop. The present invention is not concerned with generating the various function table signals required to convey information between the various shown in FIG. 95 devices shown. In Fig. 97 therefore only the circuit arrangement is shown which is required to set, reset and test the aforementioned D flip-flop.

Fig. 97 shows the D flip-flop 97-100 which is set by a function table signal FT 451 of the computer system; this function table signal is used by the system shown in FIG. 96 shown encryption device 96-211 α generated. This D flip-flop is reset by a function table signal FT 896 of the central processing system, which is generated by the control unit of the central processing system on the basis of a command 96 in order to control the AND circuit 97-11. To generate the function table signal FT 451, a command from the computer system is provided, which is taken from the memory in the usual way; that is, the memory is controlled by the control counter CCl (95-104) via the B adder 95-139 and the memory address decryption device 95-141 . After this early coupling of the clock signal ί 3 has been stored, the AND circuit 97-1 is opened. The output signal of this AND circuit 97-1 is coupled to the CNAA flip-flop circuit 0 (97-2) , which is then switched to the setting state at _{clock time t 4.} If the command requiring the setting of the D flip-flop 97-10 is stored in the command register IR-I during a first short period, the signal CHJP 20 is only generated at the clock time t _{t of} this short period, i.e. at the time when this command is entered into the Command register IR-2 is relocated. It follows from this that the AND circuit 97-1 is only opened at the clock time t _{s of} the next short period. The setting output signal of the CA ^ yi flip-flop 0 is therefore only _{generated at the clock time i 4 of} the mentioned next short period. This output signal of the CN, 4/4 flip-flop circuit 0 is supplied to the AND circuit 97-3 as a pass signal. This AND circuit 97-3 is opened by the coupling of a clock signal 1 1; From the information given above, it follows that the output signal of this AND circuit 97-3 is generated in the second short period after the instruction has been stored in the instruction register IR-I . The output signal of this AND circuit 97-3 is the function table signal FT 451, which is required for setting the D flip-flop circuit 97-10. This D-flip-flop 97-10 therefore generates its setting output signal at the clock time t _{2 of} the second short period which follows the storage of the command in the command register IR-I. If the D flip-flop is in the setting state, this indicates that the computer system has combined a group of summary commands and that these commands can now be processed. This processing can then be initiated by the central processing facility checking this D-flip-flop during one pass of the control loop.

It goes without saying that the command of the computer system by means of which the D flip-flop 97-10 is set is only provided in the program if the computer operator is using the central processing system can execute new summary commands.

The computer system itself also has the option of checking the D flip-flop circuit. These The test is then made when the computer system receives another group of summary commands ready for processing by the central processing plant. In this case the The computer system determines whether the D flip-flop is set or not. If it is set, it will thus indicated that the previous group of summary commands has not been filed or otherwise has been treated by the central processing facility. So if the computer determines that if the D flip-flop is in its setting state, it initiates the transfer of control to another program in accordance with the test command.

337 338

A similar format, namely computer system ITS, has another command for checking the D flip-flop circuit. 97 XXPXXMMMMM, where P in turn can assume the As in the case of the D-toggle value 1 or 2 for setting the command provided for the checking circuit 97-10 , this computer system will be identified; In this case, the M-digit test command decrypted and then encrypted denotes the memory address since to generate intermediate signals, ie in this case the signals CHJP 20 and CHJP 21 to which the controller is to be transferred. As with when the flip-flop 97-10 is found in the set state of setting the D flip-flop 97-10. In the present example, the CA / ^ flip-flop 0 (97-2) by (Fig. 28B) this is the memory address 02500, in which the signal CHJP 20 is set. The D word is located by the signal io. These commands generate CHJP 21 as well as the simultaneous coupling of the also the end signal 614.
Clock signal i3, the AND circuit 97-4 is opened, so that the CW / 1 ^ flip-flop circuit 1 (97-5) in magnetic tape synchronizing device 53
their setting status can be switched.

The setting output signal of this flip-flop circuit 15 The essential parts of the magnetic tape synchro 97-5 is coupled as a blocking signal to the AND circuit nizing device are schematically coupled in Fig. 59 to 71 97-3 , so that the function tables are shown. The synchronization device is generated by signal FT 451 when a test command is initiated, not commands from the central processing system 14 ; If the D-flip-flop was to be controlled and generated the control signals for this point in time in its reset state, it is 20 magnetic tape recorders and the central processing unit is not set. management system their own condition and that of one

The setting output signals of the multivibrators of the selected tape devices with. It monitors the 97-2 and 97-5 are connected as pass signals to the transmission of the serially arranged digits from the AND circuit 97-6, the output information words of which from the output divided for this purpose as a pass signal to the AND circuits 25 output -Buffer storage of distributor 13 97-7 and 97-8 is coupled. As a further through to a selected tape device during the entry signal, the AND circuit 97-8 receives the storage of data on magnetic tape; reverse output signal of the D flip-flop 97-10. If it monitors the transmission of the D-flip-flop arranged in series at the time of the nth digits of information words from an execution of the test command in the setting state, then the selected tape device to the input buffer is opened the AND circuit 97-8, whereby you save of the distributor during the readout output signal as the last transmission signal to the information from the magnetic tape. While AND circuit 97-7 is being coupled. If the same-digits are generated from the tape device to the processing system and the clock signal ti is generated at the same time, the magnetic tape CNLA used for the representation AND circuit 97-7 then becomes an output signal 35 of the data on the magnetic tape. This signal CNLA is fed to a number of code from the synchronizing device in the code switching elements, which convert a jump on the central processing system; initiate a new program, with this, however, the digits are transported from the central jump in accordance with the M digits of the processing system to the tape device, so the command takes place through which the check of the D-Kipp-40 is used for the representation of the data in the interconnection is initiated. machine used code in the magnetic tape

The D flip-flop 97-10 is also converted from code. The central processing plant synchronizer checked. To count the read out or stored digits. For this purpose, the function table signal is remote on the twelve-digit basis and the words on FT 897 from command 97 of the central processing 45 of the ten-word basis. Has generated the synchronizing device. The AND circuit 97-12 is prepared by the function table signal processing ten words, it transmits an FT 897. Command from the central processing system to the be-The command 97 belongs to the program for the tape device in question, in order to continue with the read or write control loop and the operation is continued at the command register IR-I. If such an instruction is not decrypted by the central processing facility; If this 5 ° is present, it will generate end signals, the process has already been described elsewhere. whereby the tape device in question is in operation, the D flip-flop circuit 97-10 is at the time of the setting. These and other functions of the magnet execution of a command 97 by the central association synchronization device are now in the operating system in the setting state, so the connection with the AND circuit 97-9 in the magnetic tape storage is opened and a command sequence is generated described,
special jump signal, as a result of which the control in the processing system generated by the encryption matrix 10-18 is transferred to the program identified by the function table signals for the magnetic tape error 97. Storage are indicated by the number 8 as well as the num- In this context, reference is made to F i g. 28 and mer of the command from which they are generated, refer to the description. 60 den. The following preparation steps apply

The one in the program of the central processing well for read and write operations as well as for

The command 96 provided in the system is in the format of rewinding operations.
96 XXPXXXXXXX, where P is 1 or 2

can assume to the computing system 1 or 2 to preparation steps

mark. The format shows that P 65

represents the eighth digit and in the resolution- 1. Occurrence of the command 60XXXXTXXXXX. In

processing device 10 .4-31 (Fig. 10A) decrypts this format, the number T denotes the

will. The test command 97 of the central processing-selecting tape device. The number of the tape device

339 340

If this command is entered into the B register 10Α-Π, it generates at least the main latching signal to be stored there for the next step to the 72 UMIR. Is the tape device set to reverse

To be available. (Current gate 72BG ignited), it creates the intermediate

The instruction 60 generates the function table lock signal 72 UBIR, provided that the signal FT 860, in order to determine whether the control unit is not currently operating. Under the same conditions of exposure to the tape synchronizer, the interlock signal 72 UFIR will be clear. If this is the case, it is generated when the device is in the forward position be flip-flop 60 a in its setting state and finds it (current gate 72FG ignited). If this is the case, the signal 60ZF is not generated. If, on the other hand, the tape recorder is in the first block position (only control circuits are occupied, then the signal 60ZF io main interposer current gate 72MIG is triggered), so that the AND circuit 62 a is opened by the device, the signals 72 UFIR and becomes and a signal 860 generated, which emitted via the 72 UBIR. If the device is currently in operation, OR circuit 626 to the conditional jump line will not be coupled to either of the two last-mentioned signals (FIG. 28). For the present testifies. These two signals are used in the setting case, it is assumed that the signal 60A V is not displayed at the input of the flip-flop circuit 61 FI or 61 BI; in this case the will now be coupled. So that these flip-flops performed the state next step. of the currently selected tape device and not

2. The radio will indicate to the AND circuit 59 a that of an earlier tape recorder,

tation table signal FT 863 coupled. These AND- they are put back before the tape device

The circuit is opened at time t ₀ and the signals generated become effective. The provision

thus generates a signal 59 FRS, the following result occurs on the basis of the signal 60ZF, which is transmitted via a

has: Delay device RDF 61 e (0.15 micro-

a) It either switches the write intermediate lock seconds) to the reset input of the relevant flip-flop 596 or the read intermediate lock is coupled to the flip-flops. After the flip-down circuit 59c returns to its setting state for 0.15 microseconds, the flip-flop switches are reset, provided that one of these two flip-flop circuits 61F / and 61 BI is in the reset state. In addition, the presence or absence of the lock via the AND circuit 59 d causes the input signals 72 UFIR and 72 UBIR of the current switch-off toggle circuit 59 e to be reset. selected tape device. If the signal is 72 UFIR

b) With the function table signal FT 863 30 on, the flip-flop 61F / some is reset and the flip-flop 60a is created and generated instead of the output signal 61 FIR thus generating the signal 60ZF. In addition, the signal 61FIR. If the signal 72UBIR is present operational signals 6OB, F, R, W and RW from the den, the flip-flop 61B / is set and memory 606 is removed. generates the output instead of the output signal 61 BIR

c) The memory 61a is cleared so that the output signal 61BZR. If the tape recorder is in the new digit T, by which the tape recorder in the first block position, both blocking signals are located, can be stored. The on, so that the output signals 61 FIR and 61 BIR flip-flop 616 is set, whereby for the are generated. If the tape recorder is not in operation at the output of the memory 61a, ten ready (main interposer current gate deleted) or AND circuits 61-0 to 61-9 pass signals are in operation, the devices will be switched off. gnale 72 UFIR and 72 UBIR not generated; There are

d) The magnetic tape intermediate lock flip-flop and thus not the output signals 61FIR and 62 d as well as the magnetic tape selection flip-flop 61 to BIR.

62 e are postponed; at the same time the a) The output signals 61 FIR or 61 BIR

Toggle circuit 62 / return to the waiting state 45 via the OR circuit 61g to the AND circuit

placed, whereby it is coupled instead of the output signal tion 61 h , which also depends on the output

62VA now generates the signal 62UZ. output signal of the delay device 61z controlled

e) Finally, the function table signal is set. Simultaneously with the coupling of the Si- FT 863 , the toggle switch 61 r seen for the first data block previously 60ZF to the delay device 61 e is returned. 50 this signal was also sent to the delay inputs

2 A. At the cycle time t _Q are connected to the AND circuit direction 61 /; after a delay

61c the clock signal * 3 as well as the function table of 200 microseconds can therefore use the AND switch

signal FT 863 on, so that the B register 61 ft generate the signal 61Pl, if at this

10Λ-27 located T-digit in the memory 61a AND circuit at the same time the signal 61FIR resp.

can be saved. This digit signal 55 61BIR is present. At the same time, the

is then sent to one of the ten output lines delay device 61 / controlled individual

this memory, which to the AND circuits 61-0 pulse generator 61 / generates a pulse 61Pa. This

lead to 61-9 , coupled. This AND switching pulse is also generated when the pulse

gen were already prepared in step 2c, so that 61Pl is not generated.

that AND circuit, now the initial 60 b) by the pulse 61Pl, the magnetic tape crossing signal of the memory is turned 61a, between the blocking flip-flop 62 reset d to the. d via a terminal board 61, and an amplifier addition is generated, the magnetic tape Kippschalein selection output signal, whereby the selection processing 62 e set. The toggle switch 62 / is provided for the availability of the signal 61SXT for the tape device in question. 65 is also set, indicating that the

2 B. The selection signal 615ΆΓΓ indicates that the selected tape device is free. To this end

selected tape device causes its state to be controlled by the flip-flop 62 / the signal 62 UA

to communicate. If the tape device is ready for operation, it is generated.

341 342

c) The magnetic tape a write or read operation or a toggle switch 62 e is also set by the pulse 61 Ρα when the winding process is carried out (whereby the pulse 61 Pl is not present, which means that the pulse 61 Pl is not generated would be), it is shown that the selected tape recorder has not been given enough time to set the flip-flop 62 d to stand up. In this case, the flip-flop opens notify 62 d state. By this pulse, the AND circuit 62 k, so that it does not set the radio, however, the function table signal jFr876 to the conditional jump circuit 62 / provided for the availability of the magnetic tape; will be able to connect line. For the sake of simplicity, if the pulse 61Fl is not generated, the toggle remains assumed here that the program is set back so long circuit 62 / and thus generates the io waits until the corresponding tape recorder is free, signal 62ΤΓΆ. If the pulse 61Pl was not generated and a signal 61Pl is generated, whereby the main interlock current gate of the selected flip-flop 62 / is set,
th tape device is deleted, it is assumed that the central processing selected tape device has not generated the signal 72 UMIR in step 5, that this is generated; this signal blocks the AND circuit 15 selected tape recorder is free (function table signal 62 g does not and thus does not prevent the setting FT 872), so can be arranged by the processing system less magnetic tape intermediate lock toggle circuit 62 ii on more that a write or reason of momentum 61Pa. Read operation or a rewind operation carried out

3. Exam 99-6 now follows, and it will already be. Before an instruction for the execution of this operation is given in connection with the instructions 99, it must be entered in the register RP-I (10-45). During this test, it should be determined whether a control word is stored in which whether one of the magnetic tape selection flip-flops, the eleventh, tenth and ninth digits, identify the operating mode such as flip-flop 62 e, in its setting of the tape device. There is a status for each operating mode, provided that several synchronization devices are provided to set up the function table signal FT 866. There is the tilting witness. This function table signal has switched on 62 e in its setting state, so one of them is carried out the task, which is coupled to the main test line by the / -Ziffer signal and an eleventh digit from the register RP-I in the ReSprung to a command 64 to be stored in register60ö in order to provide the following signals. produce:

4. The function- 30 is / equals 3 generated by the command 64, the signals 6OF and 6OR table signalfT864, the magnetic tape selection is generated in the memory 60 in order to also check a read operation as toggle switch 62e. Located rend to perform the preroll.

the flip-flop 62 e is in its setting state, is / equals 4, whereby a read operation is selected

the end of the function of the return flow is identified by the AND circuit 62 j, the

table signalfT864 to the conditional jump line 35 signals 605 and 6Oi? generated,

transferred, which causes the control to a command If 7 equals 5, which causes a write operation

72 is output and the magnetic tape selection toggle is marked, the signals 60F and

circuit is reset. 60 W generated.

5. The Funktionstabellen- generated by the command 72 is 7 equal to 6, whereby a signal is rewinding FT872 checks the state of which is shown for the supply 40, the signals are 6OB and availability are 60RW of the magnetic tape provided for tilting testifies.

circuit 62 /. This flip-flop is located 62 / Umspulung
by an activated pulse 61Pl (step 2 B)

In its setting state, the AND circuit is activated. During rewinding, 62 / is not prepared after step 5 and therefore the function 45 preparation ^{commands function table signal table signal / 7} r872 cannot be transmitted. Generated in this FT 866. By this function table signal case, the next command is excluded from the AND circuit 60g is opened at the clock time t _x selected tape device provided for command sequence excluded and thus transfers the number 6 of the eleventh leads. However, was not the coil to 61Pl, b so sawn digit of the register RP-I in the memory 60, the flip-flop circuit 62/50 Rückstellzu- in place whereby the signals 6OB and 60 RW are generated, stand, and the generated from it Output signal 62 TTÄ At the same time, the function table signal opens the AND circuit 62 /, so that the FT 866 sends the function table signal FT 872 prepared by the signal 62 UA to the conditional AND circuit 6OA, whereby the selection signal jump line can be coupled and thereby the flip-flop circuit 60 / gives microcontroller to part of the program for a period of 0.15, is set in 55 seconds; at the end of this 0.15 microdem do the following steps. Seconds this toggle switch is

6. The function delay device 60 generated by command 76 / via the single pulse generator table signal FT 876 checks the magnetic tape between 60 A: reset. While the toggle switch is disabled toggle switch 62iZ to determine whether the 60 / is in the set state, the AND-selected tape devices are prepared as a result of power cut-off 60 circuits 60 m, 6On, 60 o, and 60p; is not available. If this is the case, since these AND circuits are then not switched on under the main interrupter current gate of this tape recorder, influenced by the selectively switched on operating signals, the toggle switch must open. If in the present case the austung62o "is in the setting state [see step selected tape device not in the first block position, 2B parts]; 60 B is opened and thus generates the selection signal toggle switch displayed. If the selected tape is 60 BP. This signal 60 BP is not available to all tape devices because it is already supplied, but is only available for the selected device.

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344

advises effective. As a result, the power gate 72 BG of the tape device in question is ignited, provided it has not already ignited. If the selected tape device is in the first block position, the flip-flops 61 // 'and 61W are in the setting state; in this case, the flip-flop circuit 61 * provided for the first block is set by the block signal 61FB due to the coupling of the function table signal FT 866 to the AND circuit 61 /. The AND circuit 60 p is blocked by the signal 61 FS and can therefore not respond to the signal 60S. The signal 60SF is therefore not generated.

At the cycle time t _t , the function table signal FT 866 determines whether the selected tape device is in the return position and the magnetic tape can return. The time period required for changing the blocking signals 72 RFIR and 12UBIR is longer than the time segment between the clock times J ₁ and t _A ', and this change is not brought about by the new selection _{signal generated at the clock time ^ 1.} At the cycle time t _t , the output signals 61F / and 615 / therefore still indicate the status of the selected device. In other words, these signals indicate whether the device was previously operated in forward or reverse direction. If the device is in the forward position , are the signals 61BIR and 61F72? at the AND circuit 72 m does not appear, so that this AND circuit cannot respond to the signal 60S. The AND circuit 62 η can therefore not transmit the function table signal FT 866 to the conditional jump line at the _{clock time i 4.} As will be explained, the program provides a 0.8 second delay at this point before the current sequence of operations continues, so that the clutch of the center drive wheel and the length of the belt loops can be adjusted according to the now required reverse operation. If, on the other hand, the tape recorder is already in the reverse position, the AND circuit 62 m is opened by the signal 60S and transmits the function table signal FT 866 to the conditional jump line, whereupon the program continues immediately with the next step.

In this next step, instruction 67 is started to generate function table signal FT 867. If the selected tape device is not in the first block position, then the signal 61 FBI is applied to the AND circuit 62 o, which, under the influence of the function table signal FT 867, couples a signal to the conditional jump line.

If the signal 61FFI is not present, then is the tape device in question in the first block position; in this case there is a delay of 1.8 seconds Provided in the program so that the leader tape prior to commencing a read or write operation can pass the head 73 β.

The AND circuit 6Or is opened by the signals 62 UA, 61 BIR and 60RW and the simultaneous coupling of the function table signal FT 867 , whereby the flip-flop 60 rw is set. The AND circuit 60 1 is opened by the output signal of this flip-flop circuit, provided that a first block signal 61FS1 is not present. This AND circuit therefore generates the rewinding signal 69RWP. The rewind current gate62i? H ^/ G of the selected tape device is triggered. Since the signal 60SF has already been generated, the return flow gate 72SG will also fire. In this state, the selected tape device is ready for a rewind operation. As is known, the magnetic tape of the tape device in question is brought back into the first block position by this rewinding.
By switching the toggle switch 60 rw

The AND circuits 60 κ and 6Ov have been prepared in their setting state. Assuming that the signal 60RWP was generated, the current gate 72 R WG is ignited and thus the contacts of the rewinding relay 72 rvvr 2 opened, whereby the signal

is 72 UBIR is switched off. The signal 72 UFIR is also not present. Therefore, the counter signals 72 UBIR and 72 UFIR are generated and coupled to the input of the AND circuit 60 u , whereby the connected to the output of this AND circuit

ao nen switching elements generate the pulses 60Fl and 60F. If the tape device had been in the first block position, the signal would be 61FS has been coupled to the AND circuit 6Ov, which then under the influence of the setting off

a5 output signal of the flip-flop 60 would have been opened and the generation of the pulses 60Fl and 60F would have caused. The pulses 60Fl and 6OF are thus generated on the basis of the setting of the flip-flop 6OrW, regardless of whether the pulse signal 6OjRHPF is generated or not. The trigger circuit 60 rw is reset by the pulse 60Fl and the memory 61a is cleared. In addition, the flip-flops 61 & and 61 k are reset by this pulse. If the memory 61 α is cleared, the selection signal 61 SXT for the switched-on tape device goes out. Another device in the group concerned can then be selected. For this purpose, the flip-flop 60 a is switched to its setting state by the pulse 60F, whereby the signal 60ZT ^{7 is} terminated. At the same time, the magnetic tape selection flip-flop 62 e is set, whereby a signal is coupled via the OR circuit 28 A -13 to the main test line.

If it was determined by the function table signal FT 872 in the fifth preparation step that the selected tape device is free, the program can continue with a write or read process instead of rewinding. For the sake of brevity, the operations and tests described above are only mentioned in the following description of the read and write sequences when they are necessary for an understanding of the description.

Spelling sequence

1. Check the status of the read-write control circuits

The function table signal FT861 generated by instruction 61 is coupled to AND circuit 646. The reset output signal of the flip-flop 64 a can be coupled to the other input of this AND circuit, which indicates that these control circuits are occupied. Due to the simultaneous coupling of these signals, the AND circuit 64 b generates the signal 64 PZ 3 AV, which is coupled to the conditional jump line by the AND circuit 62 b,

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346

to transfer control to another command sequence. Command 61 can also be omitted at the beginning of a write sequence as the read-write control circuits are usually free at this point in the program.

2. Filling the address register (Fig. 35) of the Magnetic tape synchronizer

The function table signal FT 874 generated by the command 74 causes the distributor 13 and the central processing system 14 to put the start address in the five least significant digits of the register RP-I , which in the present case represents the control word for this command sequence, into the memory address register 29-50 is stored in the manner as stated in the description of the distributor.

3. Relocation of magnetic tape control data under the influence of the function table signal FT 866 etc.

a) The function table signal FT 866 generated by command 66 occurs both in the read and write sequences and in rewinding operations. By this function table located in the eleventh signal, the digital position / -Clause from the register RP-I is re-stored in the memory b 60th In the present case, this number corresponds to the number 5, as a result of which the signals 60F and 60PF are generated.

b) The flip-flop 60 / is set by the function table signal FT 866 and reset via the delay device 60 / and the individual pulse generator 60 & after a delay of 0.15 milliseconds. While this toggle switch is in the setting state, the AND circuits 60 m and 60o are prepared and thus generate the write and forward signals 60 WP and 60FP, which control the selected tape device when the signals 60 W and 60F are switched on.

c) The pulse 6OF and the delayed pulse 6OF / are generated by the same pulse of the individual pulse generator 60 k , which switches the flip-flop 60 ζ to the reset state in order to terminate the selection signals. In the present case, the pulse of the individual pulse generator 60 k is diverted via the AND circuit 6Or w in order to generate the pulses 60Fl and 60F. The functions of the signal 60Fl have already been described. It should be noted that this pulse clears the memory 61a and terminates the selection signal 61SXT applied to the selected tape device.

d) The pulse 6OF also has special tasks to perform in the read or write sequences. This pulse is coupled to AND circuits 59 / and 59 g , but in the event of a write sequence only becomes effective at AND circuit 59 /, which is opened by signal 60 W. This AND circuit 59 / generates the signal 59 WPi ?, whereby the write drive toggle circuit 59 b is reset. This signal also fulfills the following tasks:

1. It causes via the OR circuit 65 and a pulse delay unit 65 b, the setting of the word counter 65 wx to 10, by the pulse RS 6553, at the same time also sets the word control member 63 α.

2. The signal 59 WPR also switches the flip-flop 67 a to the setting state, whereby the AND circuit 67 b is opened under the influence of the signals 66 TSS and 66 TON . The signal 66 TSS comes from the output AND circuit of the fourth stage of the clock generator 66c, which is advanced at the clock time t _7. The pulse 66 TSS changes the state of the binary counter 66 bc, whereby the ίο pulse 66 TON during two counting sequences of the

Binary counter 66 bc is generated once (once for every twelve short periods). If these two pulses on the setting of flip-flop 67a together for the first time, so the flip-flop 67 is a reset b via the AND circuit 67 and the flip-flop 67 set c, whereby the signal 6753 WST is generated.

e) By the pulse 66 TSS, which has set the Kippschalrung 67 c, the AND circuit 67 d is opened in conjunction with the signal 6753 WST , whereby the flip-flop 67 c is reset and the signal 6753 is generated, which indicates that the output memory has been cleared. (The signal 6753 WST was thus 24 microseconds.) The signal 6753 WERD the multivibrator is also set to 67 s, is / prepared whereby the AND circuit 67. The AND circuits 68 r and 68 χ are opened by the signal 6753 WST and the simultaneous coupling of the corresponding clock signals, so that the output buffers 68 d and 68 ν can be cleared and prepared for the write operation. From the output buffer memory 68 d z. B. read out a digit during the cycle times t ₀ , I ₁ when the signal TTO is switched on, while the next digit is _{read out during the cycle times i 4} , t _s and when the signal TTO is switched on; in this way two digits are read out in each short period. In a similar way, one digit is read out from the buffer memory 68 ν during the cycle times ίο, t _% when the signal TTO is switched on, and the other digit is read out during the cycle times t ₆ , t ₇ also when the signal TTO is switched on. A total of twelve AND circuits are provided for each of the AND circuits 68 r, 685, 68 χ and 68 y ; likewise twelve AND circuits are provided for the AND circuits 68 dd and 68 vd in order to transmit the signals 5 3 RV (1 to 12) and S 3 RD (1 to 12) to the twelve separate read lines of the output buffer memory 68 ν or 68 d to be coupled. In this way, both output buffers are flushed in the five short periods tt ₀ to tt _s .

e) The word toggle circuit 63 α is reset by the signal 67 S 3 WERD. Simultaneously, this signal sets the word interrogation toggle 63 & to provide an interrogation signal 6353 RF to the priority circuits 29-94, indicating that access to memory is requested for the removal of the first word.

f) The word received from the memory by way of the priority is d 68 and the magnetic tape synchronizer ν 60 in the form of information signals PMR (1 to 60) supplied to the output buffers 68th These output buffers correspond to the buffer memories 40-20 and 40-18 shown in FIG. 40 and are shown here in FIG. 68 only the

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347

348

For clarity repeated. The word toggle

63 α is now in its reset state, so that the signal 53 WCV is generated. Like F i g. 34 shows, this leads to the generation of the signal 53 WV at the AND circuit 34-27. The first word can therefore be stored in the output buffer memory 68ν. As has already been described elsewhere, the AND circuit 34-15 then outputs the signal 5 3 /? Fi? generated, whereby the flip-flop 63 b is reset.

g) A delayed memory free signal S3 BA is coupled from the AND circuit 34-42 to the AND circuit 67 /. Since this AND circuit is opened at the same time by the signal generated by the flip-flop 67 e , it generates the signal 67 S3RSWD at the clock time i ₂ or t _t. With this signal, the flip-flop circuit 67e , which has fulfilled its task, is now reset. This signal also sets the flip-flop 67 g in order to generate a ready signal 6753 WSUC, as a result of which the AND circuit 67 h is partially opened.

gO The signal 67 5 3 RSWD also sets the memory interrogation toggle circuit 63 b again; Similarly, the word flip-flop 63 is a set and the signal generated 53 WCD, so that the second from the memory taken word under the influence of the signal produced by the AND gate 34-24 signal 53 WD which the write control gates of the odd buffer memory 40-20 controls, can be stored in the output buffer memory 68 d.

h) In the meantime, the function table signal FT 866 has checked in which direction the selected tape recorder is set, this check being carried out in the present case with the aid of the AND circuit 62 p. This signal is fed to the central processing system via the conditional jump line, so that this processing system can provide the mentioned delay of 0.8 seconds in the program if the direction of travel has to be switched. In the present case, the signal 60F indicates that the tape recorder must be set to advance.

i) In the meantime, the function table signal FT 866 has also opened the AND circuit 64 c, so that the tenth (K) digit 1 in the register RP-I is sent to the setting input of the flip-flop circuit

64 d can be switched on, whereby this flip-flop is switched to the setting state and generates a signal 64 NUM , which indicates that a numerical code is being used.

Ϊ) The function table signal FJ 866 is also connected to the AND circuit 66 α, so that it transfers the eleventh (/) digit 5, which is in the register RP-I , to the setting input of the flip-flop 66 b , whereby the two signals 66 5 3 P 200 and 66 S 3 WBG are generated. The 6653P200 signal controls the pulse width so that 200 pulses per inch are recorded on the tape.

i ") The function table signal FT 866 is also used to open the AND circuit 66 c, so that the ninth (L) digit 0 from the register RP-I can be coupled to the setting input of the flip-flop 66 d . This flip-flop then generates the signal 66 5 3 BBO, which controls the space between the data blocks during the write process, in this case this space is 1 inch.

j) The signal 6653 WBG is coupled to the AND circuit 6Sd via the OR circuit 65c. At the same time, the signal 64NUM and the setting signal 6553 RS of the word counter are applied to this AND circuit. The AND circuit 65 d is opened by the simultaneous coupling of these three signals and thus sets the digit counter 65 de to ίο 12. Now the next step can be carried out.

4 a) Set the selected one in motion
Magnetic tape

The AND circuit 59 g is opened by the function table signal FT867 generated by the command 67 and the signal 62 UA [preparation step 2, 2 B, b)]. Thereby, the flip-flop is switched Bandeinschalt 59 e [preparation step 2, a)] in the set state and generates the signal 59535Γ6 which the AND circuits 59h, 59i and 59 is / fed. Of these AND circuits, however, only the AND circuit 59 is opened h in the present operation sequence. This AND circuit has already been opened by the write signal 72UWF generated by the tape recorder. The tape device itself was set to the write position by the selection and switch-on signals 61 SXT, 60WP and 6FP. This AND circuit is also prepared by the signal from the flip-flop 59 b [sub-step 3, d)]. In addition, the reset output signal 59 WCDC of the flip-flop circuit 59 k is also applied to this AND circuit. In this way, the AND circuit 59 h is completely opened with the simultaneous coupling of the signal 5953 Γ6 and generates the signal 59 WSTU. The flip-flop 59 k is set by this signal and thus generates the mean drive signal 59 WCDG, which - as already described above - initiates the tape feed in the tape device in the write position.

4 b) The signal 59 WSTU is also connected to the input of the AND circuit 67 / together with the signal 66 5 3 BBO. This AND circuit then generates a signal that is coupled via the restartable delay circuit 67 / and the individual pulse generator 61k to the setting input of the flip-flop 67 m , which then sends the signal 6753WTi? generated. The restartable delay circuit 67 / delays the signal by 8.7 microseconds, which means that the start of the write process is delayed until 1 inch of the tape length has passed the read-write position.

5 a) Activation of the read-write operation

The function table signal FT 868 generated by the command 68 is coupled to the AND circuit 64 e. This AND circuit is opened at the clock time t _Q by a corresponding clock signal and thereupon generates the signal 64 S 3 RST, which sets the flip-flop 64 / provided for initiating the read-write operation. This flip-flop then generates the signal 64 RWST.

In addition, the flip-flop circuit 64 a is reset by the signal of the AND circuit 64 e and thus indicates that the read-write circuits are occupied.

349

350

Due to the simultaneous coupling of the signals 64 RWST, 6753 WSUC [paragraph 3g)] and 67 S3 WTR [paragraph 4 b)], the AND circuit 67 Λ is opened and generates the signal 67S3SUCR. This signal sets the read-to-write toggle switch 67 η and resets the write-lock toggle switch 67 ο. In addition, the flip-flop 67 g is reset by the same signal. In addition, this signal also resets flip-flops 67m and 64 /. If the flip-flop 67 η is in its setting state and if the flip-flop 67 o is in its reset state, the AND circuit 67p is opened and can generate the signal 67S3 WOP.

5 b) write operation

The AND circuit 66 e is opened by the simultaneous coupling of the signals 6753 WOP, 66S3P200, 66T57 and 66TOiV. The two last-mentioned signals 66 TS7 and 66 TON are derived from the clock generator 66 c and from the binary counter 66 bc . These pulses are applied once every twelve short periods or every 48 microseconds to the AND circuit 66 e , whereupon the latter generates an output signal which is set by the toggle circuit 66 / provided for the digit writing cycle; this flip-flop 66 / then remains set for a short period since it is reset by the next clock pulse t7. As long as the signal 67S3 WOP is present, this process is repeated, with the signal 66 S 3 TWC being generated.

For the recording of data on the selected magnetic tape, all the preconditions are now met. The output signal S 3 WCD of the word control multivibrator (FIG. 63) is applied to the AND circuit 68 vd of the output buffer memory 68 ν. The output signal 65S3DC-12 of the digit counter is applied to both AND circuits 68 vd and 68 dd . The signal 66S 3 TWC is generated once every twelve short periods and has a duration of one short period. During the cycle times t ₂ and t _{3 of} the short period assigned to it, the signal 6653 TWC opens the AND circuit 68a, which in turn opens the AND circuit vd that has already been set so that the five information units of a digit can be read from the buffer memory 68. These information units are registered in the flip-flops 68 / assigned to them and fed to a code conversion device 68 ί via a pulse delay device 68 d. After this conversion device has encrypted the data in accordance with the magnetic tape code, these information units are coupled to the AND circuits 68 & at the clock time t ₅ by the signal 66 S 3 TW 6 of the conversion device. This AND circuit is opened by the signal 6653 TWC and by the clock signal i7, so that the information units can be fed to the band information flip-flops 68 ti. The five signals 6853 WBB are coupled from these information flip-flops 68 ti via amplifiers to the write line of the synchronization device 53. At the same time, by coupling the signal 6653 TWC and the clock signal ί 7 to the AND circuit 68 sb, a synchronization pulse is generated, which is fed to the setting input of the flip-flop 68 SB , whereupon this flip-flop circuit sends the synchronization signal 6853 WB to the write line via an amplifier coupled. The flip-flops 68 /, in which the information units of the digits are registered, are reset by the clock pulses t4, t6, t0 or ti . The flip-flops 68 if and 6% sb are reset by the pulse 66 TS 8 generated by the clock generator 66 c at the end of that short period in which the signal 6653 TWC is applied.

ίο The information bits 6853 WBB and the synchronization bit 6853 WB are transmitted via the switched contacts 72 WRP and the front contacts 72 WRC of the excited write relay 72 wr to the read / write heads of the selected tape device and from there via the rear contacts 72RRC of the read relay 72rr connected to a zero voltage terminal. In this way, the read / write heads are energized and magnetically record the information units on the tape.

The pulse length depends on the belt speed and on the number of microseconds during which the flip-flop 68 is set ti . Since the signal 6653 TWC is generated by the setting of the toggle 66 f provided for the digit writing cycle, which in turn is set both by the signal 66TOiV and by the signal 66Γ57, the toggle 68 ti is set at the next clock time i ₇ and by the signal 66 TS 8 reset. This flip-flop thus provides a pulse that is coupled to the write line for a period of 24 microseconds. The 6653TiFC signal then only reappears with the next 66TOiV and 66 TS 7 signals, so that there is a gap of 24 microseconds before the next pulse is recorded. In the present case, this results in a pulse length of approximately V200 inches.

Digit counter 65DC

The signal 6653TiFC, which causes the reading out of the digits, the AND circuit 65 opens e during the clock time t ₃ of this signal associated short period, whereby a signal to the OR circuit 65 is / coupled, through which a further switching pulse 65 S 3 CD is produced. This incremental pulse is applied to AND circuits 65 g, 65 h and 65 /. The signal 6653 is transmitted from the WBG OR circuit 65c and disables the AND circuits 65 and 65 h /. To open the AND circuit 65 ζ, the signal 65 5 3 DCl of the digit counter is required, but this is not generated in this case because the counter was initially set to 12. The only AND circuit that can be opened by the incremental pulse is the AND circuit 65 g. The output signal of this AND circuit is fed in a known manner to the digit counter in order to switch it down from the most significant digit to the least significant digit. This means that eleven incremental pulses are required to switch the counter down from 12 to 1. The counter is designed in such a way that it is reset to its starting position 12 by the twelfth step pulse. If the eleventh digit is recorded, the digit counter is switched to 1 and generates the output signal 65 5 3 DCl. This signal is coupled to the AND circuit 65 /, which is also provided by the signal 64 NUM and the signal of the AND

351

352

Circuit 65 e is set. The counter is reset to its starting position 12 by the next step pulse, which is generated during the recording of the twelfth or last digit of a word, and at the same time opens the prepared flip-flop 65 i, which in turn generates the end-of-word signal 65 S 3 WEND.

Word counter

The word counter can also be reset. This counter is incremented by one step in ascending order by the signal S3 BA transmitted via the AND circuit 65 k. The signal S3BA is generated by the AND circuit 34-42 shown in FIG. 34 and is present when the synchronization device has preferred access to the memory and the memory-free signal MiVS was generated by activating the memory, which indicates that the control of the memory was successful. The signal S3BA is therefore always generated when a word is transferred from the main memory to the output buffer memory. Before the word counter returns to its initial state 10, it counts down ten words. The word counter is normally set to 10 by the 59 WPR signal prior to the start of the write operation; however, it can also be set to 10 using the 66S3WCAV signal. This signal is generated by the signal 66 WEI , which indicates the end of a write operation and thus resets the flip-flop 666.

Alternating operation of the word control flip-flop 63 α and repetitive operation of the word query flip-flop 63 ft

If the signal 6553 WX10 is not present at the AND circuit 63 p and this AND circuit is not blocked by the signal 64 5 3 CT , the AND circuit 63 c is activated by the simultaneous coupling of the signal 6653 WBC and the word end signal 65 S 3 WEND opens and thus sets the flip-flop 63 b so that it can query a new word from the memory. Each next word is alternately d and 68 stored ν in the output buffer memory 68, wherein this storage is controlled flip-flop control word from the state of. If this word control multivibrator is in its setting state, its output signal 6353 WCD is coupled to its reset input via the AND circuit 63d. However, this word control flip-flop is in the reset state, so its output 63S3WV is turned on via the AND circuit 63 e at its set input to set it again. In this way, the word control flip-flop is switched by the generation of the word end signal, which is coupled to the AND circuit 63 d and the AND circuit 63 e, so that the odd and even output buffer memory is used alternately.

Since the end signal S 3 WEND is only generated when the digit counter has counted a word, the two output buffers must be refilled by word query signals that are generated on the basis of other signals. The signal 67S 3 WERD coupled to the OR circuit 63 r provides the signal which carries out the first word query at the beginning of a write process. The signal 67 S 3 RB WD , on the other hand, generates the signal by which the second word is queried.

As FIG. 67 shows, the signal 67 S3WERD is generated by the AND circuit 67 d when the clock signal 66TSS and the setting output signal of the toggle circuit 67 c provided for clearing the output buffer memory are simultaneously applied to this AND circuit. The signal

ίο 67S3 WERD is therefore generated after the output buffer memory has been cleared. By this signal, the flip-flop 67 is set and e, thereby indicating that the first word has been queried. The setting output signal of this flip-flop opens the AND circuit 67 / if the signal S3BA generated by the AND circuit 34-42 is present at the same time at this AND circuit, which indicates that the first word has been taken from the main memory and into the relevant one Output buffer memory on

ao has been saved. Under the influence of these signals, the AND circuit 67 / generates the output signal 67 S3RSWD.

End of writing signals

If the writing process is to be interrupted after the current ten-word series, a signal 66 WE1 is generated by the delay device 66 g (1.5 microseconds). The AND circuit 66 / τ connected upstream of this delay device is opened when all three signals 64S3TLC0, 67S3W0P and 65S3 WEND are present at its inputs. The signal 67S3 WOP was generated during the read-write switch-on step 4 a and remains switched on until the write end signal is generated, provided it is not suppressed. The signal 65 S 3 WEND is generated at the end of a word. The signal 64 S 3 TLCO is generated by the setting of the flip-flop 64 k at the end of the ninth word, provided that the AND circuit 64 m is not blocked by the signal 64 S 3 CT. This signal 64 S 3 CT is generated by the setting output of the flip-flop 64 c / when the writing process is to be continued on the basis of a command 70.

The signal is applied to the AND circuit 64 m

65 S 3 WX 10 when the word counter 65 WX was initially set to 10 or when this counter was switched back to its starting position 65S3WX10 by the step signal S3BA by a complete ten-word cycle, indicating that ten words have been stored in the output buffer memory . Since the signal 65S3 WEND is generated at the end of each counting cycle of the digit counter and since the signal 67S3 WOP is only present after the word counter has advanced, the AND circuit 64 m can only be opened after the end of the ninth word. The flip-flop 64 c / must then be set before the end of the ninth word if the setting of the flip-flop 64 is to be prevented by the locking signal 64 S 3 CT; this blocking ensures that the write end signal

66 WEI is not generated. If all three signals are present at AND circuit 66 h , this causes delay circuit 66 g to generate signals 66 SBWHF and 66 WEI. The flip-flop circuit 67 o is set by the signal 66 S 3 WH and thus the signal 67S3 WOjP is ended.

353

354

The flip-flops 66 & and 66 d are reset by the signal 66 WEI and thus terminate the signals 6653P200, WBG and BBO. The flip-flop 67 η is also reset by the end signal; Furthermore, the flip-flop 64 d is also reset and thus terminates the signal 64 NUM. Furthermore, the flip-flop circuit 59 k is reset by the end signal 66 S 3 WEI in order to terminate the middle drive signal 59 WCDG, so that the tape feed is switched off. Via the delay circuit 59 m, the individual pulse generator 59 n, the delay circuit 59 o and the individual pulse generator 59/7, the end signal also generates the additional end pulse SO WE 2, through which the flip-flop 64 a is set and thus indicates that the circuits are free. This additional end pulse also energizes the relay 59 r via the amplifier 59 q. This closes the contacts A of this relay and generates the write disable signal 59 WC, whereby the write power gate 72 WG in the selected tape device is extinguished.

6. After the function table signal FT 868 has fulfilled its functions in step 5, a ten word check 99-2 is carried out.

7 Ten Word Examination

This check is carried out at the beginning of each new ten-word group and at the end of the writing process. The switch-on toggle circuit 64 was set by the function table signal FT 868 generated in step 5 and generated the signal 64 S 3 RST in the process. The trigger circuit 63 / was set by this signal and generated the signal 63 S 3 TENS, whereby the AND circuit 63 g was prepared. When the first digit is recorded, the AND circuit 63 g is opened by the step pulse 65 S 3 CD of the digit counter and thus sets the flip-flop 63 / back, while the flip-flop 63 h is set and generates the signal 63 S 3 CH. This signal is coupled to the main test line 28 / 4-13 and at the same time opens the AND circuit 63 / when the function table signal FT 869 generated by the command 69 is present at its other input. Due to the opening of this AND circuit is reset flip-flop 63 h and generates a signal is transmitted, the conditional jump to the line (28 Fig.). In addition, the flip-flop 63 / is set via the AND circuit 63 χ at the end of every ninth word of a group consisting of ten words. This AND circuit is opened by the simultaneous coupling of the signals 6SS3WEND, 67S3WOP and the signal 65 S 3 WX10 of the word counter, which indicates the tenth word. In this way, the conditions for checking by the function table signal FT 869 have been established again.

As will be described elsewhere, the initiation of a command 71 generates the signal 6653 FH ^ F. The signal 6653 VWF also provides the circuit 63 h for a to be performed by the function table FT signal 869 test. The additional write end signal 59S3WE2 is also coupled via the AND circuit 63 / and the pulse delay device 63 k to the flip-flop 63 h in order to set it for a later test by the function table signal FT 869.

Writing continues with no space between the blocks

If the writing process is to be continued without interruption after the current series of words has been recorded, the function table signal FT 870 is generated. With this signal, the flip-flop 64 c / is set at the time t ₀ via the AND circuit 64 ″ and thereby generates the

ίο Signal 6453C7 \ This signal is coupled as a blocking signal to the AND circuit 64 m, which prevents the generation of the write end signal 66 WEI if this blocking signal is coupled before the end of the ninth word is recorded.

In this case, additional words are taken out from the main memory of the processing system and the output buffers 68 d ν supplied and 68th The AND circuit 63 p, which is otherwise opened by the signal 6553JFZ10, is also blocked by the signal 64 S 3 CT. This signal is present when the tenth word has been stored in the output buffer memory. In this way, the AND circuit 63 p blocks the AND circuit

63 c and thus only prevents the removal of another word from the main memory if the signal 64 5 3 CT is not present. The toggle switch

64 c / is reset at the beginning of a next series of ten words by the signals 63 S 3 TENS and 6653 WBG via the AND circuit 64p and by the step pulse 65 5 3 CD of the digit counter.

Continuation of the writing process, but with

Space between the present and the

next phrase

If this command, 71, is given before the tenth word of a group is recorded, the writing sequence continues, but a space is provided between the block just recorded and the next block. This command represents an alternative command to command 70 and generates the function table signal Fr 871, which is coupled to the AND circuit 64 g, while the function table signal FT 870 is connected to the flip-flop circuit 64 c /. The AND circuit 64 g is opened in this way at the clock time t ₀ and thereby sets the flip-flop circuit 64 h , whereby it generates the signal 64 5 3 CTB. If the signal 66S3VWF or 7053ClO is applied to the OR circuit 64 y , the toggle circuit 64 h is reset. As previously mentioned, the flip-flop 64 c / prevents an end-of-write signal 66 WEI from being generated. This will continue to fill the output buffers with words taken from memory. In this case , the word counter is set to 65 S 3 WXl after the first word of the next group of ten words has been stored in an output buffer memory. In this way, the signal 6553 WEND indicates the end of the tenth word and causes a corresponding space between the blocks not to be written. For this purpose, the signals 6453 CTB, 65S3 WX1, 67S3 WOP, 65S3 WEND and 6653ÄB0 are coupled to the AND circuit 66 gc. The AND circuit 66 gc then generates the signal 66S 3 VWF. This signal sets the flip-flop 66 / for 10 microseconds and first »538/373

355 356

thereby generates the signal 66S3BBW. At the end the 69S3 sheets. In both cases, the signal 6953 RBG this signal is generated by the flip-flop 66 /. The signal S3 RBG is reset together with the pulse 66 VWR. This pulse becomes signal 65 S 3 WEND which, at the end of the input, is generated by delay circuit 66 / due to storage of the first word in the input buffer output signal of AND circuit 66 gc . 5 memory is generated, the write lock circuit 63 y is coupled to the input of the AND by the signal 6653 VWF. By the output flip-flop 67 ο set and thus terminates the signal of this AND circuit is then the word signal 67 5 3 W 0 P, which is one of the pass signals query flip-flop 63 b via the OR circuit for reading out the digits Signal 66 S 3 TWC 63 r set. That represents from this toggle switch. At the end of the gap, the signal 63 5 3 RF generated thereupon is sent to the distributor signal 66 VWR of the delay circuit 66 /, and indicates that access to the memory which the flip-flop 66 / resets is also required due to the removal of the first word . Toggle circuit 67 o back and caused at the same time By the delayed pulse 6OP in the renewed coupling of the signal 6753 WOP, so reading sequence, the AND circuit 59 g opened, since the writing process begins again. The length 15 whose input simultaneously receives the signal 6Oi? is present. of the gap signal is carried by the As a result, the read intermediate lock flip-flop-flop 66 / deemed delay loading 59 c PREV ckgestellt, whereby its output is true, and produces in this case a 59 RCDV the AND circuits 59 / and 59; front gap of 1 inch. prepares.

The signal 66 S 3 BBFP is generated during an intermediate 20 Then the function table signal is between space interval generated to the OR circuit 70 a FT 867 , whereby the switch-on toggle switch is coupled to generate a signal 70 5 3 5BB tion 59 e is set and thus Prepare the signal and at the same time the AND circuit 70 a 59535Γ6 for the AND circuits 59 h, 59 / and, which are then generated by the function table signal 59 /. This time only one of the two AND- FT 873 is opened. If the write operation is opened in 25 circuits 59 / and 59 /, whereby the gap phase takes place, the read toggle circuit rc is set and the read signal 70 PZ 3 SSB is generated to generate a conditional signal 59 RCDG of the middle drive in order to jump via the OR circuit 62 b so that the magnetic tape of the selected tape starting device is set in motion. Before the output read operation ³ ° ^s ig ^na l 59 RCDG of flip-flop 59 rc takes effect

becomes, the signal is 59 5 3 ST 6 next to the already

A series of commands, which in the reading sequence switched on signal 64 S 3 / 1P "to the AND switch

are carried out correspond to the commands of the device 65 m coupled, the output signal of

Spelling sequence. To avoid unnecessary repetition of the OR circuit 65 a is transmitted so that

These commands are therefore fetched in the following word counter as in the previous case

the description is omitted. the signal 65 5 3 RS is set to 10. This

The function table signal FT 862 checks the signal is together with the signal 64 NUM and

AND circuit 69 a. Is the read line of the Ma- the signal of the OR circuit 65c, provided that the

gnetband synchronization device occupied, read signal 69 53 Fl is applied to the digit counter

this AND circuit not prepared. If, on the other hand, 40 is set to 12, the AND circuit 65 d

the read line free, the AND circuit 69 a is coupled. Should the reading pass in the reverse direction

are opened and carried out by this function table signal, the OR switch generates

transmits the signal 69S3BU to the AND circuit 65c tung no signal; the AND circuit 65ü * becomes

626. In this case the current Opera- is not opened by the signal 65 S 3 RS. Instead of

The sequence of operations is interrupted and a jump takes place. 45 this signal causes the opening of the in

If the signal 69S3BU is sent to the AND circuit at this moment, the AND circuit is not locked

62 b not coupled because the flip-flops 69 b 65 br, so that the counter can be set to 1

and 59c are reset, the next one can. If the output signal of the OR switch

Command executed. A signal 6953 AVB, which device 65c is not on, also becomes the AND circuit

indicates that the line is free, is also generated, 50 65 g is not opened and therefore no signal can be generated

when the two flip-flops 69 ft and 69 c generate , when the step pulses 65 generate S 3 CD

are reset. will. Instead, the AND circuit 65 Λ remains

The function table signal FT 866 has the same unlocked and is activated by each step pulse as before; in this case the contains opens, so that the digit counter is incremented in the ascending eleventh (Z) digit from the register RP-I, however, according to the tendency.
neither the 3 (reading in the forward direction) nor the By resetting the intermediate reading block digit 4 (reading in the reverse direction). Accordingly, the flip-flop 59 c was the signal 59 RCDV corresponding to the signals 6Oi? and 60.RP activated; characterized the blocking of the AND neither together with the signal 6of and the circuit 69 has been lifted d. This AND circuit signal 60FP or with the signals 6OB and 60BP 60 69 d is therefore opened when the pass signal is generated. 64S3RWST due to the function table signal

FT 868 is applied by the function table signal FT 866 and if at the same time the control signal either the toggle circuit 69 b or 69 c is switched from the toggle switch setting state to its 59 RCDC of the middle drive, depending on whether the device 59 rc is generated. Readiness to read is indicated by the output signal register RP-I located / digit of a "3" or "4" 65 of this AND circuit 59 d . B is adjusted 69, the flip-flop, flip-flop 69 / set and generates the signal so it generates the signal 6953F1; is the tilting 6953i? 0P. This signal 69S3R0P prepares the circuit 69 c set, so this generates the signal AND circuit 69 / before, at each during the

357 358

Reading scanned characters to generate a signal. by the output signal for the second word, the setting signal for the flip-flop 6953 RRS 63S3 WCV, for the third word of the set-off 69 e also is so effective to the OR circuit 71g Toggle output signal. The output signals are coupled to reset flip-flops 71/716 6353 WCF and WCD of the word control flip-flop. 5 are the AND circuits 71 and 71Jr vr to-

In the selected tape device, the reads have been guided and at the same time energized to the AND circuit relays 72RR , to a transmission 34-18 and 34-16 coupled. The first mentioned way for reading out the information signals to AND circuits, each of which is made up of twelve AND circuits. This transmission path extends from lines that also receive the respective earth via the switched contacts C of the read io output signals of the various stages of the digit relay 72RR, the read / write head in the head counter. In this way, the AND circuit 73 e are prepared via the rear contacts C of the gene 71 dr and 71 vr and opened by the clock relay 72WR and the switched contacts ρ signal 6953 TRC at the clock times t ₂ , t _z , des Read relay RR. If the individual lines of characters recorded on tape are thereby opened on the read / write 15 71 vv and TLdd, so that the information heads are led past, units of the one word are entered digit by digit on the read line Information signals 73 TUI and a synchronizing buffer memory 71 ν and the digits of the next signal 73 TUS generated. The information signals advertising the word in the buffer memory 71 d alternately unities via the amplifier 71a to the setting inputs can be stored. As was described in connection with the gears of their associated flip-flops 71 b 20 the distributor, these are turned on while the synchronization pulse is then sent to the amplifier 71 d to the individual pulse generator 71 e through the pulses 53 RV and S 3 RD of the AND is switched on and thereby generates the signal 715 3 PRPR circuits 34-22 and 34-20 in the form of 60 par, which is output to the flip-flop 71 / connected information units SW1 to 5PF 60. This flip-flop then generates the 25 read.

Signal 715355 to the AND circuit 69 / an- The input buffers 71 ν and 71 d (Fig. 71)

is coupled, which is now prepared by the signal corresponding to the illustrated in detail in Fig. 39 5 3 R OP . This AND circuit th buffers 39-14 and 39-16, respectively. At this point it should be mentioned by the clock pulses il and 66ttO as well as the fact that the flip-flops, in which the information pulses and the synchronizer 66 c are opened by the clock pulses tt2 or U 4 of the clock generator 30. The three last-mentioned signals were sierimpuls, via the AND circuit 71 m appear to be reset one after the other at intervals of to the cycle times t ₂ and t ₆ after evaluating these a short period and have a duration of one signals.

Short period. At the clock time t _{x of} the period in which the signal 6953 TRC is switched on, the

which the signals 66ίίΟ, 66ίί2 and 66 «4 are generated 35 AND circuit 65n at the clock times t ₃ and t ₇ , therefore the AND circuit 69 / opens and generates a step pulse for that of the synchronizing pulse that is switched on 715355 digit counter. If the reading process is opened in forward and the toggle circuit 69 g is set. This flip-flop then generates the signal the AND circuit 65 g is connected to the counter, 69S3TRC, through which individual parts of the read 40 are timed, as in the case of the write operation. These operations - in a downward trend - will be described below. is tet. Will be reading in reverse direction

By the signal 6953 TRC those to be made, so the digit counter is opened step-by AND circuits 71c, the supplied h by the input signal via the AND circuit 65, 71 wostellsignale the flip-flops b prepared 45 by the counter in ascending Tendency to continue. In this way the information is switched. When reading in the reverse direction signals via the pulse delay means 71 h, the Wortendsignal λ of the AND circuit 65 / a code conversion means 71: supplied. generated instead of the AND circuit 65 i. This converting device converts the information units encoded in the output signal 65 5 3 DC 12 of the eleventh digit band code in 50, the AND circuit 65 / is prepared so that it is opened in accordance with the buffer memory code at the next step pulse and that and transmits these information signals an end-of-word signal is generated while the counter is equal to the cycle times t ₃ or t ₇ under the influence of the Si- timely reset to its initial state 1 signals 64 NUM and 69 S 3 TRC open AND switch, which indicates that the twelfth Digit tung71 / to a pulse delay device 71 k. 55 has been read out.

The read end signal 70 REI is generated when the

Input AND circuits 71 and the signal vv 6453 CTB input buffer memory 71 d 71dd fed under the influence of an instruction and 71 ν 71st is not generated and therefore also not applied to the These groups of AND circuits are connected to AND circuit 70 &. During reading in alternating by the word control flip-flop 63 a 60 forward direction, the AND circuit 70 c is opened. This word control flip-flop 63 α was prepared by the signals 64 NUM and 69 53 Fl initially by the signal 65 5 3 RS in its input and generates an output signal, if switched to its setting state, as the word counter on 10 gang also the signals at the same time 6553 WXlO, was discontinued. The output signal 63 5 3 WCD 65 5 3 DC 12 and 63 S 3 TENS are present. As with the case, the reading out of the first word has the effect. Because the signals appear after reading in the forward direction, the word control flip-flop is switched over at every 6553 WX10 and 65 5 3 DC 12 at the same time at the end of the word end signal 65S3 WEND as long as each of the ten words read out alternately as the signal 69 5 3 RBG is present. Standing group.

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360

The flip-flop 63 / generates the signal 63 S3 TEN'S when it is set by the AND circuit 63 η . This AND circuit is opened by the signals 69S3R0P, 6SS3WX9 and 65S3 WEND , which, however, are only present together when the tenth word has been stored in an input buffer memory. The signal 65 5 3 DC 12 present at the AND circuit 70 c is generated when the digit counter 65 de has been advanced by the same signal 6553 CD which generates the signal 65S3WEND coupled to the AND circuit 63 ″. In this way, the AND circuit 70c is opened only when the last digit of the tenth word has been stored in an input buffer memory and when access to the memory has been granted because of the last word of the group consisting of ten words; this access is indicated by the word counter advancing to 6553 WX10 .

If a read operation is performed in the reverse direction, the AND circuit 70 by the signals e Bl 6953, 6553DcI, 6553 WXlO and

Open 63 TENS S3 and generates via the AND circuit 70 b, and the delay device D1 TUREL the end signal, if the AND circuit 706 is not blocked by the signal 64 5 3 CTB.

The flip-flops 64 d are reset by the signal 10 SRI. This will get the signal

64 NUM switched off by those AND circuits that require this signal. The signal 70 REI also resets the flip-flop 69 e , whereby the signal 69 5 3 R OP is terminated. At the same time, the flip-flop 59 RC is reset and thus terminates the signal 59 RCDG. As a result, the middle drive wheel comes to a standstill, since the AND circuit 73 m is blocked and the middle drive toggle switch 73 & is reset. In addition, the end signal 70 .REl generates the signal 59ÄE2 via a restartable delay circuit 59 s (6 milliseconds) and a single pulse generator 59 Λ The signal S9RE2 also sends the signal 59RE3 via another restartable delay circuit 59 m (6 milliseconds) and a single pulse generator 59 ν generated. In addition, the relay 59 or via the delay circuit 59 m and the amplifier 59 w is excited by the signal 59 RE 2. By energizing the relay 59 *, the contacts A of this relay close and generate the signal 59RC, which clears the power gate 72 AG and de-energizes the relay 72 RR and thus switches off the signal 72 URB or 12URF.

The ten-word flip-flop circuit 63 A is set by the signal 59 RE 3 either via the AND circuit 63 r at a time other than the clock time t _i or via the AND circuit 63 / and the delay device 63 k . The signal 7053C10 is also present at the input of the OR circuit 63 s. This signal is generated on the basis of the transmission of the signal 59 RE 3 via the delay device 70 £ and on the basis of the signals from the AND circuits 70c or 70e, which indicate the end of the ten words. This signal, along with signals 7053 PRE and 64 5 3 CTB, is connected to AND circuit 7Or, the output of which indicates that the read operation should be continued after the inter-block space.

The flip-flops 696 and 69c are also reset by the signal 59 RE 3 and thus the signal 69 5 3ABG is switched off.

The flip-flop circuit 70 h is set by the signal 7053C10 and remains in this state for 5 milliseconds until it is reset by the signal 70 5 3 i? / B. This signal 70 53 RIB is generated by the restartable delay circuit 70 / (5 milliseconds). The setting signal 7053 C10 can be generated either by a command 71, which generates the signal 64 5 3 CTB , or by the read end signal 59 RE3 . In this way, the flip-flop 70A is set at the end of a block that has been read out. Since the signal 66 5 3 5BZW is generated at the end of a written block, the AND circuit 70 aa is opened by the function table signal FT 873 and generates the signal 70 PZ 355 B at the end of a block, regardless of whether it is a read - or write operation. This signal 70 PZ 355 B causes a jump to be carried out via the OR circuit 62 b.

The signal 70 5 3 i? / B also effects the resetting of the information flip-flop 70 b via the OR circuit 71g.

In the description and the accompanying drawings it has been assumed that the magnetic tape recorders are controlled only by a tape synchronizer 53. However, several such synchronization devices can be provided, with the individual groups of tape devices each having their own synchronization device. These synchronizers are controlled by the central processing plant. To select a specific synchronization device, this control can be designed in such a way that an input for a signal PSTn is provided at the gate circuits of the synchronization device to which a function table signal is applied, where η represents the number of the synchronization device concerned. In this case, this signal would represent the selection signal for the synchronization device, which is generated by decoding the 5-digit contained in the Λ register 10,4-28.

Patent claims:

1. Computing system with a memory with several addressable word storage locations, in which at least one computer is connected to the memory for the purpose of exchanging information and several different input and output devices are provided which can exchange information with the memory, characterized in that one of the individual Computers (1-10, 1-11) independent monitoring control center (1-14) for the various input and output devices (1-12) provides specific instructions for the exchange of information with the memory and to the memory (1-15) directly and to a computer (1-11) is connected via a signaling device (1-UA) , which can be set by the computer after it has transferred a keyword into a given memory location and which is from time to time by the control center (1-14) is checked that for an

Claims (8)

361 362 state of the signaling device takes effect to an instruction and word data from the To obtain memory as it is housed there in successive addresses by the computer became. 2. Rcchenanlage according to claim 1, characterized in that the monitoring control center a second arithmetic unit (FIG. 10, 10B). 3. Computing system according to claim 2, characterized in that the second arithmetic unit (Fig. 10, 10B ) responds to the setting state of the signal device (1-11 A) in order to derive and process instructions from the address sequence in the memory. 4. Computing system according to claim 2, in which the keyword is the start and end addresses indicates a plurality of instructions arranged one behind the other in the memory, thereby characterized in that the second arithmetic unit (Fig. 10, 10B) to a setting state of Signaling device becomes effective and the operations of the monitoring control center to Processing of the instructions contained in the keyword directs. 5. Computing system according to claim 2, characterized in that the second arithmetic unit has a control signal generator (10-18) for resetting the signaling device. 6. Computing system according to claim 1, characterized in that each of the various input-output devices (1-12) has a synchronizing circuit (Fig. 45, 46, 48, 49, 50, 59 to 71) which, in the operating state, has the associated input -Output device caused to transmit a predetermined amount of information to or from the memory, and a reset circuit (44-25) are assigned which puts the synchronization circuit out of operation after actuation of the assigned input-output device. 7. Computing system according to claim 1, characterized in that each of the information processing devices (computer, monitoring control center, input-output devices) is able to access the memory (1-15) at such a rate that at least two such Devices can request access to the memory within a period of time which is less than the normal memory access time, and that a lock circuit (9-13) is connected to the memory which responds to a first call to the memory and blocks subsequent calls during the memory access time . 8. Computing system according to claim 7, characterized in that a signal relay circuit (9-30, 9-31) is able to respond to the receipt of a memory call from one of the devices for the purpose of returning a signal to the calling device to indicate the readiness of the memory, if this can be proven for use. 9. Computing system according to claims 7 and 8, characterized in that the blocking circuit is coupled to a signal relay circuit (MCKA, 9-41) in order to block the operation of the circuit during the access time. 10. Computing system according to claim 7, characterized in that certain devices before other facilities are entitled to access to the memory and that during the Blocking period memory flip-flops (9-14, 9-15) are operable to be used by the devices with the to save incoming calls assigned priorities and to be linked to the blocking circle, to hold the memory in an intermediate state until the next call from the facility is made while the priority call is held in the lock. 11. Computing system according to claim 7, characterized in that each information processing device which is able to call the memory in certain time segments for the purpose of access, is assigned a given time for calling during a certain period of time, that a suitable control circuit (9-62, 9- 60), which, when set, can block access to the memory during the given times that are assigned to certain calling devices, prevents certain devices from writing to the memory, and prevents the operation of the lock circuit from being inhibited (9-80 ) when a memory read is to be performed. 12. Computing system according to claim 9, characterized in that a memory lock flip-flop (9-13) responds to an initial call to memory to prevent the gates (9-4, 9-5) the address lines of each of the units leading to the address registers of the memory to put out of service for a certain period of time, whereby the memory of further Calling units for a given length of time meanwhile is spared. 13. Computing system according to claim 12, characterized in that an additional flip-flop (9-14, 9-15) by a memory call from the supervisory control center or the input-output devices can be set during the memory lock time and with the lock flip-fiop is coupled so that the memory is held in an intermediate state until the next Call from the facility adjusts the auxiliary flip-flop. 14. Computing system according to claim 1, characterized in that each of the input-output devices is able to carry out a specific work flow after responding to a received, precisely specified instruction, and a trigger flip-flop (44-20) which is set by the input-output device when it requires an instruction, and that a gate circuit (Fig. 28A) coupled to the flip-flops, which examine their state at certain time intervals, responds to the setting state of any flip-flop, to influence the control center (Fig. 10, 10B) to give an appropriate instruction to the input-output devices whose flip-flops are set and to reset the tested flip-flops. 15. Computing system according to Claim 1, characterized in that the gate circuit is repeated tests the status of all flip-flops in a group 509 538/373 363 364 and can be operated by any flip-flop to a fixed state to examine the flip-flops one by one, which of them is set, and then to do the Control system to cause an appropriate instruction to the input-output device output whose flip-flop is set, and to put this flip-flop in the reset state bring to.. 16. Computing system according to claim 14, characterized in that each input-output device has an adjustable bistable circuit which is brought into a state by the system whenever an instruction is required from the control center, that a transmission circuit (Fig. 28) in the control center for a test of one of the bistable circuits with participation a test instruction is responsive to the state of the bistable circuits at certain time intervals to test, wherein in the on-state the program of the control center is transferred to a workflow in order to receive appropriate instructions to deliver to the input-output devices, their bistable circuit on the mentioned On-state has been set. 17. Computing system according to claim 6, characterized in that the monitoring control center a priority control circuit (Fig. 29) which can be put into operation in order to give the fastest input-output devices first access to memory. 18. Computing system according to claim 7, characterized in that the monitoring control center Has control circuits that work essentially independently of the computer (1-11), to the exchange of information between the individual input-output devices and the Control memory, the hierarchy of control functions for transmission in accordance carried out with the established priorities for the individual input-output devices will. 19. Computing system according to claim 7, characterized in that the monitoring control center, a dispatch system (Fig. 29) to control the transfer of information between several input-output devices and a 4-way storage unit according to the defined priority regulations and has a priority circle (2iM> 5), which after receiving a . first signal becomes operational indicating a desired memory access from a given Input-output device displays to generate a second signal which, upon response for an existing first signal for certain devices and a nonexistent first Signal for those with a higher priority than the specific devices indicates that the devices provided have been given priority for one of these devices, Has control circuits (29-69) responsive to a second signal for the particular device, to read out the memory address for this device and the contents of the memory location read in the buffer registers (29-18) and generate a signal indicating that the memory is not busy and that access to the memory was successful, a memory address changing device (29-52) which is operable after reading out a memory address to convert the address into the next address to be read out and storing the resulting new address in the address register (29-50) in place of the to effect fetched address, and buffer and address control devices (29-80, 29-83) which respond to a signal, which has an unoccupied memory and which has the ability indicates to the input-output device that information can be received in order to read out from the buffer register to the input-output device. 20. Computing system according to claims 1 to 19, characterized in that an instruction is placed in the memory, which displays a certain number of information units, which are supplied to or removed from the memory by an input-output device should be that the exact number of between the input-output device and the memory transmitted information units is registered in the memory and that the control center brings the device to a halt after the registered number of the predetermined digit equals. Considered publications:
H. Rutishauser, A. Speiser, E. Stiefel, "Program-controlled digital computing devices", Basel, 1951, pp. 16 to 19;
FTZ, 1951, pp. 491 to 497;
Proc. IRE, December 1948, pp. 1452 to 1460. In addition 30 sheets of drawings 509 538/373 3.65 © Bundesdruckerei Berlin DRAWINGS SHEET 1 Number: Int. CL: German class: display day: 42m-14 April 8, 1965