US2982472A - Binary digital computer with magnetic drum storage - Google Patents

Description

May 2, 1961 H. D. HUSKEY BINARY DIGITAL. COMPUTER WITH MAGNETIC DRUM STORAGE Filed May 2, 1955 10 Sheets-Sheet 2 INVENTOR Ea/rIyD. Husk/6y BY/flml, (Z I A RNEYS y 2, 1951 H. D. HUSKEY 2,982,472

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I 56 am 2'5 FLIP-FLOP 247 FL V 32? READ COMMAND ser SET WAIT TRANSFER RESET RESET 5 TRANSFER RESET 6'57 WAIT NEXTCOMMAND SET RESET mvsmon HwrryD.Hws1cqy 328 Ml45hw J947 (J A ORNEYS H. D. HUSKEY May 2, 1961 BINARY DIGITAL COMPUTER WITH MAGNETIC DRUM STORAGE Filed May 2, 1955 10 Sheets-Sheet 9 XQTWR W-W$$ I I I mu IIIIIIIIIIIIIIIIIIIIIIIII II III lllllilfll I m a 4 W a f .25: ab 9 3 N 41 2 n 9 R 2 2 7 I z E 3 3 I 1! I 3 3 G a. M j Z w a 3/ A I r fi T U C v P e w 6 I H M 6 8 W 3 If f ,M 0 E 9 N :1 54 2 x 2 8 7 9 m A J A m 4 1 J: 2 L I 15. i AW? a W z 2 m m m M a a a7 w T A 3 2 Z 9 o 5 4 4 3 8 P 1 P 7 2 0 0 E E P 6 5 I 3 0 33 r 5 V C W 9 N 2 Q a 1 a l u a n E a 0 5 5 a 2 4L 2 2 A W n n T. a P9 a 3 3B 5 0 H a w 4 R m E 0 w, y z 7 m z w z m 7 w 4 3 w a a z z e I P. u w a m a M w 0 v A P n a, 2 y W i 0 5 P E J! 9 rv a 3 n S m 4 93 W W 8 2 8 9 E w z R J A g M v 5 z m h w M 2 4 M s 2 h 7 a w n s w c M A RNEYS United States Patent 015 2,982,472 Patented May 2, 1961 ice BINARY DIGITAL COMPUTER WITH MAGNETIC DRUM STORAGE Harry D. Huskey, 2655 Buena Vista Way, Berkeley 8, Calif.

Filed May 2, 1955, Ser. No. 505,186

14 Claims. (Cl. 235-167) This invention relates to methods and apparatus for computing and more particularly to methods and apparatus for high speed general purpose computing.

Continuing developments in science, business planning, and technology generally have increased tremendously the magnitude of problems requiring computation for solution. Despite the fact that mathematical formulas may be available whereby such problems can be solved, the calculations involved in reaching a solution may be so extensive as to render the solution a practical impossibility if attempted manually, even with the aid of mechanical calculators now known. For example, some problems can require periods of time measured in years for a person to solve the problems manually even with the aid of a mechanical calculating machine operated by the person as he proceeds with the calculations. To meet this situation, the art to which this invention relates has developed high speed electronic computers capable of accepting information representing the problem to be solved and the instructions for solving the problem and then performing the required calculations in but a minute fraction of the time that it would take to perform the calculations manually, even with the aid of mechanical calculating equipment now known.

Methods and apparatus for computing have therefore progressed to the point where it is now possible to solve problems requiring extensive calculations or computation quickly enough so that the solutions can be obtained within practical time limits. Examples of problems whose solution becomes practicable by such methods and apparatus include problems in the field of science generally, problems concerning military weapons such as determining missile trajectory, and such problems in mathematics as the preparation of extensive mathematical tables. Other examples of problems whose solution becomes practicable by such methods and apparatus are found in the business world and include such problems as production planning and control where many thousands of components may have to be assembled in a finished product, payroll problems where many and varied deductions may have to be applied to thousands of different employees, insurance policy transactions requiring a large number of arithmetic and printing operations, and problems in the accounting field generally where extensive entries and calculations are needed according to the technique being employed. By utilizing high speed electronic computers, it is possible to complete the required calculations for problems such as those mentioned above so quickly that a particular problem may be solved in a matter of minutes as compared to days, months, or even years if performed manually, even with the aid of mechanical calculators. High speed electronic computers have thus become a valuable tool for both governmental and private business activities.

While high speed electronic computers are known generally, those available prior to the present invention tend to be extremely complex and extremely costly. For example, a general purpose digital electronic computer of the type known to the art at present can occupy a fair sized room, or even rooms, and will have thousands of electronic tubes and more thousands of other electrical components which make up the computer. Obviously, the manufacturing of such a computer is a time consuming and costly matter and, obviously also, such a computer is a costly piece of equipment to purchase. Computers of this type are therefore beyond the practical means of many potential users who could otherwise benefit from them. While there are also available so-called small general purpose computers, those available prior to the present invention tend to suffer the objection that they do not have the capacity to solve many problems which general purpose computers are supposed to be capable of solving. In other words, these so-called small general purpose computers sacrifice general problem solving ability for cost.

The present invention is therefore directed squarely at the problem of providing a small high speed general purpose electronic computer which will perform a great variety of computations thus giving it a wide range of utility as a machine aid to computation. Primarily because of its size, a computer constructed in accordance with the teaching of the present invention is relatively inexpensive compared generally to high speed general purpose electronic computers available prior to the present invention. Being relatively inexpensive, a computer constructed in accordance with the teaching of the present invention has the great practical advantage that it brings apparatus of this type within the economic reach of potential users of such equipment who cannot afford the more costly equipment heretofore needed for general computation purposes. It is therefore an object of the present invention to provide new and improved apparatus for high speed general purpose computing whereby such computing may be accomplished relatively inexpensively as compared generally to methods and apparatus available prior to the present invention.

It is another object of the present invention to provide such apparatus whereby an extremely flexible computer command structure is provided.

It is still another object of the present invention to provide such apparatus giving high arithmetic speed as compared to comparable methods and apparatus known prior to the present invention.

It is a further object of the present invention to provide such apparatus whereby the signs of numbers being processed may be inspected and the number complemented if required while the number is being transferred from a source to a destination.

It is a still further object of the present invention to provide such a computer of small physical size and increased reliability as compared generally to high speed general purpose computers available prior to the present invention.

Briefly described, a preferred practice according to the teaching of the present invention comprises converting data to be processed into sequential bits of yes or no information according to the binary number system. Where the data being processed is a number, the first bit of information denotes the sign of the number, i.e. whether the number is positive or negative. The sequential bits of information are preferably recorded or stored in a delay line type of memory and each group of bits of information representing a word (such as a command or a number) may recirculate from and back into the memory always maintaining the same sequence of the yes or no hits making up the group. Instructions (commands) for accomplishing a given series of calculations, for example, and the numbers or other data involved in the calculations may be stored in the memory.

A group of sequential bits of yes or no information representing a command contains bits determining the source or location in the memory from which another group of sequential bits of information is to be obtained; contains bits determining the destination or location in the memory to which said other group of bits is to be sent; contains bits determining when the transfer is to take place; contains bits determining whether said other group of bits is to be transferred unchanged, is to be transferred absolute value, or is to be complemented; and contains bits determining which group of bits representing a command is to be read as the next command. A command word according to the teaching of the present invention therefore performs many functions. It may be described as a two address type of command, i.e. it determines both source and destination and it not only determines the time for the transfer to take place from one address to the other address but it also, in elfect, links the next command to it. A preferred practice of the present invention therefore includes the rapid execution of a plurality of commands.

High arithmetic speed is facilitated by performing any required modification of a group of sequential bits of information representing a number while, in response to a command, said group is being transferred from a source to a destination. The first bit of information in the group being transferred is inspected to determine if it is a yes bit or a no bit. Then, depending upon whether the command being obeyed specifies an addition or a subtraction, for example, and depending upon the sign of the number (the first bit of information), the number may be complemented. As an example, if the command .is addition and the number is negative, the first yes bit of information represents the sign and is passed unchanged. No bits of information following the sign bit are passed unchanged up to and including the first yes bit of information which follows the sign bit. Thereafter, all yes bits of information are changed to no bits and all no bits to yes bits. In this way, modification of a group of bits of information being transferred actually takes place in transit.

In combining two groups of bits of information of the same length wherein each group represents a number, the first bits of information in the groups, i.e. the sign bits, are combined first and any resulting carry bit is suppressed so that it is not added to the sum obtained by combining the two second bits of the groups. The combining continues, respective bit with respective bit for the two groups of bits until the last bit of one group is combined with the last bit of the other group. Any resulting carry is then combined with the sum obtained as a result of combining the sign bits of the two groups but, again, any further carry to the sum obtained by combining the second bits of the respective groups is suppressed. The practice of the present invention therefore provides for end around carry coupled with carry suppression.

A preferred embodiment of apparatus according to the teaching of the present invention comprises a magnetic drum type of memory having a plurality of lines or tracks each capable of storing up to 128 words. Each word preferably consists of 25 bits of yes or no information. A magnetic induction reading head, erase head, and writing head are so associated with the magnetic drum that as each word is read from the drum it is in effect lifted off of the drum and then subsequently written back into the drum in the sequence in which it was read. Pulse gates. coincidence gates, and or gates are provided in various circuit arrangements which may include one or more electronic flip-flop devices. Such circuitry enables repeated recirculation of words from a line of the memory back to the same line of the memory; enables simultaneous recirculation and transfer of the word to another line of the memory; and enables simultaneous blocking of such recirculation while transferring another word in place of said word.

A sign inspection circuit is provided through which all data being transferred from one part of the memory to another part of the memory, or to the arithmetic circuits, passes. Depending upon the command being executed, the sign inspection circuit may or may not modify the data being transferred and if it does modify the data, such modification occurs as the data passes through the sign inspection circuit. Two arithmetic circuits are provided, one handling single length words (25 bits of information long) and the other handling double length words (50 bits of information long). A multiplication circuit forms part of the arithmetic circuit which handles the double length words. Input-output circuitry is also associated with the double word length arithmetic circuitry and the multiplication circuitry whereby it is possible to utilize certain flip-flops for a plurality of functions depending upon whether addition, subtraction, multiplication, input, or output is being accomplished.

Other objects and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the attached drawings in which:

Fig. 1 is a block diagram showing the relation of and indicating the direction of data transfer for the principal parts making up a preferred embodiment of apparatus according to the teaching of the present invention;

Fig. 2 shows a preferred form of electronic bistable device forming a part of apparatus according to the teaching of the present invention;

Fig. 3 is a circuit diagram of the electronic device shown in Fig. 2;

Fig. 4 shows a coincidence (and) gate used in a preferred form of apparatus according to the teaching of the present invention;

Fig. 5 is a circuit diagram of the gate shown in Fig. 4;

Fig. 6 shows an or gate;

Fig. 7 is a circuit diagram including the gate shown in Fig. 6;

Fig. 8 shows a pulse gate;

Fig. 9 is a circuit diagram of the pulse gate shown in Fl 8;

i ig. 10 is a schematic showing of a preferred form of a memory and means for recirculating information from and back into the memory according to a preferred practice of the present invention;

Fig. 11 is a schematic showing similar to that of Fig. 10 and indicates the path of travel of data going from the memory back to the memory;

Fig. 12 is another schematic showing of a preferred type of memory showing how data is recorded on the surface of the memory;

Fig. 13 is a circuit diagram of a timing part of a preferred form of apparatus according to the teaching of the present invention;

Fig. 14 shows various types of electrical pulses, and their time. relation, obtained by means of the circuitry shown in Fig. 13;

Fig. 15 is a circuit diagram of another timing part of a preferred form of apparatus according to the teaching of the present invention;

Fig. 16 shows various types of electrical pulses, and their time relation, obtained by means of the circuitry shown in Fig. 15;

Fig. 17 shows the make-up of a preferred form of command word according to the teaching of the present invention;

Fig. 18 is a circuit diagram of circuitry utilized in read ing a command wo'rd;

Fig. 19 is a circuit diagram of source and destination switching parts of a preferred form of apparatus according to the teaching of the present invention;

Fig. 20 is a circuit diagram showing how data may be recirculated from and back to a memory line, transferred from a memory line, and transferred into the memory line;

Fig. 21 is a circuit diagram showing the sign inspection part of a preferred form of apparatus according to the teaching of the present invention;

Fig. 22 is a table showing the states of certain flip-flops shown in Fig. 21 for different types of operations;

Fig. 23 is a circuit diagram showing an accumulator part of a preferred form of apparatus according to the teaching of the present invention;

Fig. 24 is a truth table illustrating the operation of the circuit shown in Fig. 23;

Fig. 25 is a circuit diagram showing the control part of a preferred form of apparatus according to the teaching of the present invention;

Fig. 26 is a table showing the states of certain flip-flops shown in Fig. 25 for different command operations;

Fig. 27 is a circuit diagram showing, in isolated relation, the discriminator part of the circuitry shown in Fig. 25; and

Fig. 28 is a circuit diagram showing the product accumulator and input-output parts of a preferred form of apparatus according to the teaching of the present invention.

In order to facilitate an understanding of methods and apparatus according to the teaching of the present invention, the following detailed description is presented under applicable headings the first of which follows immediately.

GENERAL STRUCTURE As has been mentioned above, high speed general purpose computers available prior to the present invention are generally quite massive pieces of apparatus. Typical examples require a fair sized room to house the apparatus and they include thousands of electronic tubes and more thousands of other electrical circuit components. In contrast, a preferred embodiment of apparatus constructed in accordance with the teaching of the present invention may be housed in a cabinet which may be compared in size with an office file cabinet rather than an entire room. The number of electronic tubes involved is less than one thousand instead of being in the thousands and the number of other electrical circuit components is correspondingly reduced. By using printed circuit techniques, plugin units, and the like, the entire apparatus is extremely compact as compared to the usual apparatus for high speed general purpose computing available prior to the present invention.

It is thus apparent that apparatus constructed in accordance with the teaching of the present invention can be appreciably lower in cost than larger types of general purpose computing apparatus known in the art prior to the present invention. While the larger apparatus admittedly has greater data processing capacity, it will be evident from the detailed description which follows that apparatus according to the present invention has extreme flexibility giving it proportionately much greater data processing capacity than would be expected for its size. In other words, while the size of a preferred embodiment of apparatus according to the teaching of the present invention is appreciably less than typical apparatus available prior to the present invention, the data processing capacity of my apparatus is by no means reduced in the same proportion.

Since apparatus according to the teaching of the present invention is a general purpose electronic digital computer, the data processed by the apparatus is preferably in the form of sequential bits of yes or no information according to the binary number system. In the memory, the sequential bits of information are stored as sequential small discrete areas magnetized according to the particular yes, no pattern of the group of bits of information representing a particular portion of data such as, for example, a number which is to be added to, subtracted from, etc. another number. In transferring data represented by a group of sequential bits of yes or no information, a

yet bit is generally represented by an electrical pulse a} pearing timewise in the digit position occupied by the yes bit while a no bit is represented by the lack of an electrical pulse appearing in the digit position occupied by the no bit.

It is to be understood that when it is stated that data passes from one part of the apparatus to another part, suitable electrical power supply means are provided to cause the described transfer to take place when it is supposed to take place. Also, when it is stated that information or data is stored in the memory, which is described in greater detail hereinafter, it is to be understood that the memory is suitably mounted so that the described storage may take place. In short, such things as power supply for the apparatus, the actual physical mounting of electrical circuit components and the like are not described in detail since it will be understood by those skilled in the art that the various parts can be located readily and power supplied thereto to cause them to 01:- erate as described.

The major blocks or parts making up a preferred embodiment of apparatus according to the teaching of the present invention are shown in Fig. 1. Referring to Fig. I, it will be noted that block 1 designates the memory or information storage part of the apparatus, block 2 designates a source switching part of the apparatus, block 3 designates a sign inspection part of the apparatus, and block 4 designates a destination switching part of the apparatus. Upon examining the arrows shown on leads 5-8, it is apparent that information may pass from the memory or information storage medium 1, via the source switching part 2, the sign inspection part 3, and the destination switching part 4, back to the memory. This is a basic information transfer pattern in the sense that information transferring from one part of the memory to another part of the memory goes through the sign inspection part 3 in the course of the transfer. As is brought out more fully hereinafter, the sign inspection part 3 performs its function of inspecting the information and modifying it if required without interrupting transfer. This obviously speeds up the transfer time.

Referring back to Fig. 1, it will be noted that lead 6 bears the letter designation EB and lead 7 bears the letter designation LB. These letters stand for Early Bus" and Late Bus" respectively. The significance of the Early Bus designation is that data fed therethrough may be said to be source data while data fed through the Late Bus may be said to be destination data.

Again referring to Fig, 1, it will be noted that block 9 designates an accumulator or adder part of the apparatus, block 10 designates a product accumulator which is another adder part of the apparatus also utilized in the arithmetic process of multiplication, and block 11 designates an input-output part of the apparatus whereby data to be processed may be fed into the apparatus and the processed data taken from the apparatus. Both the accumulator and the product accumulator are shown as being connected so that data from either of them passes to the source switching part 2, through the Early Bus 6, through the sign inspection part 3, and then through the Late Bus 7 to the destination switching part 4. The data may then return to either the accumulator 9 or the product accumulator 10, or it may go to the memory 1 depending upon the instruction (command) being executed. It is significant to note that for the transfer just described, the transferring data always goes through the sign inspection part 3 of the apparatus.

The input-output part of the apparatus designated by block 11 is shown as being connected to the product accumulator 10 by dotted lines 12 and 13. The dotted lines indicate that input data may proceed from the in put-output part of the apparatus to the product accumulator and, correspondingly, output data may proceed from the product accumulator to the input-output part of the apparatus. Of course, the input-output part 11 of the apparatus is utilized only during actual input of data to Or output of data from the product accumulator. As indicated by the arrows associated with block 11, input data will come from a suitable external source, not shown, which feeds into the input-output part of the apparatus. Likewise, output data feeds from the input-output part of the apparatus to a suitable output data receiving device, not. shown,

Again referring to Fig. 1, it will be noted that the large upper block 16 designates the control part of the apparatus while the large lower block 17 designates the timing part of the apparatus. As indicated by its name, the control part of the apparatus is in effect the nerve system of the apparatus in that it controls when and where data transfer takes place in the apparatus. Control part 16 therefore connects to all of the other parts of the apparatus as shown by the lines leading to the memory and the source and destination switching parts, and as further shown by the short lines indicated as going to other designated parts of the apparatus, the actual connecting lines being omitted in these instances to avoid confusing Fig. l unnecessarily. The only part of the apparatus shown in Fig. 1 to which the control part does not connect is the timing part designated by block 17.

The timing part 17 of the apparatus is, in effect, the pulse or heart beat of the apparatus. It synchronizes the operation of the other parts designated by blocks in Fig. 1 so that when a given transfer of data is to take place, such a transfer will take place at exactly the right time. This is obviously necessary in an apparatus which, for example, must combine or add together data in an arithmetic type of operation to provide a desired correct answer. If the data is in electrical pulse form then a pulse being combined with another pulse must be in exact step or else the proper combination of the pulses will not be effected. Since the timing part of the apparatus is the synchronizing part, it connects to all of the other parts of the apparatus designated by the blocks shown in Fig. 1. This is shown by the short lines extending from the timing part 16 and indicated as going to other designated parts of the apparatus.

In summary, as regards the general structure of a prefered embodiment of apparatus constructed in accordance with the teaching of the present invention, data may be transferred from the memory, accumulator, or product accumulator to the memory, accumulator, or product accumulator via the source switching part, Early Bus, sign inspection part, Late Bus, and destination switching part of the apparatus. Input from a suitable external source, not shown, goes via the input-output part of the apparatus to the product accumulator. Output goes from the product accumulator to a suitable external destination, not shown, via the input-output part of the apparatus. The control part of the apparatus controls all data proccessing operations including data transfer and the like while the timing part of the apparatus insures that all parts of the apparatus operate in proper synchronism.

ELECTRONIC COMPONENTS AND TERMINOLOGY Certain electronic components forming part of a preferred embodiment of apparatus according to the teaching of the present invention are utilized in substantially all of the parts making up the entire apparatus described above in relation to Fig. 1. Therefore, in order to facilitate further detailed description of the various parts of the apparatus designated by the blocks shown in Fig. 1, such electronic components are described in detail in this particular part of the over-all detailed description thereby making it unnecessary to repeat such detailed description in connection with further description of each major part or block making up the complete apparatus. The electronic components which are selected for description in this part of the detailed description may be regarded as basic units common to substantially all parts making up the preferred embodiment of the apparatus.

Flipfi0p.-Since, digital computation is utilized in the practice of the present invention and the apparatus op erates in the binary number system, it is necessary to provide a bistable device which is capable of storing a yes or no bit of information. A bistable device is of course one which has two stable states and is capable of being changed in state from one to the other of the states and vice versa. For high speed operation, where the data being processed is represented by electrical pulse train patterns, this means that the bistable device must be capable of changing states substantially instantaneously as required.

Such a bistable device is commonly referred to in the art as a flipflop. Fig. 2 shows a typical representation of a flipflop, the latter being indicated generally by the reference numeral 18. It will be noted that there are three input leads 19-21 and two output leads 22 and 23 associated with flipflop 18. The upper half 24 of the flipflop is shown as shaded while the lower half 25 is shown unshaded. As shown, the flipflop can be assumed to represent a no hit of information. It is further assumed that an output lead from the shaded half of the flipflop is low whereas an output lead from the unshaded half of the flipflop is high. Therefore, as shown in Fig, 2, output lead 22 is assumed to be low and output lead 23 is assumed to be high. When the flipflop changes state, lead 22 goes high and lead 23 goes low. The terms high and low refer to the electrical potential relation of the output leads and are commonly used in the sense described by those skilled in the art.

If it be assumed that the state of the flipflop shown in Fig. 2 is such that output lead 23 is high, then an input signal occurring on lead 19 will change the state of the flipflop so that output lead 22 becomes high and lead 23 becomes low. Once changed, the flipflop can be reset by a signal on input lead 20. As the flipflop is shown in Fig. 2, a signal on input lead 20 is ineffective to change the state of the flipflop since the side to which the signal is applied is already high.

Lead 21 is shown as being connected to the crisscross lines at the middle of the flipflop shown in Fig. 2. The significance of this type of input is that it will change the state of the flipflop no matter what its previous state was. Thus, while a signal on input lead 20 is ineffective to change the state of the flipflop as it is shown in Fig. 2, a signal on lead 21 will change the state. The utility of a type of input capable of changing the state of the flipflop no matter what its previous state was becomes more apparent in the description of the operation of parts of the complete apparatus given hereinafter. It is to be understood, of course, that the signals referred to as being applied to the flipflop via leads 19-21 are electrical pulses of very short duration.

It is apparent that the flipflop is in itself a simple memory capable of remembering a single fact. In other words, if a single pulse is fed into the flipflop on one of the input leads, 18 for example, the flipflop can change state and will remember that it has changed state if another signal is sent on the same lead. Conversely, if it has changed state and an input signal is fed into it on another lead, it will remember that it has changed state so that the new input is effective to reset it to its former state. The terms set and reset are commonly utilized in describing the condition of a flipflop. Thus, as shown in Fig. 2, the flipflop is reset and it is set by a signal on either lead 19 or lead 21.

Fig. 3 shows a typical circuit for the flipflop 18 shown in Fig. 2. This figure shows a double triode 26 with the left portion shown shaded to indicate that this particular portion of the triode is conducting. This corresponds to the shaded representation 24 for the upper part of flipflop 18 of Fig. 2. With the left portion of triode 26 conducting, it is apparent that output lead 23 is high in potential as compared to output lead 22. It is further apparent that a pulse or signal of proper polarity appearing on lead 19, for example, will cause the grid of the left portion of double triode 26 to change potential. Such change in potential can cause the flipfiop to change state so that the right hand portion of double triode 26 becomes conducting and the left hand portion becomes non-conducting. Output lead 22 is then high instead of output lead 23. A signal of proper polarity appearing on lead 21 results in a signal which is applied substantially equally to the clamping crystal diodes on both sides of the flipflop. Due to the non-linear resistance characteristic of the crystal diodes, the signal has little effect on the potential of lead 22 since this lead is assumed to be substantially negative. However, the crystal diode which connects to lead 23 will conduct and the end result is therefore like the case described with respect to a signal appearing on lead 19, namely, the grid of the left portion of double triode 26 is driven negative and the flipflop changes state. A signal of proper polarity appearing on lead 21 is therefore effective to change the state of the flipfiop irrespective of its existing state. As may be observed from Fig. 3, output leads 22 and 23 are each connected between a pair of clamping crystal diodes so that the output potential can swing only a certain amount. Further description of the circuitry shown in Fig. 3 is deemed unnecessary since it is typical for an electronic flipfiop and is readily understood by those skilled in the art.

Coincidence (and) gates. In transferring data in electrical pulse form from one part of the apparatus to an other part, it is frequently necessary to condition the transfer at a particular point or points on whether two or more signals or pulses coincide. This is accomplished by utilizing so-called coincidence gates, often referred to as and gates. Fig. 4 shows such a gate. Referring to this figure, the coincidence gate is designated generally by the reference numeral 27. Two input leads 28 and 29 feed into the gate and a single output lead 30 leads from the gate. The character of the gate is such that output lead 30 will not be energized, or go high, unless both input leads 28 and 29 are energized, or are both high.

A simplified representation of typical circuitry for coincidence gate 27 is shown in Fig. 5. As will be evident to those skilled in the art, this is a typical coincidence gate of the diode type wherein output lead 30 will be high only if both input leads 28 and 29 are high. Thus, due to the non-linear characteristics of diodes 31 and 32, if either lead 28 or 29 is at a sufficiently minus voltage then output lead 30 will be at this minus voltage also. However, if both leads 28 and 29 are sufiiciently positive, or sufficiently relatively positive, then output lead 30 will be correspondingly different in potential and will be high. Further detailed description of this particular circuit and the coincidence gate in general is deemed unnecessary since it is believed to be evident to those skilled in the art.

Or gates-Just as it is frequently necessary to condition transfer of data on the coincidence of certain signals or pulses, it is also frequently necessary to transfer data if any one or more than one of two or more input leads happens to be sufficiently high in potential. This type of gate is commonly referred to in the art as an or gate. Such a gate is designated generally by the reference numeral 33 in Fig. 6 and a typical circuit for the gate 33 is shown in the right hand portion of Fig. 7.

Referring to Fig. 6, one of the input leads is shown as being lead 30 of the coincidence gate of Fig. 4 and the other input lead is designated by the reference numeral 34. If either of these input leads 30 or 34 is high then output lead 35 will be high. While only two or gate input leads 30 and 34 are shown in Fig. 6 any practicable number can be employed and output lead 35 will be high if one of the input leads is high.

Referring to the circuit shown in Fig. 7, it is noted that leads 30 and 34 feed to diodes 36 and 37 respectively.

Therefore, if either lead 30 or 34 (or both) is high, then the anode of the corresponding diode will be high and the diode characteristic is such that it will conduct and cause output lead 35 to be high. It is apparent that, in the circuitry shown in Fig. 7, the or gate input leads 30 and 34 are the output leads of two coincidence gates of similar circuit arrangement.

Pulse gates.Pulse gates, as employed in a preferred embodiment of apparatus according to the teaching of the present invention, are devices capable of accepting input signals from one or more sources and producing or passing an output pulse of extremely short duration so that very fine synchronization of operations performed by the apparatus may be achieved. For example, as is brought out more fully hereinafter, a pulse gate may have to supply a signal during a minute fraction of time which occurs between other time fractions and the signal must be of such short duration that it can be sandwiched in between the other times without affecting signals which may occur at the other times. Coincidence (and) gates and or gates of the types described above operate relatively slowly as compared to pulse gates and hence the latter perform the important function of enabling precise timing to be accomplished for control purposes.

Fig. 8 shows such a pulse gate which is designated generally by the reference numeral 38. Upon examining Fig. 8 it will be noted that there are three input leads 39-41 to gate 37 and one output lead 42. Referring to Fig. 9, which shows a typical circuit for gate 38, it will be noted that input leads 39 and 40 are input leads to a portion of the pulse gate circuit which is actually a coincidence gate circuit like that shown in Fig. 5. Thus, the output lead 43 of this portion of the pulse gate circuit leads to the suppressor grid 44 of the pentode 45 shown in Fig. 9. The characteristics of the pentode are such that a signal appearing on suppressor grid 44 as a result of a coincidence of inputs on leads 39 and 40 holds up the potential level so that a short duration pulse appearing on input lead 41 is passed as a short duration output signal on pulse gate output lead 42. While gate 38 is shown as having two input leads 39 and 40 for the coincidence gate part of the circuit, it could have one such lead or more than two such leads within practical limits. Further description of the pulse gate is deemed unnecessary as its circuitry and operation are believed evident to those skilled in the art.

THE MEMORY In the computer art, the term memory may be defined as referring to that part of the computer which is capable of storing data fed into the computer, retaining the data, and giving up or feeding out the data when asked in the proper manner. As mentioned above, a single flipflop is a type of memory in that it can remember a single fact. Obviously a group of flipfiops will have a memory capacity equal to the number of fiipfiops involved. Since a practical memory must have a substantial capacity to be useful for general computation purposes where the memory may have to store hundreds, if not thousands, of so-called words, it is preferred to use a medium which is capable of substantial storage.

One such type of memory is the magnetic drum type wherein the data to be stored is recorded on the magnetizable surface of the drum in discrete magnetized areas. A preferred embodiment of apparatus according to the present invention utilizes a magnetic drum type of memory because of its economy, ruggedness, and high performance characteristics as compared to other types of memories now known in the art. Inasmuch as it is possible to magnetize up to approximately separate discrete areas per lineal inch on a magnetizable drum surface, it is apparent that a single track on the drum circumference can contain a substantial;

11 number of groups of magnetized areas which can represent numbers or other data being processed. In this connection, since the art commonly uses the term word to denote a number or other type of data being processed in a computer apparatus, this term is sometimes used hereinafter in the remainder of the detailed description.

In accordance with the teaching of the present invention, the information recorded in each track on the magnetizable surface of the magnetic drum may be continuously read and re-recorded on the drum surface. This is therefore a volatile system wherein, in effect, the Words are lifted from the drum surface for a brief period of time and then put back onto the drum surface. When lifted from a track on the drum surface, so to speak, they may be transmitted from the drum to an output destination or to be recorded in another track on the drum and new words may come into the track in place of the old words.

This basic recirculation aspect according to the teaching of the present invention is shown schematically in Fig. where the reference numeral 46 designates the magnetizable material circumference or outer surface of magnetic drum 47. Assuming that a portion of the magnetizable surface 46 contains a line or track of discrete magnetized areas representing bits of information, as the drum revolves in the direction of the arrow shown in Fig. 10, the magnetized areas can come successively under the magnetic induction reading head 48. As each discrete magnetized area on the drum surface is sensed, or read, by reading head 48, such sensing can cause an electrical pulse to pass through lead 49 to amplifier 50. The amplifier causes a. write pulse to appear on lead 51 which transmits the write pulse to magnetic induction writing head 52 where the pulse is re-recorded as a discrete magnetized area on the surface of the drum.

Each bit of information will thus be re-recorded in exactly the same sequence and in the same track on the drum surface but will be displaced circumferentially from its former position in the track. After each magnetized area passes under reading head 48, it then passes under magnetic induction erasing head 53 which causes all areas to have the same magnetization as they approach writing head 52. As each area passes under the writing head, the latter will change the magnetization of the area if the writing head is energized by a pulse at that precise instant of time. It is to be realized that all equally spaced apart discrete areas representing a group of bits of information are magnetized areas with the magnetization of the areas representing the yes bits being different from the magnetization of the areas representing the no bits. Therefore, erasing head 53 simply changes the magnetization of the areas representing the yes bits so that they become areas representing no bits and thus all areas approach the writing head as areas representing no bits of information. The writing head 52 simply replaces some of the no bits with the proper yes bits in order that the relation of yes and no bits for any given group will be proper to represent the information correctly according to the binary number system.

Fig. 11 is a schematic showing similar to Fig. 10 to emphasize that the effect of the arrangement shown in Fig. 10 is as if the bits of information stored in a track on the drum surface were shaved from the drum surface and then spilled back over the shaving apparatus to get back onto the drum surface in the same order and in the same track from which they came. Erasing head 53 may be said to be the shaving apparatus and dotted line 54 may be said to represent the bits of information going from the drum surface 46 and spilling over the erasing head to at back onto the drum surface.

Fig. 12 is another schematic showing and shows a magnetic induction writing head 52 writing yes bits of information into a track 55 on drum surface 46. The dots 56 represent discrete magnetized areas in track 55 which represent the yes bits. Figs. 10-12 are to be understood as being quite simplified and as being illustrative of the storage of bits of information in a track or line on the drum surface and the simple recirculation of such bits of information from said track, through an external circuit, and back to the track. One significance of even this simplified showing is that it makes it apparent that each word (group of bits of information) in each track on the drum surface can be made available in an external circuit at a given period of time. Those skilled in the art will thus recognize this as a delay line type of memory since, for a given word, one must wait for it to appear in the external circuit if it is to be taken from the memory.

In a preferred embodiment of apparatus in accordance with the teaching of the present invention, the memory has a capacity of approximately 1,000 words with each word being about 25 binary digits in length. The words can be longer than 25 digits in length and the memory can have a greater capacity than stated but the stated capacity and word length are preferable because they help to reduce the size of the apparatus without unduly sacrificing the high speed general purpose computation ability of the apparatus. To accommodate the approximately 1,000 words capable of being stored in the memory, seven memory lines or tracks, such as track 55 shown in Fig. 12, are provided and each track has a capacity of 128 ZS-digit length words. In addition to the seven tracks, or long lines, mentioned, there are short tracks on the memory surface some of which are only one 25-digit word long and others of which are two 25- digit words long. This is brought out more fully in the later description.

In referring to a word as being 25 digits long, this is to be understood as meaning that there are 25 available digit positions for yes or no bits of information which make up the word. Thus there are 25 uniformly spaced apart discrete areas which can be magnetized to represent the yes or no bits of information. As will be understood by those skilled in the art, in representing a number, for example, according to the binary system, a 1 (yes) is placed in each digit position where it is necessary to have 2 to a power corresponding to the digit position to make up the complete number. Thus, the number 5 is represented according to the binary number system by 101, the number 10 represented by 1010, and the number 15 represented by 1111, all reading from right to left and with the right hand digit position being the units position as is well known by those skilled in the art.

Translated into electrical terms this means that to represent a given number by magnetizing discrete areas on the drum surface according to the binary number system, the areas will be magnetized to represent ls (yes bits) and 0's (no bits) as required for the number involved. Where the words being processed are numbers, the first of the 25 digit positions is utilized as the sign digit. The remaining 24 digit positions are utilized to represent the number. With 24 magnetizable areas available per word it is apparent that if the particular number is a low number like 5, 10 or 15, then not more than the first four of the 24 areas will involve 1's (yes bits) and all the rest will be magnetized to represent Os (no bits). On the other hand, if the particular number (word) is in the millions then most of the 24 magnetizable areas may involve ls (yes bits). In any event, insofar as numbers are concerned, each word capacity goes up to 2 to the 24th power thus enabling the memory to store very large numbers and the apparatus to process very large numbers in arithmetic operations. In fact, as is brought out more fully later in the description, it is possible to process so-called double length words which go up to 2 to the 49th power. This can accommodate a very large number. Alternatively, words may represent fractions or they may represent any other coded information.

TIMING Referring back to Fig. 1, it will be observed that the timing part (designated by block 17) of a preferred embodiment of apparatus according to the present invention is shown as being connected to the other parts of the apparatus as indicated by the small arrows extending from block 17. This, of course, is because the timing part synchronizes the action of the other parts and, so to speak, keeps all parts in step. It is evident that this is required since, to take merely one example, when electrical pulses are being recorded or written onto surface 46 of magnetic drum 47, corresponding electrical pulses going to different tracks on the drum surface must be recorded at exactly the same instant of time so that the relative word positions in the tracks will be the same. There can be no overlapping or variable gaps in relative word positions in the different tracks or else it would be impossible to command certain transfers to take place because the word positions would be unknown.

The exact uniform spacing of digit positions, sometimes called pulse positions, in every track on the magnetic drum surface is achieved by providing a master heart heat, so to speak, which is permanently recorded on magnetic drum surface 46 as one long track containing uniformly spaced apart discrete areas magnetized to represent ls (yes bits). There are enough of these magnetized areas to provide precise control for 128 words each 25 digits long, it being understood that the last or 25th digit of one word is uniformly spaced from the first digit of the next subsequent word in the track. In other words, there is the same spacing between digits in digit positions 24 and 25 of one word as there is between this 25th digit and the first digit of the next succeeding word. Such a permanently recorded long line of uniformly magnetized discrete areas is indicated by dotted line 57 in Fig. 13 which is hereinafter referred to as the clock pulse track because, during each revolution of the magnetic drum, it presents uniformly spaced apart magnetized areas to a magnetic induction reading head 48 so that the latter can sense each magnetized area in succession.

Fig. 13 thus shows a magnetic induction reading head 48 as reading clock pulse track 57 to sense each of the magnetized areas present in the clock pulse track. As each discrete magnetized area is sensed, a pulse is produced which is fed to the amplifier designated by block 58. The amplified pulse is then fed to a suitable wave shaping component 59 from which it appears on output line 60 as a so-called write pulse (WP pulse). A switch 61 is provided whereby it is possible to interrupt the production of write pulses. Thus, if switch 61 is open nothing can be recorded or re-recorded on the magnetic drum surface because every magnetic induction writing head 52 is controlled by a write pulse. Hence, if a write pulse is not available the magnetic induction writing head cannot function. Switch 61 enables the operator to erase manually any information stored in the memory.

Fig. 14 illustrates schematically a shape which the write pulses appearing on output lead 60 may assume as a result of the re-shaping action of whatever electrical component is used to provide the wave shape. Thus, referring to Fig. 14, the write pulses (WP pulses) are shown as being square shaped pulses 62, this being simply illustrative of the shape which the pulse can take, the important point being that each write pulse be shaped like every other write pulse.

Referring back to Fig. 13, it will be noted that lead 63 is connected to the output of pulse gate 59 and feeds into a peaker 64 which has an output lead 65. The characteristics of peaker 64, or whatever equivalent electronic component is used, are such that it produces a sharp pulse coinciding with the trailing edge or trailing steep side 66 of each write pulse 62. This is shown in Fig. 14 where the sharp pulses 67 are shown as coinciding substantially in time relation with the trailing steep sides 66 of the write pulses 62. Sharp pulses 67 are hereinafter referred to as shift pulses (Sh pulses).

Again referring to Fig. 13, it will be observed that lead 68 is connected to the output lead 65 of pulse gate 64 and feeds into a suitable electronic delay device indicated by block 69. The output from the delay device feeds into a pulse gate 70 which has an output lead 71. The characteristics of delay device 69 and pulse gate 70, or whatever suitable equivalent component is utilized, are such that pulses appear on lead 71 which are delayed a minute fraction of time from the write and shift pulses which appear on output leads 61 and 65 respectively. This is shown in Fig. 14 where the sharp pulses 72 are shown as being delayed timewise from the write and shift pulses. The delay is such that a pulse 72 occurs after a write pulse in approximately one-third of the interval of time between write pulses. This can be observed from Fig. 14 where it will be noted that the indicated positioning of a pulse 72 is approximately the first third of the distance between successive write pulses 62. Pulses 72 are sometimes hereinafter referred to as CP1 pulses.

Again referring to Fig. 13, it will be noted that lead 73 is connected to output load 71 and feeds into a suitable electronic delay device designated by block 74 which in turn feeds into a pulse gate 75, or suitable equivalent device, having an output lead 76. Delay device 74 and pulse gate 75 operate like delay device 69 and pulse gate 70 to provide output pulses on line 76 which are sharp pulses spaced timewise from the write, shift and CPI pulses. This is shown in Fig. 14 where the sharp pulses 77 are shown as occurring after their associated write, shift, and CPI pulses. The delay is such that a particular CP2 pulse 77 occurs in approximately two-thirds of the time from one write pulse to the next succeeding write pulse. This can be observed from Fig. 14 where it will be noted that the pulse position 77 is indicated as being roughly two-thirds of the distance between write pulses 62 going from left to right.

It is therefore evident that each time that magnetic induction reading head 48 senses a magnetized area in the clock pulse track, four timing pulses are produced. The first is a write pulse 62, the next is a shift pulse 67, the next is a CPI pulse 72, and the next is a CP2 pulse 77. Furthermore, all of these pulses result before the reading head 48 senses the next succeeding magnetized area. With magnetic drum 47 rotating at a relatively high rate of speed, it is apparent that the pulse production is extremely rapid and that the apparatus is therefore capable of very high speed operation electronically.

Another timing track permanently recorded on the magnetized surface 46 of magnetic drum 47 is a socalled word pulse track designated by the dotted line 78 in Fig. 15. This track contains discrete areas magnetized as yes bits of information and spaced uniformly apart so that there is a spacing of 24 digit positions between each adjacent pair of such magnetized areas. Thus, in contrast to the clock pulse track which has a yes magnetized area for every one of the 25 digit positions constituting a word, the word pulse track has only one yes magnetized area per word. However, four different timing pulses are derived from the word pulse track and this is accomplished by the circuitry shown in Fig. 15.

Referring to Fig. 15, it is noted that three magnetic induction reading heads 48 read the word pulse track 78. These three magnetic induction reading heads are physically positioned or spaced with respect to each other so that they are a predetermined number of digit positions from each other. This means that if a yes magnetized area passes under one of the magnetic induction reading heads and travels on at a constant speed to pass under the next reading head, then the signal derived from the second reading head will occur after the first reading head signal a predetermined period of time. In the example shown in Fig. 15, and in accordance with a preferred practice according to the teaching of the present invention, pulses are derived from the word pulse track at the ninth digit position of a 25 digit position word, the 17th digit position, and the 25th digit position. This means that the reading heads 48 which originate the 17th and 25th digit position signals must be spaced exactly right with respect to the reading head 48 which originates the 9th digit position signal so that the 17th digit position signal will occur 8 digit positions in time behind the 9th digit position signal and the 25th digit position signal will occur 8 digit positions in time behind the 17th digit position signal When a yes magnetized area on the word pulse track 78 passes under the magnetic induction reading head 48 which originates the 9th digit position signal (the right hand reading head 48 as shown in Fig. a pulse is fed to amplifier 79 and from the amplifier to gate 80. A CPI clock pulse (see Fig. 14) is shown as being fed into gate 80 on CPI clock pulse lead 71. The characteristics of gate 80 are such that this gate, in effect, gates the CPI pulse through during the 9th digit position of each 25 digit position word so that a CPI pulse appears on output lead 81 during every such 9th digit position. Since the CPI pulse is a sharp short duration pulse it is apparent that the output of gate 80 is a sharp short duration output signal which occurs precisely during the 9th digit position in any given word. The fact that the CPI pulse is gated during the 9th digit position is indicated by the symbol P9-CP1 shown in Fig. 15.

The magnetic induction reading head 48 which originates the 17th digit position signal feeds into an amplifier 82 which in turn feeds into a gate 83. A shift pulse (Sh pulse) is also applied to gate 83 on shift pulse output lead 65 (see Fig. 13) during each clock pulse time so that when the gate receives a signal from amplifier 82, the sharp short duration shift pulse is gated through by gate 83 and appears on lead 84 as an input to flipflop 85.

The shift pulse which is gated through by gate 83 is actually the shift pulse produced on the trailing edge of the 16th digit position clock pulse. This shift pulse is applied to flipflop 85 and the latter introduces an additional digit position delay in changing to its set state. Thus, when the shift pulse is gated through to lead 84, it sets flipfiop 85 causing lead 86 to become high during exactly the 17th digit position (17th clock pulse time). When flipfiop 85 is set, lead 86 is high and lead 87 is low. The latter therefore represents the not 17th digit position signal (rzP17). Flipfiop 85 is reset by the next succeeding CPZ! clock pulse fed in on lead 76 and which follows the shift pulse which set the fiipfiop. As is shown in Fig. 14 the CP2 pulse trails the shift pulse so that the resetting action can take place as just described.

During the 24th digit position (24th clock pulse time), the left hand magnetic induction reading head 48 shown in Fig. 15 reads a yes magnetized area appearing in word pulse track 78 and emits a signal which is fed to amplifier 83. The amplifier output signal is, in turn, fed to gate 89. A CPZ clock pulse is also fed to gate 89 via lead '76 during each clock pulse time. Therefore, when amplifier 83 feeds a signal to gate 89, the characteristics of the gate arc sch that the CPZ pulse is gated through and appears on lead 90 to set flipfiop 91. Since the CP2 pulse was fed to gate 89 during the latter part of the 24th clock pulse time and prior to start of the 25th clock pulse time (see Fig. 14 for the relative spacing involved) then fiipflop 91 is set during the 25th clock pulse time and consequently flipflop output lead 92 is high during the 25th clock pulse time. correspondingly flipflop output lead 93 is low during the 25th clock pulse time. Lead 92 therefore bears the designation EWP 16 meaning end of word pulse and lead 93 bears the designation nEWP meaning not end of word pulse.

Flipfiop output lead 92 feeds to gate 94 which has a CPZ pulse fed thereto via lead 76 during each clock pulse time. Therefore, this 0P2 pulse, which occurs during the latter portion of the 25th clock pulse time and precedes the next succeeding clock pulse time which is the first clock pulse time for the next word (pulse occurring during the first digit position) is gated through by gate 94 and goes via lead 95 to reset fiipfiop 91. This CP2 pulse also sets fiipfiop 96 so that during the first clock pulse time of the next succeeding word, output lead 97 is high and output lead 98 is low. These leads therefore are also indicated as P1 meaning a pulse occurring during the first digit position of a word and nPl meaning no pulse during the first digit position of a word. Flipfiop 96 is reset by the CPZ pulse which occurs during the latter part of the first clock pulse time, this CPT pulse being fed into gate 99 via lead 76. Gate 99 gates this CP2 pulse through and the latter is fed via lead 100 to reset fiipflop 96. Lead 100 is therefore also indicated as having a P1-CP2 signal applied thereto meaning the CPZ pulse which occurs during the latter part of the first clock pulse time.

When flipfiop 91 or 96 is set, flipflop output lead 92 or 97 is high for a relatively long period of time as compared to the duration of any clock pulse. This is shown in Fig. 16 where the relatively wide pulse 101 represents the EWP pulse appearing on line 92. When the CP2 pulse fed to gate 94 on line 76 is gated through by this particular gate it resets ilipflop 91 so that pulse 101 terminates abruptly. This is evident from the relative posititioning of the EWP-CPZ pulse 102 shown in Fig. 16 as compared to the EWP pulse 101. The same relation holds for the P1 pulse which appears on flipflop output lead 97, this pulse being indicated by the reference numer' al 103 in Fig. 16, which is terminated abruptly by the P1-CP2 pulse indicated by the reference numeral 104 in Fig. 16.

The various clock pulses and the various pulses derived from the word pulse track are fed to various flipflops and gates involved in carrying out operations capable of being performed by apparatus according to the present invention. Of course, what pulses, flipfiops and gates are involved at a given time depends upon the particular operation being carried out. However, it is to be understood as a general proposition, that every fiipflop is controlled by at least one of the clock pulses which occurs during every clock pulse time so that the flipflop will be set or reset at precisely the correct clock pulse time involved.

COMMAND As is indicated by the clock diagram shown in Fig. 1, during operation of apparatus in accordance with the teaching of the present invention, data may transfer from one part of the apparatus to another part of the apparatus. Usually, this transfer is from a line, or track, of the memory, through Other parts of the apparatus wherein the data is modified in some manner, and then back to a line, or track, of the memory. Such transfer is in response to a so-called comman which is also a 25- digit length word and which is read from an appropriate track on the memory just as words representing numbers are read from the memory.

Fig. 17 shows the make-up of a command according to the teaching of the present invention. According to this figure, the command has a length of 25 digit positions, i.e. will occupy 25 sequential discrete areas in a memory line. When the command is recorded in a line, or track, 56 on the magnetizable drum surface 46, line one of seven lines for example, the 25 sequential discrete areas which represent the command will be magnetized as yes or no bits of information in order to represent the particular command involved properly according to the binary number system.

Fig. 17 shows that the 25 digit positions constituting a command word are grouped into different groups and that the different groups control different aspects involved in accomplishing transfer of data. Thus, it is noted that digit positions 1 and 17 are labeled characteristic (Ch). Characteristic includes such types of transfer, for example, as transfer unchanged, transfer absolute value, or transfer for addition or subtraction. Since two digit positions are utilized for the characteristic, it is readily possible to specify the types of transfer mentioned according to the binary number system.

When a magnetic induction reading head 48 reads the discrete areas in digit positions 1 and 17 (the reading of the area in digit position 1 occurring first in time sequence), P1 and P17 pulses can result if these areas are magnetized as yes bits of information. It is thus possible to ottain P1 and P17 pulses, to obtain neither pulse or to obtain a pulse for only one of these digit positions. According to the binary system this gives the possibilities of 11, O, 01 or and it is therefore evident that the four possibilities of simple transfer, absolute value transfer, add or subtract may be specified.

Again referring to Fig. 17 it is observed that digit positions 2-5 are labeled source (S). Source means where the data is transferred from or, to put it another way, where the data which is fed to the Early Bus 6 originates. The usual sources are the various long lines or tracks on magnetizable drum surface 46.

Since four digit positions are allotted to determine source, it is apparent that, according to the binary number system, up to sixteen possible sources may be designated. Thus, when a magnetic induction reading head 48 reads discrete areas in digit positions 2-5 an electrical pulse will be produced each time that the reading head reads an area magnetized as a yes (1) bit. Assuming that none of the four areas is magnetized as a yes bit then the output from the reading of these four areas will be 0000 which designates the 0 source. Conversely, if each area is magnetized as a yes bit then the reading head wiTl produce four electrical pulses (1111) which designates source 15. Thus, by having a range from 0 to 15, any one of 16 sources may be designated. It is to be understood that a source, such as a long line of the memory, may contain a number of words. Once the source has been designated, another part of the command (T) determines what particular word of the source is to be transferred. The possible pulses which may be derived from the reading of discrete areas in digit positions 2-5 are designated P2, P3, P4, and P5.

Again referring to Fig. 17 it is noted that digit positions 6-9 are labeled destination (D). Destination means where the data is to be transferred to or, to put it another way, where the Late Bus 7 sends the data. It is apparent therefore that digit positions 6-9 correspond in function to digit positions 2-5 and further detailed description concerning the destination digit positions is deemed unnecessary. Any one of sixteen possible destinations may be selected and the pulses which may be derived from the reading of discrete areas in digit positions 6-9 are identified as P6, P7, P8 and P9. It is apparent that these pulses occur subsequent to any source pulses P2-P5.

Again referring to Fig. 17, it is observed that digit positions 10-16 are labeled time of next command (Tc). Time of next command means where the next 25 digit length word which is to serve as a command is located in terms of its word position in a particular line, or track, on the magnetizable drum surface which contains command words. In a preferred practice of the present invention, command words will be located in line zero (0), in other words, in the first long line of the seven long lines on the drum surface although additional lines may be used also if desired. Since a long line is stated to have 128 words it is necessary to provide enough digit positions in each command word to select any word position from word position 0 to word position 127 in the long line, or

track, which contains the command words. By providing digit positions 10-16 there are seven available digit positions and in the binary number system 27 equals 128. Digit positions 10-16 can therefore designate any command word from a command word located in word position 0 of the command line up to a command word in word position 127 of the command line. As a magnetic induction reading head 48 reads the discrete areas in digit positions 10-16, pulses which may be produced from such reading are identified as P10-P16 pulses, these being Tc pulses.

Referring back to Fig. 17, it is noted that digit positions 18-24 are labeled time of transfer (T). Time of transfer means during which word time, or word times, one or more of the words in a line, or track, on drum surface 46 is to be transferred. Since digit positions 18-24 total 7 positions then, as described above in connection with digit positions 10-16, any word from word 0 to word 127 in any of the long lines, or tracks, on the drum surface may be designated by its numerical position in the long line and this determines during which word time actual transfer will take place if but a single word is to be transferred. As is described more fully hereinafter, plural word transfer is also possible. Pulses which may be produced from the reading of discrete areas in digit positions 18-24 are identified as PIS-P24 pulses, these being T pulses.

The 25th digit position shown in Fig. 17 determines whether a command is an immediate or a deferred command. An immediate command is one which causes transfer of data to occur beginning with the very next word time following the actual reading of the command. In other words, transfer starts with the first digit of the word which immediately succeeds the 25th digit of the command word. A deferred command is one in which transfer starts one or more word times following the word time during which the command is actually read. If the command is read in word position 0, deferred transfer can occur as late as during the next succeeding word position 0. This is. of course, the maximum delay possible with 128 word lines. A pulse which may be produced by reading a discrete area in the 25th digit position of the command word is designated P25, or the UB pulse.

As is brought out more fully hereinafter, a deferred command causes transfer to take place for exactly one single length word time. In contrast, an immediate command can cause transfer to take place during one word time or during all of the word times of a long line, or track, on the drum surface. Thus, with just one command it is possible to transfer all of the 128 words in a long line, or track, on the drum surface. It is to be noted, furthermore, that the command shown in Fig. 17 and described above is a two-address command in that it not only gives the address of the source but it also gives the address of the destination. Also, in chain fashion, so to speak, each command links to it the next command to be obeyed.

Fig. 18 is a circuit diagram showing how the command pulses are made available. Dotted line represents a line, or track, on drum surface 46 which contains command words. As stated above, command words are preferably located in the first long line, or track, on the drum surface. Wherever they are located, a particular command word being read will, during the reading, pass under a magnetic induction reading head 48 digit by digit in sequence starting with the digit in the first digit position and ending with the digit in the 25th digit position. Each time that the magnetic induction reading head 48 reads a discrete area magnetized as a yes bit of information (a 1) it will send a pulse to amplifier 106 which in turn feeds to gate 107. The characteristics of gate 107, or whatever equivalent electronic component is utilized in lieu thereof, are such that each time it is thus energized it will gate a CPI pulse which is fed into the gate on CPI pulse lead 71. Each CPI pulse thus gated is fed via lead 108 and sets flipflop 109 causing ipflop output lead 110 to go high, the latter also being designated as the C bus (command bus). Flipflop output lead 111, connected to the other side of the flipflop, is obviously the not command bus and hence is also desig' nated aCo. Command pulses P1 to P45 can thus appear on bus 110 depending upon the state of flip-flop 110. The pulses which appear on bus 111 are therefore obviously the complement of the pulses which appear on bus 110.

Fig. 18 shows that the command word recirculates so that it is recorded back onto the command line. Recirculation occurs because each time that fiipflop 109 is set lead 112 goes high and energizes pulse gate 113. The characteristics of the pulse gate are such that it gates a write pulse fed into it on WP line 60 (see Fig. 13) each time that the gate is energized by lead 112 going high. The gated write pulses energize magnetic induction writing head 52 which magnetizes discrete areas on the drum surface to correspond to the pattern, or timing, of the write pulses. The command word is thus recorded in exactly the same sequence and with exactly the same make-up as it was read. Flipflop 109 is reset by a shift pulse fed to it on Sh line 65 immediately following each write pulse which appears on line 60. Erase head 53 is omitted in Fig. 18 since it is to be understood that there is always an erase head between a reading head and a writing head.

SOURCE AND DESTINATION SWITCHING As the command word is read, pulses produced on C0 bus 110 and nCo bus 111 during the reading of the discrete areas in digit positions 2-9 are fed to the source and destination switching parts 2 and 4 of the apparatus (see Fig. 1). More precisely, the PZ-PS pulses proceed through the destination switching part and into the source switching part followed by the P6P pulses which go into the destination switching part but not beyond it.

Fig. 19 shows the destination switching part which is designated generally by block 4 in Fig. 1. The source switching part designated generally by block 2 in Fig. l is not shown separately in Fig. 19 since it is exactly the same in arrangement as the destination switching part, it being understood that if the source switching part were shown it would be connected to the destination switching part by the two lines 114 and 115 shown in Fig. 19 and would be an exact replica of the destination switching part with the lines 114 and 115 corresponding to bus lines 110 and 111. This is the reason that, in the left hand portion of Fig. 19, the source coding S0 to 87 appears beside the destination coding D0 to D7.

As the discrete areas in digit positions 2-5 of the command word are read, or sensed, any pulses fed through to C0 bus 110 proceed into the fiipfiop register shown in Fig. 19 and are shifted along by shift (Sh) pulses which occur each clock pulse time. These shift pulses are fed into the fiipfiop register on line 116 (the Csh time) which, as is described hereinafter, comes from the control part 16 of the apparatus. Assuming, for example, that a P2 pulse appears on bus 110, this pulse, in effect, passes through coincidence gate 117 when the next shift pulse appears on line 116 and sets fiipfiop 118. When fiipllop 118 is thus set, flipflop output lead 119 is high. Hence, when the next shift pulse appears on line 116, gate 120 output lead 121 goes high thus setting flipflop 122.

The same shift pulse which causes lead 121 to go high, as just described, also resets flipflop 118 by causing coincidence gate 123 output lead 124 to go high. The new state of fiipflop 122, that is, the set state, is thus the old state of flipflop 118 as it existed immediately prior to the shift pulse just mentioned. Now this shift pulse has caused fliptlop 118 to become reset. Therefore, in the flipflop register being described, each flipfiop which is reset by a shift pulse, in effect, preserves its state immediately prior to the shift pulse long enough for this state to be transferred to'the next succeeding flipflop. If additional circuit components are desired to increase the delay time during which, in effect, a particular flipfiop retains its state so that the flipflop has a longer time to transfer its state to the next succeeding flipflop, then such additional delay components may be provided as will be understood by those skilled in the art.

The pulse shifting thus continues during the time interval in which the discrete areas in digit positions 2--9 of the command word are read. At the end of this time interval, any P2P5 pulses (source pulses) have set the proper fiipfiops in the source switching part of the apparatus. Likewise, any P6-P9 pulses (destination pulses) have set the proper ones of the four destination flipflops in the manner described above in regard to two of these flipfiops 118 and 122. Whether a particular source or destination fiipflop remains set at the end of the time interval depends on whether the corresponding discrete area is magnetized as a yes (1) bit of information. Thus, fiipfiops 118 and 122 will remain set if there is a yes area in digit positions 9 and 8, respectively, of the command word. As is explained more fully hereinafter, the command shift pulses (Csh pulses) cease to appear on line 116 immediately following the reading of the magnetized area in digit position 9 of the command word and hence all of the coincidence gates whose output leads connect to the source and destination flipfiops, such as gates 117 and 123 for example, are blocked after any P9 pulse has entered the destination switching part.

Depending upon the final set, reset states of the source and destination llipfiops, the two input leads to one of the four coincidence gates 125 shown in Fig. 19 will be high and likewise the two input leads to one of the four coincidence gates 126 will simultaneously also be high. This means that one of the four gate output leads 127 will be high at the same time that one of the four gate output leads 128 is high. Signals are thus produced on two of eight lines which gives sixteen possible combinations of pairs of lines thus enabling any one of sixteen destinations to be selected and, in similar manner, any one of sixteen sources. The output leads of the various source and destination flipfiops thus connect to gates which partially decode the switching information into signals on two of eight lines. As is brought out more fully hereinafter, the rest of the decoding takes place at other gates which actually pass the data which is caused to be transferred by the command involved.

TRANSFER GENERALLY General recirculation of data from a line, or track, on the memory surface back onto the same line, or track, has been described above in connection with Figs. 10 and 11. However, for a more detailed description, reference is made to the typical memory circuit shown in Fig. 20. In Fig. 20 the dotted line 129 represents one of the seven assumed long lines on the memory drum surface. It will be recalled that such a line, or track, is said to contain 128 25 digit length words.

As the magnetic drum 47 rotates, reading head 48 senses the yes magnetized discrete areas which represent ls in the digit positions involved, the absence of a yes area in any digit position of course representing a zero in that digit position. Each time that a yes magnetized area is sensed, the resulting pulse is amplified by amplifier 130 and appears on lead 131 as an input to coincidence gate 132. A CPI clock pulse also feeds into gate 132 on CPl clock pulse line 71. Therefore, at CPI clocl: pulse time, a signal, or sharp pulse, is fed on lead 133, through junction lead 134, and into flipflop 135 on lead 136 setting the flipflop. The flipfiop output lead 137 goes high thus energizing pulse gate 138. The characteristics of pulse gate 138 are such that it, or whatever equivalent electronic component is used in its place, gates a write pulse (another clock pulse, it will be recalled) fed into the pulse gateon write pulse lead 60. The

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