GB749836A - Electronic system for computing and otherwise handling information - Google Patents

Abstract

749,836. Digital electric calculating-apparatus; electric digital-data-storage apparatus. REMINGTON. RAND, Inc. March 30, 1953 [March 31, 1952], No. 8700/53. Class 106 (1). In an electronic system for storing, transferring and processing information in accordance with predetermined instructions, the information and instructions having alphabetical, numerical and symbolical significance and being represented by electric impulse groups according to a combination code, comprising conversion means, analyzing and distinguishing means, manipulation and utilization circuits including computing apparatus for the performance of mathematical processes, control circuits, and interconnection means, the conversion means converts impulses within a group which arrive at the input of the system in parallel into impulses in serial disposition in time and/or converts impulses within a group which arrive at the output from the system in serial disposition into impulses in parallel, the analyzing and distinguishing means receive impulse groups, distinguish between groups which are representative of numerical information and other groups, and keep the other groups from being utilized in mathematical processes, the manipulation circuits store, transfer and otherwise handle information in processes other than mathematical, the utilization circuits use information in mathematical processes, the control circuits control the operation of the utilization and manipulation circuits in accordance with the instructions, and the interconnection means include common transmission circuits to which the inputs and the outputs of the conversion means, the analyzing and distinguishing means and the manipulation and utilization circuits are selectively connected in accordance with instructions for the transmission of information thereamong. General arrangement.-The computing system described comprises a main element COM, Fig. 1, connected to the control unit SC and to, e.g. ten, magnetic-tape " transducers " TT which provide input and output as well as an auxiliary memory, for the element COM. Input information is entered on the magnetic tapes by one or more keyboard-operated " typers T and output information is read from the tapes, decoded and printed by one or more printers P. The computing element COM is similar to the computor described in Specification 736,144 but handles information (both alphabetic and numerical) in a combination code as described below. It comprises a main mercury tank memory MM, Fig. 2, and mercury-delay-line registers including the following which each store a single word:-registers CC (control counter) and CR (control register) which have similar functions to the corresponding registers described in Specification 736,144; an "X" register for storing a multiplier or quotient, an " L " register for storing a multiplicand or divisor; an "F" register for storing three times a multiplicand and an "A" register which with an " algebraic adder AA forms an accumulator. Additional " V " and " Y " registers store two and ten words respectively, and input and output registers I and O each store 60 words. One-word synchronizing registers SYI1, SYI2 and SYO1, SYO2 (not shown in Fig. 2) also are provided in the input and output circuits. As in the computor of Specification 736,144, information is transferred via a "high speed bus amplifier" HSBA, instructions are set up on a "static register " or staticiser SR having an address section associated with MM and a function section associated with re-coding gate-controlling matrices or function tables FT and timing control pulses are supplied from a pulse generator and a cycling unit CU; a normal cycle of operations comprises steps α, #, y, # controlled by a " cycle counter " CY, and extended operations such as multiplication and division are controlled by a " programme counter " PC. The element COM comprises also a sign and magnitude comparator CP, a multiplier-quotient counter MQC and checking circuits such as OFC associated with HSBA. Some of the registers and other devices are duplicated and mutually checked. The unit SC includes a data-entering keyboard, control switches, neon indicators and a printer. Detailed circuits of most of the system are given. These electronic circuits include trigger pairs of hard valves having-one and two stable states, called " delay flops " (DF) and " flipflops " (FF) respectively, germanium diode coincidence gates (G), " or " gates or buffers (B), pulse shaping circuits (PFR) described below, and anti-coincidence circuits or " quarter adders " (Q). Trigger pairs having symmetrical inputs and used as binary counters (BC) and delay flops employing thyratrons, called " thyraflops " (TF), are also employed. Word code.-A word length or minor cycle comprises 91 pulse times P0-P90, Fig. 159, divided into 13 sections of which 12 may each store a character (decimal digit, letter, &c.) according to a 7-digit binary combination code, the 13th section being blank to provide a space between words (SBW). The word may comprise, e.g., an 11-digit decimal number with sign, or two 6-character instructions, Fig. 154, in which 3 characters define a location in the main memory, 2 characters define the type of instruction, and 1 character is always zero (unused). In the code, the 7 digits are divided into a 4-digit " excess-three " portion XS3, Fig. 167, a 2-digit zone, and a check digit. Decimal digits are represented by the excessthree code, e.g. " 1 " is represented by the binary number 4=0010 (the least significant digit being on the left) the zone digits being 00, and letters A, B, C, &c. in increasing numerical order of the combined XS3 and zone digits. The check digit is always such as to make the total number of " 1's " odd. Plus and minus signs are represented by 1100 00 1 (zero) and 0100 00 0 respectively. Timing pulse generator.-Timing or clock pulses of 0.08 Ás at a frequency of 2.25 mc/s. are generated by an arrangement similar to that described in Specification 736,144 including a crystal-controlled oscillator whose sinusoidal output is supplied through a ringing circuit to a clipper, the stabilized output of which comprises a series of sharp positive master timing pulses. The latter are supplied to local " clock gate driving " circuits each of which includes a transformer having two output windings which supply positive and negative timing pulses (TP+ and TP - ) respectively. Pulse-shaping circuits ; timing pulse or " clock " gates.-The timing pulses TP+ and TP - are applied to " clock " gate circuits PFR such as that shown in Fig. 19, so as to re-shape a series-mode non-return-to-zero signal (positive for " 0," negative for " 1 ") applied to the control grid of a normally conducting valve V1 (conduction being indicated by shading). When a negative " 1 "-representing signal pulse cuts off the valve, the raised anode potential allows the next TP+ pulse to be gated via point A to the control grid of valve V2 of trigger circuit PF so that the latter is switched over to the " 1 "-representing condition at the midpoint of the input pulse. PF remains in this condition until the input signal to V1 returns to positive when the correct anode potential allows the next TP-pulse to be gated via point B and to restore the PF to the condition shown. Non- return-to-zero outputs are obtained from the tappings indicated in the anode circuits of the trigger valves V2, V3. Cycling unit.-This comprises two pairs of delay line loops in each of which a single pulse is circulated; the loops in each pair have delays of 7 and 13 pulse lengths respectively, and outputs obtained from selected tappings of these loops are combined in coincidence gates to produce selected pulses t0-t90 defining the pulse positions in a minor cycle, Fig. 159 (" t " denoting absolute time). The t-pulses are produced independently from each pair of loops and checked against one another and against the output from the end of an auxiliary 27- pulse-length delay line from which further tappings are taken, any error in the selective timing being registered on a trigger circuit which stops further operations of the computer. Main memory.-This comprises 7 mercury tanks each containing 18 ten-word channels. Only 100 of these channels are used to form the main information memory; 6 channels are used for each of the registers I and O, Fig. 2, 1 for the Y-register, 1 in each tank for temperature control, and 6 channels are spare. Each information circulation circuit comprises, from the mercury channel ML, Fig. 52, an intermediate frequency amplifier IFAD and further amplifier A, with automatic gain control AGC, a delay network DC, gate CG, pulse-shaping circuit PFR and mercury delay line driver MLD. When information is to be read out or entered in a channel, signals from SR, Fig. 2, applied to control gate GT, cause the opening of output and input gates G0, G1, connected by lines HSB1M, HSB2M to the amplifier HSBA; for entry of information, also a signal TSR applied through gate G<SP>1</SP>R inhibits recirculation gate CG. For highly sensitive automatic temperature control, the current through a heating coil is determined by the degree of coincidence between a timing pulse delayed in the temperature control channel and a further pulse applied directly to a coincidence gate. A standby control system also is provided including a bellows-controlled microswitch. Amplifier HSBA.-As shown diagrammatic-. ally in Fig. 64, information from duplicate registers A, X, F, L and #A, #X, #F, #L or from duplicate output gates of registers CC, CR, V,Y, SYI1, SYI2, supplied to duplicate buees HSB1A, #HSB1A, is sent to register input gates via output buses HSB2A, #HSB2A respectively; also either of the buses HSB1A, #HSB1A is connected to the memory MM through a switch SWI and bus HSB2M, and either of HSB2A, #HSB2A may be connected to register SY02 through switch SW2. Informati