US2940669A  Radix converter  Google Patents
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 US2940669A US2940669A US415286A US41528654A US2940669A US 2940669 A US2940669 A US 2940669A US 415286 A US415286 A US 415286A US 41528654 A US41528654 A US 41528654A US 2940669 A US2940669 A US 2940669A
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 FAPWRFPIFSIZLTUHFFFAOYSAM sodium chloride Chemical compound data:image/svg+xml;base64,PD94bWwgdmVyc2lvbj0nMS4wJyBlbmNvZGluZz0naXNvLTg4NTktMSc/Pgo8c3ZnIHZlcnNpb249JzEuMScgYmFzZVByb2ZpbGU9J2Z1bGwnCiAgICAgICAgICAgICAgeG1sbnM9J2h0dHA6Ly93d3cudzMub3JnLzIwMDAvc3ZnJwogICAgICAgICAgICAgICAgICAgICAgeG1sbnM6cmRraXQ9J2h0dHA6Ly93d3cucmRraXQub3JnL3htbCcKICAgICAgICAgICAgICAgICAgICAgIHhtbG5zOnhsaW5rPSdodHRwOi8vd3d3LnczLm9yZy8xOTk5L3hsaW5rJwogICAgICAgICAgICAgICAgICB4bWw6c3BhY2U9J3ByZXNlcnZlJwp3aWR0aD0nMzAwcHgnIGhlaWdodD0nMzAwcHgnIHZpZXdCb3g9JzAgMCAzMDAgMzAwJz4KPCEtLSBFTkQgT0YgSEVBREVSIC0tPgo8cmVjdCBzdHlsZT0nb3BhY2l0eToxLjA7ZmlsbDojRkZGRkZGO3N0cm9rZTpub25lJyB3aWR0aD0nMzAwJyBoZWlnaHQ9JzMwMCcgeD0nMCcgeT0nMCc+IDwvcmVjdD4KPHRleHQgeD0nNjkuNzcxNicgeT0nMTcwJyBjbGFzcz0nYXRvbS0wJyBzdHlsZT0nZm9udC1zaXplOjQwcHg7Zm9udC1zdHlsZTpub3JtYWw7Zm9udC13ZWlnaHQ6bm9ybWFsO2ZpbGwtb3BhY2l0eToxO3N0cm9rZTpub25lO2ZvbnQtZmFtaWx5OnNhbnMtc2VyaWY7dGV4dC1hbmNob3I6c3RhcnQ7ZmlsbDojM0I0MTQzJyA+TjwvdGV4dD4KPHRleHQgeD0nOTcuMzcxNicgeT0nMTcwJyBjbGFzcz0nYXRvbS0wJyBzdHlsZT0nZm9udC1zaXplOjQwcHg7Zm9udC1zdHlsZTpub3JtYWw7Zm9udC13ZWlnaHQ6bm9ybWFsO2ZpbGwtb3BhY2l0eToxO3N0cm9rZTpub25lO2ZvbnQtZmFtaWx5OnNhbnMtc2VyaWY7dGV4dC1hbmNob3I6c3RhcnQ7ZmlsbDojM0I0MTQzJyA+YTwvdGV4dD4KPHRleHQgeD0nMTE4LjYyNicgeT0nMTU0JyBjbGFzcz0nYXRvbS0wJyBzdHlsZT0nZm9udC1zaXplOjI2cHg7Zm9udC1zdHlsZTpub3JtYWw7Zm9udC13ZWlnaHQ6bm9ybWFsO2ZpbGwtb3BhY2l0eToxO3N0cm9rZTpub25lO2ZvbnQtZmFtaWx5OnNhbnMtc2VyaWY7dGV4dC1hbmNob3I6c3RhcnQ7ZmlsbDojM0I0MTQzJyA+KzwvdGV4dD4KPHRleHQgeD0nMTg2Ljg0NicgeT0nMTcwJyBjbGFzcz0nYXRvbS0xJyBzdHlsZT0nZm9udC1zaXplOjQwcHg7Zm9udC1zdHlsZTpub3JtYWw7Zm9udC13ZWlnaHQ6bm9ybWFsO2ZpbGwtb3BhY2l0eToxO3N0cm9rZTpub25lO2ZvbnQtZmFtaWx5OnNhbnMtc2VyaWY7dGV4dC1hbmNob3I6c3RhcnQ7ZmlsbDojNUJCNzcyJyA+QzwvdGV4dD4KPHRleHQgeD0nMjE0LjQ0NicgeT0nMTcwJyBjbGFzcz0nYXRvbS0xJyBzdHlsZT0nZm9udC1zaXplOjQwcHg7Zm9udC1zdHlsZTpub3JtYWw7Zm9udC13ZWlnaHQ6bm9ybWFsO2ZpbGwtb3BhY2l0eToxO3N0cm9rZTpub25lO2ZvbnQtZmFtaWx5OnNhbnMtc2VyaWY7dGV4dC1hbmNob3I6c3RhcnQ7ZmlsbDojNUJCNzcyJyA+bDwvdGV4dD4KPHRleHQgeD0nMjIyLjkzMicgeT0nMTU0JyBjbGFzcz0nYXRvbS0xJyBzdHlsZT0nZm9udC1zaXplOjI2cHg7Zm9udC1zdHlsZTpub3JtYWw7Zm9udC13ZWlnaHQ6bm9ybWFsO2ZpbGwtb3BhY2l0eToxO3N0cm9rZTpub25lO2ZvbnQtZmFtaWx5OnNhbnMtc2VyaWY7dGV4dC1hbmNob3I6c3RhcnQ7ZmlsbDojNUJCNzcyJyA+LTwvdGV4dD4KPC9zdmc+Cg== data:image/svg+xml;base64,PD94bWwgdmVyc2lvbj0nMS4wJyBlbmNvZGluZz0naXNvLTg4NTktMSc/Pgo8c3ZnIHZlcnNpb249JzEuMScgYmFzZVByb2ZpbGU9J2Z1bGwnCiAgICAgICAgICAgICAgeG1sbnM9J2h0dHA6Ly93d3cudzMub3JnLzIwMDAvc3ZnJwogICAgICAgICAgICAgICAgICAgICAgeG1sbnM6cmRraXQ9J2h0dHA6Ly93d3cucmRraXQub3JnL3htbCcKICAgICAgICAgICAgICAgICAgICAgIHhtbG5zOnhsaW5rPSdodHRwOi8vd3d3LnczLm9yZy8xOTk5L3hsaW5rJwogICAgICAgICAgICAgICAgICB4bWw6c3BhY2U9J3ByZXNlcnZlJwp3aWR0aD0nODVweCcgaGVpZ2h0PSc4NXB4JyB2aWV3Qm94PScwIDAgODUgODUnPgo8IS0tIEVORCBPRiBIRUFERVIgLS0+CjxyZWN0IHN0eWxlPSdvcGFjaXR5OjEuMDtmaWxsOiNGRkZGRkY7c3Ryb2tlOm5vbmUnIHdpZHRoPSc4NScgaGVpZ2h0PSc4NScgeD0nMCcgeT0nMCc+IDwvcmVjdD4KPHRleHQgeD0nMTUuNjk3NicgeT0nNTMuNTkwOScgY2xhc3M9J2F0b20tMCcgc3R5bGU9J2ZvbnQtc2l6ZToyM3B4O2ZvbnQtc3R5bGU6bm9ybWFsO2ZvbnQtd2VpZ2h0Om5vcm1hbDtmaWxsLW9wYWNpdHk6MTtzdHJva2U6bm9uZTtmb250LWZhbWlseTpzYW5zLXNlcmlmO3RleHQtYW5jaG9yOnN0YXJ0O2ZpbGw6IzNCNDE0MycgPk48L3RleHQ+Cjx0ZXh0IHg9JzMxLjY5MzEnIHk9JzUzLjU5MDknIGNsYXNzPSdhdG9tLTAnIHN0eWxlPSdmb250LXNpemU6MjNweDtmb250LXN0eWxlOm5vcm1hbDtmb250LXdlaWdodDpub3JtYWw7ZmlsbC1vcGFjaXR5OjE7c3Ryb2tlOm5vbmU7Zm9udC1mYW1pbHk6c2Fucy1zZXJpZjt0ZXh0LWFuY2hvcjpzdGFydDtmaWxsOiMzQjQxNDMnID5hPC90ZXh0Pgo8dGV4dCB4PSc0NC4wMTA5JyB5PSc0NC4zMTgyJyBjbGFzcz0nYXRvbS0wJyBzdHlsZT0nZm9udC1zaXplOjE1cHg7Zm9udC1zdHlsZTpub3JtYWw7Zm9udC13ZWlnaHQ6bm9ybWFsO2ZpbGwtb3BhY2l0eToxO3N0cm9rZTpub25lO2ZvbnQtZmFtaWx5OnNhbnMtc2VyaWY7dGV4dC1hbmNob3I6c3RhcnQ7ZmlsbDojM0I0MTQzJyA+KzwvdGV4dD4KPHRleHQgeD0nNDMuMTU0NycgeT0nNTMuNTkwOScgY2xhc3M9J2F0b20tMScgc3R5bGU9J2ZvbnQtc2l6ZToyM3B4O2ZvbnQtc3R5bGU6bm9ybWFsO2ZvbnQtd2VpZ2h0Om5vcm1hbDtmaWxsLW9wYWNpdHk6MTtzdHJva2U6bm9uZTtmb250LWZhbWlseTpzYW5zLXNlcmlmO3RleHQtYW5jaG9yOnN0YXJ0O2ZpbGw6IzVCQjc3MicgPkM8L3RleHQ+Cjx0ZXh0IHg9JzU5LjE1MDEnIHk9JzUzLjU5MDknIGNsYXNzPSdhdG9tLTEnIHN0eWxlPSdmb250LXNpemU6MjNweDtmb250LXN0eWxlOm5vcm1hbDtmb250LXdlaWdodDpub3JtYWw7ZmlsbC1vcGFjaXR5OjE7c3Ryb2tlOm5vbmU7Zm9udC1mYW1pbHk6c2Fucy1zZXJpZjt0ZXh0LWFuY2hvcjpzdGFydDtmaWxsOiM1QkI3NzInID5sPC90ZXh0Pgo8dGV4dCB4PSc2NC4wNjg0JyB5PSc0NC4zMTgyJyBjbGFzcz0nYXRvbS0xJyBzdHlsZT0nZm9udC1zaXplOjE1cHg7Zm9udC1zdHlsZTpub3JtYWw7Zm9udC13ZWlnaHQ6bm9ybWFsO2ZpbGwtb3BhY2l0eToxO3N0cm9rZTpub25lO2ZvbnQtZmFtaWx5OnNhbnMtc2VyaWY7dGV4dC1hbmNob3I6c3RhcnQ7ZmlsbDojNUJCNzcyJyA+LTwvdGV4dD4KPC9zdmc+Cg== [Na+].[Cl] FAPWRFPIFSIZLTUHFFFAOYSAM 0.000 description 1
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Classifications

 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
 H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
 H03M7/02—Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word
 H03M7/12—Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word having two radices, e.g. binarycodeddecimal code
Description
June 14, 1960 G. w. HoBBs RADIX CONVERTER Filed March lO, 1954 5 SheetsSheet l ts t7 sof/M532 Inventor. George W Hobbs,
His Attorney.
June 14, 1960 G. w. HoBBs 2,940,669.
RADIX CONVERTER Filed March 10, 1954 5 SheetsSheet 2 20 o/ODES of? 6LOW TUBES j l I I l I I l I I I hvehtor: George W. Hobbs,
,His Attorney.
June 14, 1960 G. w. HoBBs 2,940,669
RADIX CONVERTER Filed March 1o, 1954 l5 sheetssheet s awe. munumo hvento: George W. Hobbs,
by 'mM/Pm His Attorney.
Jupe 14, 1960 G. w. Horsesl 2,940,669
RADIX CONVERTER Filed March l0, 1954 5 SheetsSheet 4 George W. Hobbs,
by MQW His Attorney.
June 14, 1960 G. w. HoBBs RADIX CONVERTER 5 SheetsSheet 5 Filed March l0, 1954 Inventor George W. Hobbs, uumlr His Attorney United States Patent O i RADIX CONVERTER George W. Hobbs, Scotia, N.Y.,vassignor to General Electric Company, a corporation of New York Filed Mar. 10, 1954, Ser. No. 415,286
` 17 Claims. (Cl. 23S155) This invention generally relates to number :radix translating systems, and more particularly to systems for converting numbers expressed in decimal notation to that of binary notation for purposes of computation or the like.
With the ever increasing reliance being placed upon digital calculating machines to solve longer and more complex mathematical problems has resulted the evolution of calculators of immense size having many thousands of parts and consuming tremendous quantities of power. Various means of simplifying the numerous and diversified arithmetic processes performed by these machines have long been sought, and it has been previously determined that the circuitry for performing these arithmetic functions may be greatly simplified in many instances by performing computations in the binary number system rather than in the decimal or other number system.
The representation of a number in binary notation, however, has the disadvantage of requiring more than three times as many digits as the representation of the same number in decimal notation. This fact coupled with the general familiarity in dealing with numbers in decimal form, makes it more desirable and expedient for the human operator to initially enter the problem in decimal form into the machine and provide a means within the machine itself `for converting this number into binary notation prior to performing the calculating functions. Such means have been termed by those skilled in the art as radix converters and where the numbered data in decimal form is converted into binary form, as decimal to binary converters.
`rIhe present invention provides such a converter for a high speed calculating device wherein numbers conventionally represented in decimal notation may be both automatically and instantaneously converted into binary notation. In accordance with the present invention, a multidigit number represented in conventional decimal form is initially stored in the device by means of a manually operated keyboard, punched card, or the like. Thereafter, in a series of sequential operations, each digit of this multiorder decimal number is individually converted into its binarycoded form and individually entered into a summing accumulator in additive relation with the other binarycoded digits. Upon the completion of these sequential operations, the resulting summation standing in the accumulator constitutes the binary number lform of the original decimally represented number. Since the various digits of the decimal number actually represent the product of that decimal digit and one of the various powers of the decimal radix such `as 10, 100, 1,000, 10,000, etc., dependent upon the notative position of this digit in the multiorder decimal number, the present invention incorporates means for entering each binarycoded digit into the proper stages of the binary accumulator by a process of shifting the binarycoded digits either before or after entry, thereby enabling this resulting summation to equal the actual binary equivalent of the original number.
ifice for translating a number expressed in one radix` toA that of another.
Other objects and many attendant advantages of this invention will be more readily comprehended to those skilled in this art upon a consideration of the following detailed description of preferred embodiments of the invention taken in conjunction with the accompanying drawings wherein:
Fig. 1 functionally illustrates one preferred embodiment of the invention, in block diagram form,
Figs. 2 and 3 schematically illustrate preferred cir' cuitry employed in this embodiment, v
iFig. 4 is a pulse waveform diagram depicting the time relation of the programming pulses generated by the circuitry of Fig. 3,
Fig. 5 is a block diagram functionally illustrating a second embodiment of the invention, and l.
Fig. 6 is an electrical diagram, partially in schematic form, depicting the additional circuitry of Fig. 5..
Prior to commencing the detailed description of the preferred embodiments of the invention, a more thorough comprehension thereof may be had by initially con Sidering the mathematical basis for the operations performed. Considering that any ve digit decimal number a b c d e may be expressed as the sum of the following four products and a decimal digit e:
binary `equivalent of a by the binary equivalent of 104 or 10,000; multiplying the binary equivalent of b by the binary equivalent of 103 or 1,000, and so forth.
Inasmuch as the binary equivalent of each above integral 10s multiple number is known as follows:
this process may be mathematically represented by allowing the capital letters A, B, C, D, and E to represent the binarycoded form of each of the decimal digits a, b; c, d, and e, respectively:
Since the only quantities that vary for each number conversion operation are the numerical values of the decimal digits a, b, c, d, and e, the resulting binary equivalent number may be expressed in terms of the binarycoded `form of these unknowns as follows:
(AO0AAA000A 0000) (BBBBBOBOOO) (CCOOCOO) (DODO) lE Patented June 14, 1960 represented in binary form as 00AMr3)(lB)B(BlC)(B+C)A(B+D)CDE wherethis later association of binarycoded digits mathematically represents the ordinal position of these digits or as mathematically expressed equals:
just as the association of decimal digits a, b, c, d, e Ymay be mathematically expressed as:`
To convert the decimal number a, b, c, d, and e, to its binary form in accordance with the a'bove mathematically illustrated process, therefore, each of these decimal digits a, b, c, d, e may beindividually converted into their binarycoded form A, B, C, D, and E, respectively, andthereafter each of these binary digits may be individually shifted and entered into various ordinal stages of a summing accumulatorV in accordance with the above designated physical arrangementfor may be individually entered in the accumulator and thereafter shifted tothe desired stages thereof as will be more fully comprehended hereinafter.
SYSTEM' BLOCK DrAGaAM Fig. 1
` Referring now to the block diagram of Fig. 1 for an overall consideration of one preferred embodiment ofthe present inventionoperating in accordance with this mathematical process, a decimal to binary digit converter 10, represented by the block labeled digit conversion matrix, generates the binarycoded form of any of the decimal digits 19, inclusive, over the four output lines numbered 11, 112, 13, and 14, in response to energization of a corresponding one of the nine numbered input lines entering therein. That is, energizing input line number 1 by an impulse results in a pulse being generated over` output line 14, representing the ibinarycoded form of decimal number 1 or (0001); similarly, .energizing input line 2 results in a pulse being generated over output line 13 connected thereto, representing the binarycoded form of decimal number 2 or (0010), or energizing line numbered 3 results in output pulses being generated over both lines 13 and 14, designating the'binarycoded form of decimal number 3 or (0011), `and `so forth. Y
A plurality of control lines 15, 16, 17, 13, and 19, one for each denominational order of the decimal number to be converted, are connected to carry impulses to the digit conversion matrix for sequentially converting each digit of the decimal number to its binarycoded form. Consequently, a pulse directed over control line 15 passes through keyboard 20 to the digit conversion matrix 10 resulting in the highest order decimal digit, a, being conmediate the control lines and the input lines to the digit conversion unit 10. This keyboard unit preferably comprises a series of vertical rows of switches labeled a, b, c, d, and e, one row for each order of the decimal number to be converted. Each of these rows a, b, c, d, and e, comprise a plurality of switches numbered 19, inclusive, having one terminalvof` each switch connected in common to a corresponding one of the control lines 15, 16, 17, 18, or 19 andthe other terminal thereof connected to a correspondingly numbered one of the nine input lines of the digit conversion unit 10. Thus, for example, should the keyboard digits 6, 3, 8,15, 0, be depressed, entering thedecimal number 63850 into the system, control, line 15 is connected through switch 6 of keyboard row a to the sixth input line of digit conversion unit 110; control line 16 is connected through verted into its binarycoded form A, and a plurality of I pulses representing A, being generated over output lines "11, 12, 13, and 14. Similarly, pulses directed over the remaining four control lines 16, 17, 13, and 19 pass through keyboard 20 to the digit conversion matrix 10 resulting in the lesser order decimal digits b, c, d, and e, respectively, being converted into their binarycoded VformsAB, C, D, and E, and impulses representing these l v switch 3 of keyboard row b to thethirdginputlline of digit Vconversion unit 10; control Yline 17 is connected through depressed switch 8 of keyboard row cto the eighthV input line of digit conversion unit 1t);k and control line 18 is connected through depressed switch 5' of keyboard column d to the ifth input line of digit conversion unit 10. Consequently, for each energizationof con# trol line 15, the binarycoded form of decimal digit 6 is generated by digit conversion unit 10; for each energization of control line 16, the binarycoded form of `decimal digit 3 is generated by digit conversion unit 10;
for each energization of control line 17, the binarycoded form of decimal digit 8 is' generated by digit conversion unit 10; and for each energization of control line 1,8, the binarycoded form of decimal digit 5 is generated by digit conversion matrix 10. v
Thus, the combination of the separate control lines 15, 16, 1'7, 18, and 19, the keyboard matrix 20, and the digit conversion matrix 10 provide the means for individually generating the binarycoded formof any of the decimal digits a, b, c, d, and e, where each of these digits may comprise any of the decimal numbersl 19, inclusive, that may be entered into the keyboard. p
For summing each of these binarycoded digits generated as a series of pulses over lines 11, 12, 13, and 14, by digit conversionfunit 10, a multistage shifting accumulator 26 is provided having the inputs of the vfirst' four stagesV thereof connected to additively receive' each of the binarycoded numbers. Accumulator 26 includes a plurality of cascaded binary counting stages, each stage having'a separate input and adapted Vto sum two pulses and after receiving the second pulse to generate a carryover pulse to the next succeeding stage.` The individual f The remainder of the system illustrated iri the. Ileft' of v the figure'generallyzcomprses programming control cirl cuitry for directing impulses over each of the control Vlines 15, 16, 17, 18, and 19, and the control shift line 27 in a stepbystep predetermined sequence'to individually convert each of the decimal Ydigits a, b, `c, d, and e into its binarycoded'forrn A, B, C, D, and E, respectively, and` to individually and collectively shift these binarycoded digits in the accumulator' to assumethe predetermined ordinal positions mathematically represented above as:
 A00A(A+)(Aimetete)(B+C)A{B+D)CDE y To facilitate an understanding of this programming system initiating the various Operations wherein. each digitk is individually converted to its binarycodedform and shifted to the abolire designated prearranged 'ordinalvposition in the accumulator stages, referenceis'now made to CHART I Time Operation Action Accumulator Reading Pulse Line 15 Add A A Pulse Shift Line 27 Shift Accumulator A0 Pulse Shift Line 27 Shift Accumulator A00 Pulse Shift Line 27 000 Pulse Line 15. Pulse shift Line Pulse Line l5. Pulse Line 16 Pulse Shift Line 27. Pulse Line l Add A Pulse Line 16 Pulse shift Lme 27 Pulse Line 15 Pulse Shift Line Pulse Line 16.. Pulse Line 17.. Pulse shift Lme 27 Pulse Llue B) (A+ Pulse Llne 17 Add C A00A(A+B)(A+B B(B+C)(B+C) Pulse shift Line 27 Shift Aeeumulater; AO0A(A B)(A+B)B(B+O B O Pulse Line AddA AO0A(A+B)(A+B)B(B+C) B o A Pulse shift Line 27 A00A(A+B)(AB)B(B+o) B+0 A0 Pulse Line 16 A00A(A+B)(A+B)B(B C (B+C)AB Pulse Line 1s A00A A+B (A+B)B(B+o) (P+C)A(B+D Pulse shift Line 27 A00A(A+B) (A+B)B(B+C)(B+O)A(B+D 0 Pulse Line 17 Add A00A(A+B)(A+B)B(B+G)(B+G)AB+D)C as maismensenmassa Pulse shift Lef III shift Accumulator A00A(A+B)(A+B)BB+C) B+o)A BD 0Do Pulse Line 19 Add E A00A(A+B)(A+B)B B+C)(B+C)A(B+D ODE the accompanying four column tabulated chart illustrating CHART II in the rst column thereof, labeled Time, the chronological time interval for each programmed operation; D im 1 Bum y illustrating ln the second column thereof, labeled Operaee a tion, the function performed by the programming sysg l tern at this time interval; illustrating in the third column c=8 l000=0 thereof, labeled Action, the result of this programmed gig wg function; and illustrating in the fourth column thereof, labeled Accumulator Reading, the resulting binary A 1. t d, number standing in the accumulator upon the completion Time wim a or rea mg of this operation. lg For example, considering the operation occurring at t, 11000 time to, a .pulse generated over control line 15 passes t lgg through the depressed key of column a of keyboard matrix m 20, thence entering the correspondingly numbered input 1101100 line of digit conversion matrix 10 to generate the binary +110 coded form of this decimal digit, A. These binarycoded te 1110010 pulses are then directed to the first four stages of shifting +l1. accumulator 2.6 resulting in the binary number A standing il in the flst `four stages of the accumulator. At time t1, s +110 the programming circuit directs a pulse over accumulator t9 1 1110000 shift line 27 and the number standing in the accumulator +11 26 is thereby shifted one place to the left res'ulting'in the 50 tm 11110011 accumulator reading of A0. Upon compleung thlrty of tu 111100111) these separate operations as indicated by the tabulated chart wherein each of the control lines 1S, 16, 17, 18, and lggg 19, and the shift line 27 are pulsed in a predetermined +11 time sequence, it is observed that the resulting number tu '11"11010101 standing in the accumulator is the desired binary equiva +1000 lent of the original decimal number. t1., 1111011101 For further clarifying this manner of entering and im lllloll) vshifting each of the binarycoded digits, a second twocolumn chart below is provided lfor illustrating this seil" 11110211118?) quence of operations employing the multidigit decimal 00.1: m number 63850. The first column of this chart, labeled ti: :In 111110001010 Tme, again indicates the time interval for each opera +110 tion, and the second column, labeled Accumulator Readno 111110010000 ing, illustrates the binary number standing in the act 1111100102922 cumulator upon the completion of this operation. Thus, it is observed that at time t0, ybinary number 110 (the t "r 111110012921111 binarycoded form of decimal number 6) has been entered t m IlO the aCCllmll'laOI. vAt time t1, Shift 11118 27 haS bCCIl i 11 1111100101000() energized by the programming circuit, resulting in the +1000 shifting of 110 (the binarycoded form of decimal 6) one 70 ne 11111001011000 place `to the left, and so forth. Following this chart it is t llloololflgg observed that upon the completion of these thirty operat Y tions, asv discussed above, the resulting number standing t?, 'j 11111082521111110211) in the accumulator then constitutes the binary form of 0 ythe originally entered decimal number 63850. ne 1111100101101010 7 Summarizing the programming presented by these charts, the programming systemat the left of the ligure comprises' a means for generating a predetermined sequence of pulses over vthe plurality of control lines and a control shift line; the pulses being generated over the various control lines as follows:
Over line 1S at times to, t4, t6, t9, and izo.
over line at times t7, m, tu, f1.1, 17, and tgz.
Over line 17 at times t15, tm, and t25.
Over line 18` at times t23, and izq.
Over line 19 at time tzg.
Over shift line 27 being generated at times t1, f2, f3, t5,
fs, tu frs, frs, 19, fai, 124, f2s, and f2a For generating these different sequences of pulses over diierent ones of the control lines and the shift line 27, the programming circuit comprises a pulse source, generally indicated by the box numbered 28, generating a continuous supply of recurring pulses through an electrical gating member 29 to a frequency divider circuit 30, and thence to a programming matrix circuit 31. Frequency divider 30, preferably including a plurality of cascaded binary frequency dividing stages, is supplied as a means for separating each of the incoming pulses received from pulse source 28 and directing a coded potential over a plurality of output lines representative of each pulse. This coded potential from the frequency divider, being directed to the program matrix 31, conditions this matrix for generating the desired sequence of pulses over the control lines and the shift line.
To insure that pulses are not spuriously generated by the program matrix in response to noise signals and irregularities in the supply potential, a second pulse source, generally indicated by the box 32, provides a second series of recurring pulses through a gate circuit 33 to additionally energize program matrix 31. Pulses from the second pulse source 32 are ltime displaced from the pulses of source #l (28) and are coincidentally combined bythe program matrix for eliminating any undesired energization of the control lines.
The overall operation of this system is then as follows: After entering each of the digits of the multidenominational decimal number in the keyboard by depressing the correspondingly numbered keys in each .row thereof, start switch 34 is closed energizing gates 29 and 33 by a source 35 to open position and enabling pulse sources 28 and 32 to repetitively direct impulses to frequently divider 3Q and program matrix 31, respectively. Each of the rst thirty pulses generated by source 2S are thereafter separated by the frequency divider circuit 3l) into various combinations of potentials over the output lines thereof, and thence redirected by programming matrix 31 into separated pulses over different output lines in the information graphically Y i 12, 13, and 14, whereby each of these nine input lines is v connected to a different one or ones of the four output lines for generating the binarycoded form of a different decimal digit. Considering the connection of the line 9, for example, conducting devices '37 convey pulsesreceived over line 9 to output lines 11 and 14. f Consequently, for any pulse received over line 9, the binarycoded form of decimal digit 9 (1001) is generated `by the output of this matrix. Similarly, each of the other lines numbered 1 through 8, inclusive, are connected to various ones of the four output Ylines 11, 12, 13, and 14 for generating the binarycoded'forms of any of the decimal digits l8 in response to energization of a correspondingly numbered input line. ,l Y Keyboard matrix 20 comprises a plurality of columns of switches generallyY labeled a, b, c, d, and e, each column having nine switches corresponding /to'each of the decimal digits l throughv 9, One terminal of the switches of each column are connected in common with a different one of each of the control lines, and the other terminals thereof are individually connected to a diiferentrone of the nine input lines`leading into digit conversion matrix 10. Closure of any one of the nine switches in each column electrically connects the control line associated 4with that row of keys with the input line of digit conversion'matrix 1i) corresponding` to the decimal number of the key depressed. For example, closure of switch numbered 9 in column a of the keyboard matrix, connects controlline 15 Vto line 9 of the digit conversion matrix; similarly, closure of switch 4 of the column b interconnects control line 16 With digit conversion matrix input line `4, and so forth. Y Y
Thus, the combination of keyboard matrix 20 and digit conversion matrix 10 provides the means for'individually generating the binarycoded form of each digit of a multidigit number that has been ystored in the keyboard matrix Y20'in response to energization of the control line associated with that denominational order. I
These binary'coded pulses generated by digit conversion matrix 10 are thereafter directed over lines 11, 12, 13, and 14 to enter the first four stages 38, 39, 4G, and 41 of shifting accumulator 26, as discussed above, and the resultingbinary number standing in the accumulator v Vmay thereafter be ordinally shifted as desired. one stage to the left by 'each pulse received over shift line 27.
As discussed above, accumulator 26 may be basically comprised of a plurality of identical binary summing stages in cascaded connection, each stageadapted to count `two pulses and yafter receiving the second consecutive above `discussed pattern, enabling each of the thirty operations to be initiated for converting the decimal number stored in the keyboard matrix into its binary form. Upon completion ofvthese thirty operations, the next succeeding pulse .passing through this programming circuitry, indicating that the sequential conversion operations have been completed, is directed backwardly over stop line 36 to close gates 29 and 33 and reset the system for a new conversion operation.
i Detailed circuitry of the keyboard matrix and digitconversion matrix F ig. 2
'arrangement with four vertically disposed output lines 11,
pulse to generate a carryover pulse to the next succeeding stage. For summing these pulses, each stage preferably includes a twostep onoif flipflop adding circuit such as an EcclesJordan connected vacuum tube circuit or the like l(not shown) adapted to alternately conduct in response to consecutive input pulsesfapplied to their control; grids. For shifting the count storedin each stage to the next succeeding stage on the left in response to each pulse received over. the shift line 27, vvacuumv tube circuitry, as known in the art, is supplied to intermittently connect the various stages responsively toirnpulses over lines 27, and to transfer a pulse to the succeeding stage on the left only when the preceding stage is in the one The remaining functions performed by the accumulator such Vas indicating thelresulting binary number standing in the stages uponthe completion ofoperations and clearing the count stored therein to permit a new series of operations are also well known in the art. Indicating the count may be performed by connecting neon light indicators to one of the EcclesJordan connected tubes in each stage; these indicators being illuminated when the stage is in the one (1) or conducting condition. Alternatively, the binary number standing in the stages may be transferred or cleared to a storage register 42, as generally illustrated in block diagram form, or to a printing mechanism (not shown) if desired.
For clearing all stages to the zero condition after the completion of all operations and transferring the count of each stage to such a storage register, an impulse may be transmitted over line 43 and directed to each stage of shifting accumulator 26. This impulse operates to return each stage to the zero or nonconducting condition and at the same time enables each stage which has been flipped from the one to the zero condition to generate an impulse to the corresponding stage of the storage register. Such storage registers, as known in the art, may also comprise a plurality of binary counting stages in cascaded connection'such as is shown by Patent 2,666,575, each stage connected to a corresponding stage of the shifting accumulator 26. The storage register additionally being responsive to impulses over line 44 to transfer the count to other portions of the system in the same manner as performed by clearing the shifting accumulator by impulses over line 43, discussed above.
To insure that extraneous or spurious pulses are not received over control lines 15, 16, 17, 18, and 19, and thereby allowed to pass through the keyboard matrix and digit conversion matrix to enter accumulator 26, oneway gating circuits 45, 46, 47, 48, and 49 may be placed in each of these control lines. Such gates as well known in the art may comprise vacuum tubes biased to conduct and transmit impulses from the plate circuit thereof only upon receiving a pulse of suiciently large amplitude. In this manner the radix converter is protected against change in line voltage or a change in tube characteristics that may otherwise result in a false count being entered into the accumulator.
Programming circuitry Fig. 3
The programming circuitry of the present invention may most descriptively be termed the timing circuitry or the time sequence controlling circuitry, for this circuitry provides the means for generating the electrical impulses that both initiate the individual conversion of each digit into its binarycoded form, and additionally initiate the shifting of these binarycoded digits to their proper position in the accumulator. In addition, after the completion of these conversion operations and shifting operations, this circuitry provides an impulse for returning all circuits to their initial condition, and preparing the system for a new conversion operation. v y
For generating these different sequences of pulses, the
v programming circuit is energized by a pulse source, generally indicated by the box numbered 28 in the lower central portion of the figure, propagating a continuous supply of recuring pulses through an electrical gating member enclosed Within a dotted box numbered 29 to a frequency divider circuit 30, and thence to a programming matrix circuit 31. Frequency divider 30, preferably including a plurality of cascaded binary frequency dividing stages 50, 51, 52, 53, and 54, provides'the means for receiving each of the incoming pulses from source 28 and separating each of these incoming pulses into a different code of potentials on the output lines of the flip,flop stages.l The output potentials of each of these Hipop stages thence energize the ten vertical input lines of the programming matrix 31 resulting in the thirtyone horizontal output lines of this matrix being consecutively energized one at a time in response to each succeeding impulse entering the input stage of the frequency divider 30.y As shown, these output lines are preferably connected to predetermined ones of these input lines by diodes or resistors or the like.
For example, prior to receiving the lirst impulse from impulse source 28, output line 55 of tlipflop 50 has a more positive potential than output line 56, and similarly output line 58 of flipflop 51 :is more positive than output one of the more negative lines leading from frequency.
divider 30. Consequently, only line to is rendered positive. Upon receiving the second impulse from pulse source 28, the first flipflop stage 50 of frequency divider 30 changes its conducting condition resulting in output line 56 thereof being more positive than line 55. Following the connections of these vertical lines again, it is observed that in this instance, the second uppermost 'horizontal line, labeled time t1, of matrix 31 is now the only line now connected to all five positive lines leading from frequency divider 30. Consequently, matrix output line time t1 may be considered as being energized by the second input pulse from source 28. Similarly, following the connections from frequency divider 30 through the matrix to the output lines thereof, it is observed that for each succeeding pulse received by frequency divider 30, the next succeeding line of matrix 31 is energized by a more positive potential, and therefore this combination of frequency divider 30 and matrix 31 in effect divcrts each pulse from pulse source 21 over aditferent output line of matrix 31, resulting in each succeeding output yline thereof being energized in time succession by the pulses from source 28.
Having these separate output lines individually energized at succeeding time intervals, any desired time sequences of pulses may be readily taken from matrix 31 by merely connecting a common line to bridge any series of these output ylines. For example, as discussed above, it is desired to generate pulses at times to, t4, t6, t9, tm' over control line 15. This may be performed by merely connecting this control line to the rst, fifth, seventh, tenth, and twentyfirst horizontal lines of matrix 31, as shown. Similarly, as discussed above, since it is desired to transmit pulses over line 16 at times t7, tw, tu, 11 117, and tm, line 16 may be connected to the eighth, eleventh, thirteenth, fteenth, eighteenth and twentythird horizontail output lines of matrix 31, as shown. Thus, each of the control lines 15, 16, 17, 18, and 19, and the control shift 'line 27 maybe energized to transmit any desired sequence of time separated pulses by connecting each of these lines to the correspondingly numbered output line of matrix 31.
For providing sharpedged pulses over these control lines, time displaced pulses from a second pulse source 32 may be coincidently combined with the matrix output pulses by directing these secondary pulses through open gate 29 and through summing impedances 65. Each of the summing irnpedances 65 are connected in circuit with impedances 66, which in turn are individually energized by the potentials across the selected ones of the matrix output lines. Hence, when the potentials across a given one of the impedances 66 is sutiiciently positive, a coincidently received impulse from source 32 is directed through the corresponding summing impedance 65, combined with this more positive potential, and permitted to pass through the associated biased rectifying element 67a to the desired control line.
Referring to the time sequence chart, Fig. 4, for an illustration of these events occurring at time t4, it is noted that at this time instant the bridge line connected to the fth uppermost matrix output line receives its most positive potential, and this potential remains until the fifth pulse from source 28 energizes frequency dif vider 30. However, upon the next succeeding impulse from the time displaced source 32 being received through 'summing impedance 65', theadded potentials of this more positive line and this latter impulse through summing impedance 66 exceed the rectifier biasing potential E, enabling a sharpedged pulse to be propagated through the rectifier 66a to control line 15. i
Rather than individuallyy entering each of the binarycoded digits into the first four stages of a shifting accumulator and thereafter bodily shifting these digits to the desired ordinal positions in the accumulator, as depicted by Figi, these binaryfcoded digits may be individually generated, as before, but ordinally shifted prior to being entered into the accumulator, and thereafter directly entered into the correct ordinal positions in a nonshifting accumulator.
Referring to the block diagram at Fig. for an understanding of one preferred embodiment of this latter operating system, the individual digits of the decimal number are again entered and stored in a keyboard matrix by Vdepressing the appropriate keys thereof. There* after start switch 34 is closed commencing the energization of a programming matrix 68, preferably of the same type as shown by Fig. 3. Energizing this program matrix again propagates a. predetermined time' sequence of impulses through the gating means, as shown, to indi' viduatllyy energize each of the control lines 15, 16, 17, 18, and 19, as before, resulting in impulses being directed to theproper input 4lines of the digit conversion matrix unit 10 for individually :generating the binarycoded forms A,B, C,'D, and E'of each of the decimal digits a, b, c, d, and e, that had been previously stored in the keyboard. These binarycoded impulses transmitted by matrix 10 over output lines 11, 12, 13, and 14 are thence directed to a shifting network or shift matrix, generally designated 69, which adjusts their columnwise position and finally transmits the shifted signals to the desired stages of a nonshifting accumulator, generally designated 70127037, inclusive.
As shown by Fig. 6, the shift matrix circuitry, generally enclosed within a dotted box numbered 69, may preferably take the form of a passive network having four vertically disposed input lines for receiving the binarycoded pulses from lines 11, 12, i3, and`14 Vgenerated by the digit conversion matrix 1). interconnecting each of these vertical lines with all of the diagonally arranged output lines 7394, inclusive, of the matrix leading to the input stages 'l through 7iiy, respectively, of nonshi'fting accumulator 70,` are provided coupling impedance such as the resistor 75 and a diode or rectifier 76'. Input pulses received over any of the vertical lines 11, 12, 13,
horizontally disposed shift lines numbered 95 through 1126, inclusive, yare interconnected with` each of these vertical input lines and each of these diagonal output lines through a second impedance, such as the resistor 77. Y
Energizing any one of these series of horizontal shift lines, therefore, permits the impulses from the vertical lines to be directed through only a given series of the horizontal output line. Forv example,. assuming that uppermost horizontal line 95 is energized by an impulse, an impulse coincidently transmitted over vertical line 11 Y is' conducted downwardly to energize each of its related impedances 75. Howeventhe only energized impedance 77 associated with this line isV connected to the uppermost horizontal line 95. Consequently, this impulse over line 11 is directed through only the uppermost impedance 75 and rectifier 76 to the uppermost diagonal line 78 and thence to stage 70) of nonshifting accumulator 7l). Similarly, binarycoded impulses over vertical lines 12, 13, and 114 are controlled by this shift pulse over line 95 to enter the lesser preceding three stages 70x, 70W, and 70V, in this instance. Should horizontal shift line 99 be energized by a pulsefrom programming matrix 63, thc next succeeding pulse coincidently received over vertical input line 11' is therefore directed only to stage 70s of nonshifting accumulator 7i), and likewise pulses over the remaining vertical lines 1'2, 13, and 14 are directed to stages '70,", 70g, and 73p. Thus, it is observed that the binarycoded pulses from digit conversion matrix 10 may be individually shifted to any four successive stages of nonshifting accumulator 70 by coincidently supplying a shift controlling pulse over the corresponding horizontal shift line leading from program matrix 6d.
As discussed above in relation to Fig. 3, any desired sequence of pulses may be taken from the thirtyone output lines leading from program matrix 3l by merely connecting a bridging line to any one or ones of these thirty'one lines.k Thus, uppermost shift line 95 of shift matrix 69 may receive an impulse at time t0, as shown, by in Fig. 3, and similarly all of the remaining shift lines merely connecting this line to the matrix output line tu may be energized at the time instants indicated in the ligure, by merely connecting these shift lines to the corresp'ondinglyv designated output lines of matrix 31.
To eliminate the possibility of extraneous pulses being generated over these shift lines, these lines are preferably connected to the colresponding lines of program matrix 31 in the same manner as are control lines 15, 16, 17, 13, and 19; that is, through a series'ef mixing circuits (not shown) that are similar to the mixing circuits 65, 66, and 67 of Fig. 3. Y
For an understanding of the manner and timesequence of shifting these binarycoded pulses prior to their being entered into the accumulatorV inaccordance with this second embodimentl of the invention, a third operational l chart is given below listing in the first ,fourl columns thereof themime, Operation Action,'and.Accu mulator Readingl in a manner similar to Chart I,
Referring to this chart and to Fig. 6, it is noted that at time t0, the programming matrix propagates a rst impulse over control line i5 and at thesame time transmits aY second pulse over shift line 9S. This rst pulse, passing through keyboard 20 and digit conversion matrix 1t), results in impulses being generated over matrix lines` 11, 12, 13 and 14, representing the binarycoded d'ivi'ts A; and this second pulse shifts'these binarycoded impulsesto the uppermost four stages 70y,'7f0x, 79W, and 70V of the' accumulator, resulting in the binary'number A standing in the accumulator. At later'time t4 a ksimilar pulse is transmitted over control line 15. However, at this instant a diierent shift line 96 is coincidently energized, resulting in the binarycoded digit A being shifted to enter a different series of the accumulator stages '7d1',
7ilu, 7dr, and 7dr, resulting in theac'cumulat'or readingV Although for Vpurposes of simplicity, the above preVV ferredV embodiments of the invention have been disclosed as systems for converting a relatively small `five place decimal number Q b, c, d, andqe, tofits Vbinary form, theV CHART III Time Operation Action Accumulator Reading Pulse Line 15 and Shift Line 95 Enter Shlfted A A Pulse Line 15 and Shift Line 90.. Enter Shfted A AOOA Pulse Line 15 and Shift Line 97. Enter Shifted A AOOAA Pulse Line 16 and Shift Line 97 Enter Shlfted B.. Pulse Line 15 and Shift Line 98. Enter Shifted A.. )A Pulse Line 16 and Shift Line 98 Enter Shifted B.. +B) Pulse Line l and Shift Line 99 Enter Shlited B (A+B)(A+B)B Pulse Line 16 and Shift Line 100 Enter Shifted B. AO0A(A+B)(A+B)BB Pulse Line 17 and Shift Line 100 Enter Shifted C AO0A(AB)(A+B)B(B C) tu Pulse Line 16 and Shift Line 101. Enter Shifted B AO0A(A+B)(A+B)B(B Pulse Line 17 and Shift Line 101 Enter Shiited AO0A(A+B)(A+B)B(B+O)(BlC) m Pulse Line and Shift Line 102.' Enter Shfted A.. AGOA( +B) (A+B) (B+C)(B+O)A Pulse Line 16 and Shift Line 103 EnterShifted B. AO0A(A+B)(AlBgBiCXBiCMB tu Pulse Line 18 and Shift Line 103 Enter Shifted D.. AO0A(A+B)(A+B B(B+C)(B+C)A(B+D) t Pulse Line 17 and Shift Line 104 Enter Shiited 0... AO0A(A+B)(A+B)B(B+C)(BlC)A(B+D)O tf1 Pulse Line 18 and Shift Line 105 Enter Shifted D AO0A(A+B)(A+BgB(B}C)(B+C)A(B+D)CD t Pulse Line 19 and Shift Line 100 Enter Shifted E. AO0A(A+B)(A+B B(BC)(B+C)A(B+D)CDE capacity of this system, of course, is not limited to any such range of numbers, for by enlarging the capacity of the programming generator by the addition of more frequency dividing stages and a larger program matrix, and by increasing the number of vcontrol lines and adding more rows to the keyboard matrix and more cascaded stages to the accumulator, it is obvious that many larger decimal numbers may be readily and substantially inf stantaneously converted into their binary equivalent form. For example, applying the introductory mathematical analysis to a six place decimal number a, b, c, d, e, f, it may be readily determined that the binary equivalent of this number may be represented as: 4
In a simlar manner, a seven digit decimal number a, b, c, d, e, f, g, may be represented in binary form as:
Whereas on the other hand, the binary equivalent form of the smaller four place decimal number a, b, c, d, may be represented as:
AAA (A +B) (A +B)0(A+C)BCD In converting each of these different order decimal numbers, the digits of each order are again stored in the various banks of a keyboard matrix or other suitable storage means, and a sequence of pulses from an appropriate programming generator again individually converts each of these decimal digits into their binarycoded form and thence operates to shift these various binarycoded digits into the proper stages of the accumulato as determined by the above binary formula.
These and many other variations of the specific circuitry illustrated and described may be readily made by those skilled in the art in accordance .with the basic invention herein disclosed without departing from thel spirit and scope of this invention, and therefore this invention is to be considered as limited only in accordance with'the features thereof as set forth in the claims appended hereto.
What I claim as newand desire to secure by Letters Patent of the United States is:
1 In a decimal to binary number translator a plurality of control lines including one for each order of a multidigit decimal number to vbe translated, a converter for generating outputpulses corresponding to the binarycoded form of. any decimal digit l9, inclusive, in responseA to energization of a corresponding one of nine input lines leading therein, a plurality of switch means for each order control line for selectively connnecting each order control line to any one of said nine converter input lines in accordance with the decimal digit of that order to be converted, an accumulator energized by the output of said converter for additively summing the binarycoded pulses generated thereby, and a programming generator sequentially energizing each of said control lines and said accumulator in a stepbystep predetermined time sequence pattern, whereby pulses are individually directed through said control lines, switch means, and converter to additively enter the accumulator as a series of additive factors whose total sum corresponds to the binary translated form of the multidigit decimal number.
2. In a decimal to binary number translator a plurality of control lines including one for each order of a multidigit decimal number to be translated, means for generating signals representative of the binarycoded form of any of the decimal digits l9, inclusive, in response to energization of a different one of nine input lines connected thereto, a plurality of switch means for selectively connecting each order control line to any one of said input lines in accordance with the decimal digit of that order to be converted, an accumulator including a plurality of cascaded binary stages energized by the output of said generating means for additively summing said binarycoded signals, and programming means for energizing each of said control lines in a predetermined time sequence pattern, whereby as each order control line is energized the binarycoded form of the digit of that order is additively entered in the accumulator, said programming means additionally energizing said accumulator to control the desired column position of said binarycoded digit entries in the accumulator stages.
3. In a decimal to binary radix converter, means including a plurality of decimal order control lines for individ ually generating pulses representing the binarycoded form of each digit of a multidigit decimal number settable therein, an accumulator including a plurality of cascaded binary stages, and programming means energizing said generating means, said programming means also connected to said accumulator for providing an ordi.r
nal shift in timevsequence thus enabling the individual conversion of each digit of the decimal number into its binarycoded form and the additive entry of the resulting binarycoded pulses in predetermined column order in the accumulator stages, whereby upon completion of said programming sequence the resulting summation in the accumulator constitutes the binary form of said decimal number.
4. In a decimal to binary radix converter means including aplurality of decimal order control lines for selectively storing each decimal digit of a multidigit decimal number, means responsive to said selecting means and adapted to individually generate the binarycoded form of each digit by a different series of simultaneously generated pulses over diiferent ones of four output lines, an accumulator including a plurality of cascaded binary summing stages, and programming means ata/ideati senting each stored digit and the addition of each such series of simultaneously generated pulses by said accumulator in predetermned column arrangement in the accumulator stages, whereby upon completion of operA sponse to energization of a corresponding one of nine v input lines leading therein, a plurality of switch means for each order control line for selectively connecting each order control line to one of said nine converter input lines in accordance with the decimal digit of that order to be converted, an accumulator energized by the output of said converter for additively summing theV binarycoded pulses generated thereby, and a programming generator sequentially energizing each of said control lines and said accumulator in a stepbystep predetermined time sequence pattern, said programming generator comprising a frequency/divider circuit including a plurality of cascaded stages adaptedA to be energized by a recurring pulse source, a matrix having a plurality of interconnected input lines and output lines, said matrix input lines being individually energized by different stages of said frequency dividerto provide a predetermined voltage on a dilerent one of said output lines in response to each pulse received by said frequency divider, and means for connecting said order control lines` to different ones of said matrix output lines in accordance with said desired time sequence.
6. In a decimal to binary number translator a plurality of control lines including one for each order of a multidigit decimal number tobeV translated, a nine input linevfour Voutput line'matrix for generating output vpulses over said four lines corresponding to the binarycoded form of any decimal digit l9, inclusive, in response `to energization of a corresponding one of the nine input lines leading thereinja plurality of switch means for each' order control line forselectively connecting each order control line to one of said nine converter input lines in accord 16 rst matrix, a frequency divider circuit adapted to be energized vby a recurring pulse source and includinga plurality of cascaded flipflop stages, a second matrix having a plurality of interconnectedrinput lines and output lines, said second vmatrix input lines being individually energized by different stages of said frequency divider to provide a predetermined voltage on a diierent one of the output lines thereof in response to each pulse received by said frequency divider, and means for connecting said control lines to different ones of said matrix output lines. 8. In a decimal to binary number translator a plurality of control lines including one for each order of a multil digit decimal number to be translated, a converter for generating output pulses corresponding to the 'binaryc'oded form of any decimal digit 19, inclusive, in response Y to energization ot a correspondingone of nine input lines ance with the decimal digit of that order to be converted, f
an accumulatorA energized by the output of Vsaid converter for additively vsumming the binarycoded pulses generated thereby, and aprogramming generator sequentially energizing each of said control lines and saidi accumulator in a stepbystep predetermined time sequence pattern, said programming generator comprising a' frequency divider circuit adapted to be energized by a` recurring pulse source and including a pluralityV of cascadedV stages, a matrix having a plurality of interconnected input lines and output lines, said matrix input lines being individuy ally energized bydiiierent stages of said frequency divider to 'provide a predetermined voltage on ai diiferent one of said output lines in response to each pulse received by said frequency divider, and means Vfor *connecting Vsaid order ing one of said nine inputlines leading therein, a plurality of banks of switchingmeans inuordinal array, one bank for each order of the decimal number, the switches of each Vbank having one terminal thereof connected in common with a corresponding order control Iline andthe other terminals thereof individually connected to different ones lof said rst matrix input lines, a multistage accumulator connected to be energized by the output of said leading therein, a plurality of switch means for each order control line for's'electively connecting each order 'control line to oneof said nine Converter input lines in accordance in said accumulator stages, and a programming generator for sequentially energizing each of said order control lines and said accumulator shift line in a predetermined time sequence pattern, 'whereby pulses are individually directed through said order control lines, switch means, and converter to add'itively enter the accumulator as a series of binarycoded digits andare individually and collectively shifted in avpredetennined manner to be additively registered by vthe accumulator asa series` of factors whose total sum corresponds to the binary translated form of the multidigit decimal number.` 1
9.` A decimal to binary convertercomprising a multistage binary counter adapted to be energized by a source of voltage pulses, a plurality lof mixing circuits adapted to be energized by a'second source of voltage pulses out of time phase relation with said Yiirst source, a rst electric matrix having 'a plurality of interconnected input and output conductors, said input conductors being energized bydifierent stages LAof said counter to provide av predetermined volta'ge ona different I"one'of said output conductors for each different number registeredin said counter, a plurality of control lines 'including one for each order Vof a multidigit decimal number to be translated, a 'converter for generating output pulses corresponding to the binarycoded form of any decimal digit 19, inclusive, in response to energization of a correspondingone of nine input lines leading thereinya plurality of switch means foreach order control line for selectively connecting each orderV control line toV one of said nine converter input' lines in accordance with the' decimal digit ofy that order to be converted, a multistage accumulator energized by the output of `said converter for additively summing the binarycoded pulses generated thereby, meansy for connecting said control lines to different ones of said matrix output lines to enable the sequential energization of each said control line in a predetermined time sequence pattern, and means interconnecting reach of k'said' mixing circuits with adifferent onev of said control lines'for coincidently'combining pulsesfrom said second source with the potentials derived from said matrix.
10. In a djecimalto` binary converter a plurality of control lines including at least one for each order of a multidigit decimal number to vbe converted, a translator for generating Voutput pulsesr corresponding to the rbinarycoded form of any decimal digit 1 9, inclusive,
in response to energization of a corresponding one ofv nine input lines leading therein, Va plurality of switch means for each order control line'for selectively connecty ing each order control line tol any one of said nine conl verter input lines in accordanceywithl the decimal digit 17 y of that order to be converted, an ordinal shifting matrix for receiving said binarycoded impulses and adapted to direct said pulses through different output lines thereof, an accumulator having a plurality of stages each energized by a different one of said matrix output lines, and a programming generator sequentially energizing each of said order control lines and said shift matrix in a predetermined sequential time sequence pattern, whereby the binarycoded pulses are individually directed through said control lines, switch means, and matrix shifter to additively enter the accumulator as a series of additive factors whose total sum corresponds to the binary converted form of the multidigit decimal number.
ll. In a decimal to binary converter means responsive to a recurring pulse source over a single input line for generating individual time spaced pulses over a plurality of output lines in a predetermined time sequence, a plurality of control lines including one for each order of a multidigit number, a converter for generating output pulses corresponding to the binarycoded form of any decimal digit l9, inclusive, in response to energization of a corresponding one of nine input lines leading therein, a plurality of switch means for each order control line for selectively connecting each order control line to any one of said nine converter input lines, a multistage accumulator energized bythe output of said converter for additively summing the binarycoded pulses generated thereby, means for connecting each of said control lines to a ditferent one of said generator output lines, a plurality of mixing circuits adapted to be energized by a second source of voltage pulses out of time phase relation with said first recurring pulse source, and means interconnecting each of said mixing circuits with a different one of said control lines for coincidently combining pulses from said second source with the individual time spaced pulses transmitted by said generating means.
l2. In a decimal to binary converter means responsive to a repetitive series of time spaced pulses received over a single input line for generating an equal number of space separated and time separated pulses over a plurality of output lines, wherein pulses generated over one said output line occur at dierent time instants than pulses over the remaining lines, a plurality of mixing circuits adapted to be energized by a second source of voltage pulses out of time phase relation with said first source, a plurality of control lines including one for each order of a multidigit number, a converter for generating output pulses corresponding to the binarycoded form of any decimal digit 19, inclusive, in response to energization of a corresponding one of nine input lines leading therein, a plurality of switch means for each order control line for selectively connecting each order control line to any one of said nine converter input lines, a multistage accumulator energized by the output of said converter for additively summing the binarycoded pulses generated thereby, means connecting each of said control lines to different ones of said generator output lines for enabling the sequential energization of each said control line in a predetermined time sequence pattern, and means interconnecting each of said mixing circuits with a dilferent one of said control lines for coincidently combining pulses from said second source with said generator pulses.
13. In a decimal to binary converter an accumulator including a plurality of cascaded Ibinary stages having shifting means for transferring the count of each stage to a succeeding stage, means responsive to a time recurring pulse source for generating time spaced pulses over a plurality of separate lines, wherein pulses generated over one line occur at different time instants than pulses over other lines, means for energizing said accumulator shift means by the impulses over one of said separate lines, a converter for generating output pulses corresponding to the binarycoded form of any decimal digit 1 9, inclusive, in response to energization of a corresponding one asadee ofinine inputlines leading therein, means for directing these binarycoded. pulses to the first four stages of said multistage accumulator, a plurality of switch means for selectively interconnecting given ones of said plurality of separate generator lines to different ones of said nine converter input lines in accordance with the decimal digit of that order to be converted, a plurality of mixing circuits adapted to be energized by a second source of voltage impulses out of time phase relation with said tirst time recurring pulse source, and means interconnecting each of said mixing circuits with a different one of said plurality of separate generating lines. v
14. A decimal to binary converter comprising means responsive to a time recurring pulse source for generatingA time spaced pulses over a plurality of separate control lines, wherein pulses generated over each said control line occur at diiferent time instants than pulses over the rother control lines, a matrix having nine input lines in predetermined circuit connection with four output lines for generating the binarycoded form of a different one of the decimal digits 19, inclusive, in response to energization of a different one of said input lines, a plurality of banks of switching means in ordinal array, one bank for each order of the decimal number, the switches ofeach bank having one terminal thereof connected in common with a corresponding order control line and the other terminals thereof individually connected to differentones of said matrix input lines, a multistage accumulator energized by the output of said matrix for additively summing the binarycoded pulses generated thereby, a plurality of mixing circuits adapted to be energized by a second source of'voltage' pulses out of time phase relation with said first source, and means interconnecting each of said mixing circuits with a different one of said control lines for coincidently combining pulses from said second source with the pulses from said time recurring pulse source.
l5. In a decimal to binary converter means responsive to a repetitive series of time spaced pulses received over `a single input line for generating an equal number of space separated and time separated pulses over a plurality of control lines, wherein pulses generated over one said control line occur at diiferent time instants than pulses over the remaining lines in a predetermined time sequence, a translator for generating output pulses corresponding to the binarycoded form of any decimal digit 19, inclusive, in response to energization of a corresponding one of nine input lines leading therein, a plurality of switch means for each control line for selectively connecting each control line to any one of said nine converter input lines in accordance with the decimal digit of that order to be converted, an ordinal shifting matrix for receiving said binarycoded impulses and adapted to selectively direct said impulses over a plurality of dilferent channels, an accumulator having aplurality of stages each energized by a different one of said matrix channels, and means for additionally energizing said shifting matrix by impulses received over said control lines for shifting each of the binarycoded digits into predetermined stages of the accumulator whereby the total sum of these binarycoded digits corresponds to the binaryconverted form of the multidigit number.
16. In a decimal to binary converter means responsive to a repetitive series of time space pulses received over a single input line for generating an equal number of space separated and time separated pulses over a plurality of control lines, wherein pulses generated over one said control line occur at different time instants than pulses over the remaining lines, a matrix having nine input lines in predetermined circuit connection with four output lines for generating the binarycoded form of a different one of the decimal digits 19, inclusive, in response `to energization of a different one of said input lines, a plurality of banks of switching means in agaatraen ordinal array with one bank for each order of therldecimal number, the switches of each bank having one terminal thereof connected in common with a diierentcontrol line andthe lother terminals thereof individually connected to different ones of said` matrix input lines, an ordinal shifting matrix energized by said matrix and given'o'nes 'of said control lines yfor receiving'said binarycoded impulses and selectively Adirecting said impulses to dierent banks of ordinally arranged channels responsively Vto the impulses from said given control Vlines, and I'an accumulator having aVplurality of cascaded stages consecutively arranged in banks "with Yeach bank adapted to be energized by a different "bank leading from said shifting matrix.
17. A decimal to binary converter comprising means responsive 't'o a recurring pulse source vover a single vinput for Agenerating,individual time space pulses over a plurality of 'separate output lines connected thereto in any desired time sequence, a plurality of control lines in` cluding one for each order Aof a multidigit decimal number to be translated, a converter generating output pulses corresponding to Ithe binarycoded form of any decimal digit 19, inclusive, in response to energization of ia vcorresponding one of nine input lines leading therein,` a plurality o'f switch means for each order controlv line 'for selectively connecting each order control line to one of 'said nine converterinput lines in accordance with the decimal digit of that order to be converted, an accumulator having a plurality of stages each having a separate input line, land an ordinal shifting network for receiving Asaid binarycoded impulses for selectively directing said impulses to 'different ordinally arranged stages of the accumulator; jsaid shifting network including a plurality of input lines for"receiving said binarycoded impulses andjincludin'gone'tcontrol linefor each of the various V@Ordinalf,positions'iof the accumulator adapted to receive the binarycoded impulses, a Aplurality of `mixing circuits interconnecting each control line fin commonwith each :ofi the input lines, :all of said mixing circuits interconnecting any `given'one of the control lines being connected to a Vdifferent K consecutive series of accumulator stages, VVand means for transmitting a Vgiven time sequence of pulses'to'said Ycontrol lines whereby said'binaiycoded y pulses are individually directed through said shift network "to, 'additively enter the accumulator stages as a jseries of factors `whose total sum corresponds to vfthe binary convertedvform of 'the multidigit number.
Referencescuentista@ sie 'er this patent UNrrEnisrA'rns PATENTS Y v Degen f j seprr, 1937 OTHER REFERENCES "Electronic Engineering, October 1953, pp. 407410.
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US3021065A (en) *  19570226  19620213  Ibm  Decimal to binary translators 
US3131294A (en) *  19600603  19640428  Hazeltine Research Inc  Electronic calculating machine 
US3132245A (en) *  19580527  19640505  Ibm  Data transfer device 
US3141963A (en) *  19590706  19640721  Wissenschaftlich Tech Buro Fur  Circuits and control for mantissa devices in binary computing machines 
US3205363A (en) *  19590819  19650907  Philips Corp  Universal photologic circuit having input luminescent elements arranged in matrix relation to output photoconductive elements with selective mask determining logic function performed 
US3774164A (en) *  19720522  19731120  Western Data Prod Inc  Data terminal system 
US4292624A (en) *  19741025  19810929  Serp William K  International Morse Code number generator 
US4725816A (en) *  19841210  19880216  John Fluke Mfg. Co., Inc.  Matrix keyboard encoder circuit 
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US3132245A (en) *  19580527  19640505  Ibm  Data transfer device 
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