US3771016A - Method for driving a plasma display panel - Google Patents

Method for driving a plasma display panel Download PDF

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US3771016A
US3771016A US00237792A US3771016DA US3771016A US 3771016 A US3771016 A US 3771016A US 00237792 A US00237792 A US 00237792A US 3771016D A US3771016D A US 3771016DA US 3771016 A US3771016 A US 3771016A
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voltage
voltage signal
sustaining
symmetric
wall
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T Toba
S Umeda
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Fujitsu Ltd
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Fujitsu Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
    • G09G3/293—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for address discharge
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
    • G09G3/294—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for lighting or sustain discharge
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
    • G09G3/297—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels using opposed discharge type panels
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
    • H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
    • H04N3/12—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by switched stationary formation of lamps, photocells or light relays
    • H04N3/125—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by switched stationary formation of lamps, photocells or light relays using gas discharges, e.g. plasma
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display

Definitions

  • FIG. 1 is a diagrammatic representation of FIG.
  • FIG. 1 A first figure.
  • FIG. 1 A first figure.
  • PATENTED NBY 3.771.016 SHEET 30F 9 9 ADDRESS m w REGISTER E E i E I (D D l DRIVER 2 COUNTER GATE I H (2) ADDRESS 4 (a; 36 REGISTER CLOCK 4) l7 l9 8 I (5)
  • FIGQ [3R Flt-113s METHOD FOR DRIVING A PLASMA DISPLAY PANEL BACKGROUND OF THE INVENTION 1.
  • This invention relates to the apparatus and method for driving a plasma display panel, and in particular, to the apparatus and method of inverting the state of a discharge cell, that is, inverting the state from write to erase and vice versa.
  • a typical plasma display panel of the prior art is composed of a pair of electrodes coated by a dielectric layer such as glass.
  • the electrodes are opposed to each other, and the space therebetween is filled with a suitable discharging gas such as neon.
  • Letters or figures are displayed by a discharge spot in the discharge cell formed between the opposed electrodes, and memory function is carried out by wall charges accumulated in the dielectric layer.
  • a wall voltage generated by the wall charges depends on a sustaining voltage and if the waveform of the applied sustaining voltage is, for instance, symmetric, the wall voltage takes a value between zero and a level, that is, between the erase state and the write state.
  • the wall voltage can assume either of two stable states, positive and negative (it may be said to take three stable states if the zero level is taken into account).
  • a pulselike sustaining voltage Vs is previously applied so that the voltage in the discharging space periodically changes its polarity as shown in FIG. 1. If a writing voltage Vw higher than the firing voltage V, is applied, a discharge spot is produced in the discharge cell, the wall charges are accumulated in the dielectric layer and the wall voltage V is established as shown by the dotted line. Thus, the potential difference between the next sustaining voltage V and the wall voltage V approaches a value more than the firing voltage V,, and hence a discharge spot is produced again so that the polarity of the wall voltage V is inverted.
  • the potential difference between such erasing voltage V,,- and the wall voltage due to the previous sustaining voltage has to exceed the firing voltage V,.
  • the wall voltage after inversion depends on the pulse width. If the pulse width is narrow, the voltage can be rather high and the voltage just after the application of the sustaining. voltage is different from the voltage remaining after a lapse of time, the level of which depends on the cell to some extent. Therefore, the range of the height and width of the pulse of the erasing voltage is very small and hence the inversion from display to erase modes of operation cannot be surely carried out.
  • the selection of the discharge cell to be energized by inverting its wall voltage is done by so-called voltage coincidence method wherein driving is done from both electrodes and the desired inverting pulse is applied only to the electrodes of a single cell when the driving voltages come to equal value, and hence the discharge is occasionally made by a pulse voltage applied to a single electrode (so-called semi-select trouble).
  • the sustaining voltage is composed of waveforms A and B as shown in FIG. 2.
  • the waveform A includes a pulse al of a voltage +V and a pulse a of a voltage V
  • the waveform B includes a pulse b of a voltage V, and a pulse h of a voltage +V
  • a discharge spot SP1 is produced by only the voltage of the waveform A
  • a discharge spot SP2 is produced by only the voltage of the waveform B.
  • the ratio of the number of the waveforms A to that of the waveform B is 1:10
  • the ratio of the brightness of the state 1 of the wall voltage V to that of the state 2 of the wall voltage V is about 1:10, and hence a display can be carried out by the state 2. Therefore, a memory function is provided with the state 1 corresponding to a logic 0 and the state 2 to a logic 1 for instance.
  • FIGS. 3A, B and C show the case of conversion from the state 1 to the state 2, wherein the wall voltage V is converted to the wall voltage V by the converting pulse CPl as shown by the arrow.
  • FIGS. 38 and 3C show the case of conversion from the state 2 to the state 1, wherein the wall voltage V is converted to the wall voltage V by the converting pulses CP2 and CP3 as shown by the arrow.
  • the purpose of the pulses CPl, CP2 and CP3 is the same as the converting pulse V shown in FIG. 1, and these pulses are applied to the selected cell accoring to the voltage coincidence method. Accordingly, the possibility of semi-select trouble is high.
  • An object of this invention is to provide a sure transition of the state of the discharge cell without semiselect trouble.
  • Another object of this invention is to enlarge the extent of the transition of the state of the discharge cell.
  • the transition of the state is carried out in two steps.
  • the first step a preparatory converting voltage is applied to the row (or column) electrode of the selected discharge cell to change the polarity of the wall voltage, and second, a converting voltage is applied to the column (or row) electrode to change the state of the selected discharge cell.
  • the potential difference between the converting voltage and the wall voltage changed by the preparatory voltage exceeds the firing voltage.
  • FIG. 1 is a graph of the prior art showing the conversion of the voltage states of a discharge cell upon applying a symmetric sustaining voltage
  • FIG. 2 is an explanatory graph of the function upon applying a non-symmetric sustaining voltage
  • FIGS. 3A, B and C are graphs showing the voltage states of a discharge cell of the prior art and, in particular, showing the conversion of the state of a discharge cell upon applying a non-symmetric sustaining voltage;
  • FIG. 4 is an explanatory view of the electrodes and discharge cells of a plasma display panel
  • FIGS. 5A to E show a series of graphs explaining the conversion of the state of a discharge cell according to the teachings of this invention upon applying a symmetric sustaining voltage
  • FIG. 6 is a block diagram of a circuitry in accordance with this invention for carrying out the function shown in FIG. 5;
  • FIG. 7 shows the waveforms for explaining the function of the parts of the circuitry shown in FIG. 6;
  • FIGS. 8A to E show a series of graphs as another example of the conversion of the state of a discharge cell according to this invention upon applying a nonsymmetric sustaining voltage
  • FIG. 9 is a block diagram of a circuitry for carrying out the function shown in FIG. 8;
  • FIG. 10 shows an example of the gate circuit shown in FIG. 9
  • FIG. 11 shows an example of the driver shown in FIG. 9
  • FIG. 12 shows an example of the decoder shown in FIG. 9
  • FIGS. 13A to S show the waveforms for explaining thefunctions of the parts of the circuitry shown in FIG. 9;
  • FIGS. 14A to 1-1 show the waveforms of various nonsymmetric sustaining voltages.
  • FIG. 4 shows schematically a plasma display panel wherein the electrodes X, and Y are selected to convert the state of a discharge cell A.
  • a voltage V shown in FIG. 5 is applied to the selected electrode X while a voltage Vy is applied to the selected electrode Y and hence a voltage V is applied to the selected discharge cell A. That is, a preparatory converting voltage V is applied after the application of the sustaining voltage V to convert the wall voltage V Next, a converting voltage V is applied so that the potential difference between V and V exceeds the firing voltage V,; immediately, the discharge is started, but the wall voltage V is distinguished because the pulse width of V is too small to produce the wall voltage.
  • a voltage V B is applied to a semi-selected cell B on the electrode Y,,.
  • a device for carrying out the above-mentioned driving method is shown in FIG. 6, and its function will be hereinafter explained on referring to FIG. 7.
  • a sustaining voltage V a preparatory converting voltage V, and a converting voltage V, are applied to a plasma display panel 1 by drivers 2 and 3 composed of a group of amplifiers such as transistors or the like. These drivers 2 and 3 are controlled by the output of gate circuits 4 and 5 composed of a plurality of AND gates and OR circuits.
  • the logical functions of the gate circuits 3 and 4 are carried out under the control pulse of a location pulse generator 10 and the output of address registers 6 and 7.
  • the address signals are applied to convert the state of the selected cell through input terminals 8 and 9.
  • the location pulse generator 10 includes a counter 12 which counts the clock CL derived from a clock generator 11, the counter 12 being shown as an octal notation counter in FIG. 6.
  • the output signals of the counter 12 are denoted as (l) to (8); the output (1) is coupled to the gate circuit 4 and the sustaining voltage V is applied to each row electrode from the driver 2.
  • the output (6) is applied to the gate circuit 5 and the sustaining voltage is applied to each column electrode from the driver 3.
  • Address signals are added to the input terminals 8 and 9, and the state converting signal, which is an erase-command signal in this example, is applied to the input terminal 13 to enable an AND gate 14 and to reset a flip-flop 15 by the output (2) of the counter 12.
  • the flip-flop 15 is set by the output (5) and hence the 6 output of the flip-flop 15 takes a form shown as (15) in FIG. 7.
  • the output (15) of the flip-flop 15 is coupled to the AND gates 16 and 18 and an output signal (16) of the AND gate 16 is derived from the output signal (3) of the counter 12 to be applied to the gate circuit 5.
  • the preparatory converting voltage V is applied to only selected column electrodes from the AND gate 16 and the output of address register 7.
  • the output of the counter 12 is added to a waveform shaping-and-delay circuit 17.
  • This circuit 17 is composed of, for instance, a monostable multi-vibrator and a delay-line, and its input pulse is waveform-shaped to a narrow pulse by the monostable multi-vibrator.
  • the output signal (18), as shown in FIG. 7, of the AND gate 18 is a pulse output having a width smaller than the output signal (4) of the counter 12, and it is delayed from the leading edge of the output signal (4).
  • the output signal (18) is added to a gate circuit 4 and the output of the address register 6 is also added to the gate circuit 4 and hence the converting voltage V is applied to only selected row electrodes by the driver 2.
  • one voltage denoted as V M is applied to selected row electrodes and another voltage denoted as V to selected column electrodes to effect a state conversion or erasure in the selected cell without semi-select trouble, as shown on reference to FIG. 5.
  • the peak value of the preparatory converting voltage V and the converting voltage V may be equal to that of the sustaining voltage V and hence the circuit of the drivers 2 and 3 is simple.
  • the output signal (18) of the AND gate 18 is delayed through the delay circuit 19 and added to the address registers 6 and 7 so that these registers are reset.
  • the preparatory converting voltage V may be applied to the selected row electrodes and the converting voltage to the selected column electrodes.
  • one half of it may be applied to the row electrodes while another half is applied simultaneously to the column electrodes in the opposite polarity.
  • a sustaining voltage which changes periodically its own polarity, may be applied to either one of the row or column electrodes.
  • the preparatory converting voltage V is applied to either the row or column electrodes, the wall voltage of the discharge cell on the selected electrodes is changed, and then the converting voltage V, is applied to the other selected electrodes so that the state of the selected cell is converted.
  • a voltage V is applied to the semi-selected cell B on the selected electrode Y,, and a discharge spot is produced by the preparatory converting voltage V, but the state is not changed.
  • a voltage V, is applied to the semi-selected cell C on the selected electrode X, and the state is not changed because the voltage V has the same polarity as the sustaining voltage V,. Thus, the state of the selected cell can be converted without semi-select trouble.
  • a circuit for driving the display panel will be described as follows.
  • the sustaining voltage is applied to each electrode from drivers 33 and 35 which are controlled by the outputs of the gate circuits 37 and 39.
  • the outputs 'of a location pulse generator 40 and decoders 42 and 44 are applied to the gate circuits 37 and 39, respectively.
  • Input address data signals XD and YD are applied to the decoders 42 and 44 from address registers 46 and 48 to be decoded.
  • the location pulse generator 40 includes a clock generator 51, a counter 50, a J-K flip-flop 54, AND gates 56, 57, and 58, OR circuits 62 and 64, a monostable multivibrator 66, and a conversion-demand signal CNG is added to AND gate 58.
  • the counter 50 is an undecimal counter in this example, and its output signalsare denoted as (1) to (11 Output signals (1) and are coupled to the gate circuit 37 through the OR circuit 64, and the output (1) is connected to the driver 33.
  • Output signals (6) and (8) are connected to the gate circuit 39 through the OR circuit 62 and the output signal (8) is coupled to the driver 35.
  • Gate circuits 37 and 39 each comprises illustratively, as shown in FIG.
  • an AND gate 60 and an OR circuit 62 In the gate circuit 37, the outputs of the decoder 42 and the monostable multivibrator 66 come to the input of the AND gate 60; the outputs of the AND gate 64 and the AND gate 60 are coupled to the inputs of the OR circuit 62, and the output of the OR circuit 62 is connected to the driver 33.
  • the output signals of the decoder 44 and the AND gate 50 are connected to the input of the AND gate 60; the out put signals of the OR circuit 62 and the AND gate 60 are both connected to the inputs of the OR circuit 62, and the output of the OR circuit 62 is added to the driver 35.
  • FIG. 11 An example of the driver 33 (or 35) is shown in FIG. 11, wherein O1 to Q12 are transistors and D1 is adiode.
  • the output signal of a monostable multivibrator 66 is applied to the base of the transistor 02 and it controls the switching of the transistor Q1.
  • the output signal (l), as shown in FIG. 13B, of a counter 50 is coupled to the base of the transistor O4 to control the switching of the transistor Q3.
  • the output signals of the gate circuit 37 are coupled to the bases of the transistors Q6, Q8, Q10 and Q12, respectively, to control the switching of the transistors Q5, Q7, Q9 and Q11 and to generate the voltages V V and V,, at the electrodes X1 to Xn.
  • the driver 33 is generally the same as the driver 35, but does not include transistors Q1 and O2.
  • decoders 42 (or 44) is shown in FIG. 12. Any one of the output signals: of the NAND gates 70 to 79 comes to zero by the input of 1248 codes. Numerals 80 to 83 also denote NAND gates.
  • FIGS. 13A, to S the function of the circuit of FIG. 9 will be explained.
  • the clock CL (FIG. 13A) of the clock generator SE is counted by the counter 50, and the signals (1), (3), (5), (6), (8) and (10) are shown in FIGS. 138, C, D, E, F and G, respectively.
  • the output of the OR circuit 64 is shown in FIG. 13H.
  • Output signal VMMV is derived from the output of the monostable multivibrator 66, and is shown in FIG. 13M.
  • the signal VFF is shown in FIG. 13N as the output of the flip-flop FF, signals V and V are the voltages applied (see FIGS.
  • signal VA is shown in FIG. 138 as the voltage applied to the selected cell.
  • the preparatory converting voltage and the converting voltage, the hatched parts of the voltages V and V are not applied.
  • the voltage V is applied through the diode D1 shown in FIG. 11, simultaneously with the output (10) of the counter 50 to the row electrode and with output (6) of the counter Sill to the column electrode.
  • the voltage V H is applied through the transistor Q3, simultaneously with the output (1) of the counter 50 to the row electrode and with the output (8) of the counter 50 to the column electrode.
  • the output signal of the AND gate 58 is applied to the flip-flop 54 simultaneously with the output signal (1) of the counter 50, and the flip-flop 54 is set by the next clock CL and reset by the output (6).
  • the flip-flop 54 is set, the AND gates 56 and 57 are enabled by the output of the flip-flop 54 and the output (3) of the counter 50 is coupled to the gate circuit 39.
  • the input address data YD is decoded by the decoder 44 and applied to the gate circuit 39, and hence the preparatory converting voltage V of the voltage V is applied only to the selected column electrode.
  • the output (5) of the counter 50 is connected to the monostable multivibrator 66 from the AND gate 57, converted to a narrow pulse and applied to the gate circuit 37 and the driver 33. This pulse is applied to the base of the transistor ()2 shown in FIG. 11 and the transistor O2 is turned on, whereby the transistor O1 is converted to the on-state and the converting voltage V is applied.
  • the input address data XD is decoded by the decoder 42 and coupled to the gate circuit 37, and hence the converting voltage is applied only to the selected row electrode.
  • the voltage VA is applied to the selected cell A.
  • the wall voltage V is changed by the preparatory converting voltage V, and the potential difference between the converting voltage V and the changed wall voltage exceeds the firing voltage V, so that the discharge takes place.
  • the pulse width of voltage V is not wide enough to establish the wall voltage and hence the wall voltage is converted to the level V Converting the semiselected cell, the semi-select trouble does not take place as described in reference to the graphs of FIG. 8.
  • the above example is the case when the state 1 of the wall voltage V is converted to the state 2 of the wall voltage V and the conversion from the state 2 to the state 1 can be done in a similar way.
  • the method shown in FIG. 3C can be combined with the method mentioned just above.
  • the preparatory converting voltage V and the converting voltage V may be added to either column or row electrode as well as in the case of the above-mentioned symmetric sustaining voltage.
  • FIGS. 14A to H show the various methods of applying the sustaining voltage.
  • two types of voltages i.e., half of V and half of V
  • the nonsymmetric sustaining voltage combine with V H and V, and are applied to the discharge cell.
  • the preparatory converting voltage and the converting voltage are applied in the same way as in the above-described example.
  • FIGS. 14C and D show a case wherein the voltages V and V,, are applied to the row and column electrodes, respectively.
  • FIGS. 14E and F show a case wherein a voltage corresponding to V has a narrow width and a peak value generally equal to V
  • FIGS. 14G and H show the sustaining voltage in the case wherein the state of the .wall voltage has three stable states, that is, high, low
  • the waveform of the preparatory converting voltage is able to be the same as that of the sustaining voltage.
  • conversion of the state is carried out in two steps, wherein the preparatory converting voltage and the converting voltage are successively applied, and in the semiselected cell to which the preparatory converting voltage is applied; the time when the wall voltage is changed, is shifted but the state is not converted.
  • the semi-selected cell to which the converting voltage is applied the potential difference between the converting voltage and the previously applied sustaining voltage is less than the firing voltage V and hence the discharge does not take place and the state is not converted. Accordingly, the semi-select trouble does not appear at all and the range of the converting voltage, that is, the range of the peak value and pulse width, can be extended.
  • the preparatory converting voltage may have the same waveform as the sustaining voltage and the circuit need not be complicated.
  • Apparatus for selectively displaying and storing information comprising:
  • a plasma display panel comprising a plurality of energizable radiation emitted elements disposed in an array, each of said emitting elements having first and second electrodes defining a discharge region therebetween for receiving a discharge gas and wall covering for storing wall charges, said emitting elements having a characteristic firing voltage;
  • Apparatus as claimed in claim 1 wherein there is further included means for applying a sustaining voltage to each emitting element, and wherein said first means provides the preparatory converting voltage of a waveform substantially similar to that of the sustaining voltage.
  • a method of selectively energizing a plasma display panel comprising a plurality of pairs of spaced electrodes for defining a'discharge space therebetween filled with a discharge gas, each of the electrode pairs having a dielectric layer for forming thereon a wall voltage maintained by periodic sustaining voltage signals applied to the electrodes to effect a discharge between the electrodes of a pair, whereby the wall voltage is changed from a first state to a second state, said method comprising the steps of;
  • the sustaining voltage signals are non-symmetric and have high and low peak values
  • said first voltage signal is substantially similar in waveform with respect to that of the non-symmetric sustaining voltage signals of low peak value
  • said second voltage signal having a peak value intermediate between the high and low peak values of the non-symmetric sustaining voltage signals and a pulse width smaller than that of the non-symmetric sustaining voltage signals of high peak value
  • Apparatus for selectively displaying and storing information comprising:
  • a plasma display panel including a plurality of pairs of spaced electrodes each defining therebetween a discharge space filled with a discharge gas and coated with a dielectric layer for forming thereon a wall voltage disposable in first and second states;
  • first voltage signal to one electrode of a selected electrode pairs during one cycle of said sustaining voltage signal, said first voltage signal having a potential difference with respect to said sustaining voltage signal and a pulse width of sufficient magnitudes to produce a discharge to convert the wall voltage
  • third means for applying a second voltage signal of opposite polarity to said first voltage signal to the other electrode of said selected electrode pair during said one cycle of the sustaining voltage signal, said second voltage signal having a potential difference with respect to that wall voltage produced by said first voltage signal and a pulse width of sufficient magnitudes to effect a discharge to convert the wall voltage to its second state.
  • said first means provides a symmetric sustaining voltage signal, said first voltage signal being substantially similar in waveform to that of said symmetric sustaining voltage signal, and said second voltage signal has a peak value approximately equal to that of said symmetric sustaining voltage signal and a pulse width smaller than that of said symmetric sustaining voltage signal.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of Gas Discharge Display Tubes (AREA)
  • Transforming Electric Information Into Light Information (AREA)
US00237792A 1971-03-25 1972-03-24 Method for driving a plasma display panel Expired - Lifetime US3771016A (en)

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JP46017533A JPS5133373B1 (en, 2012) 1971-03-25 1971-03-25

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US (1) US3771016A (en, 2012)
JP (1) JPS5133373B1 (en, 2012)
FR (1) FR2130663B1 (en, 2012)
GB (1) GB1385211A (en, 2012)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3851210A (en) * 1973-06-22 1974-11-26 Owens Illinois Inc Method of driving and addressing gas discharge panels by inversion techniques
US3851211A (en) * 1973-06-28 1974-11-26 Ibm Sustain sequence circuitry for gas panel display devices
US3906451A (en) * 1974-04-15 1975-09-16 Control Data Corp Plasma panel erase apparatus
US3953762A (en) * 1973-10-03 1976-04-27 Nippon Electric Co., Ltd. Circuit for supplying a specified one of plural external electrodes of a gas discharge display panel with unidirectional firing voltage pulses and for supplying others with pulses of a reduced voltage
US4027196A (en) * 1975-11-12 1977-05-31 International Business Machines Corporation Bilateral selective burst erase system
US4393405A (en) * 1980-08-22 1983-07-12 Kabushiki Kaisha Suwa Seikosha Synchronizing circuit for matrix television set

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3811124A (en) * 1972-06-12 1974-05-14 Ibm Solid state gas panel display circuits with non-inductive solid state isolation between low level logic and high level drive signal functions

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2859385A (en) * 1958-11-04 Visual display apparatus
US3513327A (en) * 1968-01-19 1970-05-19 Owens Illinois Inc Low impedance pulse generator
US3601531A (en) * 1968-10-08 1971-08-24 Univ Illinois Plasma display panel apparatus having multilevel stable states for variable intensity

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2859385A (en) * 1958-11-04 Visual display apparatus
US3513327A (en) * 1968-01-19 1970-05-19 Owens Illinois Inc Low impedance pulse generator
US3601531A (en) * 1968-10-08 1971-08-24 Univ Illinois Plasma display panel apparatus having multilevel stable states for variable intensity

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3851210A (en) * 1973-06-22 1974-11-26 Owens Illinois Inc Method of driving and addressing gas discharge panels by inversion techniques
US3851211A (en) * 1973-06-28 1974-11-26 Ibm Sustain sequence circuitry for gas panel display devices
US3953762A (en) * 1973-10-03 1976-04-27 Nippon Electric Co., Ltd. Circuit for supplying a specified one of plural external electrodes of a gas discharge display panel with unidirectional firing voltage pulses and for supplying others with pulses of a reduced voltage
US3906451A (en) * 1974-04-15 1975-09-16 Control Data Corp Plasma panel erase apparatus
US4027196A (en) * 1975-11-12 1977-05-31 International Business Machines Corporation Bilateral selective burst erase system
US4393405A (en) * 1980-08-22 1983-07-12 Kabushiki Kaisha Suwa Seikosha Synchronizing circuit for matrix television set
US4496977A (en) * 1980-08-22 1985-01-29 Kabushiki Kaisha Suwa Seikosha Synchronizing circuit for matrix television set

Also Published As

Publication number Publication date
DE2212800A1 (de) 1972-10-12
GB1385211A (en) 1975-02-26
DE2212800B2 (de) 1977-02-03
FR2130663A1 (en, 2012) 1972-11-03
FR2130663B1 (en, 2012) 1976-08-06
JPS5133373B1 (en, 2012) 1976-09-18

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