US3713885A - Memory matrix and its process of fabrication - Google Patents

Memory matrix and its process of fabrication Download PDF

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Publication number
US3713885A
US3713885A US00015651A US3713885DA US3713885A US 3713885 A US3713885 A US 3713885A US 00015651 A US00015651 A US 00015651A US 3713885D A US3713885D A US 3713885DA US 3713885 A US3713885 A US 3713885A
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United States
Prior art keywords
bands
strips
strip
band
lines
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Expired - Lifetime
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US00015651A
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English (en)
Inventor
J Gallard
I Lagadec
P Betremieux
H Feissel
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Bull SA
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Societe Industrielle Honeywell Bull
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/83—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption
    • G11C29/832—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption with disconnection of faulty elements

Definitions

  • ABSTRACT A memory matrix and the process for fabricating said matrix, wherein a conductive array is formed of two mutually orthogonal and insulated sets of parallel conductive metallic bands, each band being formed of two superposed conductive strips, the lower strip of each band of the first set passing through an opening in the lower strip of each band of the second set and the upper strip of each band of the second set passing 7 through an opening in the upper strip of'each band of the first set, and wherein coupling elements selectively couple bands of one set to bands of the other set.
  • Such matrices realized in the form of thin films, present a great disadvantage.
  • the metallic bands of copper for example, have a thickness of only a few microns, whereby they have a high resistance which is prejudicial to transmission of electrical signals.
  • the object of the present invention is to alleviate this disadvantage. Accordingly, the invention relates to a memory matrix realized of thin films, and its process of fabrication.
  • jthe memory matrix comprises of one part having first andsecond sets of parallel lines formed of metallic conducting bands disposed on an insulating plane support in such a manner that each line of one of the sets crosses at right angles and is insulated from all of the lines ofv the other set, and of another part having coupling elements which couple certain lines of one of the sets to certain lines of the other.
  • each of the metallic bands comprises at least two superposed strips and wherein, at the crossing points of the bands, the lower strip of one line of the first set is provided with a firstopening through which passes the lower continuous strip of one line of the second set and the upper strip of said line of the second set is provided with a second opening through which passes the continuous upper strip of said line of the first set without being in electrical contact with the lower continuous strip of said line of the second set.
  • each line is formed of at least two layers.
  • the transmission resistance of the lines is therefore reduced and, in the instance of the'band having two superposed layers, practicallydivided in half in relation to known matrices Obviously, the thickness of each strip once being chosen, the number of superposed strips'of a band is determined to provide the desired conductance value of aline.
  • the matrix comprises, at each crossing point, a small insulating plate disposed between a continuous strip of the line'of one set and a continuous strip of the line of the other set. Moreover, the portionsof the first opening formed between the lower strips of the two bands which cross are filled with an insulating material.
  • the matrix in accordance with the invention may be obtained by known techniques of deposition and of removing portions of thin films on an insulating support.
  • the process for realizing on an insulating plane support a matrix such as specified above is characterized in that there is coated uniformly on such support a first conductive layer and then there is cut in this layer first notch couples, substantially parallel, distributed according to a pattern of 1 rectangular meshes. Next, each portion of the first layer which is between the two notches of a couple is covered, overlapping at its two edges, by an insulating plate, followed by coating everything with a second conductive layer.
  • the bands of the two sets of lines are etched in such a manner that, on one hand, the bands of the first set havefor their lower strips the portions of the first conductive layer included between aligned and adjacent notch couples and, on the other hand, the bands of the second set are orthogonal to the bands of the first set, the upperstrips' of the first set passing over the first notch couples and the insulating plates, after which there is cut in the upper strips of the bands of the second set, second notch couples disposed on each side of the upper strips of the bands ofthe first set.
  • first and second notch couples form respectively the first andsecond openings mentioned above;
  • the coupling elements between the word lines and the bit lines are resistors. It is then possible to deposit on the insulating support, prior to'the deposit of the first conductive layer, a layer of electrically resistive material, after which there is cut inthe two layers the first notch couples. Then, after having put in place the insulating plates and covered everything with a second conductive layer, there is etched, simultaneously with said bands, in the two conductive layers and the resistive layer, a lamella having a pattern connecting, in each of the rectangular meshes, one band of one set toone band of the other, and passing substantially through the center of the mesh. Then there is formed the second notch couples and there is eliminated, at least partially, the portions of the two conductive layers covering the lamellae.
  • each mesh there is a resistor which connects a word line to a bit line. It is then necessary, in order to write into ;the memory (encode) the desired information, to destroy certain of these resistors. To effect this, the matrix is then covered with a protective insulating layer having a window at the center of eachmesh, the area of the window being substantially less than that of the mesh.
  • the matrix comprises supplementary word lines coupled to corresponding bit lines through resistors such as specified above, in series with a strip, for example of the same material as the resistor, easily fusible by a high intensity current.
  • enlarged pads of the same material as these fusible strips are disposed at the extremities of the fusible strips, in order to facilitate the application of the high intensity current for the elimination of such strips.
  • FIG. 1 is a view, in perspective and to a large scale, of one embodiment of the memory matrix of the invention
  • FIGS. 2 to 7 illustrate different stages in the process of fabrication of a memory matrix in accordance with the invention.
  • FIG. 8' is a schematic view of a memory matrix providing supplementary lines in accordance with the invention.
  • the portion of the memory matrix shown in FIG. 1 comprises, arranged on an insulating plane support 1, word lines 2 and bit lines 3.
  • the word lines are mutually parallel, as are the bit lines which are orthogonal to the word lines,
  • a rectangular mesh 4 in the interior of which is disposed a coupling element, constituted in this memory matrix of a resistor formed of resistive lamella 5 coupling a word line 2 to a bit line 3.
  • These lamellae 5 have a sinuous pattern and pass substantially through the center of meshes 4.
  • Each word line 2 is a conductive metallic band formed of two superposed strips 6 and 7.
  • each bit line 3 is a conductive metallic band formed of two superposed strips 8 and 9.
  • the extremities of each lamella 5 are respectively affixed to the resistive strips 10 and 11 underlying bands 2 and bands 3 and in electrical contact therewith.
  • the strip 11 and lower strip 8 of a band 3 comprise an opening 12 through which passes, without contact with the latter, the strip 10 and the lower strip 6 of a band 2.
  • the upper strip 7 of a band 2 comprises an opening 13 through which passes, without contact with such strip 7, the upper strip 9 of a band 3.
  • bands 2 and strips 10 are insulated from bands 3 and strips 11.
  • smallinsulating plates 14 are disposed between them.
  • FIGS. 2 5 One such matrix or a similar matrix can easily be obtained by employment of the process described hereinafter in regard to FIGS. 2 5.
  • This process utilizes techniques well-known in photoengraving. Therefore, all the operations obvious to the specialist, the cleaning, the formation of the masks in photosensitive lacquer, the etching of the'deposited layers, etc., are not described.
  • an insulating support 1 There'is coated successively, for example by depositing under vacuum, the plane surface of an insulating support 1 with a uniform resistive layer 20 (for example, a layer of chromium of which the resistance can be of the order of ohms per square), and then with a first conductive layer 21 (for example, of copper).
  • a uniform resistive layer 20 for example, a layer of chromium of which the resistance can be of the order of ohms per square
  • a first conductive layer 21 for example, of copper
  • support I is recovered (for example by deposition in a vacuum) with a second conductive layer, and then the three layers (the resistive layer and the two conductive layers) are etched to form the bands of the two sets of lines and the coupling resistors between the bit lines and word lines.
  • Bands 2 of the word lines are etched in a manner such that their lower strips 6 consist of the portions 24 of the first conductive layer 21 comprised between aligned notch couples 22 and 23 and the portions of layer 21 joining such portions 24.
  • Bands 3 of the bit lines are etched'orthogonal to bands 2, in, a manner such that their upper strips 9 (etchedin the second conductive layer) pass over notch couples 22 and 23 and over insulating plates 24.
  • notch couples 25 and 26, disposed on both sides of the upper strips of bands 3, are cut in the upper strips of bands 2.
  • bands 10 and 11 of the resistive material of the layer 20 there is also created under such bands, bands 10 and 11 of the resistive material of the layer 20.
  • a band 50 there is etched similarly, in the two conductive layers and the resistive layer, a band 50, having a pattern which connects in each mesh 4 a band 10 to a' band 11 (these bands 50 being in electrical contact with bands 2 and 3) and which passes substantially through the center of the mesh.
  • the matrix is covered again with a layer 31 of photosensitive lacquer (FIG. 7) and then with an appropriate mask 32 hiding certain meshes 4.
  • a layer 31 of photosensitive lacquer FIG. 7
  • an appropriate mask 32 hiding certain meshes 4.
  • the encoding of the matrix may therefore be accomplished by eliminating at one time all of the resistors not desired. Nevertheless, in order to compensate for encoding errors or to modify the code, it is advantageous to provide supplementary word lines connected to bit lines through couplings able to be cut at will after the encoding.
  • the supplementary word lines 2 are connected to .bit lines 3 by resistors 5 in series with a fusible strip 33 (for example of the same material as that of resistors 5), FIG. 8.
  • Enlarged pads 34 and 35 are provided on each side of strip 33.-Therefore, therev can be applied to pads 34 and 35 the contacts of a generator delivering a current of sufficient intensity for volatizing the corresponding strip 33.
  • Memory matrices in accordance with this invention in which the coupling elements are not resistors, do not permit the resistive strips 10 and 11 underneath the respective word lines 2 and bit lines 3. They can be, therefore, realized with the aid of a process similar to that which has been described above, but not involving the operation of depositing a uniform resistive layer 20 on insulating support 1 prior to the deposit of the first conductive layer.
  • a memory matrix comprising first and second sets of parallel lines, formed of conductive metallic bands disposed on an insulating plane support in a manner such that each line of one set crosses at right angles to and is insulated from all lines of the other set,
  • each of said bands comprises at least two superposed strips, and at the crossing points of said bands, the lower strip of one line of said first set is provided with a first opening through which passes the structurally continuous lower strip of one line of said second set, and the upperstrip of said line of said first set, and means for insulating said continuous lower and upper strips one from the other disposed between said continuous strips of the two sets at the crossing point.
  • said insulating means comprises a small insulating plate disposed between the continuous strips of the two sets, such that the portions of saidfirst opening disposed between the lower strips of the bands which cross are filled with an insulating material.
  • the memory matrix of claim 1 further comprising an insulating layer provided with windows through which appear at least partially said coupling means or the lines of connection of said coupling means.
  • a conductive matrix comprising: first and second sets of conductive metallic bands, each band of one of said sets crossing and being insulated from all bands of the other set, each band being formed of two superposed conductive strips, the lower strip of each band of said firstset being provided with first openings through which pass respective continuous lower strips of the bands of said second set, and the upper strip of each band of said second set being provided with second openings through 'which pass respective continuous upper strips of the bands of said first set, and means for coupling predetermined bands of one set to predetermined bands of the other set, said coupling means comprising lamallae of resistive material in series with a strip which is easily fusible by high intensity current ap-' plied to its extremities.

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  • Apparatuses And Processes For Manufacturing Resistors (AREA)
US00015651A 1969-03-06 1970-03-02 Memory matrix and its process of fabrication Expired - Lifetime US3713885A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR6906298A FR2036207A5 (de) 1969-03-06 1969-03-06

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US3713885A true US3713885A (en) 1973-01-30

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DE (1) DE2010264A1 (de)
FR (1) FR2036207A5 (de)
GB (1) GB1269465A (de)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4112496A (en) * 1974-12-13 1978-09-05 Sanders Associates, Inc. Capacitor matrix correlator for use in the correlation of periodic signals
WO2004093092A1 (de) * 2003-04-17 2004-10-28 Infineon Technologies Ag Improved magnetic memory
US20050018495A1 (en) * 2004-01-29 2005-01-27 Netlist, Inc. Arrangement of integrated circuits in a memory module

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3055775A (en) * 1960-06-10 1962-09-25 Space Technology Lab Inc Superconductive switching component
US3366519A (en) * 1964-01-20 1968-01-30 Texas Instruments Inc Process for manufacturing multilayer film circuits
US3525617A (en) * 1965-07-13 1970-08-25 Int Computers & Tabulators Ltd Method of making electrical circuit structure for electrical connections between components
US3540954A (en) * 1966-12-30 1970-11-17 Texas Instruments Inc Method for manufacturing multi-layer film circuits

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3055775A (en) * 1960-06-10 1962-09-25 Space Technology Lab Inc Superconductive switching component
US3366519A (en) * 1964-01-20 1968-01-30 Texas Instruments Inc Process for manufacturing multilayer film circuits
US3525617A (en) * 1965-07-13 1970-08-25 Int Computers & Tabulators Ltd Method of making electrical circuit structure for electrical connections between components
US3540954A (en) * 1966-12-30 1970-11-17 Texas Instruments Inc Method for manufacturing multi-layer film circuits

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4112496A (en) * 1974-12-13 1978-09-05 Sanders Associates, Inc. Capacitor matrix correlator for use in the correlation of periodic signals
WO2004093092A1 (de) * 2003-04-17 2004-10-28 Infineon Technologies Ag Improved magnetic memory
US20050018495A1 (en) * 2004-01-29 2005-01-27 Netlist, Inc. Arrangement of integrated circuits in a memory module

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Publication number Publication date
FR2036207A5 (de) 1970-12-24
DE2010264A1 (de) 1970-09-24
GB1269465A (en) 1972-04-06

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