GB1269465A - Improvements in or relating to memory matrices and the production thereof - Google Patents
Improvements in or relating to memory matrices and the production thereofInfo
- Publication number
- GB1269465A GB1269465A GB00739/70A GB1073970A GB1269465A GB 1269465 A GB1269465 A GB 1269465A GB 00739/70 A GB00739/70 A GB 00739/70A GB 1073970 A GB1073970 A GB 1073970A GB 1269465 A GB1269465 A GB 1269465A
- Authority
- GB
- United Kingdom
- Prior art keywords
- lamellμ
- memory
- bands
- layers
- notches
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/83—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption
- G11C29/832—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption with disconnection of faulty elements
Landscapes
- Semiconductor Memories (AREA)
- Control Of Motors That Do Not Use Commutators (AREA)
- Apparatuses And Processes For Manufacturing Resistors (AREA)
Abstract
1,269,465. Read only memory. SOC. INDUSTRIELLE HONEYWELL BULL. 5 March, 1970 [6 March, 1969], No. 10739/70. Heading G4A. [Also in Division H1] The invention relates to a read only memory and to a process for fabricating a memory matrix. An insulating support 1 is coated with a uniform resistive layer 20 and then with a first conductive layer 21. A series of parallel notch pairs 22, 23 is cut through the two layers to form a rectangular mesh pattern and an insulating plate 14 is placed between each pair to overlap the notches. The plate may be a varnish uniformly deposited and cut by photo engraving. A further conductive layer is added and the three layers are etched to provide orthogonal bands 2, 3 and resistive lamellµ 5 connecting bands 2 and 3, bands 2 being formed by the layers situated between the notches and by the portions connecting these layers. Notches are cut in the top layer of bands 2 adjacent the cross-over points with bands 3. The memory may be covered with a photosensitive lacquer having windows partially exposing the lamellµ, selective lamellµ may be masked and the remaining lamellµ etched away to provide the memory. The lamellµ may have fusible portions situated between enlarged pads so that selected lamellµ may be destroyed by passing large currents through the fusible portions.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR6906298A FR2036207A5 (en) | 1969-03-06 | 1969-03-06 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1269465A true GB1269465A (en) | 1972-04-06 |
Family
ID=9030226
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB00739/70A Expired GB1269465A (en) | 1969-03-06 | 1970-03-05 | Improvements in or relating to memory matrices and the production thereof |
Country Status (4)
Country | Link |
---|---|
US (1) | US3713885A (en) |
DE (1) | DE2010264A1 (en) |
FR (1) | FR2036207A5 (en) |
GB (1) | GB1269465A (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4112496A (en) * | 1974-12-13 | 1978-09-05 | Sanders Associates, Inc. | Capacitor matrix correlator for use in the correlation of periodic signals |
US6768150B1 (en) * | 2003-04-17 | 2004-07-27 | Infineon Technologies Aktiengesellschaft | Magnetic memory |
US20050018495A1 (en) * | 2004-01-29 | 2005-01-27 | Netlist, Inc. | Arrangement of integrated circuits in a memory module |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3055775A (en) * | 1960-06-10 | 1962-09-25 | Space Technology Lab Inc | Superconductive switching component |
US3366519A (en) * | 1964-01-20 | 1968-01-30 | Texas Instruments Inc | Process for manufacturing multilayer film circuits |
GB1143957A (en) * | 1965-07-13 | 1969-02-26 | Int Computers Ltd | Improvements in or relating to electrical circuit structures |
US3540954A (en) * | 1966-12-30 | 1970-11-17 | Texas Instruments Inc | Method for manufacturing multi-layer film circuits |
-
1969
- 1969-03-06 FR FR6906298A patent/FR2036207A5/fr not_active Expired
-
1970
- 1970-03-02 US US00015651A patent/US3713885A/en not_active Expired - Lifetime
- 1970-03-05 DE DE19702010264 patent/DE2010264A1/en active Pending
- 1970-03-05 GB GB00739/70A patent/GB1269465A/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
FR2036207A5 (en) | 1970-12-24 |
DE2010264A1 (en) | 1970-09-24 |
US3713885A (en) | 1973-01-30 |
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