US3623013A - Data processing network and improved terminal - Google Patents

Data processing network and improved terminal Download PDF

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US3623013A
US3623013A US849822A US3623013DA US3623013A US 3623013 A US3623013 A US 3623013A US 849822 A US849822 A US 849822A US 3623013D A US3623013D A US 3623013DA US 3623013 A US3623013 A US 3623013A
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Prior art keywords
terminal
data
address
remote
message
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Cornelius C Perkins
Godfrey Liu
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Unisys Corp
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Burroughs Corp
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Assigned to BURROUGHS CORPORATION reassignment BURROUGHS CORPORATION MERGER (SEE DOCUMENT FOR DETAILS). DELAWARE EFFECTIVE MAY 30, 1982. Assignors: BURROUGHS CORPORATION A CORP OF MI (MERGED INTO), BURROUGHS DELAWARE INCORPORATED A DE CORP. (CHANGED TO)
Assigned to UNISYS CORPORATION reassignment UNISYS CORPORATION MERGER (SEE DOCUMENT FOR DETAILS). Assignors: BURROUGHS CORPORATION
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/22—Handling requests for interconnection or transfer for access to input/output bus using successive scanning, e.g. polling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices

Definitions

  • Assignee Burroughs Corporation W t ABSTRACT A data processing system having a central or main data processor and a plurality of remote data terminals each having at least one selectively changeable terminal address, The central processor is coupled in a poll-select environment to the various remote terminal processors via :1
  • the respective remote terminals are able [52] U.S.Cl 340M725 to modify the poll-select sequence as set up by the central [5!] lnLCL "04 3/00 processor by selectively changing its terminal address for [50] FieldotSear-eh 340/1725 either the poll or select mode. Additionally. groups of the remote terminals may be assigned a selectively changeable Relflfllc Cmd group or broadcast address which may be changed either lo- UNITED STATES PATENTS cally at the remote terminal or remotely by the central proces- 3,245.038 4/l966 Stafford et al.
  • This invention relates to an on-line data processing system and more particularly to an improved on-line multiterminal data processing system in which the remote terminals individually have a selectively changeable address capability.
  • the address of the remote terminals may be altered locally at the remote terminal or remotely in response to a command from the central processor.
  • a real time or on-line system is generally defined as a data processing system in which the time delay in a central processor responding to an input stimulus from a remote terminal is negligible in the time reference of the remote users equipment.
  • the terminal disclosed and claimed in the hereinabove identified Perkins et al. patent permits a wide variation in the system discipline of an on-line data procesing system.
  • the improved remote terminal. sold commercially as the Burroughs TCSOO. greatly facilitates on-line systems by permitting the communication line-discipline function to be handled remotely at each remote terminal and by providing computational capability at each such terminal.
  • These additional terminal capabilities in effect relieve the central processor of the time consuming task of establishing communication linediscipline as was necessary in the prior art systems using for example the teletypetype terminals at the remote station.
  • Upstream communication between ones of the remote terminals and a central data processor may be blocked in effect by the poll or sequence routine established in the system in view of a particular communication backlog. For example, in the morning after the central processor has been operating during off-hours, the central processor or the terminals may have a backlog of information to be sent over the communication net. During this period in which the central processor is in a select mode of operation for an extended period of time, one or more remote terminals may wish to communicate over the same line with the central processor. This of course is not possible in a normal poll or select environment as the central processor generally establishes the routine or frequency with which the respective terminals are selectively addressed, for example in a poll or select sequence.
  • a terminal In this mode of operation a terminal must await its turn as determined by the frequency with which the central procexor addresses the respective terminal in either a poll or select mode.
  • the problem of a remote terminal obtaining access to the computer via the communication link is further compounded in those instances in which for one reason or another various high traffic terminals are polled more frequently than low traffic terminals or the central processor goes into an extended select mode sequence.
  • the one or more remote terminals desiring access to the central processor on a particular mode basis would simply have to await their normal turn as determined by the computer controlled inquire message sequence.
  • FIG. 1 is a block diagram of a data processing system utilizable in accordance with the principles of the present invention
  • FIG. 2 is a block diagram of a remote terminal embodying the principles of the present invention
  • FIG. 3 is a logical block diagram of a remote terminal computer embodying the principles of the present invention.
  • FIG. 4 is a logic flow diagram of one method of operating applicant's remote terminal in an on-line communication net with a central data processor
  • FIG. 5 is a logic flow diagram of yet another method of operating applicants selectively addressable remote terminal in accordance with another aspect of the principles of the present invention.
  • FIG. I there is shown a block diagram of a typical on-line data communication system in which the principles of the present invention are utilizable.
  • a central data processor II with its associated complement of input/output storage devices l3, l5, 17. I9 and 21, is connected via a communication link 22 to a plurality of remote data terminals 23.
  • the central data processor may be located, for example, in the main business office of a commercial firm and the remote terminals 23 may be located in the branch offices of the commercial firm.
  • the branch offices may be in the same general location or remote therefrom and in each case the remote terminals 23 are connected via a modem or line communication adapter 25 to the communication link 22.
  • the communication link 22 may include for example standard telephone lines connecting the remote data terminals 23 via a central communication dial exchange 27 to the site of the central processor 11.
  • the remote data terminals are preferably arranged in a multidrop or multipoint poll and select transmission environment whereby the respective remote data terminals 23 are arranged to perform data processing functions in accordance with their respective programs ofi-line and to communicate with the central data processor ll whenever the remote terminal is ad' dressed by an inquiry message.
  • the remote terminal 23 may be described as comprising three major sections: a remote processor 33. including a main memory 35 and an input/output keyboard 37; a line discipline processor 41. with its auxiliary memory 43 and terminal address control logic 45; and a tenninal buffer store 47.
  • the output of the buffer store 47 is coupled by an appropriate device. for example. a modem 25 to the input of the communication line 22.
  • the structure and operational interrelationship of the sections of the terminal 23 is discussed in detail hereinafter in conjunction with FIGS. 3. 4 and 5 with similar reference numerals being used to designate the respective sections of the terminal 23.
  • FIGS. 1 and 2 in conjunction with table I below. the fonnat and function of the various portions of inquiry and response messages transmitted between the central processor and the remote terminals may be understood.
  • the remote terminal 23 is preferably capable of operating in either an off-line or an on-line mode. In the off-line mode, processing tasks are accomplished by'the remote processor 33 in accordance with program and object data stored in its memory. In the on-line mode, the remote processor 33 relies upon communications with the central processor over the communication link for at least a portion of its operation. In the on-line mode, the remote terminal 23 preferably operates in a poll and select environment.
  • a poll inquiry message or poll is defined as a message by which the central data processor ll interrogates one of a plurality of addressed remote terminals. for example in a predetermined sequence, and inquires whether the addressed remote tenninal has a message ready for transmission to the central processor.
  • a select inquiry message or select is defined as a message by which the central data processor interrogates one of a plurality of addressed remote terminals in the communication net informing the addressed remote terminal that the central processor has a message ready for transmission to the addressed remote terminal.
  • the line-discipline processor 4 In either the poll or select mode. ifan addressed remote terminal is not ready to receive a message. i.e.. it is either being operated off-line or it is otherwise not ready to receive or send a message in response to the received inquiry message addressed to it, the line-discipline processor 4] automatically responds with an appropriate "not ready" message to the central processor 11. As shown in entries B and D of table I. the line-discipline processor 4i responds to a poll with an EOT and to a select with a NAK to indicate that it is not ready to send or receive a message respectively. Upon receiving the negative acknowledgement from the addressed remote processor. the central processor either retransmits its message which may have been garbled in the transmission channel or it may continue on its poll or select sequence to the next remote terminal in the normal addressing sequence.
  • the message format includes. reading left to right, characters 1. 2. 3 N.
  • the respective characters indicated are those of The USA Standard Code For Information Interchange (USASCII).
  • Entry A of table I illustrates a message exchange for a typical poll operation.
  • the first character in the message transmitted by the central data processor ll comprises an end of transmission character EOT. All transmissions may begin with this EOT character or another suitable character.
  • EOT character Following the EOT character are two address characters AD] and AD2.
  • AD address characters
  • each remote terminal 23 would have assigned to it a plurality of dual character addresses which are for example stored in an expected message portion of the memory of the line discipline procemor 41.
  • the poll POL and inquiry ENQ characters Following the address characters are the poll POL and inquiry ENQ characters.
  • Entries (I and D of table I show a similar message from the central data processor 11 as assembled and transmitted for the select message with the SEL character replacing the POL character of the poll message format illustrated in entries A and 8.
  • each terminal 23 through its line discipline processor 41 responds only to the messages specifically addressed to that terminal even though the communication network is in what is known as a multipoint or multidrop mode.
  • each terminal 23 receives all messages transmitted by either a remote terminal or the central processor. If as in prior systems each terminal 23 has only a single address. the terminal is in effect a slave to the central processor which establishes the poll and select routine and the frequency with which each respective terminal 23 in the net will receive a poll or select message addressed to it.
  • the terminal address control logic 45 which may comprise a shift register or other memory store and logic gating for storing an address generated either by the arithmetic unit of the remote processor 33 or of line discipline procesor 4
  • a remote terminal is enabled to gain access to the central processor by interrupting the pollselect sequence established by the remote processor. Basically this interruption of the poll or select mode may be accomplished by either programming the central processor to change the inquiry transmission mode if it does not receive either a positive or negative acknowledgment from the terminal to which the last message was addressed or by having the remote terminal transmit a control character message if its address has been modified.
  • FIGv 3 there is illustrated a logic block dia gram of applicantremote data terminal 23.
  • the remote data terminal 23 comprises three major sections: the remote processor 33. the line discipline processor 4! and the terminal buffer 47.
  • the remote or terminal processor 33 preferably comprises a stored program machine in which object data is manipulated in an arithmetic unit 51 in accordance with a sequence of microprogram instructions stored in and withdrawn from the main memory 35 in a predetermined sequence.
  • the input channel 36 and keyboard 37 are arranged to selectively enter program and object data into the processor 33 via an input buffer register 39.
  • the main memory 35 may comprise, for example, a rotatable magnetic disk having a plurality of read/write heads for accessing an unrestricted general memory section and a plurality of read only heads for accessing a restricted stored program portion of the memory.
  • the information and object data stored in the main memory is processed in the arithmetic unit 5] which may include, for example, a full adder and appropriate input gating selection networks, not shown.
  • a memory address register (MAR) 53 is operatively associated with the memory select matrix via gates 55 and 57 to access an appropriate portion of memory in response to an address loaded in the MAR by the instruction decoder 59.
  • the memory address register 53 In operation of the remote processor in accomplishing its tasks as designated by the program being run, the memory address register 53 periodically addresses and interrogate: the main memory and withdraws therefrom an appropriate pro gram instruction indicated by the address located by the instruction decoder 59.
  • the micro instructions withdrawn from the read only portion of memory are sequentially loaded into the instruction decoder 59.
  • the output of the instruction decoder 59 enables appropriate control logic for controlling various gating functions in the processor in accordance with the contents of the instruction decoder register 59.
  • the instruction decoder in response to withdrawn program instructions controls the state machine 61 via gate 63.
  • the state machine 6 which may comprise a counter generates a sequence of timed machine state levels or timing pulses for controlling the various logic functions of the processor including, for example, the operation of an adder or the exchange of information between the memory the input buffer 39, the instruction 59 or the printer 65.
  • the arithmetic logic 51 or the memory 35 of the processor 33 may directly actuate the printer 65 via gates 67 and 69 thus providing a hard copy output of the results of the processor's computation.
  • the processor 33 As in a normal stored program machine, after each instruction is decoded by the instruction decoder 59 and executed by the memory 35 and the arithmetic logic 51, the processor 33, for example through its adder logic, generates an advance signal to increment an instruction counter associated with the instruction decoder thereby stepping the instruction counter to the next count in its orderly count sequence. In response to the new contents of the instruction counter, the next in a series of micro instructions would be withdrawn from main memory 35 and serially fed to the instruction decoder 59. In this manner, the respective sequential syllables of a memory word of a program instruction would be transferred to the instruction decoder to properly energize the control matrix for withdrawing the appropriate program steps and/or data from memory.
  • the remote processor 33 is capable of operating on-line and communicating with the central processor II as shown in FIG. I.
  • This communication with the central processor is controlled by the line-discipline processor 41.
  • the line-discipline processor 41 is preferably a stored program machine and may be similar in structure and operation to the remote processor 33.
  • the function of the line-discipline processor is to establish linediscpline in accordance with a stored microprogram for controlling the assembly, editing, formatting and parity genera tion-check of messages to be transmitted to and as received from the central processor for the remote processor 33.
  • the line-discipline processor is preferably similar in structure and operation to the remote processor 33.
  • An auxiliary or message memory 43 is arranged to store messages to be sent to and received from the central processor and to store a series of micro instructions for controlling the operation of the arithmetic unit 75 of the line-discipline discipline processor 41.
  • the message memory 43 may for example comprise a rotatable memory having a read-write portion for storing messages and a read only memory for storing micro instructions.
  • a head selection matrix, not shown, which is responsive to the memory address register 77 is used to control the accessing of the memory 43 to withdraw micro instructions and to withdraw messages stored therein.
  • the memory address register 77 of the line-discipline processor 41 controls the access to and reading of the micro instructions from the message memory to a decode register 79.
  • the micro instructions withdrawn from the memory 43 are decoded in the decode register 79 with the output of the decode register 79 controlling the state machine 8] in accordance with the contents of the decoded program step.
  • the decode register 79 controls the generation of appropriate logic gating signals for controlling the operation of the ariflimetic unit 75, which may comprise a full adder and appropriate gating for manipulating data in accordance with the decoded micro instructions.
  • state machine 8i generates appropriate timing signals in response to a signal from the oscillator 83 to control the operation of the logic gates 85, 87 and 89 and for example logic gate which control the exchange of information between the memory addres register 77 and arithmetic unit 75.
  • the operation of the state machine which may comprise a counter may be further controlled by appropriate control signals TX and RX which designate a func tion of the transmit or receive state of the line-discipline processor and buffer 47.
  • the remote processor 33 When the remote processor 33 has a message to be transmitted to the central processor II, the message to be transmitted is originally assembled by the remote processor 33 in a specific area of the memory 35. After monitoring and determining the condition of the transmit and receive flag registers 91 and 93 respectively. the remote processor selects an appropriate time and transfers the message from the memory 35 of the remote processor 33 to the memory 43 of the line discipline processor 41 for example via arithmetic logic 5] and decoder 59. Thereafter the remote 33 is free to return to its off-line task, and the line discipline processor 41 awaits the receipt of a poll from the central process I] to initiate the transmission of the message stored in the message memory 43.
  • the sequence and format of inquiry and response messages transmitted between the line-discipline processor 41 and the central processor II has been discussed hereinabove in detail in conjunction with FIGS. I and 2 and Table I.
  • the line-discipline processor 4] When the line-discipline processor 4] receives an inquiry message from the central processor I]. the appropriate RX signal, Le, a signal for example. signifying carrier detect, actuates the logic gate 95 thereby initiating the operation of the state machine 81 in the receive mode.
  • the received inquiry message is transferred bit serially from the modem 25 to the bufier storage 47 as it is received serially from the line.
  • the information stored in the buffer 47 is then compared in the comparator I01 with an expected message format previously stored, for example, in an expected message store 103, which may comprise any memory. for example, an array of flip-flops arranged to store encoded information in the form of the expected mesage format as hereinabove described in conjunction with table I.
  • the logic gates 105 and 107 in conjunction with suitable timing signals for example through [5 may be employed to transfer or couple the contents of the respective stages of the buffer store 47 and the expected message store and 103 to the comparator In this manner, the respective binary bits of the appropriate portions of the received message and expected message store may be compared bit by bit to check and determine the equivalence therebetween. Additionally, the respective bits of the received message comprising the parity bit and the address bits may be compared to determine whether parity of the received message checks and whether the message as received is addressed to the receiving terminal.
  • the output of the comparator IOI would be logically true and gate 109 would appropriately signal the arithmetic unit 75 of the line-discipline processor 4
  • the arithmetic unit 75 of the line discipline processor appropriately sets the memory address register 77 to withdraw from memory 43 an appropriate positive acknowledgement if it was determined that the line-discipline processor 4I is properly conditioned to respond to the inquiry message i.e., either a poll or select inquiry. Thereafter the message to be transmitted to the central processor may be read from message memory 43 via the logic gate 89 with an appropriate timing signal to the bufler store 47 for transmission to the central processor I I via the communication link 22.
  • the remote terminal 23 to which a particular inquiry message is addressed responds by sending a posi tive or negative acknowledgement to the central processor via the communication link.
  • the central processor 11 is able to establish and maintain a sequence or series of inquiry messages thereby providing orderly data transmission.
  • this slave-type response from the addressed remote terminal does not permit flexibility in those instances, for example, where the terminal requires a mode of transmission different than that characterized by a particular received inquiry message.
  • a terminal is given increased flexibility by providing logic circuitry, responsive either to the operator or to a received message. for selectively modifying or changing the address of the terminal.
  • the gates I21 and I23 couple the expected message store I03 to terminal address control register 125.
  • the input to the terminal address control register 125 is coupled via the gates I27 and 129 to the instruction decoder 59 of the remote processor 33 and the decode register 79 of line-discipline processor 4I.
  • the operator attending the remote terminal 23 or the line-discipline processor 4I under its microprogram control or in response to a received command. may appropriately energize the gates 127 and I29 to effect a change in the address of the remote terminal as stored in the expected message store 103.
  • This change may be accomplished by withdrawing the address from the expected message store I03 and replacing it with a new address determined by the line-discipline processor and transferred to the terminal addresscorrtrol register 125.
  • the games I21 and 123 are arranged to interchange data between the terminal address control register 125 and the store I03.
  • the gate 121 when energized couples information from the expected message store 103 to the register I25 while the gate 123 is arranged to couple information from the terminal address control register 125 to the expected message store 103.
  • the addressed portion of an expected message format as described hereinabove in conjunction with table I. may be modified or replaced.
  • This control function could of course be assigned to the microprogram of the linediscipline processor 4].
  • terminal address control logic 45 (FIG. 2) which as shown in FIG. 3 may comprise a terminal address control register I25 and appropriate logic gating IZI, I23, I27 and I29 for controlling the exchange of address data in the expected message store I03, greatly enhances the communication responsiveness and capability of the remote terminal.
  • This terminal address control logic 45 relieves the terminal from the necessity of slavishly responding to each inquiry of the central processor. For example if the operator is performing a particular routine during which it is undesirable to be in terrupted, the operator may appropriately enter information via the keyboard 37 which through decoder 59 energizes the gate 127 to initiate the exchange of terminal address information between the terminal address control register I25 and expected message store 103.
  • the operator for example insures that the terminal will not recognize a message which the central processor 11 has transmitted to the terminal under its unmodified or normal terminal address.
  • the terminal 23 when the terminal 23 is adapted to operate in a poll and select mode of transmission, it is preferable to have separate message address storage locations in the expected message store I03 for the respective poll and select inquiry messages.
  • the terminal 23 may continue to respond to the inquiry messages for which the remote terminal address portion of the expected message has not been modified.
  • the central processor's inquiry message program may be designed to include an automatic branch or jump to the other type or mode of inquiry message in the event an addressed tenninal fails to respond by sending either a positive or negative acknowledgement.
  • an addressed remote terminal may cause the central processor to change from one mode of inquiry message to the other by changing its address for a particular mode thereby causing the terminal to fail to recognize any message which is addressed to it under its old address thereby inhibiting the transmission of a response, i.e., ACK or NAK, from the addressed terminal.
  • a response i.e., ACK or NAK
  • FIGS. 4 and 5 in conjunction with the logic diagram shown in FIG. 3 two methods ofoperating appli' cant's remote terminal in a communication net will be explained.
  • the flow diagrams of FIGS. 4 and 5 represent the states or sequential steps that the logic of the terminal performs in order to determine whether a received inquiry message is addressed to it, and if so what action should be taken.
  • the linediscipline processor as determined by the state machine 81 normally resides in the idle mode I35.
  • the state machine 8I conditions the logic of the line-discipline processor 4] to look for an expected message format.
  • the receipt of a transmission reception signal RX for example a carrier detect, takes the line-discipline processor out of the idle mode and into the message receive state I37.
  • the inquiry message is stored in the buffer 47.
  • the state machine 81 After, for example, an appropriate number of data bits are received, as determined by the inquiry message format the state machine 81 generates an appropriate signal to put the line-discipline processor 41 in the parity check mode 139.
  • RX transmission reception signal
  • the remote processor would move to the respond-to-inquiry state I43 in which the linediscipline processor 41 would through its microprogram generate the appropriate acknowledgement, i.e., ACK or NAK, in accordance with its state of readiness at that time.
  • the state machine 81 would move the line-discipline processor to its text transfer state 145 wherein the sequence of withdrawing the message from memory 43 and transferring it to the buffer store 47 would begin.
  • the line-discipline processor would generate an appropriate check bit or sequence for inclusion in the message as hereinabove described in conjunction with table I. If the message were properly received at the central processor I I, it would respond with an acknowledgement stating that the message had been properly received whereupon the linediscipline processor 41 would move to state I47 to recognize that the parity either checked or did not check and go through the appropriate retransmit or return to its idle state I35.
  • the address of the received message did not favorably compare with the address portion of the expected mesage stored in expected message store 103, then either the message was not intended for the receiving terminal, or it was garbled during transmission which would be an error, or the message portion of the expected message format stored in store 103 has been changed.
  • the response of the terminal 13 at this junction would depend upon whether the response was to be active or passive. As shown in FIG. 4 if the response is active then upon failure of the inquiry message check to correspond, the line-discipline processor would move to state 149 at which it would determine whether its terminal address had been changed or modified. If it had not, the terminal, under control of the state machine 81, would ignore the message by returning to the idle state 135. If the terminal address of the receiving tenninal 23 had been changed and it was in the active response mode, the line-discipline processor 4! would move to the control character state I51 in which it would generate an appropriate control character for transmission to the central processor II.
  • This control character could signify to the central processor 1] from the addressed terminal to change transmission modes, i.e., poll to select or the reverse and to again address an inquiry message to it. In this mode of transmission, the addressed terminal would then return to the idle state 135 and await the receipt of the next inquiry message from the central processor.
  • the linediscipline processor moves to state 155 in which the received inquiry message is compared to determine whether it comprises a poll or select inquiry message. This comparison is made as hereinabove described by comparing appropriate bits of the received inquiry message with correspondingly designated bits that are stored in the expected message store 103. Ifa true comparison is made between the received and stored mtaage, the gate I09 (FIG.
  • the line-discipline processor 41 signals the arithmetic unit 75 of the line-discipline processor 41 as to which type of inquiry message has been properly received. Thereupon the line-discipline processor advances to the appropriate retrieve message address state 157 or I59, depending upon the type message received. As shown the retrieve address states may be independently modified by either an operator input or the remote command by placing the state machine in the modify address mode state 161.
  • whenever the address portion of the receive message fails to compare with that of the stored inquiry message format is determined by whether the communication system and particularly the terminals are in the active or passive mode.
  • the remote line-discipline processor 41 transmitted a control character to the central processor in place of the normal ACK or NAK response thereby alerting the processor of its new address.
  • state 141 is positive (yes) and the line-discipline processor moves successfully through states 145 and 147, as hereinabove described in conjunction with FIG. 4 to complete the transfer of the message from the terminal 23 to the central processor I I.
  • the remote terminal 23 is in the passive mode, i.e., no control address signal is to be sent to the central processor, and the address portion of the inquiry message does not compare with the terminal address in state 141, the terminal returns to the idle state I35 whether the address of the remote terminal was altered or not as shown by state I65.
  • the central processor is preferably programmed to change the mesage inquiry mode of transmission, i.e., from poll to select or from select to poll, and to readdress the terminal 23 which failed to respond to a previous inquiry message addressed to it as shown in state I67.
  • the remote tenninal 23 returns to the idle state I35 and the central processor ll after it changes inquiry mode readdresses the terminal which failed to respond to the previous inquiry message thereby accommodating the terminal with the type inquiry message which it requested by its passive action, i.e., its failure to respond to an inquiry message addressed by the central processor to it.
  • the remote terminal may be adapted to have an additional address for use for example in a broadcast mode.
  • the broadcast mode may be defined as that transmission mode in which a predetermined number of remote terminals are grouped under a common broadcast address with each terminal of the broadcast group being able to respond appropriately, for example in a predetermined sequence. in response to the receipt of a broadcast message addressed to that group.
  • An improved addressable data terminal operatively coupled in a data communication system with a central procesor through a communication net, said improved addressable data terminal comprising:
  • tenninal address control means at each one of the data terminals including memory storage means for storing a designated terminal address data for such one terminal, said address data being in coded form and distinguishable from respective data of others of the data terminals in the system,
  • comparator means for comparing the address portion of each received inquiry message with the terminal address stored in said terminal address control means to determine if the portion of the received message corresponds to the address data of said receiving terminal, and terminal address modifying means for selectively modifying said terminal address data so as to change the address data used by said comparator means for determining whether the address portion of a received inquiry message corresponds to the stored terminal address data.
  • terminal address modifying means comprises register means for storing a sequence of data bits uniquely designating the original data terminal address in a predetermined coding system
  • the improved data terminal as defined in claim 1 wherein said terminal is operable in a poll-select transmissiom mode and additionally including separate storage means for storing distinct terminal address data designating respectively a poll-inquiry message address and a select-inquiry message address.
  • said terminal address modifying means includes means for selectively and independently modifying the addres data representing the poll-inquiry message address or the selectinquiry message addres respectively.
  • a system for transmitting data between a central data site and plurality of remote data terminal sites said system com prising means at the central data site adapted to transmit a sequence of inquiry messages having an address portion and nonaddress portion to the remote terminal data sites.
  • a method of transmitting data over a communication link between a central processor site and designatable ones of a plurality of addressable remote data terminals coupled via said communication link to said central processor site comprising the steps of generating a sequence of inquiry messages at said central data processor site,
  • terminal address data uniquely designating the address of the remote terminal at which it is stored, temporarily storing received inquiry messages at each of said ten-ninals receiving said inquiry message,
  • the method of claim '7 additionally including the step of transmitting a control character from a data terminal to said central site whenever said data terminal receives an inquiry message addressed to it and its normal terminal address data has been modified.
  • the improved addressable data terminal defined in claim 1 additionally including means responsive to said comparator means for transmitting a predetermined message to the central processor.

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US849822A 1969-08-13 1969-08-13 Data processing network and improved terminal Expired - Lifetime US3623013A (en)

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JP (2) JPS5746097B1 (de)
BE (1) BE752925A (de)
CH (1) CH534924A (de)
DE (1) DE2039040C3 (de)
FR (1) FR2058236B1 (de)
GB (1) GB1341686A (de)
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US3882305A (en) * 1974-01-15 1975-05-06 Kearney & Trecker Corp Diagnostic communication system for computer controlled machine tools
US4014004A (en) * 1975-08-04 1977-03-22 Harris Corporation Automatic report register
US4041469A (en) * 1974-12-13 1977-08-09 Pertec Corporation CRT key station which is responsive to centralized control
US4188668A (en) * 1976-10-04 1980-02-12 International Business Machines Corporation Computer-controlled copier-printers
DE3003340A1 (de) * 1980-01-30 1981-08-06 Siemens AG, 1000 Berlin und 8000 München Verfahren und schaltungsanordnung zur uebertragung von binaeren signalen zwischen ueber ein zentrales busleitungssystem miteinander verbundenen anschlussgeraeten
USRE31247E (en) * 1974-01-15 1983-05-17 Kearney & Trecker Corporation Diagnostic communications system for computer controlled machine tools
FR2531791A1 (fr) * 1982-08-16 1984-02-17 Fairchild Camera Instr Co Circuit d'adressage pour equipement de test automatique
US4935866A (en) * 1981-04-03 1990-06-19 Compagnie Industrial Des Telecommunications Cit-Alcatel Multiprocessor control system
US5084875A (en) * 1989-12-13 1992-01-28 Joseph Weinberger System for automatically monitoring copiers from a remote location
US5214772A (en) * 1989-12-13 1993-05-25 Joseph Weinberger System for automatically monitoring copiers from a remote location
US5293196A (en) * 1991-04-18 1994-03-08 Canon Kabushiki Kaisha Communication control apparatus for monitoring a condition of a machine and for transmittiing the condition to an external apparatus
US5333286A (en) * 1989-12-13 1994-07-26 Joseph Weinberger Two way copier monitoring system
US5359391A (en) * 1991-04-18 1994-10-25 Canon Kabushiki Kaisha Equipment control apparatus
US5488454A (en) * 1991-04-18 1996-01-30 Canon Kabushiki Kaisha Control of equipment and of communication with plural units of equipment
US5500944A (en) * 1994-01-10 1996-03-19 Fujitsu Limited Fault indication system in a centralized monitoring system
US5530896A (en) * 1992-06-19 1996-06-25 Euro Cp S.A.R.L. Appliance control process for matching slave units to control units and for automatically assigning addresses to the slave units
US5721946A (en) * 1992-05-13 1998-02-24 Mitsubishi Denki Kabushiki Kaisha Signal transfer method having unique word assigned to terminal stations appended before control frames originated from control station and terminal stations
US5894416A (en) * 1991-04-18 1999-04-13 Canon Kabushiki Kaisha Equipment control unit
US6009284A (en) * 1989-12-13 1999-12-28 The Weinberger Group, L.L.C. System and method for controlling image processing devices from a remote location
US6064915A (en) * 1991-04-18 2000-05-16 Canon Kabushiki Kaisha Equipment control apparatus
US20090164628A1 (en) * 2007-12-20 2009-06-25 Realtek Semiconductor Corp. Circuit and method for setting data and their application to integrated circuit
US20140156069A1 (en) * 2002-07-25 2014-06-05 Intouch Technologies, Inc. Medical tele-robotic system with a master remote station with an arbitrator

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US4639889A (en) * 1980-02-19 1987-01-27 Omron Tateisi Electronics Company System for controlling communication between a main control assembly and programmable terminal units
JPS59178221U (ja) * 1983-05-13 1984-11-28 株式会社　東京衛材研究所 自動封緘包装箱
GB8432302D0 (en) * 1984-12-20 1985-01-30 Conway R Installation for visually displaying pre-determined messages
CN113626508B (zh) * 2021-07-13 2024-08-06 交控科技股份有限公司 列车特征库管理方法、装置、电子设备及可读存储介质

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US3407387A (en) * 1965-03-01 1968-10-22 Burroughs Corp On-line banking system
US3403382A (en) * 1965-06-08 1968-09-24 Gen Signal Corp Code communication system with control of remote units

Cited By (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3882305A (en) * 1974-01-15 1975-05-06 Kearney & Trecker Corp Diagnostic communication system for computer controlled machine tools
DE2500086A1 (de) * 1974-01-15 1975-07-24 Kearney & Trecker Corp Diagnostisches verbindungssystem fuer computergesteuerte werkzeugmaschinen
USRE31247E (en) * 1974-01-15 1983-05-17 Kearney & Trecker Corporation Diagnostic communications system for computer controlled machine tools
US4041469A (en) * 1974-12-13 1977-08-09 Pertec Corporation CRT key station which is responsive to centralized control
US4014004A (en) * 1975-08-04 1977-03-22 Harris Corporation Automatic report register
US4188668A (en) * 1976-10-04 1980-02-12 International Business Machines Corporation Computer-controlled copier-printers
DE3003340A1 (de) * 1980-01-30 1981-08-06 Siemens AG, 1000 Berlin und 8000 München Verfahren und schaltungsanordnung zur uebertragung von binaeren signalen zwischen ueber ein zentrales busleitungssystem miteinander verbundenen anschlussgeraeten
US4404650A (en) * 1980-01-30 1983-09-13 Siemens Aktiengesellschaft Method and circuit arrangement for transmitting binary signals between peripheral units which are connected to one another via a central bus line system
US4935866A (en) * 1981-04-03 1990-06-19 Compagnie Industrial Des Telecommunications Cit-Alcatel Multiprocessor control system
FR2531791A1 (fr) * 1982-08-16 1984-02-17 Fairchild Camera Instr Co Circuit d'adressage pour equipement de test automatique
US6282383B1 (en) 1989-12-13 2001-08-28 The Weinberger Group, L.L.C. Method of monitoring and initiating operational commands in an image processing device
US5603060A (en) * 1989-12-13 1997-02-11 Joseph Weinberger Method of controlling copy machines from a remote location
US7417753B2 (en) 1989-12-13 2008-08-26 Imaging Portals, Inc. System for automatically monitoring copiers from a remote location
US5333286A (en) * 1989-12-13 1994-07-26 Joseph Weinberger Two way copier monitoring system
US20050200882A9 (en) * 1989-12-13 2005-09-15 Joseph Weinberger System for automatically monitoring copiers from a remote location
US5361265A (en) * 1989-12-13 1994-11-01 Joseph Weinberger System for automatically monitoring copiers from a remote location
US20020048462A1 (en) * 1989-12-13 2002-04-25 Joseph Weinberger System for automatically monitoring copiers from a remote location
US5084875A (en) * 1989-12-13 1992-01-28 Joseph Weinberger System for automatically monitoring copiers from a remote location
US5214772A (en) * 1989-12-13 1993-05-25 Joseph Weinberger System for automatically monitoring copiers from a remote location
US6009284A (en) * 1989-12-13 1999-12-28 The Weinberger Group, L.L.C. System and method for controlling image processing devices from a remote location
US6064915A (en) * 1991-04-18 2000-05-16 Canon Kabushiki Kaisha Equipment control apparatus
US5359391A (en) * 1991-04-18 1994-10-25 Canon Kabushiki Kaisha Equipment control apparatus
US5293196A (en) * 1991-04-18 1994-03-08 Canon Kabushiki Kaisha Communication control apparatus for monitoring a condition of a machine and for transmittiing the condition to an external apparatus
US5894416A (en) * 1991-04-18 1999-04-13 Canon Kabushiki Kaisha Equipment control unit
US5420667A (en) * 1991-04-18 1995-05-30 Canon Kabushiki Kaisha Communication control apparatus for monitoring a condition of an image forming apparatus and inhibiting transmission of data when a power supply means is turned off
US5493364A (en) * 1991-04-18 1996-02-20 Canon Kabushiki Kaisha Equipment control apparatus having means to communicate with a centralized control apparatus
US6112035A (en) * 1991-04-18 2000-08-29 Canon Kabushiki Kaisha Equipment control apparatus
US5488454A (en) * 1991-04-18 1996-01-30 Canon Kabushiki Kaisha Control of equipment and of communication with plural units of equipment
US5721946A (en) * 1992-05-13 1998-02-24 Mitsubishi Denki Kabushiki Kaisha Signal transfer method having unique word assigned to terminal stations appended before control frames originated from control station and terminal stations
US5530896A (en) * 1992-06-19 1996-06-25 Euro Cp S.A.R.L. Appliance control process for matching slave units to control units and for automatically assigning addresses to the slave units
US5500944A (en) * 1994-01-10 1996-03-19 Fujitsu Limited Fault indication system in a centralized monitoring system
US20140156069A1 (en) * 2002-07-25 2014-06-05 Intouch Technologies, Inc. Medical tele-robotic system with a master remote station with an arbitrator
US9849593B2 (en) * 2002-07-25 2017-12-26 Intouch Technologies, Inc. Medical tele-robotic system with a master remote station with an arbitrator
US10315312B2 (en) * 2002-07-25 2019-06-11 Intouch Technologies, Inc. Medical tele-robotic system with a master remote station with an arbitrator
US20190248018A1 (en) * 2002-07-25 2019-08-15 Intouch Technologies, Inc. Medical tele-robotic system with a master remote station with an arbitrator
US10889000B2 (en) * 2002-07-25 2021-01-12 Teladoc Health Medical tele-robotic system with a master remote station with an arbitrator
US20210241902A1 (en) * 2002-07-25 2021-08-05 Teladoc Health, Inc. Medical tele-robotic system with a master remote station with an arbitrator
US20090164628A1 (en) * 2007-12-20 2009-06-25 Realtek Semiconductor Corp. Circuit and method for setting data and their application to integrated circuit
US9473344B2 (en) * 2007-12-20 2016-10-18 Realtek Semiconductor Corporation Circuit and method for setting data and their application to integrated circuit

Also Published As

Publication number Publication date
SE414086B (sv) 1980-07-07
JPS5846730B1 (de) 1983-10-18
GB1341686A (en) 1973-12-25
DE2039040C3 (de) 1982-04-08
DE2039040B2 (de) 1976-06-16
DE2039040A1 (de) 1971-04-01
BE752925A (fr) 1970-12-16
FR2058236B1 (de) 1973-01-12
NL7011182A (de) 1971-02-16
JPS5746097B1 (de) 1982-10-01
NL165858B (nl) 1980-12-15
FR2058236A1 (de) 1971-05-28
CH534924A (de) 1973-03-15
NL165858C (nl) 1981-05-15

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