US3564139A - Circuit arrangement for pushbutton-controlled electronic parallel delivery of telegraphic impulses - Google Patents

Circuit arrangement for pushbutton-controlled electronic parallel delivery of telegraphic impulses Download PDF

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Publication number
US3564139A
US3564139A US795669*A US3564139DA US3564139A US 3564139 A US3564139 A US 3564139A US 3564139D A US3564139D A US 3564139DA US 3564139 A US3564139 A US 3564139A
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United States
Prior art keywords
impulse
impulses
flip
inputs
storer
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Expired - Lifetime
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US795669*A
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English (en)
Inventor
Camillo Bodenstein
Herbert Strassner
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Siemens AG
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Siemens AG
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L13/00—Details of the apparatus or circuits covered by groups H04L15/00 or H04L17/00
    • H04L13/16—Details of the apparatus or circuits covered by groups H04L15/00 or H04L17/00 of transmitters, e.g. code-bars, code-discs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M11/00—Coding in connection with keyboards or like devices, i.e. coding of the position of operated keys
    • H03M11/22—Static coding

Definitions

  • control means including an impulse shortening circuit, is operative to terminate and transfer the impulses to be stored into the storer after a period of less than 2 microseconds.
  • This invention is directed to an electronic circuit arrangement for the transmission of impulses, such as telegraph impulses, which are selectable by means of actuating keys or the like, whereby upon actuation of a respective key switch, means are operative to cause the production of one or more impulses having a length of 2 to 3 microseconds, which are to be transferred to an n-place parallel storer.
  • impulses such as telegraph impulses, which are selectable by means of actuating keys or the like, whereby upon actuation of a respective key switch, means are operative to cause the production of one or more impulses having a length of 2 to 3 microseconds, which are to be transferred to an n-place parallel storer.
  • Such impulses preferably are generated by connecting each switch, operated by a respective key in a coder field, over an RC member and cooperable diodes, the number of which corresponds to the number of n-code elements required for the particular teleprinter symbol involved.
  • the condenser of such RC member is so dimensioned that under an impacting closure of the key switch the condenser is so charged by the first closing of the contact that an impulse of a duration of 2 to 3 microseconds is produced.
  • output condition present at such flip state is delayed for a period of less than I or 2 microseconds and then conducted to input gates of the storer, thereby terminating transfer of impulses from the code field to the storer.
  • delay periods amounts to approximately I microsecond.
  • the impulse or impulses appearing in the code field are directed to a collector gate, whereby an impulse present at the output of the gate is shortened by means of an impulse shor- ,tening stage to a duration of less than I to 2 microseconds and the rear flank of such impulse is operative to actuate a flip stage which is operative to block further transfer of impulses from the code field to the storer.
  • FIG. 1 represents a circuit diagram of a circuit arrangement in accordance with the present invention employing static bistable flip stages
  • FIG. 2 is an impulse diagram for the circuit illustrated in FIG. 1;
  • FIG. 3 is a circuit diagram similar to that of Figure I illustrating a modified arrangement employing dynamic flip stages;
  • FIG. 4 is an impulse diagram for the circuit illustrated in FIG. 3;
  • FIG. 5 is a circuit diagram, similar to FIGS. 1 and 3, illustrating a further embodiment of this invention incorporating features of the circuits of both F IGS., and
  • FIG. 6 is an impulse diagram for the circuit illustrated in FIG. 5.
  • each of the RC members is connected over diodes 2 and respective lines to the coder field containing five main lines L1 to L5.
  • Line 11 of FIG. 2 is illustrative of the impulses appearing at the input of a collector gate 3 to which the lines L1 to L5 are connected.
  • the collection impulse appearing at the output of the gate 3 has a fonn substantially as illustrated and a duration of approximately 3 microseconds.
  • Each coder line L1L5 is also connected to respective storage flip stages S1-S5 over corresponding gates Gl-GS which are preceded by respectiveinverters J l-'J5.
  • the outputs of the gates,GlG5 are also connected to the flip stages SIS5 through respective gates G6-Gl0.
  • the output from the collector gate'3 is conducted over an impulse shortening stage 7 and such output of the gate 3 is also connected over a gate 4 to a flip stageS, the output of which is conducted over an impulse delay stage 6 to the other inputs of the respective gates 01-65.
  • the release of such blocking action is effected by an impulselike resetting of the flip stage 5 over the reset line h into its original position and may take place only after the collection impulse has been terminated at c, i.e., after a duration of 3 microseconds, as otherwise the storer would be reset again by the symbol still present at the lines Ll-LS.
  • a new symbol can be immediately placed on lines L1--L5 with a minimum time involved comprising 4 microseconds, which represent the cumulative time of the collection impulse duration plus the reset impulse duration.
  • the impulse shortening time T1 of the impulse shortening stage 7, as illustrated in FIG. 2 for the impulse g (see line g of FIG. 2), must be smaller than T2.
  • the impulses appearing at the five outlets of the storers are conducted to a parallel-series symbol converter or an appropriate, preferably electronic receiver.
  • the circuit disclosed is very efficient, assuring with a very high degree of probability the prevention of the recording of mixed symbols, and at the same time, as demonstrated by experiments, makes possible extremely rapid sequences of key operation.
  • dynamic flip stages such as delay flip-flops may be utilized as illustrated in FIG. 3 with FIG. 4 illustrating the impulse forms associated with this circuit.
  • This construction employs the same circuitry for generation of the actuating impulses as illustrated in lines a and b of FIG. 4, and the lines LlL5 are connected to a collection gate 13, generally corresponding to the gate 3, but produces a negated impulse k (see line k of FIG. 4) as compared with the impulses c of the circuit of FIG. 1.
  • the impulses b in this case are transmitted to preparation inputs of storage flip stages S21-S25 as well as to the collector gate 13.
  • a negative collection impulse k of about 3 microseconds duration will appear at the output of the collector gate 13.
  • Such collection impulse is conducted to an impulse shortening stage 14 which results in a shortening of the impulse to a time of less than 1 microsecond.
  • a circuit comprising a combination of those of FIGS. 1 and 3 may be utilized, such as illustrated in FIG. 5, in which the parallel register $31-$35 receives the spacing impulses over the timing inputs while the marking impulses are fed over the static flip stage inputs.
  • the preparation inputs would permanently lie on high potential.
  • the flip stages employed should be those in which the static inputs dominate the dynamic inputs, i.e., if concurrently over this dynamic input one condition is to be produced and over the static input the opposite condition is to be produced, the flip stage involved will certainty assume the condition required by the static input.
  • Inverters 1115 and gates GIL-G15 correspond to the like inverters of FIG.
  • a circuit arrangement according to claim 1 comprising in further combination gates disposed at the respective signal inputs of said storer, a collector gate to which the code impulses are conducted, a flip stage to which an impulse appearing at the output of said collector gate is conducted, and impulse delay means connecting the output of said flip stage to said storer input gates, operative to delay a blocking impulse thereto for a period up to 2 as.
  • a circuit arrangement comprising in further combination, a collector gate to which the code impulses are conducted, a flip stage, impulse shortening means operatively connecting the output of said collector gate to said flip stage, the output of said flip stage being connected to the storer for initiating the storage operation, said impulse shortening means shortening the received impulse to less. than 2 ,us, with the rear flank thereof being operative to actuate said flip stage.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Input From Keyboards Or The Like (AREA)
  • Manipulation Of Pulses (AREA)
US795669*A 1968-02-02 1969-01-31 Circuit arrangement for pushbutton-controlled electronic parallel delivery of telegraphic impulses Expired - Lifetime US3564139A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH163968A CH486173A (de) 1968-02-02 1968-02-02 Schaltungsanordnung zur tastengesteuerten elektronischen parallelen Abgabe von telegraphischen Impulsen

Publications (1)

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US3564139A true US3564139A (en) 1971-02-16

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US795669*A Expired - Lifetime US3564139A (en) 1968-02-02 1969-01-31 Circuit arrangement for pushbutton-controlled electronic parallel delivery of telegraphic impulses

Country Status (9)

Country Link
US (1) US3564139A (ko)
BE (1) BE727775A (ko)
CH (1) CH486173A (ko)
DE (1) DE1905180B2 (ko)
FR (1) FR1598064A (ko)
GB (1) GB1205203A (ko)
LU (1) LU58582A1 (ko)
NL (1) NL6901132A (ko)
SE (1) SE356865B (ko)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3883867A (en) * 1972-04-04 1975-05-13 Omron Tateisi Electronics Co Information input device
US4150369A (en) * 1976-10-22 1979-04-17 Gaspari Russell A Intrusion alarm system
US4333091A (en) * 1981-04-17 1982-06-01 Zenith Radio Corporation Command buffers for electronic code keyer

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3448213A (en) * 1964-01-20 1969-06-03 Siemens Ag Circuit arrangement for the transmission of telegraph messages over storage communication systems
US3456077A (en) * 1965-09-22 1969-07-15 Navigation Computer Corp High speed electronic keyboard assembly

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3448213A (en) * 1964-01-20 1969-06-03 Siemens Ag Circuit arrangement for the transmission of telegraph messages over storage communication systems
US3456077A (en) * 1965-09-22 1969-07-15 Navigation Computer Corp High speed electronic keyboard assembly

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3883867A (en) * 1972-04-04 1975-05-13 Omron Tateisi Electronics Co Information input device
US4150369A (en) * 1976-10-22 1979-04-17 Gaspari Russell A Intrusion alarm system
US4333091A (en) * 1981-04-17 1982-06-01 Zenith Radio Corporation Command buffers for electronic code keyer

Also Published As

Publication number Publication date
BE727775A (ko) 1969-07-31
DE1905180B2 (de) 1971-10-21
LU58582A1 (ko) 1969-08-22
NL6901132A (ko) 1969-08-05
SE356865B (ko) 1973-06-04
CH486173A (de) 1970-02-15
GB1205203A (en) 1970-09-16
FR1598064A (ko) 1970-06-29
DE1905180A1 (de) 1970-04-16

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