US2769857A

US2769857A - Automatic phasing of synchronous multiplex telegraph systems

Info

Publication number: US2769857A
Application number: US407198A
Authority: US
Inventors: Liguori Anthony
Original assignee: RCA Corp
Current assignee: RCA Corp
Priority date: 1954-02-01
Filing date: 1954-02-01
Publication date: 1956-11-06
Anticipated expiration: 1973-11-06

Description

Patented Nov. 6, 1956 AUTOMATIC PHASING or svNcrmoNoUs MUL- TIPLEX TELEGRAPH sYsrEMs Anthony Liguori, Hackensack, N. l., assignor to Radio Corporation of America, a corporation of Delaware Application February 1, 1954, Serial No. 407,198

Claims. (Cl. 178-50) The invention relates to synchronous multiplex telegraph systems. It particularly pertains to means for phasing the receiving terminal apparatus of a multiplex system automatically with the received signals.

The invention is more specifically directed to radio te-legraph systems in which either a protected or a parity code is used. A protected code comprises a fixed number of signal elements for representin-g each character of vthe intelligence to be transmitted and a fixed ratio of signal elements of one nature to the total number of signal elements in each character of a polystatic code signal. Since the number of elements in each character is xed, the ratio between elements of one nature and the elements of opposite nature in a bistatic code signal is also fixed. One known protected code, given by way of example, is the 7-unit telegraph code in which the ratio of marking to spacing elements is 3 to 4. A parity code is one in which an even number of signal elements of one nature is always present. Usually a parity code is marde up by adding an extra element to all characters of an existing code and the ex-tra element is made to be of the one nature when the number of elements of that nature in the existing code character is odd. One known parity code, given as an example only, is made by adding an extra element to the 5-unit teleprinter code. The invention is further directed to such systems using a protected or a parity code and in which the signal elements of at least one channel are inverted with respect to the signal elements in Athe other channels. This condition exists in nearly all time division telegraph communications systems, because it has been found desirable to change the polarity of currents passing through the electromechanical receiving equipment daily to lessen the deterioration by electrolysis.

Phasing is one of the most exacting requirements encountered in any time division telegraph communications system. The probelm is many-sided. First, there is the requirement of ini-tial phasing on startup; then there is the problem of maintaining phase during operation; and finally, in the event of a slip in phase, there is the desirability of ascertaining this condition quickly and restoring the system to the normal phase relationship.

Systems for automatically synchronizing a locally generated timing wave, upon which the timing of the various functions of the receiving terminal apparatus is based, with the received telegraph signal wave are known. For example, there is the system shown and described in the copending U. S. patent application Serial Number 227,344, filed May 21, 1951, on behalf of Eugene R. Shenk, Arthur E. Canfora and Philip E. Volz, now U. S. Patent 2,716,158, issued August 23, 1955. This system has phase adjusting circuitry interposed between a source of standard reference wave and a timing wave generator to shift the phase relationship between the waves in small increments and thereby synchronize the timing waves with the reecived wave. Such systems are phased by forcing the synchronizing circuitry of the apparatus to shift the phase in response to manual operation of a control element, usually a simple push button switch. The phase of the locally generated wave is shifted in increments large relative to the shift normally produced by the automatic synchronizing circuitry until the proper phase relationship is established as indicated by electrical phase indicating means or observation of clear text on teleprinting apparatus associated with the receiving terminal apparatus.

Phasing by such means requires special operating procedure for establishing the correct phase relationship on startup. This requires that the operating personnel must be specially trained to work with the equipment and because the method is a brute force method, there is apt to be considerable time lost in establishing the proper phase relationship between the transmitting and receiving apparatus. Also, there must be some means for continuously checking the phase relationship. This requirement may be met by having an operator check the message text on the teleprinters to see that it is continuously intelligible. Where the printer apparatus is located at a distance from the receiving terminal apparatus, the requirement is usually met by having an operator continually or periodically observe a phasing indicator device; usually in the form of simple glow lamp indicators. This means must also be used where cryptographic text which is not intelligible to the operators is transmited.- This arrangement usually involves the loss of appreciable time because one operator is responsible for a number of sets of terminal apparatus and slip in phase of any one piece of apparatus is infrequent so that only a few operators are needed most of the time. When such a slip in phase does occur, however, messages are incorrectly received. Such messages, and the time of delivery thereof, of course, are of great importance to the addressee and the loss of considerable circuit time spent in asking for and receiving a repetition of the garbled message is of great importance to the communications company. Furthermore, when there is a slip in phase the transmitting and receiving apparatus are rephased according to the special procedure established for phasing on startup, and no less amount of time is lost in case of a slip in phase than is lost in phasing on startup.

It has been suggested that automatic phasing of tele graph receiving terminal apparatus with the incoming telegraph signal Wave be accomplished in response to synchronizing pulses which are positioned or poled to enable both synchronization and phasing functions to be performed automatically. However, the decided disadvantage of generating, transmitting and receiving special synchronizing pulses outweighs any advantage which might accrue therefrom.

An object of the invention is to automatically phase telegraph receiving signal apparatus on startup with the incoming telegraph signal.

Another object of the invention is to automatically check the phase relationship between the received signal and t-he locally generated timing wave.

A further object of the invention is to provide a circuit arrangement for automatically rephasing telegraph signal apparatus when a slip in phase occurs.

An advantage of the invention is that the arrangement may be readily connected into existing multiplex telegraph terminal apparatus.

The objects of the invention are attained in an electronic circuit arrangement including lcircuitry for automatically phasing the 4locally generated fundamental timing wave with a received polystatic aggregate signal wave received by -apparatus including a phase adjusting circuit to which a standard 4frequency Wave is applied and from which the locally generated fundamental or base timing wave is obtained, vfor producing other timing waves harmonically related thereto and establishing the timed functioning of the overall apparatus. The aggregate signal wave comprises a train of individual signal elements expressing a plurality of intelligence characters wherein each character is formed of a predetermined number of signal elements and there is either a single or a discrete number of prearranged ratios of signal elements of at least one static nature to the total number of signal ele-ments of each character asa whole, and wherein'the ratio of the signal elements of one of the characters is either inverted with respect to the other characters, or entirely different from theV other characters. The apparatus according to the invention comprises yan aggregate signal separating circuit to which the aggregate signal is applied to assign the signal elements of each character into a single respective individual channel. In the case of character -sequential transmission no signal separating circuit is necessary. A signal element counting circuit is coupled to the signal separating circuit, or in the case of character sequential transmission, directly to the source of aggregate signal elements, to count the signal elements of one nature of the character assigned to the counting circuit under considera'tion. The counting circuit delivers an output indicating the number of signal elements counted. An `offcount circuit or anti-coincidence circuit is coupled tc the counting circuit. This off-count or anti-coincidence circuit acts as a normal-ly open gate. A source of pulses of the proper recurrence frequency for adjusting the phase of the locally generated wave is applied to the off-count or anti-coincidence circuit. The output of the :off-count or anti-coincidence circuit is connected to the phase adjusting circuitry of the receiving terminal apparatus. When the proper count or coincidence is established in the olf-count circuit, the phase ladju-sting circuitry is unaffected. But, if the off-count circuit or anti-coincidence circuit indica-tes that an improper count, whether less or greater than the proper count, has been determined, a correction pulse is passed to the phase adjusting circuitry and the phase is advanced or retarded, preferably the Iformer, lby a predetermined amount. In practice, this predetermined amount will be equal to the amount required to step the phase by one aggregate element spacing. A single error in one code character combination will result in the stepping of the phase of the local generator timing wave; that is, one mutilated character would then tend to operate the phasing circuit. Of course, the phasing circuitl would thereupon reestablish the proper phase 1n the normal manner, but several characters would be lost 1n doing this, especially since the phase adjustment 1s usually made in the same direction, that is, either always advancing or always retarding. To overcome this situation there is preferably interposed in the circuit between the oit-count circuit and the phase adjusting circuitry a counting circuit which prevents the yapplication of correctionpulses untila prearrangedrcount over a predetermined interval of time has been established. In pracltice, it appears practical to use a single count so that only asirnple counting circuit, such as afforded by a single monostable or bistalble reciproconductive stage, is necessary. Resetting means must be applied to this pulse counting circuit to reset the circuit after Ia predetermined time interval. This may ybe accomplished easily by applying a positive or negative pulse, which can be :obtained from the timing wave generator, at the proper frequency rate for example, twice the sampling rate, by means of a differentiating circuit to the pulse counting circuit to erase the count. Similar reset means are provided in the other counting circuits so that the circuits are reset at the end of each character interval. Again, simple differentiated pulse waves obtained from the timing wave generator can be applied to operate these reset means.

Various types of signal aggregation can be handled by the circuit arrangement according to the invention. All that is necessary is to separate the incoming `aggregate signal elements into the corresponding characters and -assign them to the counting circuit to determine the proper count. For character sequential transmission it is only necessary to change the counting ratio of the counting circuit each time an inverted character is expected. This is accomplished by means of a known reset circuitry triggered by a pulse wave derived from the local timing generator. In the case of interleaved diplex operation two counting chains are established and the signal separating circuit is made to sample the incoming telegraph signal at :the signal element rate and assign the individual signal elements to the proper counting chain. At the end of the character interval the counting chain circuits are reset .to count the inverted characters at the proper time in response to a pulse derived from the timing wave generator. Thus the counting chains have preset counting factors set into them at the proper time for the character expected. If the character received has fewer or more pulses of given signal nature than expected, an off-count signal will be produced. The phase of the timing wave is then adjusted by gating correction pulses in response to the off-count signal in `accordance with the type of appara-tus and system olf operation thereof.

In order that the invention may be more clearly understood and readily put to practical use, circuit arrangements embodying the invention are hereinafter described, by way of example only, with reference to the accompanying drawing in which:

Y Fig. 1 is `a functional diagram of a circuit arrangement according to the invention; and

Fig. 2 is a graphical representation of the time relationships between the pulses developed in the circuit arrangement according to the invention and the incoming diplexv` signal.

The circuit arrangement of the invention is not limited to any one particular code or system of telegraph transmission, as will be evidenced by the various suggestions to be made hereinafter referring to several different types of telegraph signaling. In the interests of clarity and conciseness, however, the invention will be described rst in connection with the specific application of the invention to the electronic diplex receiving terminal distributor as illustrated and described in the copending U. S. patent application, Serial Number 312,346, filed September 30, 1952, on behalf of Anthony Liguori and Eugene R. Shenk, now U. S. Patent 2,734,943, issued February 14, 1956, and the seven unit protected code in which each character consists of three marking and four spacing signal elements. In conventional time division multiplex practice there are normally four channels; two channels are upright, that is, three marking and four spacing elements to determine each character, and two channels are inverted, that is, as though four marking and three spacing elements were transmitted to determine each character. Actually, at the receiving terminal the signal is reinverted before translation to the printer apparatus so that the detector elements and Subsequent utilization devices are `exactly the same for all channels of communication. The basic principle of the invention, however, involves counting the mark elements of each channel of communication before the reinversion process takes place. The circuit arrangement is so constituted that if these different counts occur at the proper times no action is caused to take place, but if for some reason a count is made which is not the count expected at the particular time, the phase of the locally generated fundamental timing wave is adjusted. Actually, two things can happen to result in an improper count: (a) improper phase relationship; (b) a mutilated character. These two causes are readily distinguished on a recurrence basis. In other words, if the mutilation appears repeatedly, it is assumed that the circuit arrangement is out of phase. However, if the mutilation occurs infrequently, it is assumed that the receiving terminal apparatus is in phase and the effect of the mutilation is disregarded insofar as the phasing system is concerned.

Referring to Fig. 1, there is shown a functional diagram of an arrangement according to the invention as applied to the electronic diplex receiving distributor of the type illustrated and described in the above-mentioned copending U. S. patent application, Serial Number 312,346, of Anthony Liguori and Eugene Richard Shenk, now U. S. Patent 2,734,943. Only those components of the diplex receiving distributor essential to the explanation of the invention are shown in Fig. 1. In '.brief, an aggregate signal regenerator 11, which itself :forms no part of the invention, to which the aggregate :signal wave received is applied at input terminals 12, de- ?livers a four-channel signal to an elementizer 13. The individual signal elements are presented over separate cir- -cuits at the output terminals 14A- 14D of the elemen- :tizer 13. The elementizer 13, which in itself forms no part of the invention, is operated in the proper time relationship in response to applied harmonically related timing waves obtained from a timing Wave generator or icommutator 15. The properly timed harmonically related :square waves are produced by the generator 15 in rersponse to the application of a fundamental locally generated base timing wave obtained from the output of a phase adjusting circuit 17 to the input of which a wave of standard reference frequency is applied from the source 19. Source 19 may, for example, generate a wave of 600 cycles/ second as shown and described in U. S. Patent 2,451,245, issued October 12, 1948, to Eugene Richard Shenk and Alfred Kahn, followed by known overdriven amplifier and clipper circuitry to produce square waves and preferably also followed by known frequency dividing circuitry.

An electronic telegraph receiving terminal distributor as thus far described requires some means of automatically synchronizing the locally generated timing wave with the incoming aggregate signal wave. Such synchronizing circuits as shown in U. S. Patent 2,309,622, issued February 2, 1943, to Warren A. Anderson may be adapted for this purpose, but a better system is found in the copending U. S. patent application, Ser. No. 227,344, tiled May 21, 1951, on behalf of Arthur Eugene Canfora, Eugene Richard Shenk and Philip Eckert Volz, now U. S. Patent 2,716,158, issued August 23, -1955. In this system, the incoming signal, as from the signal regenerator 11, is compared with the locally generated base timing wave, as obtained from the timing wave generator 15, in a phase detector circuit. Space-to-mark transitions in the aggregate signal cause a negative transition in the voltage at the anode of a signal repeating or amplifying tube. These transitions are dilferentiated in the grid circuit of a transition inverting tube and block this tube forming positive start-of-mark pulses at the anode. The start-ofmark transition pulses are applied to the respective grids of a pair of phase detector tubes to which opposite phases of a locally generated signal element rate timing wave are individually applied. The phase detector tubes are biased suiciently to block the tubes regardless of the polarity of the local signal element rate timing wave applied to the respective grids. The anode of the transition inverting tube is connected to the grids of both phase detector tubes in push-push fashion. When a start-of-mark pulse occurs, part or all of the pulse wil be coincident with the positive half-cycle of square wave local signal element rate timing wave applied to one of the phase detector tubes. When this pulse occurs coincident with the positive half-cycle of the timing wave, the pulse voltage plus the square wave voltage are sufficient to overcome the bias on the tube and the tube will conduct as long as the above coincidence lasts. If the start-of-mark pulsesare entirely coincident with the positive half-cycles at `the grid of one of the phase detector tubes, the local phase is retarded with respect to the desired relationship. if the start-of-mark pulses are entirely coincident with the positive half-cycles at the grid of the other phase detector tube, the local phase is advanced with respect to the desired relationship. The information that local phase is retarded or advanced is, therefore, contained in the form of anode current pulses in the phase detector tubes. The information thus obtained from each of the phase detector tubes is integrated across an integrating capacitor. The pulses of anode current charge these capacitors negatively and when a predetermined negative voltage is reached, a correction of the local phase is initiated by triggering a single-shot multivibrator or monostable reciproconductive circuit. The term reciproconductive circuit as employed herein is construed to include all two tube regenerative circuit arrangements in which conduction alternates in one or the other tube. The monostable reciproconductive circuit which requires one trig. gering pulse to switch from the single stable state of conduction to the single unstable reciprocal state and return is occasionally referred to as a monostable multivibrator and often referred to as a trigger circuit though not consistently distinguishing from the bistable multivibrator. The bistable reciproconductiveV circuit, which is one requiring two triggering pulses to switch from one stable state to the other stable state and return, sometimes termed a locking circuit, comprises two types of circuit. One type, the lockover reciproconductive circuit, has two trigger input terminals and requires triggering at alternate terminals to reverse the state of conduction, whereas the other type, the binary reciproconductive circuit has a single terminal and the conductivity is reversed upon each application of vtriggering potential to the one terminal. The monostable reciproconductive circuit is then in the unstable condition of conduction after which the circuit willbe restored to the normal condition upon the elapse of a prearranged time period depending on the circuit constants. The phase correcting circuits will remain in the normal condition until the associated integrating capacitor is again charged suciently negative by the phase detector circuit to repeat the above cycle.

When the first reciproconductive circuit is triggered, it is desired to cause the locally-generated timing wave to advance in phase, since the information on the associated integrating capacitor is that the timing wave is retarded in phase from the desired position. The triggering of the correction circuit occurs synchronously with the timing wave in response to the application of synchronizing voltage injected into the reciproconductive circuit which is arranged to trigger only under control of the information represented by the charge on the integrating capacitor, inasmuch as this voltage must reach a predetermined negative value before the circuit may be triggered. The amplitude of the positive synchronizing pulses applied to the grid of a triggering tube is larger than the increment of voltage which can appear across the integrating capacitor, in response to start-of-mark pulses, so that the actual triggering of the reciproconductive circuit is initiatcd by the synchronizing pulse after the integrating capacitor has charged suiciently negative. The Vtriggering tube accomplishes the correction by delivering a negative transition formed at the anode of the triggering tube through a coupling capacitor to one of a pair of phase adjuster tubes forming a binary reciproconductive circuit interposed between a source of standard frequency lwave v19 and the timing wave generator 15. Due to the 'phase of the synchronizing pulse applied to theadvance reciproconductive circuit, this one tube is blocked at the time the triggering tube becomes conducting. Normally, this one tube would not have become conducting until the next input pulse from the source of standard requency wave. The phase adjusting reciproconductive circuit has, therefore, ben caused to gain one half-cycle over its normal output frequency. Only the leading edge of the output pulse actually causes the advance correction to take place and, therefore, the active time of the advance reciproconductive circuit is to discharge the integrating capacitor, that is, destroy the accumulated information which caused the previous correction to take place. Therefore, the active time of the reciproconductive circuit is governed by the discharge of the associated integrating capacitor. The advance reciproconductive circuit, therefore, accomplishes two operations: it causes an advance correction to occur and it discharges the associated integrating capacitor.

A retard reciproconductive circuit which operates in a manner very similar to that described for advancing phase is used to retard the phase in response to information appearing on the corresponding integrating capacitor from the phase detector circuit. Due to the phase of the synchronizing pulse applied to the retard reciproconductive circuit, the one tube in the phase adjusting circuit is also blocked at the time the retarding function is initiated. A positive pulse from the retard reciproconductive circuit is used to cause a blanking tube to conduct. The blanking tube is normally blocked due to the applied bias. The grid of the one phase adjusting tube is held below cut-off by the conduction of the blanking tube for a length of time such that the succeeding pulse from the reference wave source has no effect on the phase adjusting circuit. Normally the one tube of 'this circuit would have become conducting on the succeeding pulse from the reference wave source. Therefore, the phase adjusting circuit has been caused to lose one-half cycle of its output frequency. The time during which the blanking tube is held conducting by the retard circuit must be greater than one-half cycle and less than a whole cycle at the operating frequency. Only the leading edge of the retard pulse is used to cause the correction to take place. lAs in the previous case, the active time of the multivibrator is governed by the discharge of the integrating capacitor. Therefore, the retard reciproconductive circuit causes the retard correction to take place, and also discharges the associated integrating capacitor.

The synchronizing circuit thus insures sampling at the center of each signal element. Such a system hunts slightly but the maximum misalignment is a small fraction of an aggregate signal element. This circuit means, as applied to the arrangement shown, would comprise a phase detector element connected between the output of the aggregate signal generator 11, an output of the timing wave generator 15 and a phase adjusting circuit element similar or identical to the phase adjusting circuit 17. In the circuit arrangement shown, the phase adjusting circuit element of the synchronizing means would be interposed in the reference wave source-timing wave generator connection preceding the phase adjusting circuit 17 to adjust the phase in either direction in steps small relative to the adjustment provided in the circuit according to the invention.

The output of the aggregate signal regenerator i1 is applied to a signal separating or signal repeating circuit 21 along with one phase of the locally generated timing wave obtained conveniently from the phase adjusting circuit 17. The signal separating or repeating circuit 21 is arranged to repeat a character-sequential signal or to select only the signal elements belonging to a desired signal character under consideration for presentation to a counting circuit 23. The counting circuit 23 is arranged to count the number of signal elements of given nature in the character under consideration and produce an output indicative of the count. For example, the counting circuit 23 may be arranged to count three mark elements to produce a given proper count potential, to provide a lower potential on a lower count and to p'rovide a higher potential on a higher count. Examples of such counting circuits are to be found in U. S. Patent 2,592,493, issued April 8, 1952, to Bertram A. Trevor and U. S. Pa cnt 2,648,767, issued August 11, 1953, to William D. Houghton. The output of the counting circuit 23 is applied to an olf-count circuit 25 along with a correction pulse, usually termed the local pulse, conveniently obtained from the timing wave generator or commutator 15. The off-count circuit 25 is arranged to block the application of any corrective pulse if the counting circuit 23 has counted the proper number of marit elements. If the counting circuit 23 has counted any other number of marking elements, say two, the local pulse is passed to the phase adjusting circuit 17, by way of a pulse gating or translating circuit 27.

At the same time the aggregate signal output of the aggregate signal regenerator 11 is applied to another signal separating or repeating circuit preferably in the form of a coincidence gating circuit 31 to which the 0pposite phase of the locally generated timing wave is applied as obtained from the phase adjusting circuit 17. The coincidence gating circuit 31, examples of which are found in the copending U. S. patent application, Ser. No. 211,272, tiled February 16, 1951, on behalf of Eugene Richard Shenk, Arthur Eugene Canfora and Anthony Liguori, now Patent No. 2,671,132 dated March 2, 1954, as well as in Patent No. 2,682,574, dated June 29, 1954, to A. E. Canfora and A. Liguori and the above-mentioned co-pending application, Serial No. 312,346, tiled September 30, 1952, now U. S. Patent 2,734,943, issued February 14, 1956, performs the same function as the signal separating or repeating circuit 21 but this type of circuit is considered preferable for reasons which will be more clearly stated hereinafter. This coincidence gating circuit 31 also is made to operate at a time intermediate to the sampling times of the signal separating or repeating circuit 21 due to the opposite phases of the timing waves obtained from the phase adjusting circuit 17. In this manner, the signal elements selected from the aggregate signal corresponding to channels A and B are applied to the counting circuit 23 and the signal elements of channels C and D are available at the output of the coincidence gating circuit 31 for application to another counting circuit preferably in thev form of a binary counting chain 33. This binary counting chain is the preferred form of counting circuit corresponding to the counting circuit 23. The binary counting chain, examples of which are found in U. S. Patent 2,636,984, issued April 23, 1953, to Arthur Eugene Canfora and in U. S. Patent 2,621,250, issued December 9, 1952, to James Albert Spencer and Edwin Raymond Liberg and in the copending U. S. Patent application, Serial No. 227,305, filed May 21, 1951, on behalf of Philip Eckert Vol2, now U. S. Patent 2,706,785, issued April 19, 1955, as well as in the above-mentioned copending applications, has the distinct advantage that a plurality of harmonically related waves in proper phase relationship can be used to actuate another off-count circuit preferably in the form of an anti-coincidence circuit 35 in a very positive manner because for any counting condition desired a negative pulse may be obtained and for any count other than that predetermined count only positive pulses are obtained. Likewise, the anti-coincidence circuit 35 performs exactly the same function as the off-count circuit 25 but is the preferred form since this positive control is so easily obtained without the addition of complex circuitry. Local pulses are applied through the anticoincidence circuit 35 and the pulse gating or translating circuit 27 to the phase adjusting circuit 17 if the binary area-sse counting chain 33 counts the number of pulses other than that expected for the signal element under consideration. For example, in the diplex operation the counting circuit 23 is arranged to count three pulses to provide a proper count and render the off-count circuit 25 ineffective to pass a local pulse, while the binary chain 33 is arranged to count four pulses to render the anti-coincidence circuit 35 ineffective to pass local pulses. Circuitry for resetting the counting chain 33 is shown and described in the above mentioned U. S. Patent 2,621,250, of James Albert Spencer and Edwin Raymond Liberg and in the copending U. S. Patent application Ser. No. 266,386, iiled on January 4, 1952, on behalf of Anthony Liguori, now Patent No. 2,685,613, dated August 3, 1954.

In 4-channel diplex operation the four groups A, C, B, D of seven signal elements have the ratios 3:4, 4:3, 4:3, 3:4, and so on. As thus far described the circuit arrangement shown in Fig. 1 applies the signal elements from alternate channels to the counting circuit 23 and the signal elements from the intervening channels to the binary counting chain 33. The counting circuit 23 must then be able to count three marks followed by four marks followed by three marks, and so on, While at the same time the binary counting chain 33 must be able to count four marks, then three marks, then four marks, and so on. In order to accommodate this change of count, reset

circuits

29 and 39 which are actuated by the local pulse are provided. These

reset circuits

29 and 39, examples of which are to be found in the above mentioned U. S. Patent 2,63 6,984, of Arthur Eugene Canfora and in the copending U. S. Patent application Ser. No. 350,566, tiled April 23, 1953, on behalf of James Stalling Harris and Chester William Latimer and Ser. No. 353,556, led May 7, 1953, on behalf of James Curtis Phelps and Eugene Richard Shenk, now U. S. Patent 2,712,037, issued June 28, 1955, as well as in the abovementioned copending applications, change the counting factor of the counting circuit 23 or the binary counting chain 33 as required to count either three or four marks in the examples mentioned. It is desirable to be able to invert the polarity or nature of the signal elements as viewed from the counting circuit 23 or the binary counting chain 33 so that other aggregations may be used. In order to do this, reset inverting circuits 49A-49D are provided. Examples of such polarity reversing circuits are found in the copending U. S. Patent applications 279,432, filed March 29, 1952, on behalf of Arthur Eugene Canfora and Anthony Liguori, now Patent No. 2,682,574, dated June 29, 1954, and the above mentioned application Ser. No. 312,346 of Anthony Liguori and Eugene Richard Shenk, now U. S. Patent 2,734,943. One such use for these inverting circuits is in the application of subdividing othe communication channel. In such an application the first channel is inverted and all of the other channels are upright, as against alternate channels being upright and intermediate channels being inverted as in the example for diplex transmission.

'Ihe particular circuit utilized for signal separating circuits 21 and 31, counting

circuits

23 and 33, and off-

count circuits

25 and 35 may be of any suitable type. However, as pointed out above, in a preferred form of the invention a coincidence gating circuit is to be used for signal separating circuit 31, a binary counting chain is to be used for counter 33 and an anti-coincidence circuit is to be used for off-count circuit 35. It is to be understood that in practical embodiments the same circuit may be used for signal separating circuits 21 and 31; counting

circuits

23 and 33 may be the same; and olf-

count circuits

25 and 35 maybe the same.

In applications involving the use of a parity code the signal separating circuits 21, 31 are chosen to handle the particular type of aggregation involved just as described before. The counting

circuits

23, 33, however, can be a simple bistable reciproconductive circuit since all that need be determined is whether the count 1s odd or i0 even. The inverted count will then be odd and the switch-over made by injecting a single reset pulse. The olf-

count circuits

25, 35 then become a simple connection, even a wire connection is possible, between the evencount tube of the single stage reciproconductive circuit and the pulse translating or gating circuit 27 and/ or the phase adjusting circuit 17.

The correction pulse gating or translating circuit 27 may be any type of pulse translating circuit, in fact it may be a wire connection if desired. Because single mutilation can also make the circuit appear to be out of phase, the circuit 27 is preferably a counter, such as a bistable re-` ciproconductive circuit, so arranged that no single correction pulse occurring in a given time period will be passed to the phase adjusting circuit 17, but if a predetermined number of correction pulses occur within the given time `the correction will be made. The -time period is determined by the reset circuit 43 which may be in itself in the form of a counter. For example, the correction or translating circuit gating pulse 27 may be a bistable lockover reciproconductive circuit which is coupled to another bistable reciproconductive circuit forming the reset circuit 43. Timing waves into the reset circuit 43 will cause an output therefrom at every other character interval. This output from the reset circuit 43 will trigger the bistable lockover reciproconductive circuit forming the counting gate 27 to prevent operation until a second pulse is obtained within the time determined by the timing wave applied to the reset and counting circuit 43. Obviously, circuits for counting more than one or two pulses may be interposed if desired for such circuits are well known in the art.

The circuit arrangement of Fig. 1 may be modified slightly to eliminate the need for resetting the counting circuit 23 and the binary counting chain 33 to count a diiferent number of mark elements on alternate characters. This is done simply by passing the leads forthe two opposite phases of the timing wave as obtained from the phase adjusting circuit 17 through a phase reversing circuit, which in practice may be readily formed by a bistable reciproconductive circuit of the type shown and described in the above mentioned copending U. S. patent application Ser. No. 279,432, of Arthur E. Canfora and Anthony Liguori, now Patent No. 2,682,574, dated June 29, 1954. Shifting the phases of the timing wave which control the sampling points of the signal separating or repeating circuit 21 and the coincidence gating circuit 31 will cause different signal characters to be presented to the counting circuit 23 and the coincidence gating circuit 31 so that reset of the counting factor need not be made. This modication will prove -to be more practical in some instances than others. The circumstances under which the circuit arrangement is to operate will determine the type of circuit to be used for signal separation or selection.

A timing diagram showing the phase relationship of the signal elements and the various operating pulses necessary for operation of a diplexed signal basis is shown in Fig. 2. Curve 81 represents the incoming signal element timing. Curves 83 and 85 represent the pulses applied to the signal separating circuits 21 and 31 to select the signal elements for application to the

counting circuits

23 and 33. Curve 87 shows the pulses which are applied simultaneously to the olf-

count circuits

25 and 35 to shift the phase if the correct number of marks is not received.

The invention claimed is:

1. An electronic circuit arrangement for automatically phasing a received polystatic aggregate signal wave, comprising individual signal elements expressing a plurality of intelligence characters wherein each character is constituted by a predetermined number of signal elements and there is a prearranged ratio of signal elements of at least one static nature to the number of signal elements of the character as a whole and wherein said ratio of at least one of said characters is different than said ratio of the other characters, with a fundamental timing Wave locally generated in a system of the type including a phase adjusting circuit to which a standard frequency wave is applied and from which said locally generated wave is obtained, including a signal repeating circuit to which said aggregate signal is applied to assign the signal elementsfof each character into an individual channel, a counting circuit coupled to said repeating circuit to count the signal elements of one static nature of the character assigned to the counting circuit under consideration and to' produce anv output indicating the count, an off-count circuit coupled to said counting circuit, means to apply a phase correcting pulse wave harmonically related to said locally generated fundamental timing wave to said ofi-count circuit, said off-count circuit being arranged to block the phase. correcting pulses of said pulse wave in response to output from said counting circuit indicating a correct number of signal elements of said one static nature, a pulse translating circuit coupled between said olf-count circuit and said phase adjusting circuit to pass said phase correcting pulses, thereby to Vary the phase of the locally generated timing wave with respect to the standard frequency wave and into a predetermined phase relationship with said received wave.

2. An electronic circuit arrangement as defined in claim l and incorporating means to reset said counting circuit responsive to a pulse wave harmonically related to said Ilocally generated fundamental timing wave, and similar means to reset said pulse translating circuit.

3. An electronic circuit arrangement as defined in claim Zand incorporating means coupled to the first said reset means selectively to vary the count of said counting circuit at which the associated off-count circuit blocks the phase correcting pulses to said phase adjusting circuit.

4. An electronic circuit arrangement for automatically phasing a received bistatic aggregate signal wave, comprising individual signal elements expressing a plurality of intelligence characters wherein each character is formed of a predetermined number of signal elements and there is a prearranged ratio of signal elements of at least one nature to the number of signal elements of opposite nature and wherein said ratio of the signal elements of at least one of said characters is inverted with respect to that of the other characters, with a fundamental timing wave locally generated in a system of the type including 'y a phase adjusting circuit to which a standard frequency wave is applied and from which said locally generated fundamental timing wave is obtained, including a signal repeating circuit to which said aggregate signal is applied to assign the signal elements of each 'character into an individual channel, a counting circuit coupled to said signal repeating circuit to count the signal elements of one nature of the character assigned to the counting circuit under consideration and to produce an output indicating the count, an off-count circuit coupled to said counting circuit, means to apply a phase correcting puise wave harmonically related to said locally generated fundamental timing wave to said off-count circuit, said offcount circuit being arranged to block the phase correcting pulses of said wave in response to output from said counting circuit indicating a correct number of signal elements of said one nature, a pulse translating circuit coupled between said of-count circuit and said phase adjusting circuit to pass said pulses, thereby to vary the phase of the locally generated timing wave with respect to the standard frequency wave and into a predetermined phase relationship with said received wave, and means to reset said counting circuit responsive to a pulse wave harmonically related to said locally generated timing wave.

5. An electronic circuit arrangement as defined in claim 4 and wherein said reset means incorporates circuitry arranged selectively to vary the count of said counting circuit at which the associated oli-count circuit blocks the pulses to said pulse translating circuit. 1

6. An electronic circuit arrangement for automatically phasing a received mark-space aggregate telegraph signal wave, comprising individual signal elements expressing a plurality of intelligence characters wherein each character is formed of a predetermined number of signal elements and therel is a prearranged ratio of marking to spacing signal elements and wherein said ratio of at least one of said characters is different from that of at least one other character, with a base timing wave locally generated in a system of the type including a phase adjusting circuit to which a standard frequency wave is applied and from which said locally generated base timing wave is obtained, including a signal repeating circuit to which said aggregate signal is applied to assign the signal elements of each character into a single channel, a counting circuit coupled to said repeating circuit to count the signal elements of one nature of the character assigned to the counting circuit under consideration and to produce an output indicating the count, an Off-count circuit coupled to said counting circuit, means to apply a phase correcting pulse wave harmonically related to said locally generated base timing wave to said ofi-count circuit, said off-count circuit being arranged to block the phase correcting pulses of said wave in response to output from said counting circuit indicating a correct number of signal elements of said one nature, a pulse translating circuit coupled between said off-count circuit and said phase adjusting circuit to pass said pulses, thereby to vary the phase of the locally generated base timing wave with respect to the standard frequency wave and into a predetermined phase relationship with said received wave.

7. An electronic circuit arrangement as defined in claim 6 and wherein said pulse translating circuit is constituted by a pulse counter arranged to pass said phase correcting pulses to said phase adjusting circuit only upon a predetermined number of pulses occurring during a given time interval.

8. An electronic circuit arrangement as defined in claim 7 and including means operative in response to said locally generated timing wave to reset said pulse counter.

9. An electronic circuit arrangement as defined in claim 6 wherein said signal repeating circuit is a signal separating circuit and including a further counting circuit, a further ofi-count circuit coupled to said further counting circuit and to said pulse translating circuit, and a further signal separating circuit to which said aggregate signal is applied to assign the elements of another character to said further counting circuit.

10. An electronic circuit arrangement as defined in claim 9 and wherein the first said counting circuit is arranged to count a predetermined number of signal elements of one nature and said further counting circuit is arranged to count a different number.

1l. An electronic circuit arrangement as defined in claim 10 and including reset means individual to said counting circuits selectively to alternate the counts of said counting circuits.

l2. An electronic circuit Yarrangement as defined in claim ll and wherein said counting circuit is constituted by a binary counting chain and said off-count circuit is constituted by an anti-coincidence circuit.

13. An electronic circuit arrangement as defined in claim l2 and wherein said anti-coincidence circuit is closed'by negative coincidence of a plurality of pulses obtained from said binary counting chain as established in the condition of conduction corresponding to the correct count.V

14. An electronic circuit arrangement as defined in claim l2 and wherein said signal repeating circuit is constituted by .a coincidence gating circuit. Y

l5. An electronic circuit arrangement as defined in claim i4 and wherein said coincidence'gating circuit is opened in response to positive coincidence of timing waves obtained from a timing wave generator coupledto the output of said phase adjusting circuit.

16. An electronic circuit arrangement as defined in claim 10 and wherein the signal'separating circuits are actuated in the proper time sequence by timing waves of opposite phase relationship and related to said base timing wave.

17 An electronic circuit arrangement as defined in claim 16 and including means to switch said timing waves to apply each wave alternately to each of said signal separating circuits.

18. An electronic circuit arrangement as defined in claim 16 and wherein said timing waves are obtained from said phase adjusting circuit.

19. An electronic circuit arrangement as dened in claim 11 and wherein said reset means includes further means to invert the counting ratio of each counting circuit.

20. An electronic circuit arrangement for automatically phasing a received polystatic aggregate signal wave, comprising individual signal elements expressing a plurality of intelligence characters wherein each character is constituted by an odd number of signal elements and wherein an even number of said signal elements are of one static nature, and the elements of at least one of the plurality of characters is inverted with respect to those of the other characters, with a base timing wave locally generated in a system of the type including a phase adjusting circuit to which a standard frequency wave is applied and from which said locally generated base frequency wave is obtained, including a coincidence signal gating circuit to which said aggregate signal is applied to assign the signal elements of each character to a single channel, a binary counting stage coupled to said coincidence gating circuit to produce one output indicative of evenness and another output indicative of oddness, a correction pulse gating circuit connected to said output and to said phase adjusting circuit, means to apply a phase correcting pulse wave harmonically related to said base timing wave to said pulse gating circuit, said pulse gating circuit being arranged to pass said correction pulses to said phase adjusting circuit in response to an odd count of the elements of said one nature and an even count of the elements of nature opposite to said one nature for each character under consideration.

References Cited in the le of this patent UNITED STATES PATENTS