US3564139A - Circuit arrangement for pushbutton-controlled electronic parallel delivery of telegraphic impulses - Google Patents

Abstract

A circuit arrangement for the parallel transmission of keyselectable telegraph impulses in which, in response to the actuation of a key, at least one impulse having a duration greater than 2 microseconds is produced and supplied to a parallel storer having at least as many storage places as the possible number of impulses in the telegraph code field, in which control means, including an impulse shortening circuit, is operative to terminate and transfer the impulses to be stored into the storer after a period of less than 2 microseconds.

Description

United States Patent inventors Camillo Bodenstein;

Herbert Strassner, Muenchen, Germany Appl. No. 795,669 Filed Jan. 31, 1969 Patented Feb. 16, 1971 Assignee Siemens Aktiengesellschalt Berlin, Germany Priority Feb. 2, 1968 Switzerland 1,639/68 CIRCUIT ARRANGEMENT FOR PUSHBUTTON- CONTROLLED ELECTRONIC PARALLEL DELIVERY OF TELEGRAPI-IIC IMPULSES 5 Claims, 6 Drawing Figs.

US. Cl 178/ 17.5, 178/17; 340/345 Int. Cl H041 13/08, H041 15/04 Field of Search 178/1 7.5,

[56] References Cited UNITED STATES PATENTS 3,448,213 6/1969 Graf [78/175 3,456,077 7/1969 Jones, Jr 178/17 Primary Examiner- Kathleen H. Claffy Assistant ExaminerCharles W. Jirauch Attorney-Hill, Sherman, Meroni, Gross and Simpson ABSTRACT: A circuit arrangement for the parallel transmission of key-selectable telegraph impulses in which, in response to the actuation of a key, at least one impulse having a duration greater than 2 microseconds is produced and supplied to.

a parallel storer having at least as many storage places as the possible number of impulses in the telegraph code field, in which control means, including an impulse shortening circuit, is operative to terminate and transfer the impulses to be stored into the storer after a period of less than 2 microseconds.

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- mum/70M Cam/l/o Horde/Islam Herbal! S/rassnor CIRCUIT ARRANGEMENT FOR PUSI-IBUTTON- CONTROLLED ELECTRONIC PARALLEL DELIVERY OF TELEGRAPI-IIC IMPULSES BACKGROUND OF THE INVENTION This invention is directed to an electronic circuit arrangement for the transmission of impulses, such as telegraph impulses, which are selectable by means of actuating keys or the like, whereby upon actuation of a respective key switch, means are operative to cause the production of one or more impulses having a length of 2 to 3 microseconds, which are to be transferred to an n-place parallel storer. Such impulses preferably are generated by connecting each switch, operated by a respective key in a coder field, over an RC member and cooperable diodes, the number of which corresponds to the number of n-code elements required for the particular teleprinter symbol involved. The condenser of such RC member is so dimensioned that under an impacting closure of the key switch the condenser is so charged by the first closing of the contact that an impulse of a duration of 2 to 3 microseconds is produced.

Problems arise in the operation of general circuits of the type in connection with the possible formation of so-called mixed symbols, i.e., erroneous impulse combinations caused bythe operation of two operating keys in rapid succession, and the invention is particularly directed to a circuit arrangement in which thepossibility of such double key operation is substantially eliminated.

SUMMARY OF THE INVENTION .deliberate very rapid consecutive operation of two keys is possible without the introduction of any errors in the transmission.

In accordance with one embodiment of the invention these results are accomplished in connection with a collector gate, to which the impulse or impulses appearing in the code field are directed, with the output of such gate being supplied to a flip stage which functions as a transfer blocking device. The

output condition present at such flip state is delayed for a period of less than I or 2 microseconds and then conducted to input gates of the storer, thereby terminating transfer of impulses from the code field to the storer. Preferably. such delay periods amounts to approximately I microsecond.

In accordance with another embodiment of the invention,

the impulse or impulses appearing in the code field are directed to a collector gate, whereby an impulse present at the output of the gate is shortened by means of an impulse shor- ,tening stage to a duration of less than I to 2 microseconds and the rear flank of such impulse is operative to actuate a flip stage which is operative to block further transfer of impulses from the code field to the storer.

In accordance with a further embodiment of the invention, features of both of the previous embodiments are utilized to provide an arrangement particularly suitable in the event contact impacts are to be expected within the first few microseconds following key depression.

BRIEF DESCRIPTION OF THE DRAWINGS In the drawings wherein like reference characters indicate like or corresponding parts:

FIG. 1 represents a circuit diagram of a circuit arrangement in accordance with the present invention employing static bistable flip stages;

FIG. 2 is an impulse diagram for the circuit illustrated in FIG. 1;

FIG. 3 is a circuit diagram similar to that of Figure I illustrating a modified arrangement employing dynamic flip stages; FIG. 4 is an impulse diagram for the circuit illustrated in FIG. 3;

' FIG. 5 is a circuit diagram, similar to FIGS. 1 and 3, illustrating a further embodiment of this invention incorporating features of the circuits of both F IGS., and

FIG. 6 is an impulse diagram for the circuit illustrated in FIG. 5.

DESCRIPTION OF'THE PREFERRED EMBODIMENTS This invention is particularly applicable to keyboard switching mechanisms such as those employed in electronic teletypewriters and similar equipment in which the respective keys are arranged in a key field Tf in which respective key actuated contacts 1, assigned to the individual symbols or the like, are closed by the operation ofthe respective keys associated therewith. Based on practical experience, such contacts are always considered as impact contacts, but it is assumed that no impacts occur during the first 2 microseconds. Line a of FIG. 2 thus may be considered as being representative of an impulse. sequence appearing immediately following the contacts 1 when actuated by the associated key, only three of the possible 32 key controlled. current paths being illustrated. In order to generate a clear brief impulse, an RC member follows each of the contacts 1. With the exception of the impulse combination 5 X0, each of the RC membersis connected over diodes 2 and respective lines to the coder field containing five main lines L1 to L5. Line 11 of FIG. 2 is illustrative of the impulses appearing at the input of a collector gate 3 to which the lines L1 to L5 are connected. As illustrated in line c of FIG. 2, the collection impulse appearing at the output of the gate 3 has a fonn substantially as illustrated and a duration of approximately 3 microseconds.

Each coder line L1L5 is also connected to respective storage flip stages S1-S5 over corresponding gates Gl-GS which are preceded by respectiveinverters J l-'J5. The outputs of the gates,GlG5 are also connected to the flip stages SIS5 through respective gates G6-Gl0. The output from the collector gate'3 is conducted over an impulse shortening stage 7 and such output of the gate 3 is also connected over a gate 4 to a flip stageS, the output of which is conducted over an impulse delay stage 6 to the other inputs of the respective gates 01-65.

The operation of the circuit of FIG. 1 will be readily'apparent in conjunction with the impulse forms illustrated in FIG. 2. Consequently, upon closure of one of the keys and contacts 1 associated therewith, impulses will appear on the lines in accordance with the desired code to be set by such key, which impulses will result in an impulse at the output of the collector gate 3 which will be conducted over the impulse shortening stage 7 to the gates G6Gl0 and over the gate'4 to the flip stage 85. As a result, the respective flip stages 81-85 will be set in accordance with the desired-code, either over merely the inverters J1-J5 and gates GIG5 or also over gates 06-010. The output of the flip stage 5 (see line e of FIG. 2) after passing through the impulse delay stage 6, which delays the impulse by time T2 =l microsecond (see line f of FIG. 2), blocks gates Gl-GS and prevents further impulse transfer over such gates and at the same time blocks the gate 4 resulting in a shortening of the setting impulse (see line d in FIG. 2) for the flip stage 5 which forms the transfer block.

The release of such blocking action is effected by an impulselike resetting of the flip stage 5 over the reset line h into its original position and may take place only after the collection impulse has been terminated at c, i.e., after a duration of 3 microseconds, as otherwise the storer would be reset again by the symbol still present at the lines Ll-LS. Following the resetting of the flip stage, a new symbol can be immediately placed on lines L1--L5 with a minimum time involved comprising 4 microseconds, which represent the cumulative time of the collection impulse duration plus the reset impulse duration.

It is not necessary to erase the stages S1 to S of the parallel register between symbols as the register may be merely reset or rather overset by each new symbol. As a result, the impulse shortening time T1 of the impulse shortening stage 7, as illustrated in FIG. 2 for the impulse g (see line g of FIG. 2), must be smaller than T2.

The impulses appearing at the five outlets of the storers are conducted to a parallel-series symbol converter or an appropriate, preferably electronic receiver.

The circuit disclosed is very efficient, assuring with a very high degree of probability the prevention of the recording of mixed symbols, and at the same time, as demonstrated by experiments, makes possible extremely rapid sequences of key operation.

Instead of the so-called RS flip-flops (static bistable flip stages) employed in the embodiment of FIG 1, dynamic flip stages such as delay flip-flops may be utilized as illustrated in FIG. 3 with FIG. 4 illustrating the impulse forms associated with this circuit.

This construction employs the same circuitry for generation of the actuating impulses as illustrated in lines a and b of FIG. 4, and the lines LlL5 are connected to a collection gate 13, generally corresponding to the gate 3, but produces a negated impulse k (see line k of FIG. 4) as compared with the impulses c of the circuit of FIG. 1. The impulses b in this case are transmitted to preparation inputs of storage flip stages S21-S25 as well as to the collector gate 13. Thus, upon actuation of any key a negative collection impulse k of about 3 microseconds duration will appear at the output of the collector gate 13. Such collection impulse is conducted to an impulse shortening stage 14 which results in a shortening of the impulse to a time of less than 1 microsecond. As the preparation input of such flip stage is permanently connected to high potential, the positive flank of the shortened impulses appearing at m sets a flip stage 15 (see line m of Fig. 4). The output of the flip stage 15 is conducted to the flip stages 521-825 of the parallel register whereby the positive timing flank of the impulse will trigger the flip stages of the register to complete impulse transfer therein. Thus, both adequate setup time (=T2) and hold time (=collector impulse T2) are available.

It will be apparent that a renewed setting of the flip stage 15 and thus of the register by a renewed striking of the key is impossible as long as the flip stage 15 has not been reset by means of its static input at p. However, in contrast to the circuit illustrated in FIGS. 1 and 2, the resetting of the timing stage 15 can take place immediately after the setting as any collection impulse still present at a can produce no positive timing flank at m. Consequently, a second symbol can be typed and identified by the flip stage only after completion of the first collection impulse at k so that a new negative flank can occur at this point. The time between the depression of two keys thus may have a minimum of 3 microseconds, providing that the receiver connected at the keyboard outlet, for example, a parallel-series converter indicated as PSU, is able to process the first symbol within such time.

If contact impacts are to be expected within the first few microseconds a circuit comprising a combination of those of FIGS. 1 and 3 may be utilized, such as illustrated in FIG. 5, in which the parallel register $31-$35 receives the spacing impulses over the timing inputs while the marking impulses are fed over the static flip stage inputs. In such case the preparation inputs would permanently lie on high potential. However, in this arrangement the flip stages employed should be those in which the static inputs dominate the dynamic inputs, i.e., if concurrently over this dynamic input one condition is to be produced and over the static input the opposite condition is to be produced, the flip stage involved will certainty assume the condition required by the static input. Inverters 1115 and gates GIL-G15 correspond to the like inverters of FIG. 1 and gates $31-$35 correspond to the gates 01-05 of FIG. I. As will be apparent from the impulse diagram of FIG. 6, the general operation is quite similar to that of the circuit of FIG. 1, with the exception of differences in the actuation and operation of the flip stages, the respective pulse of the lettered lines appearing at this correspondingly identified points of FIG. 5. Thus, a synchronizing impulse occurs at q with every key stroke, independently of the coding, which is applied to the respective flip stages S3l-S35.

It will be apparent that mixed symbol formation can occur in these circuits only when two keys are depressed within the time of the shortened collection impulse. Thus, for example, if such time is made T2=1 microsecond, at an average stroke speed of 50 cm/second, in order to obtain a mixed symbol two keys would have to be operated within a vertical difference of 0.5 u m. This value is far below the mechanical tolerances in key structures and indicates the improbability of even this rare case occurring in practical operations. Experiments have confirmed this fact.

Having thus defined our invention, it will be apparent to those skilled in the art from the disclosure herein given that various immaterial modifications may be made in the same without departing from the spirit of our. invention.

We claim:

1. In a circuit arrangement for the parallel transmission of key-selectable telegraphic code impulses in which, in response to the actuation of a key, at least one impulse having a duration greater than 2 us is produced and supplied to a parallel storer having at least as many storage places as the possible number of impulses in the telegraph field, the combination of means connected to the storer for feeding a control signal thereto for controlling the termination 2 #8. storage operations thereof, and means disposed to receive such control impulses for producing an impulse following a duration less than that of said control impulse such produced impulse being conducted to said storer and operative to effect termination of the storage operation after a storage period of less than 2 ts.

2. A circuit arrangement according to claim 1 comprising in further combination gates disposed at the respective signal inputs of said storer, a collector gate to which the code impulses are conducted, a flip stage to which an impulse appearing at the output of said collector gate is conducted, and impulse delay means connecting the output of said flip stage to said storer input gates, operative to delay a blocking impulse thereto for a period up to 2 as.

3. A circuit arrangement as defined in claim 2, wherein the marking impulses corresponding to the code combinations are fed over static inputs of the parallel storage flip stages and the spacing impulses over the dynamic preparatory inputs of said flip stages, with the preparatory inputs lying continuously at a high potential, said flip stages having static inputs which dominate the dynamic inputs.

4. A circuit arrangement according to claim 1, comprising in further combination, a collector gate to which the code impulses are conducted, a flip stage, impulse shortening means operatively connecting the output of said collector gate to said flip stage, the output of said flip stage being connected to the storer for initiating the storage operation, said impulse shortening means shortening the received impulse to less. than 2 ,us, with the rear flank thereof being operative to actuate said flip stage.

5. A circuit arrangement as defined in claim 4, wherein the marking impulses corresponding to the code combinations are fed over static inputs of the parallel storage flip stages and the spacing impulses over the dynamic preparatory inputs of said flip stages, with the preparatory inputs lying continuously at a high potential, said flip stages having static inputs which dominate the dynamic inputs.

Claims (5)

1. In a circuit arrangement for the parallel transmission of key-selectable telegraphic code impulses in which, in response to the actuation of a key, at least one impulse having a duration greater than 2 Mu s is produced and supplied to a parallel storer having at least as many storage places as the possible number of impulses in the telegraph field, the combination of means connected to the storer for feeding a control signal thereto for controlling the termination 2 Mu s. storage operations thereof, and means disposed to receive such control impulses for producing an impulse following a duration less than that of said control impulse such produced impulse being conducted to said storer and operative to effect termination of the storage operation after a storage period of less than 2 Mu s.

2. A circuit arrangement according to claim 1 comprising in further combination gates disposed at the respective signal inputs of said storer, a collector gate to which the code impulses are conducted, a flip stage to which an impulse appearing at the output of said collector gate is conducted, aNd impulse delay means connecting the output of said flip stage to said storer input gates, operative to delay a blocking impulse thereto for a period up to 2 Mu s.

3. A circuit arrangement as defined in claim 2, wherein the marking impulses corresponding to the code combinations are fed over static inputs of the parallel storage flip stages and the spacing impulses over the dynamic preparatory inputs of said flip stages, with the preparatory inputs lying continuously at a high potential, said flip stages having static inputs which dominate the dynamic inputs.

4. A circuit arrangement according to claim 1, comprising in further combination, a collector gate to which the code impulses are conducted, a flip stage, impulse shortening means operatively connecting the output of said collector gate to said flip stage, the output of said flip stage being connected to the storer for initiating the storage operation, said impulse shortening means shortening the received impulse to less than 2 Mu s, with the rear flank thereof being operative to actuate said flip stage.

5. A circuit arrangement as defined in claim 4, wherein the marking impulses corresponding to the code combinations are fed over static inputs of the parallel storage flip stages and the spacing impulses over the dynamic preparatory inputs of said flip stages, with the preparatory inputs lying continuously at a high potential, said flip stages having static inputs which dominate the dynamic inputs.

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