US3482150A - Planar transistors and circuits including such transistors - Google Patents

Planar transistors and circuits including such transistors Download PDF

Info

Publication number
US3482150A
US3482150A US646041A US3482150DA US3482150A US 3482150 A US3482150 A US 3482150A US 646041 A US646041 A US 646041A US 3482150D A US3482150D A US 3482150DA US 3482150 A US3482150 A US 3482150A
Authority
US
United States
Prior art keywords
region
base
emitter
collector
window
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US646041A
Other languages
English (en)
Inventor
Gunther Carl Maximilia Wolfrum
Theodor Henri Enzlin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
US Philips Corp
Original Assignee
US Philips Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by US Philips Corp filed Critical US Philips Corp
Application granted granted Critical
Publication of US3482150A publication Critical patent/US3482150A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond

Definitions

  • This invention relates to transistors comprising a semiconductor body having a first region, the collector region, of a first conductivity type, a second region, the base region, of the opposite conductivity type, and a third region, the emitter region, of the first conductivity type, the third region being surrounded by the second and the second region being surrounded by the first, in each case except an area defined by a boundary surface of the body, the regions being separated by junctions which are intersected by the said surface in accordance with closed figures and the said surface carrying a thin insulating layer covering the areas at which the junctions intersect the surface, which layer carries a conductive layer which contacts the emitter region through a window in the insulating layer and which extends over the insulating layer laterally of the window, forming in situ a contact area located above the collector region for connection of a supply conductor.
  • Such a transistor constitutes one determined embodiment of a planar transistor.
  • An object of the invention is inter alia to provide a construction of a planar transistor in which the maximum 3,482,150 Patented Dec. 2, 1969 potential between the collector region on the one hand and the base or emitter region on the other is not limited or hardly by properties of the insulating layer, but is limited by the junction betwen the collector and base regions, while the said conductive layer may still be extended sufiiciently for the attachment of supply conductors.
  • a capacity occurs between the conductive layer and the collector region. This capacity causes feedback, for example, when the transistor is used as an amplifying element in a grounded-base connection for amplifying an electrical signal. This feedback may become very troublesome in high-frequency uses.
  • the base of the transistor is common to the input and output circuits, while the signals to be amplified are fed to the emitter and the amplified signals are derived from the collector.
  • Another object of the invention is to eliminate the capacity causing feedback.
  • the base region extends beside the emitter region to such an extent that the contact area connected to the emitter region lies wholly above the base region.
  • This contact area or bonding pad is separated from the collector region not only by the insulating layer but also by the base region and the junction between the base and collector regions.
  • the said capacity causing feedback does not occur since the base region constitutes a shield layer between the collector region and the metal layer connected to the emitterregion. This is at the expense of an increase in basecollector capacity and base-emitter capacity. In circuits of the kind described, these increased capacities are often less interfering than the capacity causing feedback.
  • the transistor according to the invention is a high voltage transistor, it is not the total emitter-collector voltage which appears across the insulating layer in operation but only the considerably lower emitter-base voltage, thus avoiding the risk of breakdown of the insulating layer under the metal layer connected to the emitter region.
  • a further conductive layer or bonding pad is provided which contacts the base region through a window in the insulating layer and which forms a contact area located wholly above the base region for connection of a further supply conductor.
  • the conductive layer connected to the base region thus extends completely above the base region, thus avoiding breakdown of the insulating layer if a large potential difierence occurs between the base and collector regions.
  • the said insulating layer insofar located between the base region and the conductive layer connected thereto, no longer has an insulating function. Consequently, in one embodiment of the invention, the conductive layer connected to the base region lies completely within a window of the insulating layer.
  • the invention also relates to a circuit for amplifying electrical signals, including a transistor according to the invention, which is characterized in that the base is common to the input and output circuits, the signals to be amplified being fed to the emitter and the amplified signals being derived from the collector.
  • FIGURES 1 and 3 are sectional views of known transistors
  • FIGURES 2 and 4 are plan views of these transistors
  • FIGURE 5 is a sectional view of a transistor according to the invention.
  • FIGURE 6 is a plan view of this transistor
  • FIGURES 7 to 16 show several stages of the manufacture of such a transistor
  • FIGURE 17 is a plan view and FIGURE 18 is a sectional view of a transistor according to the invention.
  • the transistor of FIGURE 1 comprises a collector region 1, which may consist of, for example, n-type silicon, a p-type base region 2 and an n-type emitter region 3.
  • a collector region 1 which may consist of, for example, n-type silicon, a p-type base region 2 and an n-type emitter region 3.
  • Each of the last-mentioned two regions are surrounded by the preceding region, except at the areas at which they are bounded by the surface 4.
  • This surface is covered with a thin insulating layer 5 which cover inter alia the areas at which junctions 6 and 7 between the regions intersect the surface 4. This intersection takes place along closed lines which are shown as broken lines in FIGURE 2 and indicated by the numerals 8 and 9.
  • Above the emitter region the insulating layer 5 is provided with a window 10 Whose contact layer 11 and a supply conductor 12 form the emitter connection.
  • a base connection 13 and a collector connection 14 are formed in a similar manner. It will be evident that in such a transistor
  • This transistor comprises a collector region 21, a base region 22 and an emitter region 23.
  • an insulating layer 25 is provided with windows 30, but the conductors contacting the associated regions now have the form of enlarged metal layers 31 and 32 which extend at the sides of the windows and above the collector region 21 to form bonding pads where they are connected to supply conductors 33 and 34. It will be evident that in this case the full potential occurring between the collector on the one hand and the base on the other appears across the insulating layer 25. The same is true of the potential between the collector and the emitter, which is usually almost equally high. If these potentials are high, for example higher than 300 volts, there is a great chance of breakdown occurring in the layer 25.
  • FIGURE 19 shows a diagram of such a circuit.
  • the emitter, the base and the collector of the transistor are indicated by E, B and C respectively, and the capacity causing feedback is indicated by C
  • the signals to be amplified are fed to terminals P and Q and the amplified signals are derived from terminals R and S.
  • the window located above the base region partly surrounds the window above the emitter reigon.
  • the junctions between the regions are again shown in broken lines in FIGURE 4 and indicated by the numerals 28 and 29.
  • the collector connection is in this case formed as a conductive layer 36 at the underside of the transistor.
  • FIGURES 5 and 6 A first embodiment of a transistor according to the invention is shown in FIGURES 5 and 6.
  • This transistor comprises a collector region 41, a base region 42 and an emitter region 43. These regions are bounded by the surface 44 which carries an insulating layer 45. Junctions 46 and 47 between the regions intersect the said surface along closed curves 48 and 49 shown in broken lines in FIGURE 6.
  • the insulating layer 45 Above the emitter region 43, the insulating layer 45 is provided with a small window 50 where a conductive layer 51 contacts the said region.
  • the layer 51 is enlarged relative to the window 50 to extend beside the window, over the insulating layer to form an enlarged bonding pad and is connected in situ to a supply conductor 52.
  • a small window 53 is provided together with an enlarged conductive layer 54 and a supply conductor 55.
  • the base region 42 extends on each side of the emitter region 43 to an extent such that the conductive layers 51 and 54 lie completely above the base region and hence within the boundary defined by the line 48 (FIGURE 6).
  • the breakdown voltage between the conductive layers 51 and 54 on the one hand and the collector region 41 on the other is determined not only by the properties of the insulating layer 45 but also and substantially by the junction 46 between the collector and base regions.
  • the capacity C causing feedback does not occur. Instead of the capacity C there occurs inter alia a capacity C (see FIGURE 20). This is the capacity between the metal layer 51 and the base region 42. Further, an additional base-collector capacity C occurs which is caused by an enlargement of the base region. So the capacity C may be regarded to be replaced by the capacities C and C which in many cases are considerably less interfering than the capacity C
  • the connection to the collector region is obtained by means of a window 56 in the insulating layer 45, a conductive layer 57 which in the window contacts the collector region, and a current-supply conductor 58.
  • a silicon disc 61 of the n-type having a resistivity of Q cm., a cross-section of 25 mrns. and a thickness of 250 microns (FIGURE 7) is covered with an insulating silicon-dioxide layer 62 (FIG- URE 8) by heating in moist oxygen at 1200 C. for two hours.
  • a large number of transistors will be manufactured from the disc simultaneously and in the same usual manner. The manufacture of one of these transistors will be described hereinafter.
  • the upper side of the disc is covered with a photosensitive masking layer 63 which is illuminated in accordance with a determined pattern representing the outlines of the base region to be formed, then developed and partly dissolved, resulting in apertures 64 being formed in the layer 63 (FIGURE 9).
  • the disc 62 is introduced into an etching bath consisting of 40 gms. of ammonium fluoride (NH F) dissolved in 60 mls., of water, to which 6 mls. of concentrated hydrofluor (HF) have been added.
  • NH F ammonium fluoride
  • HF concentrated hydrofluor
  • the base region is manufactured in three stages. First a thin layer of boron oxide (B 0 is vapour deposited at 900 C. in dry nitrogen for 30 minutes. Subsequently a first dilfusion in moist oxygen takes place at 1200 C. for 2 hours, followed by an after-diffusion in dry nitrogen at 1280 C. for 24 hours. Now a base region 65 of the p-type has been formed, while the window in the layer 62 is closed again by a vitreous boron-containing oxide layer 62 (FIGURE 11).
  • B 0 is vapour deposited at 900 C. in dry nitrogen for 30 minutes.
  • a first dilfusion in moist oxygen takes place at 1200 C. for 2 hours, followed by an after-diffusion in dry nitrogen at 1280 C. for 24 hours.
  • a base region 65 of the p-type has been formed, while the window in the layer 62 is closed again by a vitreous boron-containing oxide layer 62 (FIGURE 11).
  • a window having the size of the emitter region to be formed is etched in the insulating layer 66 (FIGURE 12) with the aid of a photosensitive masking layer which is illuminated, developed and dissolved.
  • the disc 61 is subsequently heated in phosphorous vapour at 1070" C. for two hours, resulting in an emitter region 67 consisting of n-type silicon being formed.
  • the maximum potential which is permissible between the conductive layers 69 and on the one hand and the collector region on the other is again determined substantially by the properties of junction layer 75 between the base and emitter regions, and this potential may be a multiple of the maximum potential to be applied across an oxide layer.
  • window above the base region may, without objection, be
  • This conductive layer is indicated by 76 in FIGURE 16.
  • connection to the collector region may be made in the usual manner beside the emitter and base connections in a window, or at the lower side of the disc 61.
  • a more practicable embodiment of a transistor according to the invention has an emitter window 81 which lies between two base windows 82.
  • Conductive layers 83 and 84 in the windows contact an emitter region 85 and a base region 86 respectively.
  • the lines along which the junctions between the various regions intersect the semiconductor surface are indicated by the numerals 87 and 88 in FIGURE 18.
  • a transistor comprising a semiconductor body having a collector region of one type conductivity, a base region of the opposite type conductivity inset in the collector region forming a collector p-n junction extending to a major planar surface of the body, and a tiny emitter region of the one type conductivity inset in the base region forming an emitter p-n junction extending to said major planar surface, the collector, base and emitter regions all having substantial surface areas accessible at said major planar surface, a thin insulating layer on said major planar surface and covering the areas at which the p-n junctions intersect the said major planar surface, a base window opening in said insulating layer over the base region surface area, a base conductive contact in the base window and on the surface of said base region, a base supply conductor bonded to said base contact, a tiny emitter window opening in said insulating layer over the emitter region surface area, an emitter conductive contact on the insulating layer and extending through the emitter window into contact with the emitter region, the lateral extent
  • the base conductive contact comprises a conductive layer on the insulator and extending through the base window into contact with the base region, said base conductive layer being located wholly above the base region.
  • An amplifying circuit including a transistor as set forth in claim 1 and comprising an input circuit coupled to the emitter supply conductor, and an output circuit coupled to the collector region, said base supply condutor being connected in common to the input and output circuits.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)
US646041A 1966-06-29 1967-06-14 Planar transistors and circuits including such transistors Expired - Lifetime US3482150A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL6609002A NL6609002A (pt) 1966-06-29 1966-06-29

Publications (1)

Publication Number Publication Date
US3482150A true US3482150A (en) 1969-12-02

Family

ID=19797000

Family Applications (1)

Application Number Title Priority Date Filing Date
US646041A Expired - Lifetime US3482150A (en) 1966-06-29 1967-06-14 Planar transistors and circuits including such transistors

Country Status (10)

Country Link
US (1) US3482150A (pt)
AT (1) AT278094B (pt)
BE (1) BE700582A (pt)
CH (1) CH465063A (pt)
DK (1) DK119715B (pt)
ES (1) ES342362A1 (pt)
GB (1) GB1193113A (pt)
NL (1) NL6609002A (pt)
NO (1) NO120434B (pt)
SE (1) SE326776B (pt)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3911468A (en) * 1970-05-22 1975-10-07 Kyoichiro Fujikawa Magnetic-to-electric conversion semiconductor device

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3183576A (en) * 1962-06-26 1965-05-18 Ibm Method of making transistor structures
US3302076A (en) * 1963-06-06 1967-01-31 Motorola Inc Semiconductor device with passivated junction
US3305913A (en) * 1964-09-11 1967-02-28 Northern Electric Co Method for making a semiconductor device by diffusing impurities through spaced-apart holes in a non-conducting coating to form an overlapped diffused region by means oftransverse diffusion underneath the coating
US3363152A (en) * 1964-01-24 1968-01-09 Westinghouse Electric Corp Semiconductor devices with low leakage current across junction
US3373323A (en) * 1964-05-15 1968-03-12 Philips Corp Planar semiconductor device with an incorporated shield member reducing feedback capacitance
US3398029A (en) * 1963-10-03 1968-08-20 Fujitsu Ltd Method of making semiconductor devices by diffusing and forming an oxide
US3409807A (en) * 1964-01-08 1968-11-05 Telefunken Patent Semiconductor arrangement with capacitative shielding means between conductive strips and semiconductor body

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3183576A (en) * 1962-06-26 1965-05-18 Ibm Method of making transistor structures
US3302076A (en) * 1963-06-06 1967-01-31 Motorola Inc Semiconductor device with passivated junction
US3398029A (en) * 1963-10-03 1968-08-20 Fujitsu Ltd Method of making semiconductor devices by diffusing and forming an oxide
US3409807A (en) * 1964-01-08 1968-11-05 Telefunken Patent Semiconductor arrangement with capacitative shielding means between conductive strips and semiconductor body
US3363152A (en) * 1964-01-24 1968-01-09 Westinghouse Electric Corp Semiconductor devices with low leakage current across junction
US3373323A (en) * 1964-05-15 1968-03-12 Philips Corp Planar semiconductor device with an incorporated shield member reducing feedback capacitance
US3305913A (en) * 1964-09-11 1967-02-28 Northern Electric Co Method for making a semiconductor device by diffusing impurities through spaced-apart holes in a non-conducting coating to form an overlapped diffused region by means oftransverse diffusion underneath the coating

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3911468A (en) * 1970-05-22 1975-10-07 Kyoichiro Fujikawa Magnetic-to-electric conversion semiconductor device

Also Published As

Publication number Publication date
GB1193113A (en) 1970-05-28
NL6609002A (pt) 1968-01-02
DE1614261A1 (de) 1970-05-27
DE1614261B2 (de) 1972-07-13
BE700582A (pt) 1967-12-27
AT278094B (de) 1970-01-26
ES342362A1 (es) 1968-10-16
DK119715B (da) 1971-02-15
NO120434B (pt) 1970-10-19
CH465063A (de) 1968-11-15
SE326776B (pt) 1970-08-03

Similar Documents

Publication Publication Date Title
US3373323A (en) Planar semiconductor device with an incorporated shield member reducing feedback capacitance
US4314268A (en) Integrated circuit with shielded lead patterns
US3423650A (en) Monolithic semiconductor microcircuits with improved means for connecting points of common potential
US3999213A (en) Semiconductor device and method of manufacturing the device
US3990102A (en) Semiconductor integrated circuits and method of manufacturing the same
GB1203086A (en) Ohmic contact and electrical lead for semiconductor devices
US3354360A (en) Integrated circuits with active elements isolated by insulating material
US3500143A (en) High frequency power transistor having different resistivity base regions
US3440498A (en) Contacts for insulation isolated semiconductor integrated circuitry
GB1147469A (en) Semiconductor devices, integrated circuits and methods for making same
US3484865A (en) Integrated semiconductor device including igfet with interdigitated structure
US3755722A (en) Resistor isolation for double mesa transistors
US3518504A (en) Transistor with lead-in electrodes
US3659162A (en) Semiconductor integrated circuit device having improved wiring layer structure
US3450965A (en) Semiconductor having reinforced lead structure
US3473979A (en) Semiconductor device
WO1986000755A1 (en) Integrated circuit having buried oxide isolation and low resistivity substrate for power supply interconnection
US3482150A (en) Planar transistors and circuits including such transistors
US3482152A (en) Semiconductor devices having a field effect transistor structure
US3821780A (en) Double mesa transistor with integral bleeder resistors
GB1135555A (en) Improvements in or relating to semiconductor devices
GB967365A (en) Semiconductor devices
US3763550A (en) Geometry for a pnp silicon transistor with overlay contacts
US3706130A (en) Voltage distribution for integrated circuits
US3409807A (en) Semiconductor arrangement with capacitative shielding means between conductive strips and semiconductor body