US3258359A - Semiconductor etch and oxidation process - Google Patents

Semiconductor etch and oxidation process Download PDF

Info

Publication number
US3258359A
US3258359A US271459A US27145963A US3258359A US 3258359 A US3258359 A US 3258359A US 271459 A US271459 A US 271459A US 27145963 A US27145963 A US 27145963A US 3258359 A US3258359 A US 3258359A
Authority
US
United States
Prior art keywords
furnace
semiconductor
hydrogen
gas
semiconductor material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US271459A
Inventor
Frances B Hugle
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Vishay Siliconix Inc
Original Assignee
Siliconix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconix Inc filed Critical Siliconix Inc
Priority to US271459A priority Critical patent/US3258359A/en
Application granted granted Critical
Publication of US3258359A publication Critical patent/US3258359A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02312—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
    • H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
    • H01L21/31658—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe
    • H01L21/31662—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe of silicon in uncombined form
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/043—Dual dielectric
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/118—Oxide films
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/906—Cleaning of wafer as interim step

Definitions

  • My invention relates to the accomplishment of plural processes within a given enclosure and particularly to the processing of a semiconductor as to etching and oxidizing within a single enclosure.
  • Contamination invariably experienced in handling between the etching and the oxidation processes is known to have unwanted effects upon the electrical characteristics of the completed devices.
  • the art has long sought processing steps which would allow these two processes to take place within a given enclosure, a hydrogen furnace for example, this has not been possible.
  • Single crystal slices of semiconductor material are normally strongly etched as a first step in transistor manufacturing in an acid mixture such as the known CP4 or CP6 mixtures. These mixtures contain various proportions of hydrofluoric acid, HF, nitric acid, HNO and acetic acid, HCO CH This etching is performed prior to the thermal oxidation step, which is the start of the manufacturing process of a planar transistor, for example. Between the etching and the oxidizing steps the slices must be rinsed and dried, which handling gives rise to the possible contamination.
  • an acid mixture such as the known CP4 or CP6 mixtures. These mixtures contain various proportions of hydrofluoric acid, HF, nitric acid, HNO and acetic acid, HCO CH This etching is performed prior to the thermal oxidation step, which is the start of the manufacturing process of a planar transistor, for example. Between the etching and the oxidizing steps the slices must be rinsed and dried, which handling gives rise to the possible contamination.
  • a more recently developed etching procedure employs hydrogen chloride, HCl, gas, usually diluted with hydrogen, H flowing over the heated semiconductor slices at a temperature within the range of from 900 C. to l300 L. for silicon, and several hundred degrees lower for gcrnumium, such as within the range of from 500" (Y. to sun” (1.
  • This procedure gave rise to the hope that when the vapor etching was ctnnpletcd, the gas .l'low could he changed and oxidation effected without removing or in any way disturbing the freshly etched, and therefore clean, wafer slice.
  • oxidation is normally accomplished by employing water vapor, H O, or oxygen, at elevated temperatures; or the two combined at an elevated temperature.
  • Oxygen is undesirable in a hydrogen furnace for obvious reasons of safety.
  • Hydrogen chloride and water vapor arethus not compatible within a single system as required for semiconductor processing. Furthermore, water vapor contaminates the system and no amount of purging the same by lit) .' example.
  • An object of my invention is to accomplish two heretofore incompatible processing steps within. one enclosure in semiconductor manufacturing.
  • Another object is to sequentially accomplish etching and oxidation of semiconductor material within one given enclosure.
  • Another object is to repeatedly sequentially accomplish etching and oxidation of semiconductor material within one given enclosure upon successive batches of such material.
  • Another object is to accomplish etching by hydrogen chloride and subsequent oxidation by water vapor Within a single furnace in semiconductor processing.
  • the single figure illustrates a typical furnace and the auxiliaries employed to accomplish the process.
  • the etching process is accomplished within an enclosed gas flow furnace I, of which a glass tube 2 having a diameter of the order of two inches and located within the radio frequency coil 3 of an induction heater is an Provision is made by known glass-working techniques for introducing selected gases and for allowing the'exhaust of the same frotn the working volume. This is accomplished in the figure for nitrogen gas, N through flowmeter 4 and valve (stopcock) 5; for hydrogen gas, H through tlowmeter 6 and valve 7; for hydrogen chloride gas, HCl, through tlowmeter 8 and valve 9; and for carbon dioxide gas, C0 through flownteter l0 and valve 11.
  • a selected sequential gas flow is accomplished by suitable manipulation of the valves, as will be described bclow.
  • the selected gas or combination of gases flows through inlet manifold I2, through furnace 1 and out through exhaust 14 to the roof or other safe dissipation area.
  • the semiconductor wafers I5 to be processed preferably lie on a silicon carbide coated carbon support 16.
  • a ground glass joint 17. or equivalent means, is provided in tube 2 to allow the wafers I5 to be placed into and removed from furnace l.
  • the furnace is purged by continuing the hydrogen flow only for a period of five minutes. This five minute period may be reduced somewhat if rapidity in processing is important.
  • radio frequency furnace While a radio frequency furnace has been specified, this type is not essential.
  • the diffusion furnace known to this art may be employed. For larger furnace sizes for proccssing more semiconductor material at one time the gas flows specified are increased proportionately and vice versa.
  • step (f) continuing the conditions of (e) above until said water vapor oxidizes said semiconductor to a selected depth determined by the temperature and the time interval of processing according to step (e).
  • step (b) The method of claim 1 in which the concentration of the hydrogen chloride gas in step (b) is in the range of'from 3% to 10%.
  • step (d) is approximately half carbon dioxide and half hydrogen.
  • step (f) to produce an oxide coating on silicon to a depth of 1,000 angstrom units is approximately twenty minutes.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)

Description

June 28, 1966 F. B. HUGLE 3,253,359
SEMICQNDUCTOR ETCH AND OXIDATION BROCESS Filed April 8, 1963 O O 0 O o O O O o O o ,0 in r0 0 O o I NA Q: -ON
N j cm :-I
N :1] :I v!
INVENTOR.
FRANCES B. HUGLE AGENT United States Patent 3,258,359 SEMICONDUCTOR E'ICll AND OXIDATION PROCESS Frances B. llugle, Santa Clara, Calif., assignor to Siliconix Incorporated, Sunnyvale, Calif., a corporation of California Filed Apr. 8, I963, Ser. No. 271,459 (.laims. (Cl. 117-413) My invention relates to the accomplishment of plural processes within a given enclosure and particularly to the processing of a semiconductor as to etching and oxidizing within a single enclosure.
. It is known that contamination is a significant factor in the processes involved'in the manufacture of semiconductor devices for electrical use, such as the wellknown transistor. The purity of the initial semiconductor material far cxcecds tha t in general chemical practice and purposely introduced'impuritie's must in themselves be equally pure. Consequently, even careful handling between one processing department and another'in a plant manufacturing semiconductor devices is not suflicient to eliminate incidental and unpredictable contamination by unwanted substances.
Contamination invariably experienced in handling between the etching and the oxidation processes is known to have unwanted effects upon the electrical characteristics of the completed devices. Although the art has long sought processing steps which would allow these two processes to take place within a given enclosure, a hydrogen furnace for example, this has not been possible.
Single crystal slices of semiconductor material are normally strongly etched as a first step in transistor manufacturing in an acid mixture such as the known CP4 or CP6 mixtures. These mixtures contain various proportions of hydrofluoric acid, HF, nitric acid, HNO and acetic acid, HCO CH This etching is performed prior to the thermal oxidation step, which is the start of the manufacturing process of a planar transistor, for example. Between the etching and the oxidizing steps the slices must be rinsed and dried, which handling gives rise to the possible contamination.
A more recently developed etching procedure employs hydrogen chloride, HCl, gas, usually diluted with hydrogen, H flowing over the heated semiconductor slices at a temperature within the range of from 900 C. to l300 L. for silicon, and several hundred degrees lower for gcrnumium, such as within the range of from 500" (Y. to sun" (1. This procedure gave rise to the hope that when the vapor etching was ctnnpletcd, the gas .l'low could he changed and oxidation effected without removing or in any way disturbing the freshly etched, and therefore clean, wafer slice.
However, oxidation is normally accomplished by employing water vapor, H O, or oxygen, at elevated temperatures; or the two combined at an elevated temperature.
Oxygen is undesirable in a hydrogen furnace for obvious reasons of safety.
-Water vapor combines safely with hydrogen and grows an excellent oxide if hydrogen chloride is not present. It has been found, however, that if even only a trace of hydrogen chloride is present when the water vapor is introduced the semiconductor surface becomes clouded and unusable. The reverse situation is also true; namely,
that if there is residual water vapor present the hydrogen chloride etching will not be satisfactorily accomplished.
Hydrogen chloride and water vapor arethus not compatible within a single system as required for semiconductor processing. Furthermore, water vapor contaminates the system and no amount of purging the same by lit) .' example.
3,258,359 I Patented June 28, 1966 ice means of inert gasesor the equivalent accomplishes compatible operation. Such contamination on the upstream, or inlet side, of such a gas flow furnace is serious. Contamination on the downstream," or outlet side, of such a furnace is not serious, since such contamination cannot reach the work in process.
After repeated attempts to accomplish etching and oxidizing successively in the same system, Idiscovered that if the water vapor is not chemically formed until the components thereof are at the semiconductor material being processed, all contamination problems are eliminatcd I accomplish this requirement by employing a form of the water gas reaction in reverse equilibrium. Instead of steam being one of the components, as it is in producing hydrogen at the known artificial gas works, steam is formed by combining hydrogen and carbon dioxide gases at the surface of the semiconductor, which surface is maintained at a high temperature in the furnace.
An object of my invention is to accomplish two heretofore incompatible processing steps within. one enclosure in semiconductor manufacturing.
Another object is to sequentially accomplish etching and oxidation of semiconductor material within one given enclosure.
Another object is to repeatedly sequentially accomplish etching and oxidation of semiconductor material within one given enclosure upon successive batches of such material.
Another object is to accomplish etching by hydrogen chloride and subsequent oxidation by water vapor Within a single furnace in semiconductor processing.
The single figure illustrates a typical furnace and the auxiliaries employed to accomplish the process.
-In the manufacture of single or multiple semiconductor devices of the nature of transistors, diodes and integrated circuits employing these devices it is necessary to initially form an oxide on the surface of the semiconductor material in order that this can be subsequently etched away in the configuration required to fabricate the device. For the semiconductor silicon, Si, the oxide, SiO is an example.
By the processing detailed below it is possible to etch a semiconductor surface clean and to subsequently form silicon oxide without the need for tedious and impractical precautions, by accomplishing both of these processes within a furnace enclosure. The oxide coating produced is free of pinholes and is of excellent quality for subscqucntly completing the nntnufncttu'e of transistor devices.
The etching process is accomplished within an enclosed gas flow furnace I, of which a glass tube 2 having a diameter of the order of two inches and located within the radio frequency coil 3 of an induction heater is an Provision is made by known glass-working techniques for introducing selected gases and for allowing the'exhaust of the same frotn the working volume. This is accomplished in the figure for nitrogen gas, N through flowmeter 4 and valve (stopcock) 5; for hydrogen gas, H through tlowmeter 6 and valve 7; for hydrogen chloride gas, HCl, through tlowmeter 8 and valve 9; and for carbon dioxide gas, C0 through flownteter l0 and valve 11. A selected sequential gas flow is accomplished by suitable manipulation of the valves, as will be described bclow. The selected gas or combination of gases flows through inlet manifold I2, through furnace 1 and out through exhaust 14 to the roof or other safe dissipation area. The semiconductor wafers I5 to be processed preferably lie on a silicon carbide coated carbon support 16. A ground glass joint 17. or equivalent means, is provided in tube 2 to allow the wafers I5 to be placed into and removed from furnace l.
. P is'con'tinu edi until a 'de'sired'thickne sso ox de reformed '.""-The are offorn'iation is ap- A gas flow of hydrogen of a few liters per minute is 7 established prior to heating the furnace and this flow is continued until the previously given operating temperatures for the semiconductor material being processed is reached. At such time a fiow of a few hundred milliliters is started of hydrogen chloride (milliliters per minute) in addition and this is continued for approximately thirty minutes in order to etch a preferred amount away for semiconductor processing.
At the end of this period the furnace is purged by continuing the hydrogen flow only for a period of five minutes. This five minute period may be reduced somewhat if rapidity in processing is important.
Thereafter, a flow of carbon dioxide, CO is started, of the order of-a few liters per minute. Preferably, this is equal in amount to the flow of hydrogen. The equation for this oxidation agent formation is:
CO H Z CO H 0 lt'is seen that the molal quantities of these reactants are'all unify. Although l prefer to introduce approxim'ately*equal' amounts-of carbon dioxide and hydrogen, thepropo'rtions maybedrastically varied, in which case the oxidation proceeds "prop'e'rly, but morjslowly. During this oxidation 'processirt a material is maintained at a tempera Wilh'lfl' th of from 900 C. to 1350 C.,'fo'r*'silic upon the silicon-f proximately 1000 om units of oxide thickness for 20 minutes of proce ss1ng;""
' In the above equation the equilibrium point shifts from left to right as the temperature'is increased. The high temperatures previously set forth are required for the formation of any water. Thus, there is present only the gases CO and H in the upstream, or inlet, side of my apparatus and only when the hot semiconductor is reached by this combined gas flow does water vapor form. This, of course, is immediately active in forming the oxide coating desired.
While a radio frequency furnace has been specified, this type is not essential. The diffusion furnace known to this art may be employed. For larger furnace sizes for proccssing more semiconductor material at one time the gas flows specified are increased proportionately and vice versa.
This invention has been disclosed by exemplary embodiments thereof. it will be understood that various modifications may be made in these specific embodiments without departing from the scope and spirit of the invention, as is set forth in the following claims.
Having thus fully described my invention and the manner in which it is to be practiced, 1 claim:
semissnducmr 1. In a method of manufacturing semiconductor devices wherein plural processes are successively accomplished in a single furnace the steps of (at) raising silicon semiconductor material to an elevated temperature within the range of from 900 C. to 1,300 C. in an atmosphere of hydrogen gas,
(b) etching said semiconductor material by introduc ing hydrogen chloride gas into said furnace,
(e) flushing said hydrogen chloride gas out of said furnace with hydrogen gas,
(d) introducing a mixture of carbon dioxide and hydrogen gases into said furnace,
(e) maintaining the temperature of said semiconductor material withinthe range of from 1,000 C. to 1,250 C. to accomplish the reaction of said carbon dioxide and hydrogen gases to car-hon monoxide gas and water vapor at the surface of said semiconductor,
(f) continuing the conditions of (e) above until said water vapor oxidizes said semiconductor to a selected depth determined by the temperature and the time interval of processing according to step (e).
2. The method of claim 1 in which the concentration of the hydrogen chloride gas in step (b) is in the range of'from 3% to 10%.
3.-The method of claim 1 in which the gaseous mixtur'e in step (d) is approximately half carbon dioxide and half hydrogen.
4. The method of claim 1 in which the duration of the etching step (b) is of the order of thirty minutes.
5. The method of claim 1 in which the time interval of step (f) to produce an oxide coating on silicon to a depth of 1,000 angstrom units is approximately twenty minutes.
References Cited by the Examiner OTHER REFERENCES A Diffusion Mask for Go, by Jordan. J. of Electro Chemical Society, vol. 108, No. 5, pp. 478 to 481.
Vapor, Plating by Powell et al., 1955, John Wiley and Sons, N.Y., Chap. 7, page 137.
MORRIS SUSSMAN, Irimury Emmi/rm.
JACOB STEINBERG, ALEXANDER WYMAN,
Examiners.

Claims (1)

1. IN A METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES WHEREIN PLURAL PROCESSES ARE SUCCESSIVELY ACCOMPLISHED IN A SINGLE FURNACE THE STEPS OF (A) RAISING SILICON SEMICONDUCTOR MATERIAL TO AN ELEVATED TEMPERATURE WITHIN THE RANGE OF FROM 900* C. TO 1,300*C. IN AN ATMOSPHERE OF HYDROGEN GAS, (B) ETCHING SAID SEMICONDUCTOR MATERIAL BY INTRODUCING HYDROGEN CHLORIDE GAS INTO SAID FURNACE, (C) FLUSHING SAID HYDROGEN CHLORIDE GAS OUT OF SAID FURNACE WITH HYDROGEN GAS, (D) INTRODUCING A MIXTURE OF CARBON DIOXIDE AND HYDROGEN GASES INTO SAID FURNACE, (E) MAINTAINING THE TEMPERATURE OF SAID SEMICONDUCTOR MATERIAL WITHIN THE RANGE OF FROM 1,000*C. TO 1,250* C. TO ACCOMPLISH THE REACTION OF SAID CARBON DIOXIDE AND HYDROGEN GASES TO CARBON MONOXIDE GAS AND WATER VAPOR AT THE SURFACE OF SAID SEMICONDUCTOR, (F) CONTINUING THE CONDITIONS OF (E) ABOVE UNTIL SAID WATER VAPOR OXIDIZES SAID SEMICONDUCTOR TO A SELECTED DEPTH DETERMINED BY THE TEMPERATURE AND THE TIME INTERVAL OF PROCESSING ACCORDING TO STEP (E).
US271459A 1963-04-08 1963-04-08 Semiconductor etch and oxidation process Expired - Lifetime US3258359A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US271459A US3258359A (en) 1963-04-08 1963-04-08 Semiconductor etch and oxidation process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US271459A US3258359A (en) 1963-04-08 1963-04-08 Semiconductor etch and oxidation process

Publications (1)

Publication Number Publication Date
US3258359A true US3258359A (en) 1966-06-28

Family

ID=23035666

Family Applications (1)

Application Number Title Priority Date Filing Date
US271459A Expired - Lifetime US3258359A (en) 1963-04-08 1963-04-08 Semiconductor etch and oxidation process

Country Status (1)

Country Link
US (1) US3258359A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3396052A (en) * 1965-07-14 1968-08-06 Bell Telephone Labor Inc Method for coating semiconductor devices with silicon oxide
FR2005220A1 (en) * 1968-03-20 1969-12-12 Rca Corp PERFECTION IN SEMICONDUCTOR DEVICES
US3498853A (en) * 1965-01-13 1970-03-03 Siemens Ag Method of forming semiconductor junctions,by etching,masking,and diffusion
US3518115A (en) * 1965-07-05 1970-06-30 Siemens Ag Method of producing homogeneous oxide layers on semiconductor crystals
US3742904A (en) * 1971-06-03 1973-07-03 Motorola Inc Steam generator and gas insertion device
US3969164A (en) * 1974-09-16 1976-07-13 Bell Telephone Laboratories, Incorporated Native oxide technique for preparing clean substrate surfaces
US4010290A (en) * 1971-09-22 1977-03-01 Motorola, Inc. Method of fabricating an ensulated gate field-effect device
US4139658A (en) * 1976-06-23 1979-02-13 Rca Corp. Process for manufacturing a radiation hardened oxide
US4196232A (en) * 1975-12-18 1980-04-01 Rca Corporation Method of chemically vapor-depositing a low-stress glass layer
WO1999035311A1 (en) * 1998-01-09 1999-07-15 Asm America, Inc. In situ growth of oxide and silicon layers
US6749687B1 (en) 1998-01-09 2004-06-15 Asm America, Inc. In situ growth of oxide and silicon layers

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2744000A (en) * 1953-02-21 1956-05-01 Int Standard Electric Corp Method of cleaning and/or etching semiconducting material, in particular germanium and silicon
DE1029941B (en) * 1955-07-13 1958-05-14 Siemens Ag Process for the production of monocrystalline semiconductor layers
US2983631A (en) * 1958-02-10 1961-05-09 Electronique & Automatisme Sa Method for making diodes and products resulting therefrom
US3168422A (en) * 1960-05-09 1965-02-02 Merck & Co Inc Process of flushing unwanted residue from a vapor deposition system in which silicon is being deposited

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2744000A (en) * 1953-02-21 1956-05-01 Int Standard Electric Corp Method of cleaning and/or etching semiconducting material, in particular germanium and silicon
DE1029941B (en) * 1955-07-13 1958-05-14 Siemens Ag Process for the production of monocrystalline semiconductor layers
US2983631A (en) * 1958-02-10 1961-05-09 Electronique & Automatisme Sa Method for making diodes and products resulting therefrom
US3168422A (en) * 1960-05-09 1965-02-02 Merck & Co Inc Process of flushing unwanted residue from a vapor deposition system in which silicon is being deposited

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3498853A (en) * 1965-01-13 1970-03-03 Siemens Ag Method of forming semiconductor junctions,by etching,masking,and diffusion
US3518115A (en) * 1965-07-05 1970-06-30 Siemens Ag Method of producing homogeneous oxide layers on semiconductor crystals
US3396052A (en) * 1965-07-14 1968-08-06 Bell Telephone Labor Inc Method for coating semiconductor devices with silicon oxide
FR2005220A1 (en) * 1968-03-20 1969-12-12 Rca Corp PERFECTION IN SEMICONDUCTOR DEVICES
US3742904A (en) * 1971-06-03 1973-07-03 Motorola Inc Steam generator and gas insertion device
US4010290A (en) * 1971-09-22 1977-03-01 Motorola, Inc. Method of fabricating an ensulated gate field-effect device
US3969164A (en) * 1974-09-16 1976-07-13 Bell Telephone Laboratories, Incorporated Native oxide technique for preparing clean substrate surfaces
US4196232A (en) * 1975-12-18 1980-04-01 Rca Corporation Method of chemically vapor-depositing a low-stress glass layer
US4139658A (en) * 1976-06-23 1979-02-13 Rca Corp. Process for manufacturing a radiation hardened oxide
WO1999035311A1 (en) * 1998-01-09 1999-07-15 Asm America, Inc. In situ growth of oxide and silicon layers
US6749687B1 (en) 1998-01-09 2004-06-15 Asm America, Inc. In situ growth of oxide and silicon layers
US20040206297A1 (en) * 1998-01-09 2004-10-21 Armand Ferro In situ growth of oxide and silicon layers
US20050205010A1 (en) * 1998-01-09 2005-09-22 Armand Ferro In situ growth of oxide and silicon layers
US7105055B2 (en) 1998-01-09 2006-09-12 Asm America, Inc. In situ growth of oxide and silicon layers
US7112538B2 (en) * 1998-01-09 2006-09-26 Asm America, Inc. In situ growth of oxide and silicon layers
US8317921B2 (en) 1998-01-09 2012-11-27 Asm America, Inc. In situ growth of oxide and silicon layers

Similar Documents

Publication Publication Date Title
US3785862A (en) Method for depositing refractory metals
KR101869198B1 (en) Etching method, storage medium, and etching apparatus
US3258359A (en) Semiconductor etch and oxidation process
US4069094A (en) Method of manufacturing apertured aluminum oxide substrates
US4176206A (en) Method for manufacturing an oxide of semiconductor
JPH06163517A (en) Method and system for forming oxide film under low temperature
JP2005045220A (en) Heat treatment method and heat treatment equipment
GB1046157A (en) Improvements in or relating to the manufacture of semiconductor devices
US3926715A (en) Method of epitactic precipitation of inorganic material
US3657030A (en) Technique for masking silicon nitride during phosphoric acid etching
JPH0758051A (en) Semiconductor processing method, and semiconductor device manufactured by the same
EP0539356B1 (en) Gaseous cleaning method for silicon devices
US3518115A (en) Method of producing homogeneous oxide layers on semiconductor crystals
JP2001156063A (en) Method and apparatus for manufacturing semiconductor device
US3498853A (en) Method of forming semiconductor junctions,by etching,masking,and diffusion
JPS63129633A (en) Surface treatment for semiconductor
JPH07176498A (en) Reaction furnace with reaction gas preheater
JPS5821826A (en) Apparatus for manufacturing semiconductor
JPS59227128A (en) Oxidation method for semiconductor substrate
US3592706A (en) Selective etching technique for semiconductors
US3102061A (en) Method for thermally etching silicon surfaces
de Araujo et al. Selective Oxidation Using Ultrathin Nitrogen‐Rich Silicon Surface Layers Grown by Rapid Thermal Processing
JPS60107840A (en) Manufacture of semiconductor element
JPH04254328A (en) Manufacture of semiconductor device
JP2828457B2 (en) Heat treatment furnace for semiconductor