US3160799A - High-frequency transistor - Google Patents

High-frequency transistor Download PDF

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US3160799A
US3160799A US74544A US7454460A US3160799A US 3160799 A US3160799 A US 3160799A US 74544 A US74544 A US 74544A US 7454460 A US7454460 A US 7454460A US 3160799 A US3160799 A US 3160799A
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base
emitter
region
recrystallized
zone
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US74544A
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Beale Julian Robert Anthony
Beer Andrew Francis
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US Philips Corp
North American Philips Co Inc
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US Philips Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3063—Electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4918—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Definitions

  • the invention relates to a transistor comprising a semi-conductive body, to which an emitter electrode and a base electrode are applied side by side in the form of alloy electrodes, of which the associated zcnes of recrystallized semi-conductive material establish a contact with the base zone, and furthermore to a method of manufacturing such a transistor.
  • alloy electrode on a semi-conductive body is to be understood to denote herein an electrode obtained by causing a quantity of electrode material to be alloyed in a molten state on the surface of the semi-conductive body below the melting point of the semi-conductive material of this body to dissolve an adjacent part of the semi-conductive body and subsequently, by cooling, causing firstly part of the dissolved semi-conductive material to recrystallize in the form of a zone grown on the semi-conductive body, the so-called recrystallized zone, after which the remainder of the melt solidifies, which consists for the major part of the alloyed electrode material, termed hereinafter the solidified zone.
  • This solidified zone is separated by the recrystallized zone from the initial material of the body.
  • the semi-conductive material of the re crystallized zone may have absorbed active impurities from the alloyed material, these impurities determining its specific conductivity and its conductivity type.
  • the recrystallized zone of the emitter is of a conductivity type opposite that of the base zone and the recrystallized zone of the base electrode has a conductivity type equal to that of the base zone.
  • the base zone may, for example, be formed by the semi-conductive body itself.
  • a diffusion method with a suitable active impurity such a thin base zone of which the conductivity type is opposite that of the remainder of the semi-conductive body, constituting in this case the collector zone.
  • Such abase zone obtained by a diffusion method may be provided as a whole prior to the provision of the emitter electrode and the base electrode.
  • an impurity may be introduced by diffusion out of the ambient atmosphere into the surface of the semi-conductive body adjacent the electrode. This impurity may, for example, be evaporated from the electrode material itself.
  • the invention has for its object inter alia to enlarge further the frequency range of a transistor comprising a semi-conductive body to which the emitter electrode and the base electrode are applied side by side in the form of alloy electrodes, of which the associated zones of recrystallized, semi-conductive material establish a contact with the base zone.
  • the transistor is characterized in that the recrystallized material of at least one of these electrodes is removed from the side remote from the other electrode over at least half of the contact surface initially occupied by the recrystallized zone with the base zone.
  • recrystallized zone with the base zone is concerned there, whereas in the method according to the invention the recrystallized material is removed over at least half of the contact surface initially occupied by the recrystallized zone.
  • the solidified zone which may then extend beyond the recrystallized zone, may still be sufficiently large for a satisfactory connection.
  • the removed material is preferably replaced by an insulating material, for example an insulating lacquer.
  • an insulating material for example an insulating lacquer.
  • This distance between the emitter electrode and the base electrode is preferably small, for example smaller than ten-thousandths of an inch.
  • the dimensions of the surface occupied by the recrystallized zone may then be of the same order of magnitude, whereas the dimensions of the solidified zone may. be much larger.
  • the base zone itself is preferably also removed, so that also the contact surface between the collector zone and the base zone and hence the capacitance between the base and the collector are further reduced.
  • the invention furthermore relates to a method of producing a transistor comprising a semi-conductive body, to which the emitter electrode and the base electrode are applied side by side in the form of alloy electrodes, of which the associated zones of recrystallized, semi-conductive material establish a contact with the base zone.
  • this method is characterized in that subsequent to the application of these alloy electrodes the part of the surface of the semi-conductive body between these electrodes is covered by a material insensitive to etchin agents, after which the assembly is subjected to etching, so that the recrystallized material of at least one of these two electrodes is removed from the side remote from the other electrode over at least half of the contact surface with the basezone occupied by the recrystallized zone.
  • the etching process is preferably carried out until at at the most one quarter of the contact surface occupied by the recrystallized zone with the base zone remains.
  • the etching process is preferably carried out in several stages with intermediate measurement of the capacity of the base-emitter junction. More than one etching bath may be used, preferably with etching agents of different concentrations and/or by using different current passages, so that in the first stage the etching process is performed more rapidly than during the subsequent stages, in order to obtain the desired capacity more accurately.
  • This method is quite suitable for automation methods, for example, by interrupting the etching process by means of a servo-mechanism automatically when the desired capacity is attained or has dropped just below the desired value.
  • one part may be removed mechanically, for example by cutting, from the side remote from the other electrode.
  • the final shape of the remaining recrystallized zone, subsequent to etching depends less upon the initial shape of the alloy electrode, so that the final shape is better controllable by choosing a suitable shape of the front from where etching starts.
  • FIGURE 1 is a cross-sectional View of part of a transistor.
  • FIGURE 2 is a plan view of part of the transistor shown in FIGURE 1.
  • FIGURE 3 shows a test circuit for capacity between emitter and base.
  • FIGURE 4 is a block schematic representation of an etching procedure in several steps in the method according to the present invention.
  • FIGURES 5 and 6 are partial plan views of two further transistors and v FIGURE 7 is a partial cross-sectional view of the transistor shown in FIGURE 6.
  • a transistor comprises a resolidified region 1 consisting mainly of lead with about 1% by Weight of antimony and including a little germanium, an n-type germanium region 2 consisting mainly of germanium and including a little lead and a little antimony, a resolidified region 3 consisting mainly of lead, antimony and aluminum and including a little germanium, a recrystallized p-type germanium measuring the Source.
  • region 4 consisting mainly of germanium and including I a little lead, antimony and aluminum
  • an n-type base' region 5 consisting mainly of germanium into which antimony has been diffused
  • a recrystallized p-type region 7 consisting mainly of germanium and including a little indium and gallium and a resolidified region 8 consisting mainly of indium and gallium and including a little germanium.
  • the different semiconductive regions are only designated schematically in FIGURE 1.
  • the recrystallized zones 2 and 4 will extend only very slightly beyond the respective resolidified regions 1 and 3.
  • the wire 9 forms a connection to the base
  • the wire 10 forms a connection to the emitter
  • the wire 11 forms a connection to the collector of the transistor and in addition is used as a mechanical support.
  • the region 1 and the region 2 are separated from the region 3 and the region 4 by a slot 12 which is about l-thousandth of an inch wide at its bottom.
  • the slot 12 is filled to the level indicated by the broken line 13 with polystyrene lacquer applied as a solution in ethylmethyl ketone.
  • the slot 12 is applied penetrating the alloy contact and its recrystallized region and extending slightly into the undissolved p-type material of the body.
  • This slot divides the alloy contact into two parts.
  • the slot may be manufactured by ultrasonic cutting using a thin cutting head and a slurry of a fine abrasive, e.g., aluminum oxide abrasive.
  • Some aluminum is applied to only one part of the alloy contact and the whole is then heated in an atmosphere of hydrogen for about 10 minutes at 750 C. during which the two parts of the contact are molten and antimony difiuses from the two molten parts into the material of the body underneath the molten parts and into the adjacent surface parts of the body including the bottom part of the slot 12, thus forming the n-type region 5.
  • the p-type region '7 and the resolidified region 8 maybe made in a manner known per se by melting a pellet, consisting of an indium-gallium alloy, onto the germanium body.
  • the transistor described above is now immersed in an electrolytic etching bath containing an aqueous solution of sodium hydroxide, e.g., a 5% solution.
  • the three wires 9, 10 and 11 are connected to the positive terminal of a voltage source and aplatinum electrode in the bath is connected to the. negative terminal of the voltage
  • a large amount of the recrystallized material 2, .4- and 7 is etched away from beneath the resolidified regions 1, 3 and 8, so that the area of contact between the recrystallized material 2 and 4 and the n-type region 5 is reduced to be not more than one half of the area of contact present after alloying and before etching.
  • the resolidified regions 1 and 3 are not attacked substantially by the etching medium and thus undercutting of the regions 1. and 3 occurs.
  • the broken lines 18, 19 and 20 show three intermediate stages during the etching step, the final stage being indicated by the line 20a.
  • the etching may be continued until theareas of contact between the regions 2 and 4 and the regions 1 and 3 are not more than one quarter of the area of contact before the etching step.
  • the initial dimensiona is 9 thousandths of an inch and the dimension b at the end of the prolonged etching step about 4 thousandths of an inch (see FIGURE 1).
  • the areas of contact between the regions 1 and 3 and the region 5 are reduced to about the same extent.
  • thev polystyrene lacquer in the slot is removed using ethylme-thylketone as a solvent, and the whole is immersed in an etching bath for a final etch in 20 volumes hydrogen peroxide at 70 C, for about 15 seconds.
  • the regions '1, 3 and 5 are then covered with a mass 14 of polystyrene lacquer dissolved in ethylmethylketone, the lacquer penetrating into-the gaps below the regions 1 and 3 and giving'mechanical strength to th transistor. 7 v
  • FIGURE 2 shows only the slot 12 and the lines 18, 19, 20 and 20a which are substantially circular in form since the outer contour of the regions 1 and 3 joined together by the lacquer provided in the slot 12 before the prolonged etching step is initially substantially circular.
  • the transistor so produced is then encapsulated in any known manner.
  • a The transistor described above has low emitter-base and base-collector capacitances due .to the severe reduction of the area of the base-emitter junction and the basecollector junction. 1
  • FIGURE 3 shows a test circuit for measuring the base-emitter junction capacitance.
  • the test circuit comprises a generator 21 of signals having a frequency of about mc./s. at a small signal strength of about 50 mv. (R.M.S.).
  • the generator 21 is connected in series with the emitter-base junction of the transistor and a resistor 22, conductor 23 being connected to the transistor emitter and conductor 24 being connected to the transistor base.
  • the signal developed across resistor 22 is measured by means of a vacuum tube volt-meter 25 and gives an indication of the base-emitter junction capacitance.
  • this capacitance can be measured even if the transistor is immersed in water if care is taken that the resistivity of the water is high, for example, is greater than 1,000 ohm-cms. There will be stray capacitance due to the connections to the base and the emitter and this is increased if the transistor is immersed in water which has a dielectric constant of approximately 80. It is, however, found (that the base-emitter junction capacitance at zero bias can be monitored in this way down to a value of about 7 pi, the stray capacitance with the transistor immersed in water being about 3il pf.
  • FIGURE 4 is a schematic diagram showing an apparatus in which the prolonged etching step may be carried out.
  • a number of stations are provided etching being carried out at alternate stations 26 and washing in water and testing being carried out at the other alternate stations 27. Testing is carried out by a circuit as described above with reference to FIGURE 3, the voltage developed across the resistor 22 during testing being supplied not to a volt-meter but to a control device determining whether further etching is necessary.
  • the apparatus also comprises a loading station 28 and an unloading station 29. A transistor is inserted in a holder at station 28 and is thereafter moved to the first etching station 26 where the transistor is automatically connected for etching and is immersed in etching fluid in a bath 30.
  • the transistor After a predetermined time, the transistor is moved to the first testing station 27, is connected to the conductors 23 and 24 of the test circuit and is immersed in a bath 31 of washing water. When washing has been efifected for a sufficient time, the test circuit 32 is switched on and the base-emitter junction capacitance is measured. If the capacitance has not been sufiiciently reduced, the transistor is moved to the second etching station 26 along a path indicated by the broken line 33 and is again subjected to etching with the use of a bath after which it is moved to the second testing station 27. Similar procedures are followed at each succeeding station 26 and 27 until the desired capacitance is reached.
  • the output of the test circuit 32 causes operation of a relay device 34 so that no further etching is effected.
  • the broken line 33 indicates the path of the device.
  • the transistor finally reaches the unloading station 29 where it is removed from the apparatus. It is not necessary to etch to the same extent at each of the stations 26, it may be preferred to etch to a considerable extent at the first station 26 and thereafter to etch more lightly at the succeeding stations 26 in order gradually to reach the desired capacitance. Flll 'thel' the extent of etching at a subsequent station may be made dependent on the capacitance measured at the preceding test.
  • the apparatus is shown in the schematic drawing of FIGURE 4 arranged in a linear manner, but it will be obvious that the apparatus may be a rotary apparatus and further that a single testing circuit may be used and connected in turn to each station 27 for testing before the line of transistors moves on to the succeeding stations so that unloading and reloading in turn of the holders for the transistors may be effected.
  • the etching procedure may also be applied toatransistor comprising two alloy zones provided by alloying at two separate areas of a semi-conductor body, as 'indicated in FIGURE 5. It is remarked that in general the two zones may be separated by as little as tWo thousandths of an inch and the dimension of each zone in the direction of separation of the zones may be about 8-thousandths of an inch.
  • the transistor comprises two resolidified regions 36 and 37.
  • the regions 36 and 37 are connected to wires (not shown) by solder (not shown).
  • a region 38 of an etch-resistant material is provided between the two regions 36 and 37, for example, applied with a paintbrush.
  • the transistor is then etched in the manner described with reference to FIGURES l and 2, progressive stages of etching being indicated by the broken lines 39.
  • FIGURES 6 and 7 An alternative method is illustrated in FIGURES 6 and 7. Before the Wires (not shown) are secured in position, a portion of each resolidified region 36 and 37 remote from the other resolidified region is removed and in the transistor-illustrated about half of each, the shaded portions 40 and 41, are removed, for example, with a sharp blade. The wires (not shown) are connected and the etch resistant region 38 provided and subsequent progresswe stages of etching are indicated by the lines 39, the full line 39 in FIGURE 7 indicating the final extent of etching.
  • the size of the resolidified regions are greater than the areas of contact between the recrystallized material and the base region remaining after etching and hence that for a given remaining area of contact it is, in each case, comparatively simple to attach wires to the resolidified regions.
  • etch-resistant lacquers and other solvents may be used, e.g., Cerric Black Resist available commercially under the reference DH 5353 from Cellon Limited may be used and acetone as a solvent.
  • a high-frequency transistor comprising a semiconductive body having 'a collector region of one conductivity type and a thin diifused base region of the opposite conductivity type, and separate emitter and base electrodes alloyed adjacent to one another on the same surface of the body forming emitter and base recrystallized regions, respectively, contacting the base region, said base recrystallized region being of the same type conductivity as that of the base region, said emitter recrystallized region being of the opposite type conductivity to that of the base region, the semiconductive body portions underneath the emitter electrode and on the side thereof remote from the base electrode being cut away such that the cross-sectional area in a plane parallel to the body of at least the emitter recrystallized region is at most one-quarter the corresponding cross-sectional area of the overlying emitter electrode and the latter has at least three-quarters of its area on the side remote from the other electrode extending over and free of direct contact with the semiconductive body, said emitter and base electrodes being spaced apart a distance less than 0.010 inch,
  • a high-frequency transistor comprising a semiconductive body having a collector region of one conductivity type and a thin diffused base region of the opposite conductivity type, separate emitter and baseaelectrodes alloyed adjacent to, one another on the same surface of the body forming emitter and base recrystallized regions, respectively, contacting the base region, said base recrystallized region being of the same type conductivity as that of the base region, said emitter recrystallized region being of the opposite type conductivity to that of the base region, the semiconductive body portions underneath each of the emitter and base electrodes on the side of each remote from the other being cut away such that the crosssectional area in a plane parallel to the body of each of the recrystallized regions is no greater than one-quarter the cross-sectional area of their overlying "electrodes and the latter have at least three-quarters of their area on the side remote from the other electrode extending over and free of direct contact with he semiconducive body, said emitter and base electrodes being spaced apart a distance less

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
US74544A 1959-12-14 1960-12-08 High-frequency transistor Expired - Lifetime US3160799A (en)

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GB42433/59A GB940443A (en) 1959-12-14 1959-12-14 Improvements in and relating to semiconductor devices

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CH (1) CH388459A (it)
DE (1) DE1121224B (it)
ES (1) ES263136A1 (it)
GB (1) GB940443A (it)
NL (2) NL121714C (it)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5896486A (en) * 1997-05-01 1999-04-20 Lucent Technologies Inc. Mass splice tray for optical fibers

Families Citing this family (1)

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Publication number Priority date Publication date Assignee Title
DE1282190B (de) * 1964-03-12 1968-11-07 Kabusihiki Kaisha Hitachi Seis Verfahren zum Herstellen von Transistoren

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2829422A (en) * 1952-05-21 1958-04-08 Bell Telephone Labor Inc Methods of fabricating semiconductor signal translating devices
US2842831A (en) * 1956-08-30 1958-07-15 Bell Telephone Labor Inc Manufacture of semiconductor devices
US2876401A (en) * 1955-09-12 1959-03-03 Pye Ltd Semi-conductor devices
GB849477A (en) * 1957-09-23 1960-09-28 Nat Res Dev Improvements in or relating to semiconductor control devices
US2956217A (en) * 1958-11-20 1960-10-11 Rca Corp Semiconductor devices and methods of making them
US2980983A (en) * 1958-07-29 1961-04-25 Philips Corp Method of making semiconductor device
US3069297A (en) * 1958-01-16 1962-12-18 Philips Corp Semi-conductor devices
US3081418A (en) * 1956-08-24 1963-03-12 Philips Corp Semi-conductor device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2821493A (en) * 1954-03-18 1958-01-28 Hughes Aircraft Co Fused junction transistors with regrown base regions
GB807995A (en) * 1955-09-02 1959-01-28 Gen Electric Co Ltd Improvements in or relating to the production of semiconductor bodies
NL107367C (it) * 1956-04-03

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2829422A (en) * 1952-05-21 1958-04-08 Bell Telephone Labor Inc Methods of fabricating semiconductor signal translating devices
US2876401A (en) * 1955-09-12 1959-03-03 Pye Ltd Semi-conductor devices
US3081418A (en) * 1956-08-24 1963-03-12 Philips Corp Semi-conductor device
US2842831A (en) * 1956-08-30 1958-07-15 Bell Telephone Labor Inc Manufacture of semiconductor devices
GB849477A (en) * 1957-09-23 1960-09-28 Nat Res Dev Improvements in or relating to semiconductor control devices
US3069297A (en) * 1958-01-16 1962-12-18 Philips Corp Semi-conductor devices
US2980983A (en) * 1958-07-29 1961-04-25 Philips Corp Method of making semiconductor device
US2956217A (en) * 1958-11-20 1960-10-11 Rca Corp Semiconductor devices and methods of making them

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5896486A (en) * 1997-05-01 1999-04-20 Lucent Technologies Inc. Mass splice tray for optical fibers

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CH388459A (de) 1965-02-28
NL121714C (it)
NL258921A (it)
GB940443A (en) 1963-10-30
ES263136A1 (es) 1961-05-01
DE1121224B (de) 1962-01-04

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