US2957945A - Timing circuit - Google Patents

Timing circuit Download PDF

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US2957945A
US2957945A US704927A US70492757A US2957945A US 2957945 A US2957945 A US 2957945A US 704927 A US704927 A US 704927A US 70492757 A US70492757 A US 70492757A US 2957945 A US2957945 A US 2957945A
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code
binary
output
timing
channel
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George N Packard
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AT&T Corp
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Bell Telephone Laboratories Inc
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Priority to US704927A priority patent/US2957945A/en
Priority to DEW24462A priority patent/DE1183958B/de
Priority to JP3313758A priority patent/JPS372563B1/ja
Priority to FR779929A priority patent/FR1215377A/fr
Priority to GB39824/58A priority patent/GB861515A/en
Priority to ES0246497A priority patent/ES246497A1/es
Priority to BE574121A priority patent/BE574121A/fr
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/5055—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination in which one operand is a constant, i.e. incrementers or decrementers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/17—Time-division multiplex systems in which the transmission channel allotted to a first user may be taken away and re-allotted to a second user if the first user becomes inactive, e.g. TASI
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/24—Time-division multiplex systems in which the allocation is indicated by an address the different channels being transmitted sequentially

Definitions

  • This invention relates to timing circuits and, more particularly, to means for simultaneously timing a plurality of overlapping and randomly initiated operations.
  • the source identity code In order to properly identify such a speech signal source, however, it is necessary that the source identity code be sustained for a minimum interval to insure proper reception and recognition at the receiving terminal. On the other hand, this identity code should be as short in duration as is possible consistent with recognition in order to avoid excessive waste of channel time and freezeout of the speech signal. It is therefore necessary to provide means for timing the duration of the identity codes in order to meet both of the above requirements.
  • the timing means which is suitable for controlling the duration of identity code signals in a time assign ment speech interpolation system must be capable of simultaneously timing the duration of a large number of diiferent identity codes. Furthermore, a new identity code must be transmitted each time a speech signal source becomes newly active. Since speech spurts occur on a random basis for large numbers of talkers, the identity codes are also initiated on a random basis and may very Well be overlapping in time.
  • Time assignment speech interpolation systems are not the only systems requiring simultaneous timing. Any other common control or programing system such as, for example, computers or telephone central oifice control equipment, also require such timing functions. Previous timing schemes require completely regular sequences of operations, and thus are not suitable for randomly initiated operations, or require separate timing means for each of the operations to be controlled, and thus are cumbersome, expensive and unreliable.
  • a plurality of successive and regularly recurring binary timing codes are generated.
  • a single one of these codes occurring at the beginning of each interval to be timed is gated into a storage mechanism.
  • the storage mechanism, or memory is of the type which has the capacity to store a large number of separate bits of binary information and, furthermore, is one which regularly presents these bits of information on a single set of output leads.
  • the output of the code generator is also introduced into a logic circuit.
  • the logic circuit merely serves to add a given fixed binary number to any binary number presented at its input.
  • a comparison or coincidence circuit com pares the outputs of the storage mechanism and the logic circuitry and generates a signal to terminate the timed interval when these outputs are identical.
  • the operation of the multiple timing circuit of the present invention can be better understood by recognizing the basic timing information provided by a reg ularly recurring cycle of binary codes.
  • the combination of the present invention serves to recognize the particular code at which timing is to begin and to gen erate the proper code for terminating the timed interval.
  • the duration of the timed interval is then the difference between the total time required for the generation of a complete cycle of the binary codes and the time required to generate the number of codes corresponding to the number added by the logic circuitry. That is, coincidence in timing codes will not occur until the binary code generator goes through the entire code sequence and returns to the number which is less than the original code by a number equal to the number added.
  • any number of discrete codes can be generated, any number of.difierent intervals canbe simultaneously timed.
  • the duration of these intervals can be chosen to equal any integral multiple of the basic timing length of a single code element by adding the proper number.
  • these intervals are not constrained to be initiated at any predetermined times. They may occur at random and in any succession possible.
  • Fig. 1 is a block diagram of a multiple timing circuit in accordance with the present invention
  • Fig. 2 is a block diagram of a time assignment speech interpolation system utilizing a timing circuit in accordance with the present invention.
  • Fig. 3 is a block diagram of a logic circuit suitable for performing the logical function of adding two to its input.
  • a multiple timing circuit in accordance with the present invention comprising an oscillator which produces at its output oscillations at a frequency 7. These oscillations are introduced into pulse shaper 108 which shapes the sinusoidal oscillations from oscillator 100 into square top pulses having a repetition rate equal to the frequency of oscillation. These pulses are introduced into binary counter 101.
  • Binary counter 101 is of any form known in the art such as, for example, a plurality of binary cells or flipflops, and recurrently produces on its output leads the binary representations of the numbers one through 2, in succession, where n represents the number of digits in the binary code which is used to reprment these numbers. The number It may have any value desired. In the illustrative embodiment of Fig. 1, n is assumed to be equal to three and, thus, binary counter 101 has three output leads. In this case, counter 101 will generate the binary membersone through eight in succession.
  • gate circuit 102 which provides switch connections between the individual ones of its three input leads and the corresponding ones of its three output leads.
  • Gate circuit 102 is operated by a signal on lead 103.
  • Storage mechanism 104 is of the type which will store a plurality of binary bits of information for an indefinite length of time. Furthermore, the information content of storage mechanism 104 is continuously or regularly presented on three output leads. Thus, the binary code introduced into storage mechanism 104 is presented, for at least a portion of the time, on its three output leads.
  • the output of binary counter 101 is also introduced into logic circuit 105.
  • Logic circuit 105 is a circuit arrangement capable of performing the logical operation of adding a fixed number to any binary number presented at its input. Thus, logic circuit 105 has been represented by the logical operation of add m where m can be any number less than 2. There is presented on the output of logic circuit 105 the binary representation of a number which is greater than the binary number introduced at its input by a quantity m. i
  • the output of logic circuit 105 and the output of storage mechanism 104 are both introduced into a compare circuit 106. Compare circuit 106 can be any type of coincidence recognizing gate arranged to produce an output if, and only if, the input on each lead is identical to the input on a paired lead.
  • Compare circuit 106 therefore makes a digit-by-digit comparison between the output of logic circuit 105 and the output of storage mechanism 104. When these outputs are identical, a distinctive signal such as, for example, a change from no pulse to pulse, is introduced on lead 107.
  • the operation of the timing circuit shown in Fig. 1 is as follows. Simultaneously with the initiation of the operation to be timed, a signal is introduced on lead 103. This signal operates gate 102 to gate a single binary number from binary counter 101 to storage mechanism 104. This binary number will be that number at which counter 101 happens to be at the particular instant that the start signal on lead 103 enables gate 102. Assuming that the timed operation can start at any time, the actual choice of binary numbers is completely random and may comprise any number included in the output of counter 101.
  • This particular binary number is stored in storage mechanism 104 and is presented on its output leads.
  • logic circuit 105 will add the binary number m to this particular binary code. Since the input of logic circuit 105 is connected directly to the output of binary counter 101, logic circuit 105 will receive a new binary code each time counter 101 is advanced one step. The output of logic circuit 105 will therefore comprise a series of binary codes identical to the output of counter 101 but advanced in time by an amount required to generate the binary number m.
  • Compare circuit 106 compares the binary code stored in storage mechanism 104 with the series of binary numbers provided on the output leads of circuit 105. When a position is reached in this series at which the output of logic circuit 105 is identical to the number stored in storage mechanism 104, compare circuit 106 will produce an outupt on lead 107 which may be utilized to terminate the timed operation.
  • the duration of the timed interval is related to the frequency f of oscillator 100, the number n of digits produced by counter 101 and the number m added by logic circuit 105 by where T is the length of this period and the other symbols are as defined above. It can be seen that by choosing suitable values for f, n and m, a timing interval of any desired length may be provided. This interval is the time required for binary counter 101 to proceed in its count from any given number through nearly a complete cycle to a number which is less than the given number by a number m.
  • timing circuit of Fig. 1 can be used to simultaneously time a large number of operations which are initiated in a random manner.
  • a timing circuit will be described in connection with a time assignment speech interpolation system such as that disclosed in a copending patent application of F. A. Saal and I. Welber, Serial No. 686,468, filed September 26, 1957, since matured into US. Patent 2,935,569, issued May 3, 1960. It is to be understood, however, that the timing arrangements are by no means limited to a time assignment speech interpolation system. They are equally applicable to any other common control or programing systems such as computers or electronic switching systems for telephone central oflices.
  • TASI time assignment speech interpolation systems
  • TASI systems have interconnected talker lines and transmission channels by means of time separation multiplex switching (TSM switching).
  • TSM switching time separation multiplex switching
  • These systems utilize the principle that speech, or any other signal, can be adequately represented by samples spaced in time, provided the sampling rate is at least twice the highest frequency component of the signal to be represented.
  • the interconnection of talker lines and transmission channels are therefore made by simultaneously gating a particular talker line and a particular transmission channel onto a common multiplex bus for the same sample interval.
  • speech signals on all of the talker lines can utilize the same multiplex bus and yet each be accurately reproduced on the individual transmission channels.
  • TSM switching TASI systems the activity of the individual talkers is ascertained by systematically scanning speech detectors connected to the individual talker lines and synchronously generating a talker identity code for each active talker.
  • a circulating or re-entrant memory is used to register the assignment of a particular active talker to a particular idle channel. The contents of the memory are then used to control the multiplex switching operation.
  • a complete TASI system embodying the operation described above is disclosed in the above-mentioned application by Saal and Welber, Serial No. 686,468, filed September 26, 1957.
  • TASI TASI
  • in-band multifrequency signaling tones are transmitted over an idle channel to indicate the proper listener connection to be made to that channel.
  • These tones must be sustained for a sutlicient length "of time to insure theiraccurate reception, i.e., on the order of milliseconds with present filters of economical design.
  • large transmission systems having many talkers demanding connection at one time require a connect signaling arrangement which will accommodate more than one talker simultaneously.
  • timing code is generated and associated with each talker identity code as the talker becomes active and is registered in the circulating memory.
  • These timing codes are also introduced into a logic circuit which adds a fixed number to the timing code.
  • a comparison made between the output of a logic circuit and the contents of a memory will indicate, at the instant that the timing codes are identical, that the signal interval is over.
  • a talker identity code queue 322 is shown. Queue 322 stores the identity codes of those talkers which have become active in the order in which their activity was initiated. Queue 322 thus serves as a programer for the TASI transmitter illustrated in Fig. 2.
  • the means by which these talker identity codes are generated and introduced into queue 322 forms no part of the present invention and will not be described here. It is sufficient for the purposes of the present invention to assume that queue 322 generates seven digit binary codes which identify particular talker lines and which indicate an active condition on those talker lines.
  • Memory unit 309 is a re-entrant type of memory unit such as, for example, a plurality of parallel delay loops having a capacity of c words of 12 bits each, where c is the total number of transmission channels available. . These 12 bits are circulated in synchronism with each other at a rate of eight thousand revolutions persecond. Seven of these 12 bits represent the particular talker identity code provided by queue 322. Three more of these bits represent connect signal timing information which will be more fully, described below. Thev remaining two bits called channel status bits carry information as to the present status of the channel which is associated with that particular time slot in the memory unit, indicated by the number in the channel boxes along theright side of memory 309. The function of the channel status, digits will now be described.
  • the two channel status digits permit the representation in binary form of any one of four different states or conditions of each individual transmission channel.
  • states and the corresponding binary code representations have been chosen as follows:
  • I 1 Channel available for use (Idle) 00 Channel being signaled over for connection (Connection) 01 -Channel being held for disconnection (Disconnection) 10 Channel being used for speech (Busy) 11 cessive slots numbered along the right hand side to correspond with the c channels of the transmission system.
  • These slots are illustrative of the time slots which appear in a circulating delay type of memory unit. Since memory unit 309 is a circulating or re-entrant type of memory, channel one shown in the slot labeled 1, that is, the bottom slot, in the next time interval appears in the position of the slot labeled 0, that is, the top slot. At the same time, all of the other channels advance one time slot so that channel two is now in the bottom slot and channel 0 is now in the slot second from the top. This circulation continues at the rate of eight thousand revolutions per second.
  • the circuitry which is shown as being connected to the bottom slot for example, translator 310, is actually connected to a fixed position in the circulating memory loop such that all other channel time slots proceed past this position in regular succession.
  • Translator 310 for example, therefore sees the channel status digits of channel one, then channel two and so forth, down to channel c, and then to channel one again.
  • translator 310 sees the output of a bottom slot as it passes from this slot to the top slot. In this way, control functions which are governed by the output of the bottom slot are operative upon the information in the top slot.
  • a binary 00 in the channel status portion of memory unit 309 will produce an output from translator 310 on line 311.
  • This output on line 3 11 operates a memory entry switch 315 which comprises 12 separate switches connecting 12 input leads to 12 corresponding output leads.
  • Memory entry switch 315 thus gates the talker identity code from queue 322 into the top slot position in memory 309. Since memory 309 is of the circulating or re-entrant type, the channel status digits which produce this output on lead 311 are taken from the same time slot into which switch 315 introduces this talker identity code. Since each time slot ofcirculating memory unit 309 is uniquely related to a particular transmission channel, this particular talker identity code has now been assigned to a particular channel.
  • Circulating memory unit 309 will continuously circulate this talker identity code and maintain this assignment of the particular talker to the particular channel for an indefinite length of time. A definite removal or erasure of this assignment is required to disassociate this talker and this channel.
  • the signals on these output leads operate the corresponding talker gates which connect the individual talkers to a time division bus from which they are synchronously gated to the proper transmission channel.
  • this channel gating arrangement is synchronized with memory unit 309, it can be seen that the talker identity code in memory unit 309 operates to gate the talker corresponding to that code onto the time separation multiplex bus at the same instant and for the same interval that the TSM bus is connected to the transmission channel assigned to that particular time slot in the memory.
  • the TASI transmitter illustrated in Fig. 2 Before the TASI transmitter illustrated in Fig. 2 can begin sending a particular talkers speech spurt, however, it must first indicate the proper listener for which that particular speech spurt is intended. Connect signaling is therefore required in the TASI transmitter to perform this function.
  • binary signal generator 321 continuously produces on two output leads the binary number 01. As described above, this binary code indicates that a channel is being signaled over for connection.
  • memory entry switch 315 When memory entry switch 315 is enabled by a pulse on output lead 311 of translator 310, it gates this 01 binary code into the channel status digit portion of memory unit 309. Furthermore, this 01 code is introduced into the same time slot in memory 309 that the talker identity code is introduced from queue 322. Thus, there is associated with the identity of this talker and the transmission channel assigned to this particular time slot, the information that this particular channel is being used for connect signaling.
  • This connect signaling code upon arriving at the bottom of circulating memory unit 309 is introduced into translator 310 and produces an output on output lead 312.
  • the output on lead 312 enables switch 322 which samples that particular talker identity code and delivers the sample to connect signal source 323.
  • Connect signal source 323 produces a multifrequency tone signal which is frequency code to the same talker identity as is introduced at its input.
  • Such a connect signal source is disclosed in the copending application of R. L. Carbrey, Serial No. 430,181, filed May 17, 1954. It comprises seven frequency sources separately gated by the digits of the talker identity code and fed into a summing amplifier. Any other frequency coding source would, of course, also be suitable.
  • Connect signal source 323 produces on connect signal bus 324 this frequency coded signal.
  • Connect signal bus 324- may in turn be connected to the time separation multiplex bus and be gated to the proper transmission channel in synchronism with the operation of circulating memeory unit 309.
  • a frequency coded signal is transmitted over that same channel indicating to the receiver to which listener that channel is to be connected.
  • the multifrequency tone must be sustained for a period of about five to milliseconds. It is this timing which it is the object of this invention to accomplish.
  • .a one thousand cycle oscillator 325 is used to drive a threedigit binary counter 326.
  • Binary counter 326 continuously produces on its three output leads the binary representations of the numbers one through eight, respectively, in succession.
  • memory entry switch 315 is operated by a pulse on lead 311, indicating that an idle channel is available, this three-digit binary code is gated into the connect signal timing portion of memory unit 309 simultaneously with the talker identity code and the 01" channel status digits.
  • binary counter 326 The output of binary counter 326 is also introduced into a logic circuit 327 which performs the logical function of adding two to the number presented at its input. There are thus produced on three output leads of logic circuit 327 the binary representations of the numbers one through eight in succession, but these numbers appear in time two units before the corresponding number appears on the output of binary counter 326.
  • each of these advanced timing codes is introduced into a comparator circuit 328.
  • the connect signal timing digits stored in memory unit 309 are also introduced into comparator circuit 328.
  • the function of comparator circuit 328 is to make a digit-by-digit comparison between the three-digit code introduced from logic circuit 327 and the three-digit codes introduced from memory unit 309.
  • This compari- 5011 may be accomplished by any one of the means well known in the art such as, for example, by the use of coincidence gates.
  • each timing code stored in memory unit 309 is presented to comparator circuit 328 eight thousand times in each second.
  • the output codes from logic circuit 327 will be presented to comparator circuit 328 only one thousand times per second.
  • Each individual output code from logic circuit 327 will therefore be held in comparator circuit 328 for a period of eight complete revolutions of circulating memory unit 309.
  • Each output code from logic circuit 327 will then be compared with the entire contents of the connect signal timing portion of memory unit 309.
  • the output of logic circuit 327 and the particular connect signal timing code stored in memory unit 309 will coincide only after binary counter 326 has made a complete cycle and arrives at the number which is two less than the particular timing code gated into circulating memory 309.
  • the interval required for this to occur can easily be controlled by adjusting the oscillating frequency of oscillator 325 and the particular number which is added in logic circuit 327.
  • oscillator 325 has a frequency of one thousand cycles per second
  • a new timing code is generated once each millisecond and the time required to run through a complete cycle of binary codes is eight milliseconds.
  • the duration of the timed interval will therefore be six milliseconds, that is, eight minus two.
  • comparator circuit 328 Upon recognizing identical binary codes at its two inputs, comparator circuit 328 produces a pulse output on lead 329. This pulse is used in a control circuit 330 to erase the 01 connect signal status digits from the channel status portion of memory unit 309 and to write in its place the digits 11. This indicates to the memory unit that the connect signaling interval is over and that it may now begin transmitting the actual spurt of speech. This erase and write function may be accomplished, for example, by momentarily opening up the memory loops for the channel status digits in memory unit 309 and inserting the new code. The 11 digits in translator 310 cause switch 316 to be operated and by way of translator 317 cause the proper talker gates to be operated.
  • the connect signal timing portion of the memory unit 309 and the timing code have been provided to allow more than one talker to be signaled for connection at one time. This is necessary because, in a large system, many talkers will initiate speech spurts within the same connect signaling interval. If a single-acting timer were used, the last talker to become active would be required to wait until all previously active talkers had received connect signaling service. This unduly long wait would constitute an additional freeze-out and impair service accordingly.
  • binary counter 326 and logic circuit 327 have been provided to enable an unlimited number of talkers to be signaled for connection simultaneously. These connect signaling intervals may be initiated at random throughout the entire cycle of binary counter 326 and more than one such interval can be initiated on the same connect signal timing code.
  • a pulse on lead 304 occurring in the time slot assigned to a particular talker indicates that that talker is no longer active 9. and that disconnection is now desired.
  • This pulse on lead 304 operates a signal generating circuit 305 which erases the 11 active code in the channel status digit portion of memory unit 309 and substitutes therefor the channel status code 10 indicating that the channel is'now being used for disconnect signaling.
  • This chan-. nel status code 10 upon arriving at translator 310, produces an output on lead 313. This output is used by disconnect signal source 307 to produce a disconnect signal which is transmitted to the receiver to terminate this assignment.
  • the disconnect signal is initiated by a pulse on lead 313 and appears on lead 306.
  • lead 306 may be connected to the time division bus and be synchronously gated to the proper transmission channel or may be coded and transmitted over a separate transmission channel.
  • a pulse is produced on lead 332.
  • the pulse on lead 332 operates a signal generator 308 and, simultaneously an erase circuit 331.
  • Erase circuit 331 erases the entire contents of that particular time slot of memory unit 309.
  • Signal generating circuit 308 substitutes in the channel status portion the digit 00. This code indicates that the channel is now idle and may be reassigned.
  • Fig. 3 there is shown a logic circuit which is suitable for adding the number two to a three-digit binary number and thus is suitable for logic circuit 327 in Fig. 2.
  • the operations necessary for adding two to a three-digit binary number are as follows.
  • the least significant digit of the binary number always remains the same.
  • the second least significant digit of the binary number is always inverted, that is, if the digit is a one it becomes a zero and if the digit is a zero, it becomes a one.
  • the most significant digit of the three-digit binary number remains the same if the second least significant digit is a zero and is inverted if the second least significant digit is a one.
  • A is the least significant digit and C is the most significant digit.
  • Each of these digits is preferably represented by the voltage conditions on two separate conductors. For example, to represent a one, one of the conductors might have a positive voltage thereon. The other conductor would have no voltage. To represent a zero, the first conductor would have no voltage thereon and the second conductor would have a positive voltage of the same magnitude as before.
  • the least significant digit A of the input binary number remains the same and becomes the least significant digit A of the output binary number.
  • the second least significant digit B of the input binary number is inverted merely by transposing the first and second conductors 16 and 17, respectively, carrying the voltage representing this digit, to provide the second least significant digit B of the output binary number.
  • the most significant digit C of the input binary number is treated in the following way.
  • the voltage on a first conductor is simultaneously introduced into two AND gates 11 and 12 and the voltage on the second conductor 13 is simultaneously introduced into two more AND gates 14 and 15.
  • AND gates 11, 12, 14 and 15 are of any well-known configuration producing an output it and only if a positive voltage is introduced on both their input conductors. Such a gate may, for example, be made up of unilateral conducting devices, transistors or vacuum tubes.
  • the voltage on the first conductor 16, representing the digit value of the second least significant digit B, is simultaneously introduced into the other input conductor of AND gates 12 and 14, while the voltage on second conductor 17 is simultaneously introduced into the remaining input conductor of 10 AND" gates 11 and 15.
  • the outputs of AND gates 11 and 14 are introduced into OR gate 18 while the outputs of AND gates 12 and 15 are introduced into another OR gate 19.
  • the outputs of OR gates 18 and 19 comprise the most significant digit C of the output binary number.
  • Means for simultaneously timing a plurality of over lapping operations comprising recycling code generating means for progressively generating a plurality of discrete code groups, means for storing only selected ones of said code groups, each of said stored code groups being selected at the beginning of a respective one of said operations, means for translating each of said generated code groups into another one of said code groups, means for comparing said translated code groups with each of said stored code groups and means responsive to coincidences between said translated code groups and each of said stored code groups for terminating the respective one of said operations.
  • Means for accurately timing a predetermined interval between two successive operations comprising means for generating a plurality of binary code groups in regular succession, means for storing one of said code groups in response to a first one of said operations, means responsive to said code group generating means for advancing each position in said succession to another of said code groups, means for comparing the contents of said storing means and the output of said translating means, and means for initiating a second one of said operations in response to a coincidence of inputs to said comparing means.
  • a timing circuit for simultaneously timing a plurality of intervals comprising means for successively generating a sequence of binary numbers, means for storing that number of said sequence which is instantaneously generated at the beginning of each of the timed intervals, logic circuitry means for translating each number of said sequence into a different number of said sequence, means for introducing said initial sequence into said logic circuitry means, means for comparing the output of said logic circuitry means and the contents of said storing means, and means for terminating respective ones of said intervals in response to coincidences between said output and said stored codes.
  • means for timing the duration of connect signaling comprising means for generating a plurality of regularly spaced dissimilar code groups, means for associating unique ones of said code groups with newly active signal sources in said system, means for translating said code groups into different code groups, means for deriving a control signal each time the output of said translating means is identical with one of said associated code groups, and means for signaling a connection until each of said control signals is derived.
  • said translating means comprises means for adding a predetermined code group to the output of said code group generating means.
  • a signal interpolation system a plurality of signal sources and corresponding utilization circuits, a lesser plurality of transmission channels, means, including a circulating memory unit, for assigning active ones of said signal sources to idle ones of said transmission channels, and mean for transmitting signals indicating said assignments to said utilization circuits for a predetermined interval
  • said signal transmitting means comprising a cyclic code generator, means for registering a particular code in said memory unit to correspond to each one of said assignments and to control said signals, binary code addition means adapted to add a fixed binary number to the output of said cyclic code generator, and means for comparing the output code of said addition means and the codes in said memory for terminating said signals when said codes are identical.
  • circulating memory means for registering the identifications of active talkers, a timing code generator, means for associating unique ones of said timing codes with said identifications, means for adding a fixed code to said timing codes, means, controlled by said identifications for generating an identity code, means for gating said identifications to said identity code generating means, means controlled by said memory means for enabling said gating means, and means controlled by the output of said adding means for disabling said gating means.
  • Circuit means for'simultaneously timing a plurality of randomly initiated operations which comprises re cycling binary counting means, means for assigning the output number from said counting means at the initiation of each of said operations to said operation, means for adding a preselected binary number to each output number from said counting means to form a sequence of numbers advanced by said preselected number with respect to said output numbers, means for comparing each of said advanced numbers with each of said assigned numbers to determine coincidences, and means for terminating each assigned operation when and only when a coincidence occurs between the assigned number and one of said advanced numbers.
US704927A 1957-12-24 1957-12-24 Timing circuit Expired - Lifetime US2957945A (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
NL234515D NL234515A (xx) 1957-12-24
US704927A US2957945A (en) 1957-12-24 1957-12-24 Timing circuit
DEW24462A DE1183958B (de) 1957-12-24 1958-11-15 Taktgeber, z. B. fuer TASI-Systeme
JP3313758A JPS372563B1 (xx) 1957-12-24 1958-11-20
FR779929A FR1215377A (fr) 1957-12-24 1958-11-24 Circuits de distribution chronologiques
GB39824/58A GB861515A (en) 1957-12-24 1958-12-10 Improvements in or relating to timing circuits
ES0246497A ES246497A1 (es) 1957-12-24 1958-12-20 APARATO ELÉCTRICO PARA SINCRONIZAR SIMULTáNEAMENTE VARIAS OPERACIONES SUPERPUESTAS
BE574121A BE574121A (fr) 1957-12-24 1958-12-22 Circuit à temps

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US (1) US2957945A (xx)
JP (1) JPS372563B1 (xx)
BE (1) BE574121A (xx)
DE (1) DE1183958B (xx)
ES (1) ES246497A1 (xx)
FR (1) FR1215377A (xx)
GB (1) GB861515A (xx)
NL (1) NL234515A (xx)

Cited By (6)

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Publication number Priority date Publication date Assignee Title
US3092808A (en) * 1959-05-18 1963-06-04 Acf Ind Inc Continuously variable digital delay line
US3241067A (en) * 1961-04-21 1966-03-15 Bell Telephone Labor Inc Synchronization of decoder systems based on message wave statistics
DE1219983B (de) * 1963-04-24 1966-06-30 Licentia Gmbh Schaltungsanordnung zur einstellbaren Verzoegerung eines Signals unter Verwendung eines Vorwaerts-Binaer-Zaehlers
US3921133A (en) * 1970-12-07 1975-11-18 Honeywell Inf Systems Controllable timing device for signalling the end of an interval
US4220990A (en) * 1978-09-25 1980-09-02 Bell Telephone Laboratories, Incorporated Peripheral processor multifunction timer for data processing systems
DE3102782A1 (de) * 1980-01-29 1982-01-28 Nippon Hoso Kyokai, Tokyo Schaltung zum verzoegern der impulse einer impulsfolge in einem festen verhaeltnis

Families Citing this family (1)

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Publication number Priority date Publication date Assignee Title
FR2604270B1 (fr) * 1986-09-22 1991-10-18 Jutand Francis Additionneur binaire comportant un operande fixe, et multiplieur binaire parallele-serie comprenant un tel additionneur

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US2518405A (en) * 1946-11-18 1950-08-08 Hendrik C A Van Duuren Signal storing and code converting radio telegraph system
US2541932A (en) * 1948-05-19 1951-02-13 Bell Telephone Labor Inc Multiplex speech interpolation system
US2577141A (en) * 1948-06-10 1951-12-04 Eckert Mauchly Comp Corp Data translating apparatus
US2640872A (en) * 1948-04-30 1953-06-02 Int Standard Electric Corp Telecommunication exchange system
US2669706A (en) * 1950-05-09 1954-02-16 Bell Telephone Labor Inc Code selector
US2674733A (en) * 1952-12-02 1954-04-06 Hughes Tool Co Electronic sorting system
US2692303A (en) * 1950-12-19 1954-10-19 Bell Telephone Labor Inc Speech interpolated communication system
US2727094A (en) * 1950-05-17 1955-12-13 Post Office Electrically operating selecting systems
US2744955A (en) * 1953-08-24 1956-05-08 Rca Corp Reversible electronic code translators
US2779933A (en) * 1950-03-29 1957-01-29 Itt Complex pulse communication system
US2827623A (en) * 1955-01-21 1958-03-18 Ernest F Ainsworth Magnetic tape inscriber-outscriber

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Publication number Priority date Publication date Assignee Title
US2518405A (en) * 1946-11-18 1950-08-08 Hendrik C A Van Duuren Signal storing and code converting radio telegraph system
US2640872A (en) * 1948-04-30 1953-06-02 Int Standard Electric Corp Telecommunication exchange system
US2541932A (en) * 1948-05-19 1951-02-13 Bell Telephone Labor Inc Multiplex speech interpolation system
US2577141A (en) * 1948-06-10 1951-12-04 Eckert Mauchly Comp Corp Data translating apparatus
US2779933A (en) * 1950-03-29 1957-01-29 Itt Complex pulse communication system
US2669706A (en) * 1950-05-09 1954-02-16 Bell Telephone Labor Inc Code selector
US2727094A (en) * 1950-05-17 1955-12-13 Post Office Electrically operating selecting systems
US2692303A (en) * 1950-12-19 1954-10-19 Bell Telephone Labor Inc Speech interpolated communication system
US2674733A (en) * 1952-12-02 1954-04-06 Hughes Tool Co Electronic sorting system
US2744955A (en) * 1953-08-24 1956-05-08 Rca Corp Reversible electronic code translators
US2827623A (en) * 1955-01-21 1958-03-18 Ernest F Ainsworth Magnetic tape inscriber-outscriber

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3092808A (en) * 1959-05-18 1963-06-04 Acf Ind Inc Continuously variable digital delay line
US3241067A (en) * 1961-04-21 1966-03-15 Bell Telephone Labor Inc Synchronization of decoder systems based on message wave statistics
DE1219983B (de) * 1963-04-24 1966-06-30 Licentia Gmbh Schaltungsanordnung zur einstellbaren Verzoegerung eines Signals unter Verwendung eines Vorwaerts-Binaer-Zaehlers
US3921133A (en) * 1970-12-07 1975-11-18 Honeywell Inf Systems Controllable timing device for signalling the end of an interval
US4220990A (en) * 1978-09-25 1980-09-02 Bell Telephone Laboratories, Incorporated Peripheral processor multifunction timer for data processing systems
DE3102782A1 (de) * 1980-01-29 1982-01-28 Nippon Hoso Kyokai, Tokyo Schaltung zum verzoegern der impulse einer impulsfolge in einem festen verhaeltnis

Also Published As

Publication number Publication date
NL234515A (xx)
ES246497A1 (es) 1959-06-01
GB861515A (en) 1961-02-22
BE574121A (fr) 1959-04-16
DE1183958B (de) 1964-12-23
FR1215377A (fr) 1960-04-19
JPS372563B1 (xx) 1962-05-24

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