JPS372563B1 - - Google Patents

Info

Publication number
JPS372563B1
JPS372563B1 JP3313758A JP3313758A JPS372563B1 JP S372563 B1 JPS372563 B1 JP S372563B1 JP 3313758 A JP3313758 A JP 3313758A JP 3313758 A JP3313758 A JP 3313758A JP S372563 B1 JPS372563 B1 JP S372563B1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3313758A
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS372563B1 publication Critical patent/JPS372563B1/ja
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50Adding; Subtracting
    • G06F7/505Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/5055Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination in which one operand is a constant, i.e. incrementers or decrementers
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/17Time-division multiplex systems in which the transmission channel allotted to a first user may be taken away and re-allotted to a second user if the first user becomes inactive, e.g. TASI
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/24Time-division multiplex systems in which the allocation is indicated by an address the different channels being transmitted sequentially
JP3313758A 1957-12-24 1958-11-20 Pending JPS372563B1 (xx)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US704927A US2957945A (en) 1957-12-24 1957-12-24 Timing circuit

Publications (1)

Publication Number Publication Date
JPS372563B1 true JPS372563B1 (xx) 1962-05-24

Family

ID=24831408

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3313758A Pending JPS372563B1 (xx) 1957-12-24 1958-11-20

Country Status (8)

Country Link
US (1) US2957945A (xx)
JP (1) JPS372563B1 (xx)
BE (1) BE574121A (xx)
DE (1) DE1183958B (xx)
ES (1) ES246497A1 (xx)
FR (1) FR1215377A (xx)
GB (1) GB861515A (xx)
NL (1) NL234515A (xx)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3092808A (en) * 1959-05-18 1963-06-04 Acf Ind Inc Continuously variable digital delay line
US3241067A (en) * 1961-04-21 1966-03-15 Bell Telephone Labor Inc Synchronization of decoder systems based on message wave statistics
DE1219983B (de) * 1963-04-24 1966-06-30 Licentia Gmbh Schaltungsanordnung zur einstellbaren Verzoegerung eines Signals unter Verwendung eines Vorwaerts-Binaer-Zaehlers
US3921133A (en) * 1970-12-07 1975-11-18 Honeywell Inf Systems Controllable timing device for signalling the end of an interval
US4220990A (en) * 1978-09-25 1980-09-02 Bell Telephone Laboratories, Incorporated Peripheral processor multifunction timer for data processing systems
JPS56106421A (en) * 1980-01-29 1981-08-24 Nippon Hoso Kyokai <Nhk> Constant ratio delay circuit
FR2604270B1 (fr) * 1986-09-22 1991-10-18 Jutand Francis Additionneur binaire comportant un operande fixe, et multiplieur binaire parallele-serie comprenant un tel additionneur

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2518405A (en) * 1946-11-18 1950-08-08 Hendrik C A Van Duuren Signal storing and code converting radio telegraph system
GB692412A (en) * 1948-04-30 1953-06-03 Standard Telephones Cables Ltd Improvements in or relating to telecommunication exchange systems
US2541932A (en) * 1948-05-19 1951-02-13 Bell Telephone Labor Inc Multiplex speech interpolation system
US2577141A (en) * 1948-06-10 1951-12-04 Eckert Mauchly Comp Corp Data translating apparatus
US2779933A (en) * 1950-03-29 1957-01-29 Itt Complex pulse communication system
US2669706A (en) * 1950-05-09 1954-02-16 Bell Telephone Labor Inc Code selector
NL87832C (xx) * 1950-05-17
US2692303A (en) * 1950-12-19 1954-10-19 Bell Telephone Labor Inc Speech interpolated communication system
US2674733A (en) * 1952-12-02 1954-04-06 Hughes Tool Co Electronic sorting system
US2744955A (en) * 1953-08-24 1956-05-08 Rca Corp Reversible electronic code translators
US2827623A (en) * 1955-01-21 1958-03-18 Ernest F Ainsworth Magnetic tape inscriber-outscriber

Also Published As

Publication number Publication date
NL234515A (xx)
ES246497A1 (es) 1959-06-01
GB861515A (en) 1961-02-22
BE574121A (fr) 1959-04-16
DE1183958B (de) 1964-12-23
FR1215377A (fr) 1960-04-19
US2957945A (en) 1960-10-25

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