US20230377124A1 - Exposed pad integrated circuit package - Google Patents

Exposed pad integrated circuit package Download PDF

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US20230377124A1
US20230377124A1 US18/366,111 US202318366111A US2023377124A1 US 20230377124 A1 US20230377124 A1 US 20230377124A1 US 202318366111 A US202318366111 A US 202318366111A US 2023377124 A1 US2023377124 A1 US 2023377124A1
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Prior art keywords
package
flange
thermal pad
pad
solder
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Pending
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US18/366,111
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Reynaldo Corpuz Javier
Alok Kumar Lohia
Andy Quang Tran
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Texas Instruments Inc
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Texas Instruments Inc
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Priority to US18/366,111 priority Critical patent/US20230377124A1/en
Publication of US20230377124A1 publication Critical patent/US20230377124A1/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/0002—Inspection of images, e.g. flaw detection
    • G06T7/0004—Industrial image inspection
    • G06T7/0008—Industrial image inspection checking presence/absence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/4809—Loop shape
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10689—Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10969—Metallic case or integral heatsink of component electrically connected to a pad on PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components

Abstract

An IC assembly including an exposed pad integrated circuit (“IC”) package having a thermal pad with a top surface and a bottom surface and with at least one peripheral surface portion extending transversely of and continuous with the bottom surface. The bottom surface and the at least one peripheral surface are exposed through a layer of mold compound. Also, methods of making an exposed pad integrated circuit (“IC”) package assembly. One method includes optically inspecting a solder bond bonding a thermal pad of an exposed pad IC package to a printed circuit board. Another method includes wave soldering an exposed pad of an IC package to a printed circuit board.

Description

  • This application is a Continuation of U.S. application Ser. No. 17/544,896, filed Dec. 7, 2021, which is a Division of U.S. application Ser. No. 14/671,727, filed Mar. 27, 2015, the contents of each of which are herein incorporated by reference in its entirety.
    • BACKGROUND
  • Integrated circuit (“IC”) packages are often surface mounted on printed circuit (“PC”) boards or other electrical connection boards. The IC packages typically have components encased in a layer of protective mold compound. Many modern IC packages have internal components, such as IC dies, that generate significant amounts of heat. One way of dissipating heat generated by a die is to mount the die on one surface of a thermal pad that has the opposite surface exposed through the protective mold layer. This exposed surface of the thermal pad is then attached to a metal layer plated on a PC board. Heat from the die is conducted through the thermal pad and into the PC board where it dissipates.
    • SUMMARY
  • This specification discloses an IC assembly of an integrated circuit (“IC”) package. The IC package includes a thermal pad having a top surface and a bottom surface and at least one peripheral surface portion extending transversely of and continuously with the bottom surface. The IC package also includes a layer of mold compound through which the bottom surface and the at least one peripheral surface are exposed.
  • Also disclosed are example embodiments of methods of: making an exposed pad integrated circuit (“IC”) package assembly; making an electrical assembly; and inspecting a solder bond bonding a thermal pad of an exposed pad IC package to a printed circuit board.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a bottom isometric view of a prior art exposed pad integrated circuit (“IC”) him package.
  • FIG. 2 is a cross-sectional elevation view of the prior art integrated circuit package of FIG. 1 .
  • FIG. 3 is a top isometric view of the thermal pad and leads of the integrated circuit package of FIG. 1 .
  • FIG. 4 is a detail cross-sectional side elevation view of the prior art integrated circuit package of FIG. 1 solder bonded to a printed circuit (“PC”) board.
  • FIG. 5 is a top isometric view of one example embodiment of an exposed pad integrated circuit package.
  • FIG. 6 is a bottom plan view of the integrated circuit package of FIG. 5 .
  • FIG. 7 is a top isometric view of the thermal pad and leads of the integrated circuit package of FIG. 5 .
  • FIG. 8 is a detail cross-sectional side elevation view of the integrated circuit package of FIG. 5 .
  • FIG. 9 is a top plan view of a PC board.
  • FIG. 10 is a detail cross-sectional side elevation view of the integrated circuit package of FIG. 5 solder bonded to a printed circuit board.
  • FIG. 11 is a top isometric view of another example embodiment of an exposed pad integrated circuit package.
  • FIG. 12 is a bottom plan view of the integrated circuit package of FIG. 11 .
  • FIG. 13 is a top isometric view of the thermal pad and leads of the integrated circuit package of FIG. 11 .
  • FIG. 14 is a detail cross-sectional side elevation view of the integrated circuit package of FIG. 11 solder bonded to a PC board.
  • FIG. 15 is a flowchart of an example embodiment of a method of making an exposed pad integrated circuit package.
  • FIG. 16 is a flowchart of an example embodiment of a method of making an electrical assembly.
  • FIG. 17 is a flowchart of an example embodiment of a method of inspecting a solder bond that bonds a thermal pad of an exposed pad IC package to a printed circuit board.
    •  DETAILED DESCRIPTION
  • FIG. 1 is a bottom isometric view of a prior art exposed pad integrated circuit package 10 and FIG. 2 is a cross-sectional elevation view thereof. FIG. 3 is a top isometric view of a thermal pad 12 and leads 18 of the integrated circuit package of FIG. 1 . As shown in FIGS. 1-3 , the exposed pad integrated circuit package 10 has a thermal pad 12 with a top surface 14, a bottom surface 16, front and rear edges 11, 13 and lateral side edges 15, 17. A plurality of leads 18 extend outwardly from a position near the lateral sides of the thermal pad 12. A die 20 having a top surface 22 and a bottom surface 24 is bonded by a solder layer 28 to the top surface 14 of the thermal pad 12. Bond wires 26 connect proximal ends of the leads 18 to electrical contacts (not shown) on the top surface 22 of the die 20. In some embodiments the die 20 also has a contact surface on its bottom surface that is electrically connected to the thermal pad 12 by the solder layer 28.
  • Front and rear tie bars 30 each have proximal ends 32 attached to the thermal pad 12 and have distal ends 34, which project forwardly and rearwardly, respectively. The thermal pad 12, leads 18, and bond wires 26 are encapsulated in a block of mold compound 40. The block of mold compound 40 has a top surface 42, a bottom surface 44, lateral side surfaces 46, 48, a front surface 50, and a rear surface (not shown). A portion of each lead 18 projects laterally outwardly from a lateral side 46, 48 of the mold compound block 40. A terminal end of each distal end 34 of an associated tie bar 30 is flush with a corresponding front 50 or rear surface (not shown) of the mold compound block 40.
  • FIG. 4 is a detail cross-sectional side elevation view of the integrated circuit package of FIGS. 1-3 solder bonded to a printed circuit (“PC”) board 60. The printed circuit board 60 has a top surface 62, which includes metal surface portions 64, etc. The bottom surface 16 of the thermal pad 12 is bonded to the metal surface portion 64 by a layer of solder 70 having a front edge 72. Because the solder layer 70 is covered by the IC package 10 it is not possible to visually inspect the solder layer 70. Thus, if the solder layer 70 is inspected at all, it is done by x-ray. X-ray inspection of solder joints is more expensive than visual inspection and is considerably less convenient.
  • The inventors have developed new exposed pad IC packages, e.g., packages 110 and 210 shown in FIGS. 5 and 11 , which enable optical inspection of the solder bond between an IC package and associated PC board or other electrical substrate on which it is mounted.
  • FIGS. 5 and 6 are top isometric and bottom plan views of an example embodiment of an exposed pad integrated circuit package 110. FIG. 7 is a top isometric view of the thermal pad and leads of the integrated circuit package 110. As shown by FIGS. 5-7 , the IC package 110 is encased in a block of mold compound 112 with top and bottom surfaces 111, 113 and mirror image front and back surfaces 114 and mirror image lateral side surfaces 115. A plurality of leads 116 project laterally from the lateral sidewall surfaces 115 of the mold compound block 112. Package 110 has a thermal pad 118 with a top surface 120 and an exposed bottom surface 121. Thermal pad 118 has an upwardly extending front flange 122 with an exposed front surface 123. The thermal pad 118 may also have an upwardly extending rear flange 124 having an exposed rear surface 125, FIG. 6 .
  • In the embodiment illustrated in FIGS. 5 and 6 , tie bars 132, 134 are integrally formed with and extend along the lateral sides of the thermal pad 118. As best shown in FIG. 5 , these tie bars 132, 134 may project longitudinally outwardly of the exposed surfaces of flanges 122 and 124 and thus project longitudinally outwardly from the front and rear faces of the compound block 112.
  • FIG. 8 is a detail cross-sectional side elevation view of the integrated circuit package 110. As shown by FIG. 8 , a die 130 having a top surface 131 and a bottom surface 133 is bonded by a solder layer 135 to the top surface 120 of the thermal pad 118. Bond wires 139 connect proximal ends of the leads 116 to electrical contacts on the top surface 131 of the die 130. In some embodiments the die 130 also has a contact surface on its bottom surface that is electrically connected to the thermal pad 118 by the solder layer 135.
  • FIG. 9 is a top plan view of a PC board 140 on which the integrated circuit package 110 is mounted. A top surface 142 of the PC board 140 has a metal pattern thereon including a large central metal pad portion 144 that corresponds in length and width to the thermal pad 118 of the IC package 110. The central metal pad portion 144 is designed to be solder bonded to the thermal pad 118 of the IC package 110. The top surface 142 also has a plurality of smaller pad portions 146, which are adapted to be attached to the leads 116. The front and rear end portions 149, 150 of the central metal pad portion 144 may extend longitudinally beyond the outermost smaller pad portions 146.
  • FIG. 10 is a detail cross-sectional side elevation view of the integrated circuit package of FIG. 5 solder bonded to the printed circuit board 140. A solder layer 147 bonds the PC board pad surface 144 to the bottom surface 121 of the thermal pad 118. A solder fillet 148 is formed at the forward end of the solder layer 147 where the solder has wicked up the front surface 123 of the front flange 122. This solder fillet 148 is not visually blocked or obscured by the IC package 110 and is thus easily optically inspected by eye or a machine vision system. The configuration at the rear portion of the PC board/IC package assembly may be identical to that of the front portion and is thus also easily optically inspected.
  • FIGS. 11 and 12 are top isometric and bottom plan views of an exposed pad integrated circuit package 210 of another embodiment. FIG. 13 is a top isometric view of the thermal pad and leads of the integrated circuit package of FIG. 5 . As shown by FIGS. 11-13 the exposed pad IC package 210 comprises a mold compound block 212 having lateral surfaces 213 from which laterally extending leads 216 project.
  • A thermal pad 218 has a top surface 220 and a bottom surface 221. The bottom surface 221 is exposed and flush (coplanar) with a bottom surface 214 of the mold compound block 212. In other embodiments the bottom surfaces 221 and 214 are not flush. Thermal pad 218 has an upwardly extending front flange 222 having exposed front surface 223 that is flush with a front surface 215 of the mold compound block 212. An exposed rear flange 224 has a rear surface 225 that is flush with the rear surface of the mold compound block 212.
  • A forwardly projecting tie bar 232 is integrally formed on a top edge of the front flange 222. This tie bar may project forwardly from the front flange and thus projects outwardly with respect to the front surface 215 of the mold compound block 212, as best shown in FIG. 11 . A rearwardly projecting tie bar 234 integrally formed on a top edge of rear flange 224 projects from a rear surface 225 of the mold compound block 212.
  • FIG. 14 is a detail cross-sectional side elevation view of the integrated circuit package 210 solder bonded to the printed circuit board 240, which may be identical to PC board 140 described with reference to FIG. 9 . A solder layer 246 bonds a PC board central pad surface 244 to the bottom surface 221 of the thermal pad 218. A solder fillet 248 is formed at the forward end of the solder layer 246 where the solder has wicked up the front surface 223 of the front flange 222. This solder fillet 248 is not visually blocked or obscured by the IC package 110 and is thus easily optically inspected. The configuration at the rear portion of the PC board/IC package assembly may be identical to that of the front portion and is thus also easily optically inspected.
  • The manner in which the exposed pad IC packages 110 and 210 are manufactured may be essentially identical to the manner in which a conventional exposed pad IC package 10 is manufactured, except for the step of creating forward and rear solder wettable metal flange surfaces 223, 225, which are exposed through the front and rear surfaces of a mold compound block 212.
  • The manner in which the packages 110 and 210 are solder attached to a PC board or other electrical substrate with conventional reflow soldering may be similar to the attachment process for a conventional exposed pad IC package 10. As with the prior art process the PC board has a layer of solder paste applied to the surface pattern thereof that is to be attached to the package 110 or 210. The IC package 110 or 210 is then placed with the thermal pad thereof in contact with the solder paste and the assembly is moved into a reflow oven where the solder reflows and bonds the package 110 or 210 to the PC board. A significant difference is that when attaching the new packages 110 and 210 a solder fillet forms and wets the front and/or rear edge of the thermal pad and the solder fillet is visible. With the prior art attachment method and structure there is no visible solder fillet in the solder layer that attaches the thermal pad to the PC board.
  • The manner in which the exposed pad packages such as 110 and 210 are solder attached to a PC board or other electrical substrate by wave soldering cannot be performed with a conventional exposed pad package. For wave soldering to work there must be an exposed thermal pad side surface portion (front and/or rear). The solder is deposited at this exposed portion and then wicks underneath the thermal pad, soldering it to the PC board. With a conventional package 10 there is no such exposed thermal pad side surface. Thus, the inventors new exposed pad package configuration makes possible wave soldering attachment of an exposed pad IC package to a PC board.
  • In a wave soldering operation to attach an integrated circuit package, e.g., 110, to a PC board, e.g. 140 the bottom surface 113 of the mold compound block 112 is attached to the top surface of the PC board 140 by an adhesive (not shown). The adhesive holds the integrated circuit package 110 in place on the PC board 140 as the PC board is moved through a wave soldering machine. Within the wave soldering machine (not shown), molten solder is pumped to form a standing wave in a molten solder tank. The PC board 140 moved over the solder wave, which contacts the components of the integrated circuit package 110 that are glued to the PC board. The molten solder is wicked between the metal surfaces of the leads 116 of the integrated circuit package and the metal pad surfaces 146 on the PC board 140. The solder is also wicked by capillary action between the bottom surface 121 of the thermal pad 118 of the IC package and the top metal surface of central metal pad portion 144 of the PC board, forming a solder joint therebetween.
  • FIG. 15 illustrates a method of making an exposed pad integrated circuit package. The method includes, as shown at block 401, attaching a die to a top surface of a thermal pad and, as shown at block 402, leaving at least a portion of at least one transversely extending side portion of the thermal pad exposed during molding.
  • FIG. 16 illustrates a method of making an electrical assembly. The method includes, as shown at block 421, providing an exposed pad integrated circuit (“IC”) package and a printed circuit board. The method also includes, as shown at block 422, wave soldering an exposed surface of an exposed thermal pad of the IC package to the printed circuit board.
  • FIG. 17 illustrates a method of inspecting a solder bond bonding a thermal pad of an exposed pad IC package to a printed circuit board. The method includes, as shown at block 431, providing an exposed pad IC package having a thermal pad bonded to a printed circuit board. The method also includes, as shown at block 432, optically inspecting the solder bond.
  • Certain embodiments of exposed pad IC packages, which make possible visual inspection of a solder layer that attaches an exposed thermal pad of the package to an electrical substrate, have been expressly described in detail herein, along with associated methodology. Alternative embodiments of such exposed pad IC packages and associated methodology will occur to those skilled in the art after reading this disclosure. It is intended for the appended claims to be construed broadly to cover all such alternative embodiments, except as limited by the prior art.

Claims (20)

What is claimed is:
1. An integrated circuit (“IC”) package, comprising:
a thermal pad having a top surface and a bottom surface opposite the top surface;
a flange extending transversely of and continuous with the thermal pad, the flange having a surface continuous with the bottom surface of the thermal pad; and
a mold compound through which the bottom surface of the thermal pad and the surface of the flange are exposed, wherein:
the bottom surface of the thermal pad is flush with a bottom surface of the mold compound; and
the surface of the flange is flush with a side surface of the mold compound.
2. The IC package of claim 1, wherein the surface of the flange is substantially perpendicular to the bottom surface.
3. The IC package of claim 1, wherein the surface of the flange is connected to the bottom surface by an arcuate surface portion.
4. The IC package of claim 1, further comprising:
a plurality of leads extending laterally outwardly of first and second lateral side edges of the thermal pad.
5. The IC package of claim 4, further comprising:
a die attached to the top surface of the thermal pad, the die having electrical contacts connected to the plurality of leads.
6. The IC package of claim 1, wherein the flange extends a portion of a full width of the thermal pad.
7. The IC package of claim 6, further comprising:
a first tie bar projected past the surface of the flange; and
a second tie bar projected past the surface of the flange, wherein the flange is positioned between the first tie bar and the second tie bar.
8. The IC package of claim 7, wherein the first and second tie bars are integrally formed with and extended along lateral sides of the thermal pad.
9. The IC package of claim 1, wherein the flange extends a full width of the thermal pad.
10. The IC package of claim 9, further comprising:
a tie bar projected past the surface of the flange, the tie bar integrally formed on a top edge of the flange.
11. The IC package of claim 10, wherein the tie bar is positioned at a center portion of the top edge of the flange.
12. The IC package of claim 1, wherein the flange is a first flange, the IC package further comprising:
a second flange extending transversely of and continuous with the thermal pad, wherein the second flange has a second surface continuous with the bottom surface of the thermal pad, the second surface being exposed through the mold compound and flush with a second side surface of the mold compound opposite the side surface.
13. An integrated circuit (“IC”) assembly, comprising:
an IC package including:
a thermal pad having a thermal pad surface exposed through and coplanar with a bottom surface of a mold compound of the IC package; and
a flange extending transversely of and continuous with the thermal pad, the flange having a flange surface that is continuous with the thermal pad surface, and is exposed through and coplanar with a side surface of the mold compound;
a substrate including a metal pad on a top surface of the substrate; and
a solder layer bonding the thermal pad surface and a portion of the flange surface to the metal pad of the substrate.
14. The IC assembly of claim 13, wherein the solder layer includes a solder fillet corresponding to a solder of the solder layer wicked up to the portion of the flange surface.
15. The IC assembly of claim 14, wherein the solder fillet is visible from an external viewpoint of the IC assembly.
16. The IC assembly of claim 13, wherein the metal pad of the substrate has a length and a width corresponding to the thermal pad.
17. The IC assembly of claim 13, wherein the substrate includes a printed circuit board.
18. The IC assembly of claim 13, wherein the solder layer is applied by wave solder or is a layer of reflowed solder.
19. The IC assembly of claim 13, further comprising:
a plurality of leads of the IC package extending laterally outwardly of first and second lateral side edges of the thermal pad, wherein the plurality of leads includes outer terminal end portions having generally flat bottom surfaces.
20. The IC assembly of claim 19, further comprising:
a die attached to a die-attach surface of the thermal pad opposite the thermal pad surface, the die having electrical contacts connected to the plurality of leads.
US18/366,111 2015-03-27 2023-08-07 Exposed pad integrated circuit package Pending US20230377124A1 (en)

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Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11354705A (en) * 1998-06-04 1999-12-24 Toshiba Corp Semiconductor device and its manufacture
JP2002064265A (en) * 2000-08-18 2002-02-28 Toshiba It & Control Systems Corp Bga-mounting method
US6348726B1 (en) * 2001-01-18 2002-02-19 National Semiconductor Corporation Multi row leadless leadframe package
US6900527B1 (en) * 2001-09-19 2005-05-31 Amkor Technology, Inc. Lead-frame method and assembly for interconnecting circuits within a circuit module
GB2419483B (en) 2004-09-17 2008-12-24 Motorola Inc Demodulator for use in wireless communucations and receiver, method and terminal using it
JP4860939B2 (en) * 2005-04-08 2012-01-25 ローム株式会社 Semiconductor device
JP4739851B2 (en) * 2005-07-29 2011-08-03 スタンレー電気株式会社 Surface mount semiconductor device
US7932587B2 (en) * 2007-09-07 2011-04-26 Infineon Technologies Ag Singulated semiconductor package
US20100133693A1 (en) * 2008-12-03 2010-06-03 Texas Instruments Incorporated Semiconductor Package Leads Having Grooved Contact Areas
US20140151883A1 (en) * 2012-12-03 2014-06-05 Semiconductor Components Industries, Llc Method for manufacturing a semiconductor component and structure therefor
JP5383611B2 (en) * 2010-01-29 2014-01-08 株式会社東芝 LED package
US20120306065A1 (en) * 2011-06-02 2012-12-06 Texas Instruments Incorporated Semiconductor package with pre-soldered grooves in leads
JP5706254B2 (en) * 2011-07-05 2015-04-22 株式会社東芝 Semiconductor device
JP2013161903A (en) * 2012-02-03 2013-08-19 Toshiba Corp Semiconductor device and method of manufacturing the same
JP6396633B2 (en) * 2012-02-15 2018-09-26 サターン ライセンシング エルエルシーＳａｔｕｒｎ Ｌｉｃｅｎｓｉｎｇ ＬＬＣ Circuit board
US8716066B2 (en) * 2012-07-31 2014-05-06 Freescale Semiconductor, Inc. Method for plating a semiconductor package lead
US8535982B1 (en) * 2012-11-29 2013-09-17 Freescale Semiconductor, Inc. Providing an automatic optical inspection feature for solder joints on semiconductor packages
US20140151865A1 (en) * 2012-11-30 2014-06-05 Thomas H. Koschmieder Semiconductor device packages providing enhanced exposed toe fillets
US20140177764A1 (en) 2012-12-20 2014-06-26 Thomas Tetzlaff Low power packet detection employing single adc
JP5961109B2 (en) 2012-12-26 2016-08-02 パナソニック株式会社 Receiver and frequency error correction method
US9219019B2 (en) * 2014-03-17 2015-12-22 Texas Instruments Incorporated Packaged semiconductor devices having solderable lead surfaces exposed by grooves in package compound
EP3128539B1 (en) * 2014-03-27 2020-01-08 Renesas Electronics Corporation Semiconductor device manufacturing method and semiconductor device
US10382304B2 (en) 2015-03-31 2019-08-13 Motorola Mobility Llc Methods and apparatus for controlling multiple-input and multiple-output operation in a communication device based on quality of service
US9980168B2 (en) 2015-06-25 2018-05-22 Intel Corporation Apparatus and methods for power-saving low intermediate frequency receiver

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US20160286652A1 (en) 2016-09-29
US20220092767A1 (en) 2022-03-24
US11769247B2 (en) 2023-09-26

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