US20230301114A1 - Ferroelectric devices and methods of forming the same - Google Patents

Ferroelectric devices and methods of forming the same Download PDF

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US20230301114A1
US20230301114A1 US17/850,429 US202217850429A US2023301114A1 US 20230301114 A1 US20230301114 A1 US 20230301114A1 US 202217850429 A US202217850429 A US 202217850429A US 2023301114 A1 US2023301114 A1 US 2023301114A1
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layer
hafnium dioxide
doped hafnium
dioxide layer
ferroelectric
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Georgios Vellianitis
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. reassignment TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: VELLIANITIS, GEORGIOS
Priority to TW112100737A priority patent/TWI859692B/zh
Priority to JP2023017216A priority patent/JP7704791B2/ja
Priority to CN202310115882.5A priority patent/CN116419575A/zh
Publication of US20230301114A1 publication Critical patent/US20230301114A1/en
Priority to JP2025107900A priority patent/JP2025143329A/ja
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H01L27/11507—
    • H—ELECTRICITY
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • H01L23/5283—
    • H01L29/66545—
    • H01L29/6684—
    • H01L29/78391—
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0415—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having ferroelectric gate insulators
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/701—IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
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    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/033—Manufacture or treatment of data-storage electrodes comprising ferroelectric layers
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/689—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having ferroelectric layers
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6518—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by introduction of substances into an already-existing insulating layer
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6544—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials to change the morphology of the insulating materials, e.g. transformation of an amorphous layer into a crystalline layer
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6938—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides
    • H10P14/6939—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal
    • H10P14/69392—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal the material containing hafnium, e.g. HfO2
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6938—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides
    • H10P14/6939—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal
    • H10P14/69397—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal the material containing two or more metal elements
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/40—Ion implantation into wafers, substrates or parts of devices into insulating materials
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections

Definitions

  • Ferroelectric memory devices are one promising candidate for a next generation non-volatile memory technology.
  • ferroelectric memory devices include capacitor based ferroelectric random-access memory (FeRAM) and ferroelectric field effect transistor (FeFET).
  • FeRAM and FeFET devices provide for many advantages, including a fast write time, high endurance, low power consumption, and low susceptibility to damage from radiation.
  • FIG. 1 A is a circuit diagram of a FeRAM cell, in accordance with some embodiments.
  • FIG. 1 B is a cross-sectional side view of the FeRAM cell of FIG. 1 A , in accordance with some embodiments.
  • FIG. 2 A is a circuit diagram of a FeFET cell, in accordance with some embodiments.
  • FIG. 2 B is a cross-sectional side view of the FeFET cell of FIG. 2 A , in accordance with some embodiments.
  • FIG. 3 is a cross-sectional side view of a ferroelectric layer formed on a polycrystalline metal layer, in accordance with some embodiments.
  • FIG. 4 is a cross-sectional side view of a ferroelectric layer formed on a monocrystalline metal layer, in accordance with some embodiments.
  • FIG. 5 illustrates crystal structures of the monocrystalline metal layer and the ferroelectric layer of FIG. 4 , in accordance with some embodiments.
  • FIGS. 6 A and 6 B are cross-sectional side views of a capacitor, in accordance with some embodiments.
  • FIGS. 7 A- 7 C illustrates various stages of forming a ferroelectric layer, in accordance with some embodiments.
  • FIGS. 8 A- 8 C illustrates various stages of forming a ferroelectric layer, in accordance with some embodiments.
  • FIGS. 9 A- 9 G are cross-sectional side views of various manufacturing stages of a semiconductor device structure, in accordance with some embodiments.
  • FIG. 10 is the semiconductor device structure of FIG. 9 G , in accordance with alternative embodiments.
  • FIGS. 11 A- 11 F are cross-sectional side views of various manufacturing stages of a transistor, in accordance with some embodiments.
  • FIG. 12 is the semiconductor device structure of FIG. 9 G , in accordance with alternative embodiments.
  • FIG. 13 is the semiconductor device structure of FIG. 12 , in accordance with alternative embodiments.
  • first and second features are formed in direct contact
  • additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
  • present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
  • spatially relative terms such as “beneath,” “below,” “lower,” “above,” “over,” “on,” “top,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
  • the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
  • the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
  • FIG. 1 A is a circuit diagram of a FeRAM cell 100 , in accordance with some embodiments.
  • the FeRAM cell 100 includes a transistor 104 and a capacitor 101 .
  • the FeRAM cell 100 shown in FIG. 1 A is a one-transistor-one-capacitor (1T1C) type FeRAM cell.
  • the FeRAM cell 100 may be other type of FeRAM cell, such as two-transistor-two-capacitor (2T2C) FeRAM cell.
  • FIG. 1 B is a cross-sectional side view of the FeRAM cell 100 of FIG. 1 A , in accordance with some embodiments.
  • the FeRAM cell 100 includes the transistor 104 disposed over a substrate 102 .
  • the transistor 104 includes a drain region 104 a and a source region 104 b disposed in the substrate 102 .
  • the substrate 102 may be a semiconductor substrate, such as a silicon wafer.
  • the substrate 102 can include silicon or a compound semiconductor, such as gallium arsenide (GaAs), indium phosphide (InP), silicon germanium (SiGe), silicon carbide (SiC), other suitable semiconductor materials, and/or combinations thereof.
  • the substrate 102 may be doped with a dopant, such as an n-type dopant or a p-type dopant.
  • the drain region 104 a and the source region 104 b may be doped with a dopant, such as an n-type dopant or a p-type dopant.
  • a gate electrode 104 c is disposed over the substrate 102 between the drain region 104 a and the source region 104 b .
  • the gate electrode 104 c may include one or more layers.
  • the gate electrode 104 c may include one or more work function layers and a bulk layer.
  • the work function layer includes one or more layers of electrically conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi or TiAlC, or a multilayer of two or more of these materials.
  • the bulk layer may include an electrically conductive material, such as a metal.
  • the bulk layer includes W, Cu, Ti, Al, or Co.
  • the gate electrode 104 c may include additional layers, such as glue layer, barrier layer, capping layer, or any suitable layer. The work function layer and the additional layers may be optional.
  • a gate dielectric layer 104 d is disposed between the gate electrode 104 c and the substrate 102 .
  • the gate dielectric layer 104 d includes a dielectric material.
  • the gate dielectric layer 104 d includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 104 d may have a k value greater than about 7.0 and may include a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof.
  • the transistor 104 may be any suitable transistor, such as a planar transistor, a FinFET, or a nanostructure transistor, such as a gate-all-around (GAA) FET, a nanosheet FET, or a nanowire FET.
  • a planar transistor such as a FinFET, or a nanostructure transistor, such as a gate-all-around (GAA) FET, a nanosheet FET, or a nanowire FET.
  • GAA gate-all-around
  • the gate electrode 104 c may be electrically connected to the word line (WL), the source region 104 b is electrically connected to the bit line (BL), the drain region 104 a is electrically connected to the capacitor 101 , and the capacitor 101 is electrically connected to the drive line (DL), in some embodiments.
  • the drain region 104 a may be electrically connected to the capacitor 101 via one or more conductive lines 110 and one or more conductive vias 108 .
  • the capacitor 101 , the one or more conductive lines 110 , and the one or more conductive vias 108 may be embedded in a dielectric structure 106 .
  • the dielectric structure 106 and the features formed therein may be an interconnect structure, and the dielectric structure 106 includes a plurality of intermetal dielectric (IMD) layers.
  • IMD intermetal dielectric
  • the capacitor 101 may be a ferroelectric capacitor (FeCAP).
  • the capacitor 101 includes a first electrode 112 , a second electrode 116 , and a ferroelectric layer 114 disposed between the first electrode 112 and the second electrode 116 .
  • the ferroelectric layer 114 may be a high-k dielectric layer having dielectric constant greater than about 3.9.
  • the ferroelectric layer 114 may include a high-k dielectric such as a hafnium-based oxide material, such as hafnium dioxide (HfO 2 ). Other suitable ferroelectric dielectric material can be used.
  • the ferroelectric layer 114 can be a hafnium-based layer doped with any suitable elements, such as, for example, zirconium, aluminum, lanthanum, titanium, tantalum, silicon, yttrium, scandium, gadolinium, any other suitable element, or combinations thereof.
  • any suitable elements such as, for example, zirconium, aluminum, lanthanum, titanium, tantalum, silicon, yttrium, scandium, gadolinium, any other suitable element, or combinations thereof.
  • the ferroelectric layer 114 is a doped hafnium dioxide layer having orthorhombic crystal phase.
  • Other crystal phases, such as monoclinic or tetragonal phases, of the doped hafnium dioxide layer may not exhibit ferroelectric properties.
  • the doped hafnium dioxide layer having orthorhombic crystal phase includes oxygen atoms that can move to two different positions with an applied electric field, so the doped hafnium dioxide layer having orthorhombic crystal phase has two orthorhombic geometries. The two orthorhombic geometries have an interconversion barrier, which can be switched by applying an electric field thereto.
  • the doped hafnium dioxide layer includes zirconium dopant having a dopant concentration between about 40 mole percent to about 60 mole percent.
  • the ferroelectric layer 114 may be from Hf 0.6 Zr 0.4 O 2 to Hf 0.4 Zr 0.6 O 2 .
  • the zirconium dopant concentration is outside of the 40 mole percent to 60 mole percent range.
  • the dopant concentration may range from about 0.1 mole percent to about 15 mole percent.
  • the ferroelectric layer 114 may be from D 0.01 Hf 0.99 O 2 to D 0.15 Hf 0.5 O 2 .
  • Zirconium as a dopant can have a relatively higher dopant concentration because zirconium and hafnium have similar electronic structure, and the oxides of zirconium and hafnium may be substantially the same.
  • crystallization in the orthorhombic crystal phase generates a mixture of the two states. The orthorhombic phases are then polarized in one of the two states by application of an electric voltage.
  • doped hafnium dioxide layer as deposited is in an amorphous or partial crystalline state, and an anneal process is performed to increase the percentage of orthorhombic phase.
  • Doped hafnium dioxide layer is multi-phasic, which means it crystallizes in all available phases (monoclinic, orthorhombic, cubic, tetragonal). The greater percentage of orthorhombic phase in the ferroelectric layer 114 , the better the ferroelectric properties.
  • Ferroelectric properties of the doped hafnium dioxide layer may also depend on dopant concentration (lattice distortion facilities element movement when electrical field is applied), oxygen vacancy concentration (oxygen vacancy can help in creating the space in the lattice for the elements to move when electric field is applied), and fine balance between dopant and oxygen concentration.
  • Various embodiments of the present disclosure provide methods for forming doped hafnium dioxide layer having high percentage of orthorhombic crystal phase, such as greater than about 90 percent, for example greater than about 98 percent, or about 100 percent. The methods are described in detail in FIGS. 4 to 8 C .
  • the first electrode 112 includes an electrically conductive material, such as W, TaN, TiN, Ti, Ru, Pt, Ir, or other suitable electrically conductive material.
  • the second electrode 116 includes an electrically conductive material. In some embodiments, the second electrode 116 includes the same material as the first electrode 112 .
  • FIG. 2 A is a circuit diagram of a FeFET cell 200 , in accordance with some embodiments.
  • FIG. 2 B is a cross-sectional side view of the FeFET cell 200 of FIG. 2 A , in accordance with some embodiments.
  • the FeFET cell 200 includes a FeFET 204 disposed over a substrate 202 .
  • the substrate 202 may include the same material as the substrate 102 .
  • the FeFET 204 includes a source region 204 a and a drain region 204 b .
  • the source region 204 a and the drain region 204 b may include the same material as the source region 104 b and the drain region 104 a , respectively.
  • a gate electrode 204 c is disposed over the substrate 202 , and the gate electrode 204 c may include the same material as the gate electrode 104 c .
  • a ferroelectric layer 204 d is disposed between the gate electrode 204 c and the substrate 202 .
  • an interfacial layer (not shown) may be disposed between the ferroelectric layer 204 d and the substrate 202 .
  • the ferroelectric layer 204 d may include the same material as the ferroelectric layer 114 .
  • a dielectric structure 206 is disposed over the FeFET 204 , and the WL and BL are disposed in the dielectric structure 206 .
  • the WL is electrically connected to the gate electrode 204 c
  • the BL is electrically connected to the source region 204 a.
  • the ferroelectric layer 204 d is a doped hafnium dioxide layer. Similar to the ferroelectric layer 114 shown in FIG. 1 B , the methods described in FIGS. 4 to 8 C increases the percentage of orthorhombic crystal phase of the ferroelectric layer 204 d , which in turn improves the ferroelectric properties of the ferroelectric layer 204 d.
  • FIG. 3 is a cross-sectional side view of a ferroelectric layer 302 formed on a polycrystalline metal layer 304 , in accordance with some embodiments.
  • the polycrystalline metal layer 304 includes two or more crystal phases 304 a , 304 b , 304 c , and the ferroelectric layer 302 formed on the polycrystalline metal layer 304 is also polycrystalline.
  • the ferroelectric layer 302 may include two or more crystal phases 302 a , 302 b , 302 c , 302 d , 302 e .
  • An anneal process is performed on the ferroelectric layer 302 in order to increase the percentage of orthorhombic phase.
  • the ferroelectric layer 302 formed on a polycrystalline metal layer, such as the polycrystalline metal layer 304 may have less than 90 percent, such as less than about 50 percent, for example about 20 percent, of orthorhombic phase after the anneal process.
  • FIG. 4 is a cross-sectional side view of a ferroelectric layer 402 formed on a monocrystalline metal layer 404 , in accordance with some embodiments.
  • the monocrystalline metal layer 404 includes a single crystal phase and the ferroelectric layer 402 formed on the monocrystalline metal layer 404 also includes a single crystal phase.
  • the ferroelectric layer 402 is a doped hafnium dioxide layer, and the lattice constants (or lattice parameters) a and b of the monocrystalline metal layer 404 are substantially the same as the lattice constants a and b of the doped hafnium dioxide layer in orthorhombic phase.
  • the monocrystalline metal layer 404 may function as a seed layer for the ferroelectric layer 402 to crystalize thereon. If the lattice constants a and b of the monocrystalline metal layer 404 are substantially the same as those of the orthorhombic doped hafnium dioxide layer, the ferroelectric layer 402 formed on the monocrystalline metal layer 404 will try to match the orthorhombic crystal phase.
  • the lattice constant c of the monocrystalline metal layer 404 has little influence on the crystallization of the ferroelectric layer 402 , because the lattice constant c relates to a dimension out of the plane acting as seed.
  • the interface property of the monocrystalline metal layer 404 is more important than the thickness of the monocrystalline metal layer 404 .
  • the monocrystalline metal layer 404 has a symmetric crystal structure, and an angle between the lattice constants a and b is about 90 degrees.
  • the crystal structure of the monocrystalline metal layer 404 may be cubic, tetragonal, orthorhombic, or other suitable crystal structure.
  • the crystal structure of the monocrystalline metal layer 404 may be any suitable cubic structure, such as simple cubic, body centered, face centered, or other suitable structure.
  • the ferroelectric layer 402 deposited on the monocrystalline metal layer 404 will try to match the cubic-like hafnium dioxide lattice cell with the one from the monocrystalline metal layer 404 .
  • the lattice constant c of the ferroelectric layer 402 will tend to be larger; if the lattice constants a and b of monocrystalline metal layer 404 are larger, the lattice constant c of the ferroelectric layer 402 will be smaller; the cells of the ferroelectric layer 402 tend to retain their volume. In both cases, the ferroelectric layer 402 will tend to crystallize with lattice constants a and b matching the lattice constants a and b of the monocrystalline metal layer 404 . For mismatch greater than about 10 percent, beyond a certain physical thickness of the ferroelectric layer 402 (e.g., about 10 nm), the lattice will relax, so the layer can may be thin, such as less than about 10 nm.
  • the monocrystalline metal layer 404 is a NiAl layer.
  • the NiAl layer may have cubic crystal structure and may be formed by any suitable method, such as physical vapor deposition (PVD).
  • the nickel concentration of the NiAl may range from about 40 atomic percent to about 60 atomic percent, such as from about 40 atomic percent to about 45 atomic percent.
  • the nickel content may affect the size of the NiAl crystal and the degree of crystallinity. Lower nickel amount, such as from about 40 atomic percent to about 45 atomic percent, may lead to better matching of the orthorhombic structure. For example, in X-ray diffraction analysis (XRD), a peak appears around 31 to 32 degrees, which is close to orthorhombic peak of hafnium dioxide. At lower nickel concentration, such as less than 45 atomic percent, the peak is stronger.
  • NiAl is cubic with lattice constants a and b being equal, such as between about 0.286 nm and about 0.289 nm.
  • the lattice constants a and b of the ferroelectric layer 402 may be multiple of the lattice constants of the monocrystalline metal layer 404 , respectively.
  • FIG. 5 illustrates crystal structures of the monocrystalline metal layer and the ferroelectric layer of FIG. 4 , in accordance with some embodiments.
  • the monocrystalline metal layer 404 may be a NiAl layer having the crystal structure 502
  • the ferroelectric layer 402 may be a doped hafnium dioxide layer having the crystal structure 504 .
  • the lattice constant a of the ferroelectric layer 402 may be a multiple of the lattice constant a′ of the monocrystalline metal layer 404 .
  • the lattice constants a′ and b′ of NiAl are both about 0.286 nm, and the lattice constants a and b of the ferroelectric layer 402 may be about 0.572 nm, which is about twice lattice constants a′ and b′. With the lattice constants a and b being about 0.572 nm, the crystal structure of the ferroelectric layer 402 is substantially orthorhombic.
  • the ferroelectric layer 402 may be formed by any suitable method, such as atomic layer deposition, PVD, or chemical vapor deposition (CVD).
  • the ferroelectric layer 402 are formed on the monocrystalline metal layer 404 by ALD.
  • the ferroelectric layer 402 has a thickness ranging from about 3 nm to about 20 nm, such as from about 5 nm to about 20 nm.
  • the ferroelectric layer 402 has a thickness greater than about 20 nm or is formed by a process with a processing temperature less than about 350 degrees Celsius, such as from about 250 degrees Celsius to about 300 degrees Celsius, and an optional anneal process may be performed to increase the percentage of orthorhombic phase.
  • the anneal process may include heating the ferroelectric layer 402 to a temperature ranging from about 200 degrees Celsius to about 600 degrees Celsius in any suitable environment, such as oxygen gas, nitrogen gas, or hydrogen gas for a time duration of 1 second to about 300 seconds.
  • the process to form the ferroelectric layer 402 may be performed at elevated temperature, such as from about 200 degrees Celsius to about 600 degrees Celsius.
  • the ferroelectric layer 402 shown in FIG. 4 may have an increased orthorhombic phase, such as over 90 percent orthorhombic phase, for example over 98 percent orthorhombic phase.
  • 80 percent of the orthorhombic phase of the ferroelectric layer 402 may be horizontally aligned, which contributes to ferroelectricity.
  • the ferroelectric layer 402 includes crystal domains ranging from about 5 nm to about 20 nm, such as from about 10 nm to about 20 nm.
  • FIGS. 6 A and 6 B are cross-sectional side views of a capacitor 600 , in accordance with some embodiments.
  • the capacitor 600 includes the monocrystalline metal layer 404 as a first electrode, a metal layer 602 as the second electrode, and the ferroelectric layer 402 is disposed between the monocrystalline metal layer 404 and the metal layer 602 .
  • the metal layer 602 is a monocrystalline metal layer. The metal of the metal layer 602 may or may not be the same as the metal of the monocrystalline metal layer 404 .
  • the capacitor 600 includes the monocrystalline metal layer 404 as a first electrode, a metal layer 604 as the second electrode, and the ferroelectric layer 402 is disposed between the monocrystalline metal layer 404 and the metal layer 604 .
  • the metal layer 604 is a polycrystalline metal layer.
  • the metal of the metal layer 604 may or may not be the same as the metal of the monocrystalline metal layer 404 .
  • the metal layer 602 or the metal layer 604 does not affect the crystal structure of the ferroelectric layer 402 .
  • the optional anneal process is performed after the formation of the metal layer 602 or the metal layer 604 .
  • the capacitor 600 shown in FIGS. 6 A and 6 B may be utilized as the capacitor 101 shown in FIGS. 1 A and 1 B .
  • FIGS. 7 A to 7 C illustrates various stages of forming a ferroelectric layer 704 , in accordance with some embodiments.
  • the ferroelectric layer 704 is deposited on a layer 702 .
  • the layer 702 may be a metal layer, such as the first electrode 112 shown in FIG. 1 B , or a semiconductor layer, such as the substrate 202 shown in FIG. 2 B .
  • the layer 702 is the monocrystalline metal layer 404 shown in FIG. 4 .
  • the layer 702 is a dielectric layer, such as an interfacial layer.
  • the ferroelectric layer 704 may be a doped hafnium dioxide layer and may be formed by any suitable method, such as CVD, ALD, or PVD.
  • the ferroelectric layer 704 includes oxygen vacancies 706 .
  • the oxygen vacancies 706 of the as deposited ferroelectric layer 704 may range from about 2 percent to about 5 percent.
  • an ultra-high vacuum (UHV) anneal process is performed on the ferroelectric layer 704 to crystallize the ferroelectric layer 704 and to increase the concentration of the oxygen vacancies 706 .
  • the UHV anneal process is performed at a processing temperature ranging from about 20 degrees Celsius to about 450 degrees Celsius and a processing pressure less than 1e ⁇ 3 Torr, such as from about 1e ⁇ 8 Torr to about 1e ⁇ 3 Torr.
  • the UHV anneal process reduces the pressure outside of the ferroelectric layer 704 , so the oxygen atoms in the ferroelectric layer 704 escapes from the ferroelectric layer 704 .
  • the resulting oxygen vacancies 706 concentration is increased to about 5 percent to about 10 percent.
  • the removal of oxygen atoms, or the creation of additional oxygen vacancies, creates spaces for the atoms to move within the ferroelectric layer 704 , and increased orthorhombic phase can be obtained under the above mentioned UHV anneal process conditions compared to the conventional anneal process.
  • the percent of orthorhombic phase is not increased, but the ferroelectricity is expected to be higher due to the remaining oxygen atoms in the ferroelectric layer 704 have more room to move as a result of the UHV anneal process.
  • the ferroelectric layer 704 is crystallized with a major crystal phase being orthorhombic phase.
  • an optional anneal process is performed on the ferroelectric layer 704 to reduce oxygen vacancies 706 to improve reliability.
  • the anneal process may be performed in an oxygen gas environment at a processing temperature ranging from about 20 degrees Celsius to about 450 degrees Celsius and a processing pressure ranging from about 1 atm to about 20 atm for a time duration ranging from about 1 minute to about 5 hours.
  • the crystal phase of the ferroelectric layer 704 is substantially stable, so no phase change should be observed following the optional anneal process.
  • the concentration of the oxygen vacancies 706 is reduced to the level prior to the UHV anneal process, such as from about 2 percent to about 5 percent. With the lowered concentration of the oxygen vacancies 706 , device reliability is improved.
  • the ferroelectric layer 704 formed by the UHV anneal process has improved ferroelectricity as a result of increased percentage of orthorhombic crystal phase and/or more space for the atoms in the ferroelectric layer 704 to move.
  • the optional anneal process further improves device reliability.
  • the ferroelectric layer 704 may be utilized as the ferroelectric layer 114 in the capacitor 101 , and the UHV process and the optional anneal process may be performed prior to the formation of the second electrode 116 .
  • the layer 702 is the first electrode 112
  • the ferroelectric layer 704 is the ferroelectric layer 114 .
  • the ferroelectric layer 704 may be utilized as the ferroelectric layer 204 d in the FeFET 204 , and the UHV process and the optional anneal process may be performed prior to the formation of the gate electrode 204 c .
  • the layer 702 is the substrate 202 (or the interfacial layer formed on the substrate 202 ), and the ferroelectric layer 704 is the ferroelectric layer 204 d.
  • FIGS. 8 A to 8 C illustrates various stages of forming a ferroelectric layer 804 , in accordance with some embodiments.
  • the ferroelectric layer 804 is deposited on a layer 802 .
  • the layer 802 may include the same material as the layer 702 .
  • the ferroelectric layer 804 may be a doped hafnium dioxide layer and may be formed by any suitable method, such as CVD, ALD, or PVD.
  • the ferroelectric layer 804 includes oxygen vacancies 806 .
  • the oxygen vacancies 806 of the as deposited ferroelectric layer 804 may range from about 2 percent to about 5 percent.
  • an ion implantation process 810 is performed on the ferroelectric layer 804 to remove crystallinity from the as deposited ferroelectric layer 804 and to provide an amorphous phase in the ferroelectric layer 804 .
  • the as deposited doped hafnium dioxide layer may be partially crystallized.
  • the crystal phase of the as deposited doped hafnium dioxide layer may be mostly monoclinic, which does not exhibit ferroelectric properties.
  • the ion implantation process 810 introduces a dopant 808 , which may be different from the dopant of the doped hafnium dioxide layer, into the as deposited doped hafnium dioxide layer to displace the elements of the doped hafnium dioxide layer.
  • a dopant 808 which may be different from the dopant of the doped hafnium dioxide layer
  • the ion implantation process 810 introduces a dopant 808 , which may be different from the dopant of the doped hafnium dioxide layer, into the as deposited doped hafnium dioxide layer to displace the elements of the doped hafnium dioxide layer.
  • the crystallinity of the as deposited doped hafnium dioxide layer is removed.
  • the crystalline structures of the as deposited doped hafnium dioxide layer are destroyed by the dopant 808 from the ion implantation process 810 , and the resulting doped hafnium dioxide layer is an amorphous layer.
  • the ion implantation process 810 may be performed with an ion energy ranging from about 1 keV to about 10 keV. If the ion energy is less than about 1 keV, the monoclinic crystal structures in the as deposited doped hafnium dioxide layer are not destroyed. On the other hand, if the ion energy is greater than about 10 keV, the manufacturing cost is increased without significant advantage.
  • the dose of the ion implantation process may range from about 1e 13 /cm 2 to about leis/cm 2 .
  • the ion implantation process 810 may lead to shallow doping, such as about 10 nm or less.
  • the dopant 808 may be p-type or n-type dopants, such as phosphorous (P), arsenic (As), or boron (B).
  • the dopant 808 may be gallium (Ga), antimony (Sb), germanium (Ge), silicon (Si), or other suitable dopant.
  • the as deposited doped hafnium dioxide layer already includes a dopant, such as zirconium, aluminum, lanthanum, titanium, tantalum, silicon, yttrium, scandium, gadolinium, which may be different from the dopant 808 .
  • the ferroelectric layer 804 includes two different dopants.
  • the first dopant is formed in-situ during the deposition of the doped hafnium dioxide layer, and the second dopant is introduced into the doped hafnium dioxide layer by the ion implantation process performed after the deposition of the doped hafnium dioxide layer.
  • an anneal process is performed on the ferroelectric layer 804 to form orthorhombic phase.
  • the anneal process may be performed at a processing temperature ranging from about 20 degrees Celsius to about 550 degrees Celsius for a time duration ranging from about 1 second to about 1 hour.
  • the anneal process changes the amorphous phase to crystalline phase, specifically orthorhombic crystalline phase.
  • the ferroelectric layer 804 may include both monoclinic and orthorhombic crystalline phases after the anneal process.
  • the resulting ferroelectric layer 804 is crystalline and includes mostly orthorhombic phase.
  • the ferroelectric layer 804 may be utilized as the ferroelectric layer 114 in the capacitor 101 , the ion implantation process 810 may be performed prior to the formation of the second electrode 116 , and the anneal process may be performed prior to or after the formation of the second electrode 116 .
  • the layer 802 is the first electrode 112
  • the ferroelectric layer 804 is the ferroelectric layer 114 .
  • the ferroelectric layer 804 may be utilized as the ferroelectric layer 204 d in the FeFET 204 , the ion implantation process 810 may be performed prior to the formation of the gate electrode 204 c , and the anneal process may be performed prior to or after the formation of the gate electrode 204 c .
  • the layer 802 is the substrate 202 (or the interfacial layer formed on the substrate 202 ), and the ferroelectric layer 804 is the ferroelectric layer 204 d.
  • FIGS. 9 A- 9 G are cross-sectional side views of various manufacturing stages of a semiconductor device structure 900 , in accordance with some embodiments.
  • the semiconductor device structure 900 includes a substrate 902 and one or more transistors 904 disposed on the substrate 902 .
  • the substrate 902 may be the substrate 102
  • the transistors 904 may be the same transistor 104 shown in FIG. 1 B .
  • Each transistor 904 includes source/drain regions 906 and a gate electrode 908 , which may be the same as the drain region 104 a , the source region 104 b , and the gate electrode 104 c .
  • Conductive contacts 910 are electrically connected to the source/drain regions 906 .
  • the conductive contacts 910 may be disposed in an interlayer dielectric (ILD) layer 912 .
  • An interconnect structure 914 is disposed over the transistors 904 .
  • the interconnect structure 914 may be the dielectric structure 106 shown in FIG. 1 B .
  • Conductive lines 916 and conductive vias 918 are formed in the interconnect structure 914 .
  • the conductive lines 916 and the conductive vias 918 may be the conductive lines 110 and conductive vias 108 shown in FIG. 1 B , respectively.
  • a conductive layer 920 is formed on the conductive vias 918 that are electrically connected to one of the source/drain regions 906 of each transistor 904 .
  • the conductive layer 920 may include the same material as the first electrode 112 shown in FIG. 1 B .
  • the conductive layer 920 is a monocrystalline metal layer such as the monocrystalline metal layer 404 shown in FIG. 4 .
  • a ferroelectric layer 922 is formed on the conductive layer 920 .
  • the ferroelectric layer 922 may be the ferroelectric layer 402 shown in FIG. 4 .
  • the ferroelectric layer 922 is the ferroelectric layer 704 shown in FIGS.
  • a conductive layer 924 is formed on the ferroelectric layer 922 .
  • the conductive layer 924 may include the same material as the second electrode 116 of FIG. 1 B , the metal layer 602 of FIG. 6 A , or the metal layer 604 of FIG. 6 B .
  • the conductive layers 920 , 924 and the ferroelectric layer 922 are patterned to form capacitors 926 .
  • the capacitor 926 may be a FeCAP having improved ferroelectric properties as a result of having the ferroelectric layer 922 , which may be formed by the processes described in FIGS. 4 to 8 C .
  • a dielectric layer 928 is formed to embed the capacitors 926 .
  • the dielectric layer 928 may be an IMD layer and is part of the interconnect structure 914 .
  • the capacitors 926 may be formed in the interconnect structure 914 in back-end-of-line (BEOL) processes.
  • BEOL back-end-of-line
  • the capacitors 926 are formed in front-end-of-line (FEOL) or middle-of-line (MOL) processes.
  • FEOL front-end-of-line
  • MOL middle-of-line
  • FIG. 9 G additional processes are performed to complete the interconnect structure 914 .
  • RDLs redistribution layers
  • the semiconductor device structure 900 includes a plurality of FeRAM cells (a transistor 904 and a capacitor 926 ).
  • FIG. 10 is the semiconductor device structure 900 of FIG. 9 G , in accordance with alternative embodiments.
  • FeRAM cells 950 are formed in the interconnect structure 914 .
  • Each FeRAM cell 950 includes a transistor 952 electrically connected to a capacitor 926 .
  • Each transistor 952 may be a thin film transistor (TFT) that is formed in BEOL processes.
  • Each transistor 952 includes source/drain regions 954 , a metal oxide layer 956 , a gate dielectric layer 958 , and a gate electrode 960 .
  • the source/drain region 954 may include an electrically conductive material, such as a metal or metal nitride.
  • the source/drain region 954 includes TiN, TaN, W, or WN.
  • the metal oxide layer 956 serves as the channel region of the TFT.
  • the metal oxide layer 956 includes a metal oxide semiconductor material, such as indium gallium zinc oxide (IGZO), doped zinc oxide, doped indium oxide, doped cadmium, or other suitable metal oxide semiconductor material.
  • the gate dielectric layer 958 may include the same material as the gate dielectric layer 104 d of FIG. 1 B
  • the gate electrode 960 may include the same material as the gate electrode 104 c of FIG. 1 B .
  • the transistor 952 is electrically connected to the capacitor by the conductive lines 916 and conductive vias 918 .
  • FIGS. 11 A- 11 F are cross-sectional side views of various manufacturing stages of a transistor 1100 , in accordance with some embodiments.
  • an optional interfacial layer 1104 is formed on a substrate 1102
  • a ferroelectric layer 1106 is formed on the interfacial layer 1104
  • a dummy gate 1108 is formed on the ferroelectric layer 1106 .
  • the substrate 1102 may include the same material as the substrate 202 of FIG. 2 B and the ferroelectric layer 1106 may include the same material as the ferroelectric layer 704 of FIGS. 7 A to 7 C or the ferroelectric layer 804 of FIGS. 8 A to 8 C .
  • the dummy gate 1108 may include polycrystalline silicon.
  • the ferroelectric layer 1106 and the dummy gate 1108 are patterned (the interfacial layer 1104 is omitted).
  • Gate spacers 1110 are formed on sides of the dummy gate 1108 and the ferroelectric layer 1106 .
  • source/drain regions 1112 are formed on opposite sides of the dummy gate 1108 .
  • the source/drain regions 1112 may include the same material as the source region 204 a and the drain region 204 b of FIG. 2 B .
  • ILD layer 1114 is formed over the source/drain regions 1112 .
  • a contact etch stop layer (CESL) (not shown) is formed on the source/drain regions 1112 , and the ILD layer 1114 is formed on the CESL.
  • the dummy gate 1108 is then removed, and a gate electrode 1116 is formed on the ferroelectric layer 1106 .
  • the gate electrode 1116 may include the same material as the gate electrode 204 c of FIG. 2 B .
  • conductive contacts 1118 are formed in the ILD layer 1114 .
  • the conductive contacts 1118 are electrically connected to the source/drain regions 1112 .
  • a silicide layer (not shown) are formed between the conductive contact 1118 and the source/drain region 1112 .
  • the ferroelectric layer 1106 is removed during the removal of the dummy gate 1108 , and another ferroelectric layer 1120 is formed prior to forming the gate electrode 1116 , as shown in FIG. 11 F .
  • the ferroelectric layer 1120 may include the same material as the ferroelectric layer 704 in FIGS. 7 A to 7 C or the ferroelectric layer 804 in FIGS. 8 A to 8 C .
  • the ferroelectric layer 1106 may be a sacrificial layer and may be a high-k dielectric layer which does not exhibit ferroelectricity.
  • the transistor 1100 is a FeFET including the ferroelectric layer 1106 or the ferroelectric layer 1120 .
  • the ferroelectric layer 1106 or ferroelectric layer 1120 is formed by the processes described in FIGS. 7 A to 7 C or in FIGS. 8 A to 8 C .
  • the ferroelectricity of the ferroelectric layer 1106 or ferroelectric layer 1120 is improved, leading to improved device performance and reliability.
  • FIG. 12 is the semiconductor device structure 900 of FIG. 9 G , in accordance with alternative embodiments.
  • FeFET cells 970 are formed in the interconnect structure 914 .
  • the FeFET cells 970 includes a FeFET 972 .
  • the FeFET 972 includes source/drain regions 974 , a ferroelectric layer 976 , a metal oxide layer 978 , and a gate electrode 980 .
  • the source/drain regions 974 may include the same material as the source/drain regions 954 of FIG. 10 .
  • the ferroelectric layer 976 may include the same material as the ferroelectric layer 704 of FIGS.
  • the metal oxide layer 978 may include the same material as the metal oxide layer 956 of FIG. 10
  • the gate electrode 980 may include the same material as the gate electrode 960
  • the FeFET 972 may be a TFT.
  • FIG. 13 is the semiconductor device structure 900 of FIG. 12 , in accordance with alternative embodiments.
  • the FeFET 972 may be substantially the same as the transistor 952 shown in FIG. 10 .
  • the FeFET 972 includes a ferroelectric layer 982 disposed between the metal oxide layer 956 and the gate electrode 960 .
  • the ferroelectric layer 982 may include the same material as the ferroelectric layer 402 in FIG. 4 , the ferroelectric layer 704 in FIGS. 7 A to 7 C , or the ferroelectric layer 804 in FIGS. 8 A to 8 C .
  • the gate electrode 960 includes the same material as the monocrystalline metal layer 404 in FIG. 4 .
  • the FeFET 972 includes the ferroelectric layer 976 or the ferroelectric layer 982 .
  • the ferroelectric layer 976 or ferroelectric layer 982 is formed by the processes described in FIG. 4 , FIGS. 7 A to 7 C , or FIGS. 8 A to 8 C .
  • the ferroelectricity of the ferroelectric layer 976 or ferroelectric layer 982 is improved, leading to improved device performance and reliability.
  • the ferroelectric layer formed by the processes described in FIGS. 4 , 7 A to 7 C , or 8 A to 8 C has improved ferroelectricity.
  • the ferroelectric layer may be utilized in FeRAM, FeFET, or other suitable device.
  • the present disclosure provides a ferroelectric layer having improved ferroelectricity.
  • the ferroelectric layer is formed on a monocrystalline metal layer, and the ferroelectric layer includes over 90 percent of orthorhombic phase.
  • UHV anneal process or ion implantation process is performed after depositing the ferroelectric layer in order to increase the percentage of orthorhombic phase and/or to increase space within the layer for the atoms to move.
  • An embodiment is a method.
  • the method includes depositing a doped hafnium dioxide layer on a layer, and the doped hafnium dioxide layer has a first oxygen vacancy concentration.
  • the method further includes performing an ultra-high vacuum anneal process on the doped hafnium dioxide layer to increase the first oxygen vacancy concentration to a second oxygen vacancy concentration and performing an oxygen anneal process on the doped hafnium dioxide layer to decrease the second oxygen vacancy concentration.
  • Another embodiment is a method.
  • the method includes depositing a doped hafnium dioxide layer on a layer, and the doped hafnium dioxide layer is partially crystallized with a first crystal phase.
  • the method further includes performing an ion implantation process on the doped hafnium dioxide layer to amorphized the doped hafnium dioxide layer and performing an anneal process on the doped hafnium dioxide layer to crystallize the doped hafnium dioxide layer with a second crystal phase.
  • a further embodiment is semiconductor device structure.
  • the structure includes a transistor disposed over a substrate, an interconnect structure disposed over the transistor, and a ferroelectric capacitor (FeCAP) disposed in the interconnect structure.
  • the FeCAP includes a first metal layer, and the first metal layer is a monocrystalline metal layer.
  • the FeCAP further includes a ferroelectric layer disposed on the first metal layer, and the ferroelectric layer includes over 90 percent of orthorhombic phase.
  • the FeCAP further includes a second metal layer disposed on the ferroelectric layer.

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  • Semiconductor Memories (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Chemical Vapour Deposition (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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