US20220182041A1

US20220182041A1 - Variable current drive for isolated gate drivers

Info

Publication number: US20220182041A1
Application number: US17/138,091
Authority: US
Inventors: Ion C. Tesu; James E. Heckroth; Stefan N. Mastovich; John N. Wilson; Krishna Pentakota; Michael Ireland; Greg Ridsdale; Lyric Jackson
Original assignee: Skyworks Solutions Inc
Current assignee: Skyworks Solutions Inc
Priority date: 2020-12-04
Filing date: 2020-12-30
Publication date: 2022-06-09
Anticipated expiration: 2040-12-30
Also published as: US20220294427A1; US11870440B2; WO2022119835A1; US20240204756A1; US11362646B1; US11804827B2; WO2022120021A1; US20230188119A1; TW202241063A; US20220182052A1; US11539350B2; US20240186988A1

Abstract

A method for driving a high-power drive device includes providing a signal having a first predetermined signal level to an output node during a first phase of a multi-phase transition process. The method includes generating a first indication of a first parameter associated with the signal provided to the output node. The method includes generating a second indication of a second parameter associated with the signal provided to the output node. The method includes providing the signal having a second predetermined signal level to the output node during a second phase of the multi-phase transition process. The method includes transitioning from the first phase to the second phase based on the first indication and the second indication. A multi-die, distributed package technique addresses power dissipation requirements for a driver product based on size and associated power dissipation needs of the high-power drive device in a target application.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims the benefit of U.S. Provisional Application No. 63/121,702, entitled “VARIABLE-CURRENT DRIVE FOR ISOLATED GATE DRIVERS,” naming Ion C. Tesu, James E. Heckroth, Stefan N. Mastovich, John N. Wilson, Krishna Pentakota, Michael Ireland, Greg Ridsdale, and Lyric Jackson as inventors, filed on Dec. 4, 2020, which application is incorporated herein by reference.
This application is related to application Ser. No. 16/694,100, entitled “GATE DRIVER WITH INTEGRATED MILLER CLAMP,” naming Alan L. Westwick, Peter Onody, András V. Horvath, and Tamás Marozsák as inventors, filed on Nov. 25, 2019, which application is incorporated herein by reference.

BACKGROUND

Field of the Invention

This disclosure is related to circuits and more particularly to control circuits for high-power applications.

Description of the Related Art

In a typical control application, a processor system provides one or more control signals for controlling a load system. During normal operation, a large DC or transient voltage difference may exist between a domain of the processor system and a domain of the load system, thus requiring an isolation barrier between the processor system and the load system. For example, one domain may be grounded at a voltage that is switching with respect to earth ground by hundreds or thousands of volts. Accordingly, an intermediate system includes isolation that prevents damaging currents from flowing between the processor system and the load system. Although the isolation prevents the processor system from being coupled to the load system by a direct conduction path, an isolation communications channel allows communication between the two systems using optical (opto-isolators), capacitive, inductive (transformers), or electromagnetic techniques. In at least one embodiment, the isolation communications channel blocks DC signals and only passes AC signals. The intermediate system typically uses a voltage converter and output driver to provide the control signal at voltage levels suitable for the load system.
Referring to FIG. 1, in an exemplary motor control application, processor 100, which may be a microprocessor, microcontroller, or other suitable processing device, operates in a first domain (i.e., VDD1, e.g., 5 Volts (V)) and provides one or more signals for a high-power load system operating in a second domain (i.e., VDD3, e.g., 800 V). Systems 102 each include an isolation barrier 130 and an isolation communications channel for safely communicating control signals from processor 100 to drivers 106, which drive high- power drive devices 108 and 109 of a three-phase inverter used to deliver three-phase power to motor 120. Exemplary high-power drive devices include power metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), Gallium-Nitride (GaN) MOSFETs, Silicon-Carbide power MOSFETs, or other suitable devices able to deliver high currents over short periods of time.
Voltage converters 104 convert an available power supply voltage from VDD1 or VDD3 to a voltage level (i.e., VDD2, e.g., approximately 15 V) usable by the high-voltage side of systems 102 and drivers 106. Note that in other embodiments, a single voltage converter 104 converts one power supply voltage from a first voltage level (e.g., VDD3) to multiple other voltage levels (e.g., VDD1 and VDD2) and/or provides multiple outputs of a particular voltage (e.g., multiple VDD2 outputs corresponding to multiple systems 102). Drivers 106 provide switch control signals at levels required by corresponding high- power drive devices 108 or 109 of the three-phase inverter. The load motor requires three-phase power at high power levels. Systems 102 that correspond to high-power devices coupled to VDD3 (high-side inverter devices), are grounded at a voltage that is switching with respect to earth ground by the high voltage levels of VDD3. Typical high- power drive devices 108 and 109 of the three-phase inverter that are used to drive motor 120 require substantial turn-on voltages (e.g., voltages in the range of tens of Volts) and are susceptible to fault conditions that may damage those devices.
Exemplary isolated gate drivers are used in industrial and automotive applications. Conventional embodiments of gate drivers use fixed resistors to determine a fixed drive strength during the high-power drive device normal turn-on and normal turn-off process. The fixed drive strength determines a compromise between the competing goals of maximizing efficiency, minimizing radiated and conducted emissions (i.e., electromagnetic interference (EMI)), and limiting voltage stress on the external high-power drive device. Accordingly, improved techniques for controlling high-power drive devices are desired.

SUMMARY OF EMBODIMENTS OF THE INVENTION

In at least one embodiment, a method for controlling a high-power drive device includes providing a signal having a first predetermined signal level to an output node during a first phase of a multi-phase transition process. The method includes generating a first indication of a first parameter associated with the signal provided to the output node. The method includes generating a second indication of a second parameter associated with the signal provided to the output node. The method includes providing the signal having a second predetermined signal level to the output node during a second phase of the multi-phase transition process. The method includes transitioning from the first phase to the second phase based on the first indication and the second indication.
In at least one embodiment, a system for controlling a high-power drive device includes a driver circuit. The driver circuit includes an output node and a variable strength driver circuit coupled to the output node. The variable strength driver circuit is configured to provide a signal to the output node. The signal has a strength based on a multi-bit digital control signal. The driver circuit includes an indicator circuit configured to generate a first indication of a first parameter associated with the signal. The driver circuit includes a timer circuit configured to generate a second indication of a second parameter associated with the signal. The driver circuit includes a driver controller circuit responsive to a received control signal and a predetermined profile of a multi-phase transition process, the first indication, and the second indication to generate the multi-bit digital control signal.
In at least one embodiment, a system for controlling a high-power drive device includes an output node, a variable strength driver circuit configured to provide a signal to the output node having a signal level based on a multi-bit digital control signal, and a control circuit configured to generate the multi-bit digital control signal based on a received control signal, a fault indicator signal, a predetermined profile of a multi-phase transition process, an indication of a first parameter associated with the signal, and an indication of a second parameter associated with the signal.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

FIG. 1 illustrates a functional block diagram of a typical motor control system.

FIG. 2 illustrates a functional block diagram of a portion of the motor control system of FIG. 1 including exemplary fault detection circuitry and driver control circuits.

FIG. 3 illustrates an exemplary simplified representation of the portion of the motor control system of FIG. 2.

FIG. 4 illustrates timing waveforms and switching parameter definitions consistent with at least one embodiment of the invention.

FIG. 5 illustrates a functional block diagram of a portion of a packaged driver integrated circuit product including a variable strength gate driver circuit consistent with at least one embodiment of the invention.

FIG. 6 illustrates a circuit diagram of an exemplary embodiment of a variable current driver circuit consistent with at least one embodiment of the invention.

FIG. 7 illustrates exemplary variable current driver working registers and parameter values consistent with at least one embodiment of the invention.

FIG. 8 illustrates a functional block diagram of exemplary packaging of a driver product for a low-power system consistent with at least one embodiment of the invention.

FIG. 9 illustrates a functional block diagram of exemplary packaging of a driver product for a medium-power system consistent with at least one embodiment of the invention.

FIG. 10 illustrates a functional block diagram of exemplary packaging of a driver product for a high-power system consistent with at least one embodiment of the invention.

FIG. 11 illustrates a functional block diagram of exemplary packaging of a driver product for a high-power system having redundancy consistent with at least one embodiment of the invention.

The use of the same reference symbols in different drawings indicates similar or identical items.

DETAILED DESCRIPTION

Referring to FIG. 2, in an exemplary motor control application, processor 100 receives a voltage (i.e., VDD1, e.g., 5V) and provides one or more signals for a high power load system operating in a second domain (i.e., VDD3, e.g., hundreds of volts). Driver product 200 includes isolation barrier 230 and a communication channel for safely communicating control signals from processor 100 across isolation barrier 230 to drive a high-power drive device of a three-phase inverter used to deliver three-phase power to motor 120. In an exemplary embodiment, driver product 200 includes multiple integrated circuits configured as a multi-chip module in a single package. For example, driver product 200 includes primary-side integrated circuit 201 and secondary-side integrated circuit 203. Primary-side integrated circuit 201, receives a control signal from processor 100 and communicates the signal across isolation barrier 230 to secondary-side integrated circuit 203. In such embodiments, terminals 250, 252, 254, . . . , 270 are pins of a package of the multi-chip module and are coupled to external elements, e.g., discrete resistors and capacitors, and to processor 100.
Driver product 200 includes isolation barrier 230, which isolates the domains on a first side (e.g., primary-side integrated circuit 201) of driver product 200, which operates using VDD1 (e.g., a voltage less than ten volts), and a second side (e.g., secondary-side integrated circuit 203) of driver product 200, which operates using VDD2 (e.g., a voltage of tens of volts). An isolation communications channel facilitates communication between primary-side integrated circuit 201 and secondary-side integrated circuit 203. Any suitable communications technique that does not use a conductive path between the two sides may be used, e.g., optical, capacitive, inductive, or electromagnetic techniques. The isolation communications channel facilitates communication of a control signal to secondary-side integrated circuit 203 from processor 100 via primary-side integrated circuit 201.
An exemplary isolation communications channel uses digital modulation (e.g., on-off keying modulation) to communicate one or more digital signals between primary-side integrated circuit 201 and secondary-side integrated circuit 203, although other communication protocols may be used. In general, on-off keying modulation is a form of amplitude-shift keying modulation that represents digital data as the presence or absence of a carrier wave or oscillating signal having a carrier frequency fc (e.g., 500 MHz-1 GHz). The presence of the carrier for a specified duration represents a binary one, while its absence for the same duration represents a binary zero. This type of signaling is robust for isolation applications because a logic ‘0’ state sends the same signal (e.g., nothing) as when the primary side loses power and the device gracefully assumes its default state. That behavior is advantageous in driver applications because it will not accidentally turn on a load device being driven, even when the primary side loses power. However, the isolation communications channel may use other types of signals (e.g., pulse width modulated signals or other types of amplitude shift keying modulated signals). The digital modulation scheme used may be determined according to performance specifications (e.g., signal resolution) and environment (e.g., probability of transient events) of the target application.
Secondary-side integrated circuit 203 includes driver 221, which generates one or more output control signals based on received control signal CTL received from primary-side integrated circuit 201, which receives control signal IN on terminal 254 from processor 100. Driver 221 provides corresponding signals to terminals 264 and 266. Buffer 219 generates control signals CTLH and CTLL at appropriate signal levels for controlling pull-up and pull-down devices of driver 221, respectively. Buffer 219 may generate one control signal or two separate control signals for the pull-up device and the pull-down device based on received control signal CTL. External resistance R_Hadjusts the pull-up strength by 1/R_Hindependently from external resistance R_Lthat adjusts the pull-down strength by 1/R_L. Although received control signal CTL is illustrated as a single-ended signal based on input control signal CTL received from processor 100 on terminal 254, note that in other embodiments, input control signal IN and received control signal CTL are differential signals. In general, signals illustrated herein as single-ended signals may be implemented as differential signals in other embodiments and signals illustrated herein as differential signals may be implemented as single-ended signals in other embodiments.
The pull-up strength and the pull-down strength of the output control signal provided to the control terminal of high-power drive device 108 can be independently adjusted from on-resistance R_DS(ON)of the integrated pull-up output device coupled to terminal 264 using one or more passive elements. For example, resistance R_Hadjusts the pull-up strength. Resistor R_Ladjusts the pull-down strength of the signal provided to the gate of high-power drive device 108 via terminal 266 to have a strength different from the pull-up strength of the signal provided to the gate of high-power drive device 108. In a typical configuration, the pull-up time is slower than the pull-down time and resistances R_Hand R_Lwill vary with specifications of the device (e.g., power MOSFET, IGBT, GaN MOSFET, Si-Carbide power MOSFET, etc.) used as high-power drive device 108.
In at least one embodiment, the isolation communications channel feeds back voltage information or fault information from secondary-side integrated circuit 203 to primary-side integrated circuit 201. Primary-side integrated circuit 201 or processor 100 uses that information to adjust operating parameters or generate one or more fault indicators that may be used for automatically handling faults by controlling output driver 221 accordingly. For example, secondary-side integrated circuit 203 includes modules that detect fault conditions associated with high-power drive devices, e.g., desaturation detector 214, and may also detect user-initiated faults received from processor 100. Fault indicator(s) may be used by secondary-side integrated circuit 203 to prevent damage to the high-power drive devices, load system, or user of the load system. In addition, secondary-side integrated circuit 203 may send an indication of a fault or associated diagnostic information to primary-side integrated circuit 201 and/or processor 100.
In at least one embodiment, secondary-side integrated circuit 203 includes desaturation fault protection for high-power semiconductor devices, which protects against short-circuit current events that may destroy high-power drive device 108. This fault may result from an insufficient gate drive signal caused by inverter gate driver misbehavior, drive supply voltage issues, a short circuit in a power stage, or other excessive current or power dissipation of the high-power drive devices. Those events can substantially increase power consumption that quickly overheats and damages the corresponding high-power drive device. For example, when a short circuit current condition occurs in the exemplary motor drive application of FIGS. 1 and 2 (e.g., both devices of an individual inverter phase of a three-phase inverter are on), high current flows through high- power drive devices 108 and 109 and may destroy high- power drive devices 108 and 109. Accordingly, a fault detection technique detects this desaturation condition. Driver product 200 may send an indicator thereof to processor 100.
In at least one embodiment of driver product 200, desaturation fault protection turns off high-power drive device 108 following detection of the fault condition. In a typical application, terminal 262 is coupled to an external resistor and diode that are coupled to a terminal of high-power drive device 108 (e.g., the collector terminal of an IGBT or drain terminal of a MOSFET). In at least one embodiment of driver product 200, desaturation detection circuit 214 is enabled only while high-power drive device 108 is turned on. Desaturation detection circuit 214 senses when the collector-emitter voltage (or drain-to-source voltage, as the case may be) of high-power drive device 108 exceeds a predetermined threshold level (e.g., 7V). Note that the predetermined threshold level of desaturation detection circuit 214 may be externally adjusted based on the forward voltage of one or more diodes coupled to the desaturation resistor coupled to terminal 262 or based on the resistance of the desaturation resistor. In addition, a delay time may be introduced by coupling a capacitor between terminal 262 and an external power supply node.
In general, undervoltage lockout detector 212 prevents application of insufficient voltage to the control terminal of high-power drive device 108 by forcing the output on terminal 264 to be low during power-up of driver product 200. Undervoltage lockout detector 212 detects when the power supply voltage (e.g., VDD2 sensed using terminal 260) exceeds a first predetermined undervoltage lockout threshold voltage and generates an indication thereof, which may be used to disable the lockout condition. Undervoltage lockout detector 212 also detects when the power supply voltage falls below a second predetermined undervoltage lockout threshold, which may be different from the first undervoltage lockout threshold voltage, to provide noise margin for the undervoltage lockout voltage detection. The indicator generated by undervoltage lockout detector 212 may be provided to processor 100 using terminal 252. In at least one embodiment, driver product 200 includes a similar mechanism for an overvoltage condition.
Miller clamp 220 reduces effects of parasitic turn-on of high-power drive device 108 due to charging of the Miller capacitor (e.g., the collector-to-gate parasitic capacitor of an IGBT device or the drain-to-gate parasitic capacitor of a MOSFET in other embodiments of high-power device 108). That gate-to-collector coupling can cause a parasitic turn on of device 108 in response to a high transient voltage (e.g., a gate voltage spike) generated while high-power drive device 108 is turned off. A gate voltage spike is created when turning on another high-power drive device coupled to high-power drive device 108.
For example, when turning on upper high-power drive device 109, a corresponding lower high-power drive device 108 coupled to upper high-power drive device 109 experiences a voltage change dV_CE/dt causing current flow into the gate drive terminal coupled to lower high-power drive device 108. In the absence of Miller clamp 220, this current would create a voltage drop across external resistance R_Land would increase the gate-to-emitter voltage of a corresponding lower high-power drive device 108. If the gate-to-emitter voltage exceeds the device threshold voltage (e.g., 2 V), then high-power drive device 108 turns on. A similar parasitic turn-on event occurs when turning on high-power drive device 108 and the corresponding upper high-power drive device 109 is in an off state. Miller clamp 220 prevents parasitic turn-on by coupling terminal 268 to ground via a low-resistance switch that hinders or prevents the Miller capacitor current from developing a voltage sufficient to turn on the high-power drive device.
In some embodiments of driver product 200, Miller clamp 220 is not needed because a sufficiently sized gate capacitor coupled between the gate and emitter of each high-power drive device 108 shunts any Miller current and raises the level of the transient needed to parasitically turn on the device. However, such embodiments increase the gate charge voltage required to reach the threshold voltage of high-power drive device 108, increase the driver power, and increase switching losses of high-power drive device 108. In other embodiments of driver product 200 that do not use a Miller clamp circuit, the lower supply voltage is coupled to a negative voltage (e.g., −5 V) rather than ground. This configuration provides additional voltage margin to increase the likelihood that the parasitic turn-on transient does not raise the control terminal of high-power drive device 108 above its threshold voltage. However, this configuration increases cost by requiring an additional pin on the package and requiring generation of the negative voltage.
Upon detection of a fault condition by modules on secondary-side integrated circuit 203, fault logic 216 generates control signal FAULT, which may initiate shutdown of high-power drive device 108. Fault logic 216 reports the fault condition to processor 100 via primary-side integrated circuit 201. Alternatively, fault logic 216 only reports the fault condition to primary-side integrated circuit 201 and high-power drive device 108 continues operation. Then, primary-side integrated circuit 201 reports the fault condition to processor 100. Since a system may include multiple high-power drive devices (e.g., six high-power drive devices in the exemplary motor control application described herein), shutting down only one of these devices may harm the high-power drive devices or the load. Therefore, in response to detection of a fault, processor 100 may initiate a shutdown of high-power drive device 108 only after detecting a predetermined number of faults over a particular period of time or other condition is satisfied. In at least one embodiment, processor 100 initiates shutdown of high-power drive device 108 independently from any fault detection of driver product 200 (e.g., based on fault detection from another driver product 200 associated with another high-power drive device 108 or 109).
An abrupt shutoff of high-power drive device 108 may result in large di/dt induced voltages. Such voltage spikes could be damaging to high-power drive circuit 108 or the load. Accordingly, in response to a fault condition, processor 100 or driver product 200 initiates a soft shutdown of high-power drive device 108 that slowly discharges the control terminal of high-power drive device 108 at a rate having a turn-off time longer than the regular turn-off time of the output control signal. For example, fault logic 216 receives a indicator from desaturation detection circuit 214 and generates control signal FAULT based thereon that initiates a soft shutdown. In other embodiments, fault logic 216 receives an indicator from one or more other fault detection circuits. Typical implementations of a soft-shutdown function in a driver product may use an additional terminal or at least one additional external resistor coupled to terminal 264 or terminal 266.
A variable current drive technique partitions a transition (e.g., a turn-on or a turn-off) of a state (e.g., on or off) of a high-power drive device into multiple phases (i.e., intervals) that can have different characteristics. The use of variable current driver reduces or eliminates the need for external gate resistors for control of a transition of the high-power drive device. The use of multiple current settings for an output gate driver current (e.g., a gate current of the high-power drive device) during a transition of the output signal improves the transition of the state of the high-power drive device and corresponding efficiency level of the system (i.e., the ratio of useful work performed by the system to the total energy expended by the system, which affects the range of an electric vehicle per battery charge in an exemplary electric vehicle application), reduces EMI, and reduces voltage stress of the high-power drive device, as compared to conventional approaches.
In at least one embodiment of the variable current drive technique, the change of target current levels during a transition of a state of a high-power drive device is based on an indication of a control voltage of the high-power drive device (e.g., gate-to-source voltage V_GSsensed using the output node of the gate driver product) and a corresponding time limit. For example, a target current level is changed from a first predetermined current level to a second predetermined current level in response to the gate-to-source voltage V_GSof the high-power drive device reaching or exceeding the Miller plateau. The Miller plateau refers to a region of the gate-to-source voltage time response, where the gate-to-source voltage V_GSis almost constant and is a region in which the state of the high-power drive device is switching between a first state (e.g., an off-state) to a second state (e.g., an on-state). The Miller plateau is defined by gate-to-source voltage level V_{PLAT_ON}and gate-to-source voltage level V_{PLAT_OFF}, which are inflection points in the response of gate-to-source voltage V_GS. In at least one embodiment, an objective of the variable current drive technique is to reach the Miller plateau voltage as quickly as possible. However, to limit electromagnetic interference caused by the current of the variable current drive, the variable current drive technique drives the high current level only for a limited time and decreases the current after reaching the Miller plateau voltage or the expiration of a corresponding time limit. Accordingly, the variable current driver initially drives a high gate current level (e.g., 12 A) to reduce the time required to charge the gate of the high-power drive device to the Miller plateau voltage (or discharge the gate of the high-power drive device to the Miller plateau voltage, as the case may be), after which the variable current driver drives another current level to the gate of the high-power drive device (e.g., 6 A) that achieves a target change in drain-to-source (or collector-to-emitter) voltage as a function of time (e.g., dV_DS/dt_ONor dV_DS/dT_OFF) for the remainder of the transition of the state of the high-power drive device. The variable current drive technique provides improved capability to optimize the tradeoff between faster switching speed for efficiency, lower dV_DS/dt for reduced EMI, and reduced drive device output voltage overshoot as compared to conventional gate driver implementations.
In at least one embodiment of the variable current drive technique, changing target output current levels based on a time limit is used in addition to, or instead of, a threshold voltage criteria for triggering a change to a target output current level. In at least one embodiment, the variable current drive technique uses a combination of the threshold voltage criteria and a time limit (e.g., to change a target current level based on a threshold voltage or based on a time limit, whichever is reached first) to provide more reliable operation in high-noise environments where incorrect switching might otherwise occur due to noise. In at least one embodiment, the variable current drive technique measures elapsed time using a digital counter. In at least one embodiment, the variable current drive technique measures elapsed time using an RC-based system. For example, one or more timers generate indicators of how much time has elapsed since the start of a phase of a multi-phase transition process. Even if a target voltage level has not been achieved on the output node, the variable current drive technique changes the target current level and enters a next phase of the multi-phase transition process in response to expiration of a predetermined amount of time, e.g., to reduce EMI, or in response to expiration of a predetermined amount of time and another condition (e.g., a sensed current level or a sensed voltage level exceeding a predetermined threshold level).
FIGS. 3 and 4 illustrate an exemplary implementation of the variable current drive technique including a multi-phase turn-on process and a multi-phase turn-off process. An exemplary high-power gate driver powered using +15V and −4V power supplies drives high-power drive device 304. Inductor 306, which has an initial condition of I_L=20A and is coupled in parallel with a diode, represents an exemplary load. Exemplary waveforms for the gate current I_GATE, which is driven by gate driver 302, drain-to-source voltage V_DS, drain current I_D, gate-to-source voltage V_GS, and control signal CTL illustrate an exemplary multi-phase turn-on process and an exemplary multiple phase turn-off process of high-power drive device 304. Target set current I_SETillustrates exemplary target current levels (i.e., predetermined target current set points) that are used to program the actual gate current I_GATEflowing into the gate of high-power drive device 304. The resulting drain current I_Dof high-power drive device 304, and associated voltages (e.g., drain-to-source voltage V_DSand gate-to-source voltage V_GS) of high-power drive device 304 represent the response to an exemplary variable current drive profile that uses a combination of parameters, such as the Miller plateau voltages, the Miller clamp voltage, and the time limits for each phase of the multi-phase transition process. Although embodiments described herein use the Miller Plateau voltages as voltage thresholds for triggering a change in the target gate current level of a phase of a multi-phase turn-on process or multi-phase turn-off process of high-power drive device 304, other voltages, multiple switching voltages, current levels, or combinations thereof are used in other embodiments.
In at least one embodiment of the variable current drive technique, the characteristics of a multi-phase transition process for the high-power drive device are defined by the parameters of a normal turn-on profile (e.g., target current set point, a gate-to-source threshold voltage, and time limit for a phase of the multi-phase transition process). The normal turn-on process includes two phases: phase P_TON1and phase P_TON2. Each phase of the normal turn-on process has a corresponding, individually programmed sourcing current level. For example, phase P_TON1has target current set point I_{ON1_SET}. In at least one embodiment of the normal turn-on process, the Miller plateau voltage V_{PLAT_ON}is used as the threshold voltage to trigger a transition from phase P_TON1to phase P_TON2. In at least one embodiment of the normal turn-on process, target current set point I_{ON1_SET}is greater than target current set point I_{ON_SET2}(i.e., I_{ON1_SET}>I_{ON2_SET}) and time limit tom triggers a transition from phase P_TON1to phase P_TON2to limit the amount of time that the higher current level of target current set point I_{ON1_SET}is used to limit EMI. The normal turn on process enters phase P_TON2even if the gate-to-source voltage V_GSdoes not reach Miller plateau voltage V_{PLAT_ON}in response to expiration of time limit tom. Thus, the normal turn-on process progresses from phase P_TON1to phase P_TON2in response to the gate-to-source voltage V_GSof high-power drive device 304 exceeding Miller plateau voltage V_{PLAT_ON}, or in response to the time elapsed in phase P_TON1exceeding time limit tom, whichever condition comes first. Once in phase P_TON2, the normal turn-on process does not return to phase P_TON1.
Phase P_TON2has target current set point I_{ON2_SET}. Another set of variable current drive turn-on profile parameters also control phase P_TON2of the normal turn-on process. For example, current set point I_{ON2_SET}specifies the target sourcing current level for phase P_TON2of the normal turn-on process. Time limit t_ON2specifies the time at which gate-to-source voltage V_GSis expected to be above the under-voltage threshold V_{GSON_UV}. In at least one embodiment, control circuitry triggers a fault if time limit t_ON2expires prior to gate-to-source voltage V_GSexceeding under-voltage threshold V_{GSON_UV}. In at least one embodiment of the variable current drive technique, after gate-to-source voltage V_GSreaches voltage level V_POS, high-power drive device 304 remains on and drain current I_Dincreases at a rate of VDC LINK/L until a transition of control signal CTL triggers another multi-phase transition process that causes gate-to-source voltage V_GSto exceed (i.e., fall below) Miller plateau voltage V_{PLAT_OFF}.
In at least one embodiment of the variable current drive technique, the characteristics of a multi-phase transition process are defined by the parameters of a normal turn-off profile (e.g., a target current set point, a threshold voltage, and a time limit for a phase of the multi-phase transition process). The normal turn-off process includes three phases: phase P_TOFF1, phase P_TOFF2, and phase P_TOFF3. Each of the phases has a corresponding, individually programmed sinking current level. For example, phase P_TOFF1, phase P_TOFF2, and phase P_TOFF3have target current set point I_{OFF1_SET}, target current set point I_{OFF2_SET}, and target current set point I_{MC_SET}, respectively. In at least one embodiment, target current set point I_{OFF1_SET}is greater than target current set point I_{OFF2_SET}(i.e., I_{OFF1_SET}>I_{OFF2_SET}) and target current set point I_{MC_SET}is greater than or equal to target current set point I_{OFF1_SET}and greater than target current set point I_{OFF2_SET}(i.e., I_{MC_SET}>I_{OFF1_SET}and I_{MC_SET}>I_{OFF2_SET}).
Normal turn-off profile parameters including a current level parameter, a threshold voltage parameter and a time parameter (e.g., target current set point I_{OFF1_SET}, threshold voltage V_{PLAT_OFF}, and time limit t_OFF1) control phase P_TOFF1. Target current set point I_{OFF1_SET}specifies the target sinking current level for phase P_TOFF1, threshold voltage V_{PLAT_OFF}, specifies the threshold voltage for triggering a transition from phase P_TOFF1to phase P_TOFF2of the normal turn-off process. The time parameter, time limit t_OFF1specifies the time limit for phase P_TOFF1of the normal turn-off process. Variable current drive normal turn-off profile parameters (e.g., target current set point I_{OFF2_SET}, threshold voltage V_MC, and time limit t_OFF2) control phase P_TOFF2. The current parameter specifies the target sinking current level for phase P_TOFF2of the normal turn-off process. The voltage parameter, Miller clamp voltage V_MC, specifies the threshold voltage for triggering a transition to phase P_TOFF3, thereby triggering the internal Miller clamp function of the variable strength driver. The time parameter specifies time limit t_OFF2for phase P_TOFF2to trigger a transition to phase P_TOFF3of the normal turn-off process.
Phase P_TOFF3of the normal turn-off process is controlled by normal turn-off profile parameters current set point I_{MC_SET}and time limit t_OFF3. Current I_{MC_SET}specifies the target current sink level for phase P_TOFF3of the normal turn-off process. The time limit t_OFF3specifies the time at which gate-to-source voltage V_GSis expected to fall below over-voltage threshold V_{GSOFF_OV}, which represents the over-voltage limit for the gate-to-source voltage V_GSduring turn-off. In at least one embodiment, control circuitry triggers a fault if time limit t_OFF3expires prior to gate-to-source voltage V_GSfalling below over-voltage threshold V_{GSOFF_OV}.
In at least one embodiment, in response to each change in state of received control signal CTL, the variable current drive technique introduces a small deadtime, e.g., time delay t_DT, before initiating a corresponding multi-phase transition process (e.g., a turn-on process or a turn-off process) to reduce or eliminate shoot-through between the pull-up and the pull-down circuits of the gate driver. Multi-phase transition profiles, including parameters and number of phases, described herein are exemplary only. Transition profiles can be optimized for different objectives or operating conditions, to improve efficiency, reduce EMI, and reduce drain-to-source voltage V_DS(or collector-to emitter voltage V_CE) voltage stress, as compared to the conventional approach. In at least one embodiment, a soft-shutdown turn-off profile implements a multi-phase soft shutdown turn-off process, which is initiated by gate driver 302 in response to detection of a fault (e.g., a short-circuited load of the power switch). In at least one embodiment, the soft-shutdown turn-off process uses the same turn-off process as a normal turn-off process, but with different parameters. For example, the target current set point I_{SS2_SET}parameter (which corresponds to target current set point I_{OFF2_SET}of the normal turn-off profile) is set to a lower value under short-circuit load conditions than that used for normal load currents to slow the turn-off process and reduce or eliminate any resulting overshoot of drain-to-source voltage V_DS(or collector-to emitter voltage V_CE) that may damage the high-power drive device. In at least one embodiment of a multi-phase transition profile, a time limit in one or more phases of a turn-on process or a turn-off process triggers a measurement that is used to detect faults.
Referring to FIG. 5, in at least one embodiment, driver product 400 includes a primary-side integrated circuit, isolation barrier, and isolation communications channel (not shown in FIG. 5, but described above), and secondary-side integrated circuit 403. In at least one embodiment, secondary-side integrated circuit 403 of driver product 400 includes gate driver 420 coupled to terminal VO, which in some embodiments is the only terminal of driver product 400 that is coupled to the gate terminal of high-power drive device 108. In at least one embodiment, gate driver 420 integrates the Miller clamp function and eliminates external resistors coupled to high power drive device 108 described above. In at least one embodiment, gate driver 420 integrates other fault detection circuits described above (not shown).
In at least one embodiment of gate driver 420, driver controller 404 configures variable strength driver 402 to source current according to a normal turn-on profile in response to control signal CTL transitioning from a first value to a second value, configures variable strength driver 402 to sink current according to a normal turn-off profile in response to control signal CTL transitioning from the second value to the first value, or configures variable strength driver 402 to implement a soft-shutdown turn-off profile in response to control signal CTL having the second value and in response to a fault condition (e.g., a desaturation fault condition indicated by control signal FAULT). Exemplary turn-on, turn-off, and soft shutdown turn-off profiles are described above, although other profiles are used in other embodiments. The profiles independently determine values used by driver controller 404 to generate control signals using predetermined digital codes. Predetermined digital codes and other configuration parameters may be preloaded into memory 410, received from a serial interface of driver product 400, or provided to working registers of gate driver 420 or memory 410 using other techniques.
In at least one embodiment, driver controller 404 receives control signal CTL from a primary-side integrated circuit across the isolation barrier and receives a feedback signal from comparator 406, which in some embodiments is a hysteretic comparator. In at least one embodiment, comparator 406 receives a predetermined signal level from digital-to-analog converter 412. In at least one embodiment, the predetermined signal level code is stored digitally in memory 410 as part of a turn-on profile or turn-off profile and later converted to an analog signal for use by comparator 406. In other embodiments, instead of using an analog comparator, an analog-to-digital converter digitizes a level of a signal on terminal VO and digital comparison logic or driver controller 404 generates feedback signal FB, which is indicative of the comparison of gate-to-source voltage V_GSof high-power drive device 108 to a predetermined threshold voltage of a turn-on or turn-off profile. In at least one embodiment of secondary-side circuit 403, at least one set of digital codes retrieved from memory 410 corresponds to a target current set point of a variable current drive profile. Driver controller 404 accesses those digital codes to set the output current, gate current I_GATE, provided by variable strength driver 402 to the gate of high-power drive device 108 according to the variable current drive profile.
Referring to FIG. 6, in at least one embodiment of gate driver 420, variable strength driver 402 is a variable current driver including current sources that generate gate current I_GATEand corresponding voltages described above. In at least one embodiment, the current sources are implemented using current digital-to-analog converter (DAC) 421 and current DAC 422. Current DAC 421, which sources current to terminal VO in the turn-on process, is realized using p-type transistors. Current DAC 422, which sinks current from terminal VO in the turn-off process is realized with n-type transistors. Current DAC 421 and current DAC 422 each include a current-mirror structure with a fixed current input leg (e.g., transistors M_Pand M_PCof current DAC 421 and M_Nand M_NCof current DAC 422) and an output stage including binary-weighted branches or thermometer-weighted branches (e.g., branch including transistors M_P0and M_PC0, branch including transistors M_P1and M_PC1, . . . , branch including transistors M_Pnand M_PCnof current DAC 421 and branch including transistors M_N0and M_NC0, branch including transistors M_N1and M_NC1, . . . , branch including transistors M_Nnand M_NCnof current DAC 422). Corresponding switches (e.g., switches S_{OFF_P0}, S_{ON_P0}, S_{OFF_P1}, S_{ON_P1}, . . . , S_{OFF_Pn}, and S_{ON_Pn}of current DAC 421 and switches S_{OFF_N0}, S_{ON_N0}, S_{OFF_N1}, S_{ON_N1}, . . . , S_{OFF_Nn}, and S_{ON_Nn}of current DAC 422) selectively enable branches of an output stage according to a target current I_SET. An exemplary manufacturing process provides transistors having different breakdown voltages by forming gate terminals using oxide layers of different thicknesses. An exemplary high-voltage device has a thicker gate oxide and therefore has a higher breakdown voltage than a low-voltage device that has a thinner gate oxide thickness. In at least one embodiment of variable strength driver 402, rather than using high-voltage transistors to interface to the high-voltage domain, low-voltage transistors are used to increase accuracy of the current provided to terminal VO. Low-voltage devices M_P0, . . . M_Pnand M_N0, . . . , M_Nnare protected from high-voltages on terminal VO by corresponding cascode devices and provide an accurate output current to the gate of high-power drive device 108 independently from the wide range of voltages on terminal VO. Although each branch of the output stage includes a transistor and a selectively enabled cascode transistor, in other embodiments different numbers of transistors and branch topologies are used.
In an exemplary embodiment of variable strength driver 402, a maximum output current requirement is 12.4 A and is produced by a 5-bit (i.e., n=0, 1, 2, . . . , 4) current mirror digital-to-analog converter circuit with an input bias current I_BIASof 1.24 mA, and having a current gain of 10,000. The least significant bit of the binary-weighted digital-to-analog converter circuit corresponds to a current of 0.4 A. Transistors that are sized to generate that high output current create a large transient on the diode-connected input reference transistors M_Por M_Nthat generates the reference voltages V_OHFand V_OLFfor the each digital-to-analog converter circuit each time the digital input control code is updated. Therefore, variable strength driver 402 includes reservoir capacitor C_HFand reservoir capacitor CLF coupled in parallel with diode-connected transistor M_Pof DAC 421 and diode-connected transistor M_Nof DAC 422, respectively, to reduce or eliminate DAC voltage reference glitches during transitions of the output current. In at least one embodiment of variable strength driver 402, the binary-weighted or thermometer-weighted branches of DAC 421 and DAC 422 are constructed out of a plurality of smaller individual devices that sum up to a target output device size. That structure reduces the impact of semiconductor manufacturing faults on the overall functionality of the output stage. In at least one embodiment, the DAC structure of the output stage and the least-significant bit size are selected to reduce the effect of a single failure.
In at least one embodiment, variable strength driver 402 is coupled to driver controller 404 and memory 410 or other control logic and associated memory, which store variable current drive working registers. In at least one embodiment, driver controller 404 controls the turn-on and turn-off processes based on the contents of memory 410 and parameter inputs. For example, the driver controller circuit generates digital control signals to configure variable strength driver 402 according to the target current level of an active phase of a multi-phase transition process and associated contents of the working registers. In at least one embodiment, driver controller 404 executes a state machine that updates the digital control signals to configure or reconfigure variable strength driver 402 to implement the various phases of the multi-phase transition process based on indicators of parameters (e.g., a sensor output indicative of a voltage level or a current level, a timer output indicative of elapsed time, or an indication of another parameter) and predetermined parameter values (e.g., target signal levels, threshold voltage, or time limit values) stored in memory. In at least one embodiment, a fast voltage comparator is external to a driver controller circuit and provides a parameter indicator, e.g., a feedback signal indicative of a comparison of the gate-to-source voltage V_GSto a predetermined threshold voltage. In at least one embodiment, a high-resolution counter included in timer circuit 414 external to driver controller circuit 404 provides time information.
The variable current drive technique partitions a transition process into multiple phases that have independent characteristics such as current levels, threshold voltages, and time limits. In at least one embodiment, during operation, a multi-phase transition process of the high-power drive device is controlled using parameter values stored in working registers. In at least one embodiment, each parameter value is specified as an index into a corresponding look-up table of parameter values (e.g., voltage, current, or time values).
FIG. 7 illustrates exemplary variable current drive parameters for a two-phase turn-on process, a three-phase turn-off process, and a three-phase soft shutdown process described above, although other embodiments use other numbers of phases for turn-on, turn-off, or soft-shutdown. In at least one embodiment, working registers specify variable current drive parameter values for operating the gate driver in an exemplary automotive traction inverter application. For example, phase P_TON1of the multi-phase turn-on process described above is controlled by parameters stored in register ON_P1, e.g., register bits I_ON1, register bits t_ON1, and register bits V_{PLAT_ON}. Phase P_TON2of the multi-phase turn-on process described above is controlled by parameters stored in register ON_P2, e.g., register bits I_ON2, register bits t_ON2, and register bits V_{GSON_UV}. Phase P_TOFF1of the multi-phase turn-off process described above is controlled by parameters stored in register OFF_P1 stored in register bits I_OFF1, register bits t_OFF1, and register bits V_{PLAT_OFF}. Phase P_TOFF2of the multi-phase turn-off process described above is controlled by parameters stored in register OFF_P2, e.g., register bits tom and register bits V_MC. Phase P_TOFF3of the multi-phase turn-off process described above is controlled by parameters stored in register OFF_P3, register bits t_OFF3, and register bits V_{GSOFF_OV}. In at least one embodiment, a multi-phase soft shutdown process reuses the turn-off registers. In at least one embodiment, phase P_SS1of the soft shutdown process is controlled by parameters stored in register SS_P1, e.g., register bits t_SS1, and register bits V_{PLAT_SS}, phase P_SS2of the turn-off process is controlled by parameters stored in register SS_P2, e.g., register bits I_SS2and register bits t_SS2. In at least one embodiment, phase three and associated registers and register V_MCof phase two are unused by the exemplary soft shutdown process. In an exemplary embodiment, the register corresponding to each parameter stores a 3-bit index value that points to parameter values in associated parameter value tables. As referred to herein, a profile component is a stored set of parameter values for a phase of a multi-phase transition process (e.g., ON_P1 or OFF_P3). A variable current drive profile is a complete set of profile components for all multi-phase transitions of an embodiment of the variable current drive technique, representing values for ON_P1, ON_P2, OFF_P1, OFF_P2, OFF_P3, SS_P1, and SS_P2 in an exemplary embodiment.
In general, a package of an exemplary isolated gate driver product maintains an isolation barrier between two voltage domains and transfers heat generated by the enclosed die to the circuit board or surrounding air. A conventional isolated gate driver coupled to external gate resistors dissipates power generated during the turn-on process or turn-off process of the high-power drive device using the external gate resistors and internal resistance of the gate driver. The internal resistance of the conventional isolated gate driver is typically substantially smaller than the external gate resistance, causing the external gate resistors to dissipate most of the power. In at least one embodiment of a driver product, the elimination of external gate resistors increases the amount of power dissipated by a gate driver integrated circuit. The isolation barrier requirements impose an increased distance between pins on opposite sides of the isolation barrier and an exposed paddle (e.g., a thermally conductive plate or metal pad external to a package) or other heat sink structure. Thus, the isolation barrier or power dissipation specifications may require a custom-designed package, which increases cost. In the absence of external gate resistors, or if smaller external gate resistance is used, the gate driver integrated circuit dissipates a substantial portion of the power required to turn-on or turn-off the high-power drive device. When driving high-power drive devices, the power dissipation capability of the gate driver integrated circuit may limit packaging options to those packages that include enhanced power dissipation features, e.g., an exposed paddle. Use of enhanced power dissipation features on a package that also maintains an isolation barrier increases the size of package, may require a custom-designed package, and thus, increases cost of the driver product.
A multi-die, distributed package technique addresses power dissipation requirements for a driver product based on the size and associated power dissipation needs of the high-power drive device used in the target application. In at least one embodiment of a driver product, multiple die are distributed across multiple packages, e.g., one package provides galvanic isolation and at least one other package dissipates power of the variable strength driver circuit. FIGS. 8, 9, and 10 illustrate exemplary embodiments of the multi-die, distributed package technique.
In at least one embodiment of a low-power driver product, two integrated circuit die implement low-voltage control and galvanic isolation, and a third integrated circuit die includes the variable strength driver. All three die reside in the same package and modest thermal conductivity requirements for the low-power driver applications are achieved without an exposed-paddle package. Referring to FIG. 8, in at least one embodiment, driver product 700 includes package 702, which houses primary side integrated circuit die 704, isolation barrier 706, secondary side integrated circuit die 708 and variable current driver integrated circuit die 710. Primary-side integrated circuit die 704 is isolated from secondary-side integrated circuit die 708 by isolation barrier 706. Primary-side integrated circuit die 704 receives control signal CTL (e.g., a pulse-width modulated control signal) and communicates the received control signal to secondary-side integrated circuit die 708 across isolation barrier 706. Variable current driver die 710 drives low-power system 712 according to the control signal.
Low-power system 712 includes a small-sized high-power drive device, e.g., a high-power drive device used in low-power applications. Thus, a single package is sufficient to maintain the isolation barrier and to dissipate the power generated by the gate driver low-voltage control functions and variable current drive of the gate driver in low-power system 712. Relatively small high-power drive devices have low input capacitance C_GATE. The power dissipated by variable current driver die 710 is relatively low and one low-cost package including standard power dissipation features is sufficient to provide an isolation barrier and power dissipation for primary-side integrated circuit die 704, secondary-side integrated circuit die 708, and variable strength driver die 710. Signaling between the secondary integrated circuit die 708 and variable current driver die 710 includes the PWM signaling, which indicates the target on or off state for the external high-power drive device, and additional configuration, status and control signaling required between secondary integrated circuit die 708 and variable current driver die 710. In at least one embodiment of driver product 700, these signal connections remain within the package.
In at least one embodiment, a driver product uses two packages to house the integrated circuit die that provide isolation and drive capabilities to a medium-size high-power drive device in an application that consumes more power than a low-power application. A first package houses the integrated circuit die that provide isolation and low-voltage control functions. The first package maintains the isolation barrier and does not have demanding thermal conductivity requirements. A second package having enhanced power dissipation characteristics (e.g., exposed paddle or external metal pad) houses the variable current driver die. Referring to FIG. 9, medium-power system 816 includes a medium-sized high-power drive device that has a medium-sized input capacitance C_GATE. In this embodiment, a substantial amount of power is dissipated by variable current driver die 710 and may not be appropriately conducted by a package without enhanced power dissipation features. In at least one embodiment of driver product 800, package 802 is a low-power package including standard power dissipation features and houses isolation barrier 706, primary-side integrated circuit die 704, and secondary-side integrated circuit die 708. Package 810 includes enhanced power dissipation features and houses variable current driver die 710. In this two-package implementation, received control signal CTL and configuration, status, and control signaling CTRL between secondary-side integrated circuit die 708 and variable current driver die 710 use external package pins and external coupling. In at least one embodiment of driver product 800, the signaling uses parallel logic signals, a serial communication protocol (e.g., SPI bus), or combination thereof. In at least one embodiment of driver product 800, to improve conducted and radiated immunity and to reduce conducted and radiated emissions, differential signaling is utilized for the signaling between packages, although single-ended signaling may be used in other embodiments.
In at least one embodiment, a driver product drives large-sized high-power drive devices using a first package housing integrated circuit die that provide isolation and low-voltage control functions, and two or more power-dissipation-enhanced packages that house corresponding variable strength driver stages that are coupled in parallel. Referring to FIG. 10, driver product 900 includes high-power system 916, which includes a relatively large-size high-power drive device that has a relatively large input capacitance C_GATE. The power dissipated by variable current driver die 710 may exceed the capabilities of package 810, which includes paddle 814 to enhance power dissipation capability. At least one additional package including paddle 914 houses variable current driver die 910, which is another instantiation of the variable current driver die. Variable current driver die 710 and variable current driver die 910 are configured to drive at least two high-power drive devices in high-power system 916. Referring to FIG. 11, rather than couple variable current driver die 810 and variable current driver die 910 in parallel, configuring couple variable current driver die 810 and variable current driver die 910 to separately drive corresponding high-power drive devices that are coupled in parallel in high-power system 916 provides redundancy in the event that one of the variable current driver die is shorted to ground. The use of two or more variable strength driver die in separate packages, provides redundancy that enables operation at a reduced system power level in response to a failure of a high-power drive device in high-power system 916. Referring to FIGS. 10 and 11, in addition to enhancing power dissipation capabilities, separation of the variable current driver die into separate high-power packages positioned closer to the corresponding high-power drive device reduces the gate current loop. The multi-die, distributed packaging technique using two or more packages reduces system cost, while providing a variable strength drive solution for various levels of system power requirements.
Thus, a variable current drive technique that uses a variable strength driver and associated control that partitions a transition process (i.e., a turn-on process or a turn-off process) of the high-power drive device into a multi-phase transition process having multiple phases that can have different driver settings is disclosed. The use of variable current drive reduces or eliminates the need for external gate resistors for control of turn-on and turn-off transitions. The use of multiple current settings during turn-on or turn-off of a high-power drive device improves the turn-on and turn-off processes (e.g., improves efficiency, reduces EMI, or reduces drain-to-source voltage Vus and gate-to-source voltage V_GSvoltage stress) as compared to a conventional gate driver approach. The reduction or elimination of external gate resistors allows the gate driver circuit to be positioned closer to the high-power drive device, thereby reducing inductance and area of a gate loop (i.e., the area enclosed by the gate current loop). Reducing the inductance of the gate loop can reduce ringing of the gate signal. Reducing the area of the gate current loop can reduce radiated emissions and can improve the radiated immunity of the circuit. The variable current drive technique and scalable packing solutions use fewer pins and fewer external components than other techniques that use a gate driver with multiple outputs for turn-on and multiple outputs for turn-off of the high power drive device.
The description of the invention set forth herein is illustrative and is not intended to limit the scope of the invention as set forth in the following claims. For example, while the invention has been described in an embodiment in which a driver product is used in a motor application using two turn-on phases and three turn-off phases, one of skill in the art will appreciate that the teachings herein can be utilized in other applications and other numbers of turn-on phases or turn-off phases. In addition, while the invention has been described in an embodiment where variable strength driver 402 uses current DACs, one of skill in the art will appreciate that the teachings herein can be utilized with other variable strength driver topologies (e.g., variable strength driver including digitally controllable inverter segments). Variations and modifications of the embodiments disclosed herein, may be made based on the description set forth herein, without departing from the scope of the invention as set forth in the following claims.

Claims

1. A method for controlling a high-power drive device, the method comprising:

providing a signal having a first predetermined signal level to an output node during a first phase of a multi-phase transition process;

generating a first indication of a first parameter associated with the signal provided to the output node;

generating a second indication of a second parameter associated with the signal provided to the output node, in the first phase, the second parameter being a time elapsed from a start of the first phase;

providing the signal having a second predetermined signal level to the output node during a second phase of the multi-phase transition process; and

transitioning from the first phase to the second phase based on the first indication and the second indication.

2. The method as recited in claim 1 further comprising entering the first phase of the multi-phase transition process in response to a received control signal changing from a first signal level to a second signal level and in the absence of a fault condition.

3. The method as recited in claim 2 further comprising delaying entry into the first phase of the multi-phase transition process from a state providing the signal having a third predetermined signal level.

4. The method as recited in claim 1 wherein the signal is a current and the first predetermined signal level is greater than the second predetermined signal level.

5. The method as recited in claim 1 wherein transitioning from the first phase to the second phase is in response to the first parameter exceeding a first threshold value or the second parameter exceeding a second threshold value.

6. The method as recited in claim 5 wherein the multi-phase transition process is a turn-on process for the high-power drive device coupled to the output node, in the first phase, the first parameter is a sensed voltage level on the output node, and the first threshold value corresponds to a Miller plateau turn-on voltage of the high-power drive device and the second threshold value corresponds to a time limit for the first phase.

7. The method as recited in claim 5 wherein the multi-phase transition process is a turn-off process for the high-power drive device coupled to the output node, in the first phase, the first parameter is a sensed voltage level on the output node and the first threshold value corresponds to a Miller plateau turn-off voltage of the high-power drive device, and, in the second phase, a third threshold value corresponds to a Miller clamp voltage of the high-power drive device.

8. The method as recited in claim 7 further comprising:

providing the signal having a third predetermined signal level to the output node during a third phase of the multi-phase transition process based on the first indication or the second indication; and

transitioning from the second phase to the third phase in response to the first parameter falling below a third predetermined threshold level, the second predetermined signal level being less than the third predetermined signal level.

9. The method as recited in claim 1 wherein the signal is a current and the method further comprises converting a multi-bit digital control signal to the current having the first predetermined signal level, and the transitioning comprises updating the multi-bit digital control signal from a first value corresponding to the first predetermined signal level to a second value corresponding to the second predetermined signal level.

10. A system for controlling a high-power drive device, the system comprising:

an output node of a driver circuit;

a variable strength driver circuit of the driver circuit, the variable strength driver circuit being coupled to the output node and configured to provide a signal to the output node, the signal having a strength based on a multi-bit digital control signal;

an indicator circuit of the driver circuit, the indicator circuit being configured to generate a first indication of a first parameter associated with the signal;

a timer circuit of the driver circuit, the timer circuit being configured to generate a second indication of a second parameter associated with the signal; and

a driver controller circuit of the driver circuit, the driver controller circuit being responsive to a received control signal, a predetermined profile of a multi-phase transition process, the first indication, and the second indication to generate the multi-bit digital control signal.

11. The system as recited in claim 10 wherein the driver controller circuit is further responsive to a fault indication signal.

12. The system as recited in claim 10 wherein the signal is a current and the variable strength driver circuit comprises:

a first current digital-to-analog converter circuit configured to generate a turn-on voltage, the first current digital-to-analog converter circuit including a first current mirror with a fixed input stage and a first selectively configurable output stage, and a first reservoir capacitor coupled in parallel with a first diode-coupled input device of the fixed input stage, the first reservoir capacitor being coupled to ground; and

a second current digital-to-analog converter circuit configured to generate a turn-off voltage, the second current digital-to-analog converter circuit including a second current mirror with a second fixed input stage and a second selectively configurable output stage, and a second reservoir capacitor coupled in parallel with a second diode-coupled input device of the fixed input stage, the second reservoir capacitor being coupled to a power supply node.

13. The system as recited in claim 10 further comprising a storage element configured to store the predetermined profile of the multi-phase transition process, the predetermined profile including a first control value corresponding to a first target signal level of a first phase of the multi-phase transition process, a second control value corresponding to a second target signal level of the multi-phase transition process, a first predetermined threshold value, and a second predetermined threshold value.

14. The system as recited in claim 13 wherein the multi-phase transition process is a turn-on process for the high-power drive device coupled to the output node and in the first phase of the multi-phase transition process, the first parameter is a sensed voltage level on the output node and the second parameter is a time from a start of the first phase, the signal is an output current, the first target signal level is greater than the second target signal level, the first predetermined threshold value corresponds to a Miller plateau turn-on voltage of the high-power drive device, and the second predetermined threshold value corresponds to a time limit for the first phase.

15. The system as recited in claim 13 wherein the multi-phase transition process is a turn-off process for the high-power drive device coupled to the output node and in the first phase of the multi-phase transition process, the first parameter is a sensed voltage level on the output node and the second parameter is a time from a start of the first phase, the signal is an output current and the first target signal level is greater than the second target signal level, the first predetermined threshold value corresponds to a Miller plateau turn-off voltage of the high-power drive device, and the second predetermined threshold value corresponds to a time limit for the first phase.

16. The system as recited in claim 15 wherein the multi-phase transition process includes a third phase, the predetermined profile includes a third control value corresponding to a third target signal level and includes a third predetermined threshold value, the third target signal level is greater than the first target signal level and greater than the second target signal level, and the third predetermined threshold value corresponds to a Miller clamp voltage of the high-power drive device.

17. The system as recited in claim 10 further comprising:

a first integrated circuit die and a second integrated circuit die implementing low-voltage control and isolation features;

a third integrated circuit die including the output node, the variable strength driver circuit, and the indicator circuit; and

a package housing the first integrated circuit die, the second integrated circuit die, and the third integrated circuit die.

18. The system as recited in claim 10 further comprising:

a third integrated circuit die including the output node, the variable strength driver circuit, and the indicator circuit;

a first package housing the first integrated circuit die and the second integrated circuit die; and

a second package housing the third integrated circuit die, the first package including standard power-dissipation features and the second package including enhanced power-dissipation features.

19. The system as recited in claim 10 further comprising:

a fourth integrated circuit die comprising a second output node, a second variable strength driver circuit, and a second indicator circuit;

a first package housing the first integrated circuit die and the second integrated circuit die;

a second package housing the third integrated circuit die; and

a third package housing the fourth integrated circuit die, the first package including standard power-dissipation features and the second package and the third package each including enhanced power-dissipation features, and the output node being coupled to the high-power drive device and the second output node being coupled to the high-power drive device or a second high-power drive device.

20. A system for controlling a high-power drive device comprising:

an output node;

a variable strength driver circuit configured to provide a signal to the output node having a signal level based on a multi-bit digital control signal; and

a control circuit configured to generate the multi-bit digital control signal based on a received control signal, a fault indicator signal, a predetermined profile of a multi-phase transition process, a first indication of a first parameter associated with the signal, and a second indication of a second parameter associated with the signal.

21. The method as recited in claim 1 wherein the multi-phase transition process is a turn-on process for the high-power drive device or a turn-off process for the high-power drive device.