US20210213746A1

US20210213746A1 - Logic circuitry package

Info

Publication number: US20210213746A1
Application number: US16/767,582
Authority: US
Inventors: James Michael Gardner; Sirena Lu; Scott A. Linn
Original assignee: Hewlett Packard Development Co LP
Current assignee: Hewlett Packard Development Co LP
Priority date: 2018-12-03
Filing date: 2019-10-25
Publication date: 2021-07-15
Also published as: EP3933628A1; CN113168487A; US20210213751A1; BR112021010806A2; EP3688639A1; US11331924B2; CN113168446A; BR112021010632A2; US20210240400A1; US20210372840A1; US20210213748A1; US11345158B2; CN113165389A; US20210224219A1; KR20210087977A; CN113168455A; US11407228B2; BR112021010744A2; WO2020117390A1; EP3687818A1

Abstract

A logic circuitry package for a replaceable print apparatus component includes a first at least one analog cell of a first type, a second at least one analog cell of a second type, an analog-digital converter (ADC), an interface to communicate with a print apparatus logic circuit, and at least one logic circuit. The at least one logic circuit is configured to receive, via the interface, requests to perform measurements to selected ones of the at least one first and second analog cells. The at least one logic circuit is configured to selectively route analog signals from the selected analog cells to the ADC based on the requests.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This PCT Application claims the benefit of PCT Application No. PCT/US2019/026133, filed Apr. 5, 2019, entitled “LOGIC CIRCUITRY”; PCT Application No. PCT/US2019/026152, filed Apr. 5, 2019, entitled “FLUID PROPERTY SENSOR”; PCT Application No. PCT/US2019/026161, filed Apr. 5, 2019, entitled “LOGIC CIRCUITRY”; and PCT Application No. PCT/US2018/063631, filed Dec. 3, 2018, entitled “LOGIC CIRCUITRY”; all of which are incorporated herein by reference.

BACKGROUND

Subcomponents of apparatus may communicate with one another in a number of ways. For example, Serial Peripheral Interface (SPI) protocol, Bluetooth Low Energy (BLE), Near Field Communications (NFC) or other types of digital or analog communications may be used.
Some two-dimensional (2D) and three-dimensional (3D) printing systems include one or more replaceable print apparatus components, such as print material containers (e.g., inkjet cartridges, toner cartridges, ink supplies, 3D printing agent supplies, build material supplies etc.), inkjet printhead assemblies, and the like. In some examples, logic circuitry associated with the replaceable print apparatus component(s) communicate with logic circuitry of the print apparatus in which they are installed, for example communicating information such as their identity, capabilities, status and the like. In further examples, print material containers may include circuitry to execute one or more monitoring functions such as print material level sensing.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates one example of a printing system.

FIG. 2 illustrates one example of a replaceable print apparatus component.

FIG. 3 illustrates one example of a print apparatus.

FIGS. 4A-4E illustrate examples of logic circuitry packages and processing circuitry.

FIG. 5A illustrates one example arrangement of a fluid level sensor.

FIG. 5B illustrates a perspective view of one example of a print cartridge.

FIG. 6 illustrates another example of processing circuitry.

FIG. 7 illustrates one example of a memory of a logic circuitry package.

FIG. 8 illustrates another example of processing circuitry.

FIGS. 9A-9C are flow diagrams illustrating one example of a method that may be carried out by a logic circuitry package.

FIGS. 10A-10B are flow diagrams illustrating another example of a method that may be carried out by a logic circuitry package.

FIG. 11 illustrates another example of a logic circuitry package.

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific examples in which the disclosure may be practiced. It is to be understood that other examples may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims. It is to be understood that features of the various examples described herein may be combined, in part or whole, with each other, unless specifically noted otherwise.
Some examples of applications described herein are in the context of print apparatus. Not all the examples, however, are limited to such applications, and at least some of the principles set out herein may be used in other contexts. The contents of other applications and patents cited in this disclosure are incorporated by reference.
In certain examples, Inter-integrated Circuit (I²C, or I2C, which notation is adopted herein) protocol allows at least one ‘master’ integrated circuit (IC) to communicate with at least one ‘slave’ IC, for example via a bus. I2C, and other communications protocols, communicate data according to a clock period. For example, a voltage signal may be generated, where the value of the voltage is associated with data. For example, a voltage value above X volts may indicate a logic “1” whereas a voltage value below X volts may indicate a logic “0”, where X is a predetermined numerical value. By generating an appropriate voltage in each of a series of clock periods, data can be communicated via a bus or another communication link.
Certain example print material containers have slave logic that utilize I2C communications, although in other examples, other forms of digital or analog communications could also be used. In the example of I2C communication, a master IC may generally be provided as part of the print apparatus (which may be referred to as the ‘host’) and a replaceable print apparatus component would comprise a ‘slave’ IC, although this need not be the case in all examples. There may be a plurality of slave ICs connected to an I2C communication link or bus (for example, containers of different colors of print agent). The slave IC(s) may include a processor to perform data operations before responding to requests from logic circuitry of the print system.
Communications between print apparatus and replaceable print apparatus components installed in the apparatus (and/or the respective logic circuitry thereof) may facilitate various functions. Logic circuitry within a print apparatus may receive information from logic circuitry associated with a replaceable print apparatus component via a communications interface, and/or may send commands to the replaceable print apparatus component logic circuitry, which may include commands to write data to a memory associated therewith, or to read data therefrom.
One example of logic circuitry associated with a replaceable print apparatus component may include two arrays of sensor cells of different types (e.g., a first array of ink level sensor cells, and a second array of strain gauge sensor cells) and a plurality of other individual sensors (e.g., global thermal sensor, thermal diode, crack detect sensor, etc.) embedded on print material sensing circuitry. The logic circuitry may include multiplexing circuitry to selectively route analog sensor signals from the sensors to an analog to digital converter (ADC). The multiplexing circuitry may also route analog sensor signals from a first subset of the sensors to a first signal conditioning circuit (e.g., a circuit that includes a single-ended amplifier), and route analog sensor signals from a second subset of the sensors to a second signal conditioning circuit (e.g., a circuit that includes a differential to single-ended amplifier and the single-ended amplifier). The signal conditioning circuits may uniquely calibrate each sensor's measurement with different analog properties (e.g., using variable gain and offset values).
In at least some of the examples described below, a logic circuitry package is described. The logic circuitry package may be associated with a replaceable print apparatus component, for example being internally or externally affixed thereto, for example at least partially within the housing, and is adapted to communicate data with a print apparatus controller via a bus provided as part of the print apparatus.
A ‘logic circuitry package’ as the term is used herein refers to one logic circuit, or more logic circuits that may be interconnected or communicatively linked to each other. Where more than one logic circuit is provided, these may be encapsulated as a single unit, or may be separately encapsulated, or not encapsulated, or some combination thereof. The package may be arranged or provided on a single substrate or a plurality of substrates. In some examples, the package may be directly affixed to a cartridge wall. In some examples, the package may include an interface, for example including pads or pins. The package interface may be intended to connect to a communication interface of the print apparatus component that in turn connects to a print apparatus logic circuit, or the package interface may connect directly to the print apparatus logic circuit. Example packages may be configured to communicate via a serial bus interface. Where more than one logic circuit is provided, these logic circuits may be connected to each other or to the interface, to communicate through the same interface.
In some examples, each logic circuitry package is provided with at least one processor and memory. In one example, the logic circuitry package may be, or may function as, a microcontroller or secure microcontroller. In use, the logic circuitry package may be adhered to or integrated with the replaceable print apparatus component. A logic circuitry package may alternatively be referred to as a logic circuitry assembly, or simply as logic circuitry or processing circuitry.
In some examples, the logic circuitry package may respond to various types of requests (or commands) from a host (e.g., a print apparatus). A first type of request may include a request for data, for example identification and/or authentication information. A second type of request from a host may be a request to perform a physical action, such as performing at least one measurement. A third type of request may be a request for a data processing action. There may be additional types of requests.
In some examples, there may be more than one address associated with a particular logic circuitry package, which is used to address communications sent over a bus to identify the logic circuitry package which is the target of a communication (and therefore, in some examples, with a replaceable print apparatus component). In some examples, different requests are handled by different logic circuits of the package. In some examples, the different logic circuits may be associated with different addresses. For example, cryptographically authenticated communications may be associated with secure microcontroller functions and a first I2C address, while other communications may be associated with a sensor circuit and a second and/or reconfigured I2C address. In certain examples, these other communications via the second and/or reconfigured address can be scrambled or otherwise secured, not using the encryption key used for the secure microcontroller functions.
In at least some examples, a plurality of such logic circuitry packages (each of which may be associated with a different replaceable print apparatus component) may be connected to an I2C bus. In some examples, at least one address of the logic circuitry package may be an I2C compatible address (herein after, an I2C address), for example in accordance with an I2C protocol, to facilitate directing communications between master to slaves in accordance with the I2C protocol. In other examples, other forms of digital and/or analog communication can be used.
FIG. 1 illustrates one example of a printing system 100. The printing system 100 includes a print apparatus 102 in communication with logic circuitry associated with a replaceable print apparatus component 104 via a communications link 106. In some examples, the communications link 106 may include an I2C capable or compatible bus (herein after, an I2C bus). Although for clarity, the replaceable print apparatus component 104 is shown as external to the print apparatus 102, in some examples, the replaceable print apparatus component 104 may be housed within the print apparatus.
The replaceable print apparatus component 104 may include, for example, a print material container or cartridge (which could be a build material container for 3D printing, a liquid or dry toner container for 2D printing, or an ink or liquid print agent container for 2D or 3D printing), which may in some examples include a print head or other dispensing or transfer component. The replaceable print apparatus component 104 may, for example, contain a consumable resource of the print apparatus 102, or a component which is likely to have a lifespan which is less (in some examples, considerably less) than that of the print apparatus 102. Moreover, while a single replaceable print apparatus component 104 is shown in this example, in other examples, there may be a plurality of replaceable print apparatus components, for example including print agent containers of different colors, print heads (which may be integral to the containers), or the like. In other examples, the print apparatus components 104 could include service components, for example to be replaced by service personnel, examples of which could include print heads, toner process cartridges, or logic circuit package by itself to adhere to corresponding print apparatus component and communicate to a compatible print apparatus logic circuit.
FIG. 2 illustrates one example of a replaceable print apparatus component 200, which may provide the replaceable print apparatus component 104 of FIG. 1. The replaceable print apparatus component 200 includes a data interface 202 and a logic circuitry package 204. In use of the replaceable print apparatus component 200, the logic circuitry package 204 decodes data received via the data interface 202. The logic circuitry may perform other functions as set out below. The data interface 202 may include an I2C or other interface. In certain examples, the data interface 202 may be part of the same package as the logic circuitry package 204.
In some examples, the logic circuitry package 204 may be further configured to encode data for transmission via the data interface 202. In some examples, there may be more than one data interface 202 provided. In some examples, the logic circuitry package 204 may be arranged to act as a ‘slave’ in I2C communications.
FIG. 3 illustrates one example of a print apparatus 300. The print apparatus 300 may provide the print apparatus 102 of FIG. 1. The print apparatus 300 may serve as a host for replaceable components. The print apparatus 300 includes an interface 302 for communicating with a replaceable print apparatus component and a controller 304. The controller 304 includes logic circuitry. In some examples, the interface 302 is an I2C interface.
In some examples, controller 304 may be configured to act as a host, or a master, in I2C communications. The controller 304 may generate and send commands to at least one replaceable print apparatus component 200, and may receive and decode responses received therefrom. In other examples the controller 304 may communicate with the logic circuitry package 204 using any form of digital or analog communication.
The print apparatus 102, 300 and replaceable print apparatus component 104, 200, and/or the logic circuitry thereof, may be manufactured and/or sold separately. In an example, a user may acquire a print apparatus 102, 300 and retain the apparatus 102, 300 for a number of years, whereas a plurality of replaceable print apparatus components 104, 200 may be purchased in those years, for example as print agent is used in creating a printed output. Therefore, there may be at least a degree of forwards and/or backwards compatibility between print apparatus 102, 300 and replaceable print apparatus components 104, 200. In many cases, this compatibility may be provided by the print apparatus 102, 300 as the replaceable print apparatus components 104, 200 may be relatively resource constrained in terms of their processing and/or memory capacity.
FIG. 4A illustrates one example of a logic circuitry package 400 a, which may for example provide the logic circuitry package 204 described in relation to FIG. 2. The logic circuitry package 400 a may be associated with, or in some examples affixed to and/or be incorporated at least partially within, a replaceable print apparatus component 200.
In some examples, the logic circuitry package 400 a is addressable via a first address and includes a first logic circuit 402 a, wherein the first address is an I2C address for the first logic circuit 402 a. In some examples, the first address may be configurable. In other examples, the first address is a fixed address (e.g., “hard-wired”) intended to remain the same address during the lifetime of the first logic circuit 402 a. The first address may be associated with the logic circuitry package 400 a at and during the connection with the print apparatus logic circuit, outside of the time periods that are associated with a second address, as will be set out below. In example systems where a plurality of replaceable print apparatus components are to be connected to a single print apparatus, there may be a corresponding plurality of different first addresses. In certain examples, the first addresses can be considered standard I2C addresses for logic circuitry packages 400 a or replaceable print components.
In some examples, the logic circuitry package 400 a is also addressable via a second address. For example, the second address may be associated with different logic functions or, at least partially, with different data than the first address. In some examples, the second address may be associated with a different hardware logic circuit or a different virtual device than the first address. In some examples, the logic circuitry package 400 a may include a memory to store the second address (in some examples in a volatile manner). In some examples, the memory may include a programmable address memory register for this purpose. The second address may have a default second address while the second address (memory) field may be reconfigurable to a different address. For example, the second address may be reconfigurable to a temporary address by a second address command, whereby it is set (back) to the default second address after or at each time period command to enable the second address. For example, the second address may be set to its default address in an out-of-reset state whereby, after each reset, it is reconfigurable to the temporary (i.e., reconfigured) address.
In some examples, the package 400 a is configured such that, in response to a first command indicative of a first time period sent to the first address (and in some examples a task), the package 400 a may respond in various ways. In some examples, the package 400 a is configured such that it is accessible via at least one second address for the duration of the time period. Alternatively or additionally, in some examples, the package may perform a task, which may be the task specified in the first command. In other examples, the package may perform a different task. The first command may, for example, be sent by a host such as a print apparatus in which the logic circuitry package 400 a (or an associated replaceable print apparatus component) is installed. As set out in greater detail below, the task may include obtaining a sensor reading.
Further communication may be directed to memory addresses to be used to request information associated with these memory addresses. The memory addresses may have a different configuration than the first and second address of the logic circuitry package 400 a. For example, a host apparatus may request that a particular memory register is read out onto the bus by including the memory address in a read command. In other words, a host apparatus may have a knowledge and/or control of the arrangement of a memory. For example, there may be a plurality of memory registers and corresponding memory addresses associated with the second address. A particular register may be associated with a value, which may be static or reconfigurable. The host apparatus may request that the register be read out onto the bus by identifying that register using the memory address. In some examples, the registers may include any or any combination of address register(s), parameter register(s) (for example to store clock enable, clock source replacement, clock divider, and/or dither parameters), sensor identification register(s) (which may store an indication of a type of sensor), sensor reading register(s) (which may store values read or determined using a sensor), sensor number register(s) (which may store a number or count of sensors), version identity register(s), memory register(s) to store a count of clock cycles, memory register(s) to store a value indicative of a read/write history of the logic circuitry, or other registers.
FIG. 4B illustrates another example of a logic circuitry package 400 b. In this example, the package 400 b includes a first logic circuit 402 b, in this example, including a first timer 404 a, and a second logic circuit 406 a, in this example, including a second timer 404 b. While in this example, each of the first and second logic circuits 402 b, 406 a include its own timer 404 a, 404 b, in other examples, they may share a timer or reference at least one external timer. In a further example, the first logic circuit 402 b and the second logic circuit 406 a are linked by a dedicated signal path 408.
In one example, the logic circuitry package 400 b may receive a first command including two data fields. A first data field is a one byte data field setting a requested mode of operation. For example, there may be a plurality of predefined modes, such as a first mode, in which the logic circuitry package 400 b is to ignore data traffic sent to the first address (for example, while performing a task), and a second mode in which the logic circuitry package 400 b is to ignore data traffic sent to the first address and to transmit an enable signal to the second logic circuit 406 a, as is further set out below. The first command may include additional fields, such as an address field and/or a request for acknowledgement.
The logic circuitry package 400 b is configured to process the first command. If the first command cannot be complied with (for example, a command parameter is of an invalid length or value, or it is not possible to enable the second logic circuit 406 a), the logic circuitry package 400 b may generate an error code and output this to a communication link to be returned to host logic circuitry, for example in the print apparatus.
If, however, the first command is validly received and can be complied with, the logic circuitry package 400 b measures the duration of the time period included in the first command, for example utilizing the timer 404 a. In some examples, the timer 404 a may include an RC circuit, a ring oscillator, or some other form of oscillator or timer. In this example, in response to receiving a valid first command, the first logic circuit 402 b enables the second logic circuit 406 a and effectively disables the first address, for example by tasking the first logic circuit 402 b with a processing task. In some examples, enabling the second logic circuit 406 a includes sending, by the first logic circuit 402 b, an activation signal to the second logic circuit 406 a. In other words, in this example, the logic circuitry package 400 b is configured such that the second logic circuit 406 a is selectively enabled by the first logic circuit 402 b.
In this example, the second logic circuit 406 a is enabled by the first logic circuit 402 b sending a signal via a signal path 408, which may or may not be a dedicated signal path 408, that is, dedicated to enable the second logic circuit 406 a. In one example, the first logic circuit 402 b may have a dedicated contact pin or pad connected to the signal path 408, which links the first logic circuit 402 b and the second logic circuit 406 a. In a particular example, the dedicated contact pin or pad may be a General Purpose Input/Output (a GPIO) pin of the first logic circuit 402 b. The contact pin/pad may serve as an enablement contact of the second logic circuit 406 a.
In this example, the second logic circuit 406 a is addressable via at least one second address. In some examples, when the second logic circuit 406 a is activated or enabled, it may have an initial, or default, second address, which may be an I2C address or have some other address format. The second logic circuit 406 a may receive instructions from a master or host logic circuitry to change the initial address to a temporary second address. In some examples, the temporary second address may be an address which is selected by the master or host logic circuitry. This may allow the second logic circuit 406 a to be provided in one of a plurality of packages 400 on the same I2C bus which, at least initially, share the same initial second address. This shared, default, address may later be set to a specific temporary address by the print apparatus logic circuit, thereby allowing the plurality of packages to have different second addresses during their temporary use, facilitating communications to each individual package. At the same time, providing the same initial second address may have manufacturing or testing advantages.
In some examples, the second logic circuit 406 a may include a memory. The memory may include a programmable address register to store the initial and/or temporary second address (in some examples in a volatile manner). In some examples, the second address may be set following, and/or by executing, an I2C write command. In some examples, the second address may be settable when the enablement signal is present or high, but not when it is absent or low. The second address may be set to a default address when an enablement signal is removed and/or on restoration of enablement of the second logic circuit 406 a. For example, each time the enable signal over the signal path 408 is low, the second logic circuit 406 a, or the relevant part(s) thereof, may be reset. The default address may be set when the second logic circuit 406 a, or the relevant part(s) thereof, is switched out-of-reset. In some examples, the default address is a 7-bit or 10-bit identification value. In some examples, the default address and the temporary second address may be written in turn to a single, common, address register.
In the example illustrated in FIG. 4B, the second logic circuit 406 a includes a first array 410 of cells and at least one second cell 412 or second array of second cells of a different type than the cells of the first array 410. In some examples, the second logic circuit 406 a may include additional sensor cells of a different type than the cells of the first array 410 and the at least one second cell 412. Each of the plurality of sensor types may be identifiable by a different sensor ID, while each cell in a cell array of the same type may be identifiable by sub-IDs. The sensor IDs and sub-IDs may include a combination of addresses and values, for example register addresses and values. The addresses of the sensor ID and sub-ID are different. For example, an address selects a register that has a function to select a particular sensor or cell, and in the same transaction, the value selects the sensor or cell, respectively. Hence, the second logic circuit may include registers and multiplex circuitry to select sensor cells in response to sensor IDs and sub-IDs.
The first cells 416 a-416 f, 414 a-414 f and the at least one second cell 412 can include resistors. The first cells 416 a-416 f, 414 a-414 f and the at least one second cell 412 can include sensors. In one example, the first cell array 410 includes a print material level sensor and the at least one second cell 412 includes another sensor and/or another sensor array, such as an array of strain sensing cells. Further sensor types may include temperature sensors, resistors, diodes, crack sensors, etc.
In this example, the first cell array 410 includes a sensor configured to detect a print material level of a print supply, which may in some examples be a solid but in examples described herein is a liquid, for example, an ink or other liquid print agent. The first cell array 410 may include a series of temperature sensors (e.g., cells 414 a-414 f) and a series of heating elements (e.g., cells 416 a-416 f), for example similar in structure and function as compared to the level sensor arrays described in WO2017/074342, WO2017/184147, and WO2018/022038. In this example, the resistance of a resistor cell 414 is linked to its temperature. The heater cells 416 may be used to heat the sensor cells 414 directly or indirectly using a medium. The subsequent behavior of the sensor cells 414 depends on the medium in which they are submerged, for example whether they are in liquid (or in some examples, encased in a solid medium) or in air. Those which are submerged in liquid/encased may generally lose heat quicker than those which are in air because the liquid or solid may conduct heat away from the resistor cells 414 better than air. Therefore, a liquid level may be determined based on which of the resistor cells 414 are exposed to the air, and this may be determined based on a reading of their resistance following (at least the start of) a heat pulse provided by the associated heater cell 416.
In some examples, each sensor cell 414 and heater cell 416 are stacked with one being directly on top of the other. The heat generated by each heater cell 416 may be substantially spatially contained within the heater element layout perimeter, so that heat delivery is substantially confined to the sensor cell 414 stacked directly above the heater cell 416. In some examples, each sensor cell 414 may be arranged between an associated heater cell 416 and the fluid/air interface.
In this example, the second cell array 412 includes a plurality of different cells that may have a different function such as different sensing function(s). For example, the first and second cell array 410, 412 may include different resistor types. Different cells arrays 410, 412 for different functions may be provided in the second logic circuit 406 a.
FIG. 4C illustrates an example of how a first logic circuit 402 c and a second logic circuit 406 b of a logic circuitry package 400 c, which may have any of the attributes of the circuits/packages described above, may connect to an I2C bus and to each other. As is shown in the Figure, each of the circuits 402 c, 406 b has four pads (or pins) 418 a-418 d connecting to the Power, Ground, Clock, and Data lines of an I2C bus. In another example, four common connection pads are used to connect both logic circuits 402 c, 406 b to four corresponding connection pads of the print apparatus controller interface. It is noted that in some examples, instead of four connection pads, there may be less connection pads. For example, power may be harvested from the clock pad; an internal clock may be provided; or the package could be grounded through another ground circuit; so that, one or more of the pads may be omitted or made redundant. Hence, in different examples, the package could use only two or three interface pads and/or could include “dummy” pads.
Each of the circuits 402 c, 406 b has a contact pin 420, which are connected by a common signal line 422. The contact pin 420 of the second circuit serves as an enablement contact thereof.
In this example, each of the first logic circuit 402 c and the second logic circuit 406 b include a memory 423 a, 423 b. The memory 423 a of the first logic circuit 402 c stores information including cryptographic values (for example, a cryptographic key and/or a seed value from which a key may be derived) and identification data and/or status data of the associated replaceable print apparatus component. In some examples, the memory 423 a may store data representing characteristics of the print material, for example, any part, or any combination of its type, color, color map, recipe, batch number, age, etc.
The memory 423 b of the second logic circuit 406 b includes a programmable address register to contain an initial address of the second logic circuit 406 b when the second logic circuit 406 b is first enabled and to subsequently contain a further (temporary) second address (in some examples in a volatile manner). The further, e.g., temporary, second address may be programmed into the second address register after the second logic circuit 406 b is enabled, and may be effectively erased or replaced at the end of an enablement period. In some examples, the memory 423 b may further include programmable registers to store any, or any combination of a read/write history data, cell (e.g., resistor or sensor) count data, Analog to Digital converter data (ADC and/or DAC), and a clock count, in a volatile or non-volatile manner. The memory 423 b may also receive and/or store calibration parameters, such as offset and gain parameters. Use of such data is described in greater detail below. Certain characteristics, such as cell count or ADC or DAC characteristics, could be derivable from the second logic circuit instead of being stored as separate data in the memory.
In one example, the memory 423 b of the second logic circuit 406 b stores any or any combination of an address, for example the second I2C address; an identification in the form of a revision ID; and the index number of the last cell (which may be the number of cells less one, as indices may start from 0), for example for each of different cell arrays or for multiple different cell arrays if they have the same number of cells.
In use of the second logic circuit 406 b, in some operational states, the memory 423 b of the second logic circuit 406 may store any or any combination of timer control data, which may enable a timer of the second circuit, and/or enable frequency dithering therein in the case of some timers such as ring oscillators; a dither control data value (to indicate a dither direction and/or value); and a timer sample test trigger value (to trigger a test of the timer by sampling the timer relative to clock cycles measureable by the second logic circuit 406 b).
While the memories 423 a, 423 b are shown as separate memories here, they could be combined as a shared memory resource, or divided in some other way. The memories 423 a, 423 b may include a single or multiple memory devices, and may include any or any combination of volatile memory (e.g., DRAM, SRAM, registers, etc.) and non-volatile memory (e.g., ROM, EEPROM, Flash, EPROM, memristor, etc.).
While one package 400 c is shown in FIG. 4C, there may be a plurality of packages with a similar or a different configuration attached to the bus.
FIG. 4D illustrates an example of processing circuitry 424 which is for use with a print material container. For example, the processing circuitry 424 may be affixed or integral thereto. As already mentioned, the processing circuitry 424 may include any of the features of, or be the same as, any other logic circuitry package of this disclosure.
In this example, the processing circuitry 424 includes a memory 426 and a first logic circuit 402 d which enables a read operation from memory 426. The processing circuitry 424 is accessible via an interface bus of a print apparatus in which the print material container is installed and is associated with a first address and at least one second address. The bus may be an I2C bus. The first address may be an I2C address of the first logic circuit 402 d. The first logic circuit 402 d may have any of the attributes of the other examples circuits/packages described in this disclosure.
The first logic circuit 402 d is adapted to participate in authentication of the print materials container by a print apparatus in which the container is installed. For example, this may include a cryptographic process such as any kind of cryptographically authenticated communication or message exchange, for example based on an encryption key stored in the memory 426, and which can be used in conjunction with information stored in the printer. In some examples, a printer may store a version of a key which is compatible with a number of different print material containers to provide the basis of a ‘shared secret’. In some examples, authentication of a print material container may be carried out based on such a shared secret. In some examples, the first logic circuit 402 d may participate in a message to derive a session key with the print apparatus and messages may be signed using a message authentication code based on such a session key. Examples of logic circuits configured to cryptographically authenticate messages in accordance with this paragraph are described in US patent publication No. 9619663.
In some examples, the memory 426 may store data including: identification data and read/write history data. In some examples, the memory 426 further includes cell count data (e.g., sensor count data) and clock count data. Clock count data may indicate a clock speed of a first and/or second timer 404 a, 404 b (i.e., a timer associated with the first logic circuit or the second logic circuit). In some examples, at least a portion of the memory 426 is associated with functions of a second logic circuit, such as a second logic circuit 406 a as described in relation to FIG. 4B above. In some examples, at least a portion of the data stored in the memory 426 is to be communicated in response to commands received via the second address. In some examples, the memory 426 includes a programmable address register or memory field to store a second address of the processing circuitry (in some examples in a volatile manner). The first logic circuit 402 d may enable read operation from the memory 426 and/or may perform processing tasks.
The memory 426 may, for example, include data representing characteristics of the print material, for example any or any combination of its type, color, batch number, age, etc. The memory 426 may, for example, include data to be communicated in response to commands received via the first address. The processing circuitry may include a first logic circuit to enable read operations from the memory and perform processing tasks.
In some examples, the processing circuitry 424 is configured such that, following receipt of the first command indicative of a task and a first time period sent to the first logic circuit 402 d via the first address, the processing circuitry 424 is accessible by at least one second address for a duration of the first time period. Alternatively or additionally, the processing circuitry 424 may be configured such that in response to a first command indicative of a task and a first time period sent to the first logic circuit 402 d addressed using the first address, the processing circuitry 424 is to disregard (e.g., ‘ignore’ or ‘not respond to’) I2C traffic sent to the first address for substantially the duration of the time period as measured by a timer of the processing circuitry 424 (for example a timer 404 a, 404 b as described above). In some examples, the processing circuitry may additionally perform a task, which may be the task specified in the first command. The term ‘disregard’ or ‘ignore’ as used herein with respect to data sent on the bus may include any or any combination of not receiving (in some examples, not reading the data into a memory), not acting upon (for example, not following a command or instruction) and/or not responding (i.e., not providing an acknowledgement, and/or not responding with requested data).
The processing circuitry 424 may have any of the attributes of the logic circuitry packages 400 described herein. In particular, the processing circuitry 424 may further include a second logic circuit wherein the second logic circuit is accessible via the second address. In some examples, the second logic circuit may include at least one sensor which is readable by a print apparatus in which the print material container is installed via the second address. In some examples, such a sensor may include a print materials level sensor.
FIG. 4E illustrates another example of a first logic circuit 402 e and second logic circuit 406 c of a logic circuitry package 400 d, which may have any of the attributes of the circuits/packages of the same names described herein, which may connect to an I2C bus via respective interfaces 428 a, 428 b and to each other. In one example the respective interfaces 428 a, 428 b are connected to the same contact pad array, with only one data pad for both logic circuits 402 e, 406 c, connected to the same serial I2C bus. In other words, in some examples, communications addressed to the first and the second address are received via the same data pad.
In this example, the first logic circuit 402 e includes a microcontroller 430, a memory 432, and a timer 434. The microcontroller 430 may be a secure microcontroller or customized integrated circuitry adapted to function as a microcontroller, secure or non-secure.
In this example, the second logic circuit 406 c includes a transmit/receive module 436, which receives a clock signal and a data signal from a bus to which the package 400 d is connected, data registers 438, a multiplexer 440, a digital controller 442, an analog bias and analog to digital converter 444, at least one sensor or cell array 446 (which may in some examples include a level sensor with one or multiple arrays of resistor elements), and a power-on reset (POR) device 448. The POR device 448 may be used to allow operation of the second logic circuit 406 c without use of a contact pin 420.
The analog bias and analog to digital converter 444 receives readings from the sensor array(s) 446 and from additional sensors. For example, a current may be provided to a sensing resistor and the resultant voltage may be converted to a digital value. That digital value may be stored in a register and read out (i.e., transmitted as serial data bits, or as a ‘bitstream’) over the I2C bus. The analog to digital converter 444 may utilize parameters, for example, gain and/or offset parameters, which may be stored in registers.
In this example, there are different additional single sensors, including for example at least one of an ambient temperature sensor 450, a crack detector 452, and/or a fluid temperature sensor 454. These may sense, respectively, an ambient temperature, a structural integrity of a die on which the logic circuitry is provided, and a fluid temperature.
FIG. 5A illustrates an example of a possible practical arrangement of a second logic circuit embodied by a sensor assembly 500 in association with a circuitry package 502. The sensor assembly 500 may include a thin film stack and include at least one sensor array such as a fluid level sensor array. The arrangement has a high length to width aspect ratio (e.g., as measured along a substrate surface), for example being around 0.2 mm in width, for example less than 1 mm, 0.5 mm, or 0.3 mm, and around 20 mm in length, for example more than 10 mm, leading to length to width aspect ratios equal to or above approximately 20:1, 40:1, 60:1, 80:1, or 100:1. In an installed condition the length may be measured along the height. The logic circuit in this example may have a thickness of less than 1 mm, less than 0.5 mm, or less than 0.3 mm, as measured between the bottom of the (e.g., silicon) substrate and the opposite outer surface. These dimensions mean that the individual cells or sensors are small. The sensor assembly 500 may be provided on a relatively rigid carrier 504, which in this example also carries Ground, Clock, Power and Data I2C bus contacts.
FIG. 5B illustrates a perspective view of a print cartridge 512 including a logic circuitry package of any of the examples of this disclosure. The print cartridge 512 has a housing 514 that has a width W less than its height H and that has a length L or depth that is greater than the height H. A print liquid output 516 (in this example, a print agent outlet provided on the underside of the cartridge 512), an air input 518 and a recess 520 are provided in a front face of the cartridge 512. The recess 520 extends across the top of the cartridge 512 and I2C bus contacts (i.e., pads) 522 of a logic circuitry package 502 (for example, a logic circuitry package 400 a-400 d as described above) are provided at a side of the recess 520 against the inner wall of the side wall of the housing 514 adjacent the top and front of the housing 514. In this example, the data contact is the lowest of the contacts 522. In this example, the logic circuitry package 502 is provided against the inner side of the side wall. In some examples, the logic circuitry package 502 includes a sensor assembly as shown in FIG. 5A.
Placing logic circuitry within a print material cartridge may create challenges for the reliability of the cartridge due to the risks that electrical shorts or damage can occur to the logic circuitry during shipping and user handling, or over the life of the product.
A damaged sensor may provide inaccurate measurements, and result in inappropriate decisions by a print apparatus when evaluating the measurements. Therefore, a method may be used to verify that communications with the logic circuitry based on a specific communication sequence provide expected results. This may validate the operational health of the logic circuitry.
In other examples, a replaceable print apparatus component includes a logic circuitry package of any of the examples described herein, wherein the component further includes a volume of liquid. The component may have a height H that is greater than a width W and a length L that is greater than the height, the width extending between two sides. Interface pads of the package may be provided at the inner side of one of the sides facing a cut-out for a data interconnect to be inserted, the interface pads extending along a height direction near the top and front of the component, and the data pad being the bottom-most of the interface pads, the liquid and air interface of the component being provided at the front on the same vertical reference axis parallel to the height H direction wherein the vertical axis is parallel to and distanced from the axis that intersects the interface pads (i.e., the pads are partially inset from the edge by a distance D). The rest of the logic circuitry package may also be provided against the inner side.
FIG. 6 illustrates another example of processing circuitry 600. Processing circuitry 600 includes an interface (e.g., I2C interface) 602, a controller 604, a plurality of current sources 606, a plurality of sensors 608, multiplexing circuitry (MUX) 610, and analog to digital converter (ADC) 612. Interface 602 is electrically coupled to controller 604. Controller 604 is electrically coupled to current sources 606, sensors 608, multiplexing circuitry 610, and ADC 612, to control the operation of these elements.
In one example, sensors 608 include a plurality of different types of sensors (e.g., a sensor array of ink level sensor cells, a sensor array of strain gauge sensor cells, as well as individual sensors, such as a global thermal sensor, thermal diode, and a crack detect sensor). Each of these sensors 608 may be unique in its design, biasing, and signal conditioning. In some examples, processing circuitry 600 minimizes hardware redundancy by using shared busses and hardware in order to measure every sensor 608, while still providing the different biasing and signal conditioning for the different types of sensors 608. The various sensor measurement signals from all of the different sensors 608 are represented by sensor measurement signals 609. Multiplexing circuitry 610 selectively routes one of the measurement signals 609 from one of the sensors 608 at a time, as represented by measurement signal 611, to the ADC 612. The ADC 612 then conditions and converts the received measurement signal 611 to a digital measurement value 613, which may be output via interface 602.
In one example, current sources 606 include three different current sources providing three different currents 607. The current sources 606 may include a 1.9 mA current source, a 0.95 mA current source, and a 10 uA current source. In one example, each of the current sources 606 provides current to a different subset of the sensors 608. Controller 604 enables and controls the flow of current from the current sources 606. Controller 604 may also adjust the current coming from each current source 606 (e.g., by +/−15%) via a calibrate signal sent to the current sources 606.
In operation according to one example, controller 604 may receive requests through the interface 602 that identify specific ones of the sensors 608 to perform sensor measurements. In response to the received requests, controller 604 controls multiplexing circuitry 610 to multiplex the sensor signals from the identified sensors 608 such that signal integrity is not compromised. In one example, sensor measurements from all of the different sensors 608 are ultimately sent through the same ADC 612.
FIG. 7 illustrates one example of a memory 614 of a logic circuitry package, such as logic circuitry package 400 a-400 d, or processing circuitry 424 or 600. Memory 614 may include volatile or non-volatile memory. In one example, memory 614 includes registers 616 and 618. A first register 616 may store sensor measurement information, and a second register 618 may store sensor select information.
In one example, register 616 is written to in order to request the performance of sensor measurements (e.g., by sensors 608). In one example, register 618 is written to in order to control the multiplexing of signals from the sensors 608. In one example, the register 618 may be used to select one of four different subsets of the sensors 608 at a given time. These four subsets correspond to sensor select signals: SENSOR_SEL[0], SENSOR_SEL[1], SENSOR_SEL[2], and SENSOR_SEL[3]. These sensor select signals are described in additional detail below with reference to FIG. 8.
The information in registers 616 and 618 may be written to memory 614 by a print apparatus logic circuit via an interface (e.g., an I2C interface). The information in registers 616 and 618 may be read by a print apparatus logic circuit via the interface. In one example, each register 616 and 618 is an 8-bit register.
FIG. 8 is a schematic diagram illustrating another example of processing circuitry 620. Processing circuitry 620 includes a single-ended amplifier 622, a differential to single-ended amplifier 632, an analog to digital converter (ADC) 640, a sample and hold circuit 650, resistors 660 and 670, sensors 682, and multiplexing circuitry (MUX) 684 and 690. In one example, analog to digital converter 640 is a successive approximation analog to digital converter and includes a comparator 642 and a digital to analog converter (DAC) 644. In one example, sample and hold circuit 650 includes a switch 652 and a capacitor 654.
In one example, sensors 682 include an ink level sensor 682(1), a strain gauge sensor 682(2), a global thermal sense resistor (TSR) sensor 682(3), a crack detector sensor 682(4), and a thermal diode sensor 682(5). In other examples, sensors 682 may include different types of sensors than those shown. Sensors 682 may include any sensor of a logic circuitry package as previously described, for example, a cell of first cell array 410 or second cell array 412 of logic circuitry package 400 b (FIG. 4B) or a sensor of sensor array 446, ambient temperature sensor 450, crack detector 452, or fluid temperature sensor 454 of logic circuitry package 400 d.
In one example, multiplexing circuitry 684 includes switches 686(1)-686(3). In one example, the multiplexing circuitry 684 and 690 selectively routes analog sensor signals from a first subset of the sensors 682 (e.g., sensors 682(4) and 682(5)) to a first amplification circuit (e.g., amplifier 622), and routes analog sensor signals from a second subset of the sensors 682 (e.g., sensors 682(1)-682(3)) to a second amplification circuit (e.g., amplifier 632 followed by amplifier 622).
In one example, ink level sense sensor 682(1) includes an array of ink level sensing cells, and strain gauge sensor 682(2) includes an array of strain gauge sensing cells. Multiplexing circuitry 690 receives differential sensor measurements signals from sensors 682(1), 682(2), and 682(3), and selectively outputs one differential sensor measurement signal at any given time to amplifier 632 (e.g., from a selected one of the cells in sensor 682(1) or sensor 682(2), or from global TSR sensor 682(3)). In one embodiment, the multiplexing circuitry 690 includes a shared differential signal bus that is shared by all of the ink level sensing cells in sensor 682(1), strain gauge sensing cells in sensor 682(2), and global TSR sensor 682(3), with switches to switch one differential signal at a time onto the shared bus.
The differential sensor measurement signal that is output by multiplexing circuitry 690 is electrically coupled between the non-inverting input node (VIN+) 634 and the inverting input node (VIN−) 636 of amplifier 632. Sensors 682(1), 682(2), and 682(3) may be biased by biasing circuitry (e.g., current sources 606, shown in FIG. 6, or other biasing circuitry) to generate a voltage between the non-inverting input node 634 and the inverting input node 636 corresponding to the sensor reading.
A gain input of amplifier 632 receives a differential to single ended gain parameter (GAIN_D2SE) through a signal path 638, and a bias input of amplifier 632 receives a voltage bias parameter (V_BIAS) through a signal path 639. The output (V_OUT_D2SE) of amplifier 632 is electrically coupled to the non-inverting input 624 of amplifier 622 via switch 686(3) of multiplexing circuitry 684. The outputs of crack detector sensor 682(4) and thermal diode sensor 682(5) are electrically coupled to the non-inverting input 624 of amplifier 622 via switches 686(1) and 686(2), respectively, of multiplexing circuitry 684.
Switches 686(1)-686(3) may be controlled via sensor select signals (e.g., SENSOR_SEL[0], SENSOR_SEL[1], SENSOR_SEL[2], and SENSOR_SEL[3]), which are generated by writing to a sensor select register (e.g., sensor select register 618, shown in FIG. 7). SENSOR_SEL[0] selects either the ink level sense sensor 682(1) or global TSR sensor 682(3). In one example, in addition to selecting SENSOR_SEL[0], a sensor number in the range 0-125 may be selected to select one of 126 ink level sensing cells in sensor 682(1), or the number 126 or 127 may be selected to avoid conflicts on the bus when selecting the global TSR sensor 682(3) via the sensor select register 618. SENSOR_SEL[1] selects the thermal diode sensor 682(5). SENSOR_SEL[2] selects the strain gauge sensor 682(2). In one example, in addition to selecting SENSOR_SEL[2], a sensor number in the range 0-125 may be selected to select one of 126 strain gauge sensing cells in sensor 682(2). SENSOR_SEL[3] selects the crack detector sensor 682(4).
Writing a value to the sensor select register corresponding to SENSOR_SEL[0] or SENSOR_SEL[2] results in a signal that closes switch 686(3) (and opens switches 686(1) and 686(2)) to couple the output of amplifier 632 to the input 624 of amplifier 622. Writing a value to the sensor select register corresponding to SENSOR_SEL[1] results in a signal that closes switch 686(2) (and opens switches 686(1) and 686(3)) to couple the output of thermal diode sensor 682(5) to the input 624 of amplifier 622. Writing a value to the sensor select register corresponding to SENSOR_SEL[3] results in a signal that closes switch 686(1) (and opens switches 686(2) and 686(3)) to couple the output of crack detector sensor 682(4) to the input 624 of amplifier 622.
A gain input of amplifier 622 receives a single ended gain parameter (GAIN_SE) through a signal path 629. In one example, the gain of amplifier 622 is set by the values of the resistors 660 (R1) and 670 (R2), and the GAIN_SE parameter may be used to multiplex one set of resistors 660 (R1) and 670 (R2) to input 626 out of a plurality of sets of such resistors having different resistance values. The GAIN_D2SE parameter, the V_BIAS parameter, and the GAIN_SE parameter may be stored in a memory of the logic circuitry package. In one example, the GAIN_D2SE parameter may be 1, 2, 4, or another suitable value, and the GAIN_SE parameter may be 1, 8, 12, 16, or another suitable value. The GAIN_D2SE and GAIN_SE parameters may be referred to as first and second gain parameters, respectively.
The output (V_OUT_SE) of amplifier 622 is electrically coupled to a first input of comparator 642 and to one terminal of resistor (R2) 670 through output node 628 of amplifier 622. The other terminal of resistor 670 is electrically coupled to one terminal of resistor (R1) 660 and the inverting input node 626 of amplifier 622. The other terminal of resistor 660 is electrically coupled to one terminal of capacitor 654 and one side of switch 652 through an offset voltage (VDAC) node 662. The other terminal of capacitor 654 is electrically coupled to a common or ground node 630. The other side of switch 652 is electrically coupled to the output of digital to analog converter 644 and to a second input of comparator 642 through a signal path 646. The output of comparator 642 provides a digital value (ADC_OUT) (e.g., a count) through a signal path 648. The digital value output by comparator 642 may be stored in a memory (e.g., volatile or non-volatile) of the logic circuitry package and subsequently transmitted to a print apparatus logic circuit.
The output of amplifier 632 is determined by the following equation:
V_OUT_D2SE=GAIN_D2SE(VIN+−VIN−)+V_BIAS
The output of amplifier 622 is determined by the following equation:
V_OUT_SE=GAIN_SE(V_OUT_D2SE)−(GAIN_SE−1)(VDAC)
where: GAIN_SE=1+R2/R1.
A VDAC step change associated with the offset voltage may be stored in a memory. The VDAC step change may be referred to as an offset parameter. The (first and second) gain parameter(s) and offset parameter may be referred to as calibration parameters, to calibrate the logic circuitry output. Different sensor IDs or sensor types may require different calibration parameters to provide non-clipped (e.g., verifiable) and valid outputs. The logic circuitry may be configured to change the output signal based on an offset parameter by an amount that is a function of the gain parameter(s).
In the example illustrated in FIG. 8, V_OUT_SE increases or decreases as VDAC is decreased or increased, respectively. The ADC_OUT digital value (e.g., count) shift is proportional to GAIN_D2SE and GAIN_SE, while the magnitude of the sensor signal is proportional to the product of GAIN_D2SE and GAIN_SE. For example, if GAIN_D2SE=2 and GAIN_SE=8, then the overall sensor signal is subject to a gain of 16 and the ADC_OUT digital value will shift up/down by a first number of counts for each VDAC step change. For example, if GAIN_D2SE=4 and GAIN_SE=16, then the overall sensor signal is subject to a gain of 64 and the ADC_OUT digital value will shift up/down by a second number of counts for each VDAC step change, wherein the second number of counts is approximately 2 times greater than the first number of counts, to the extent that the output count is not clipped. For example, for a first type of sensor such as a strain gauge sensor, the ADC_OUT digital value may shift up/down by a first number of counts for each VDAC step change. For a second type of sensor such as an ink level sensor, the ADC_OUT digital value may shift up/down by a second number of counts for each VDAC step change where the second number is different from the first number.
Analog to digital converter 640 receives the amplified sensor signal (V_OUT_SE) and outputs a digital value (ADC_OUT) corresponding to the amplified sensor signal when the analog to digital converter 640 is active. With analog to digital converter 640 active (e.g., in response to a request from a print apparatus logic circuit for a sensor measurement), analog to digital converter 640 converts the output of amplifier 622 into a digital value via a binary search through all possible quantization levels (e.g., 256 levels) before finally converging upon a digital value to output as ADC_OUT. Digital to analog converter 644 provides the possible quantization levels to comparator 642, which compares each possible quantization level to the output of amplifier 622 to converge upon the digital value corresponding to the output of amplifier 622.
The sample and hold circuit 650 samples and holds an output voltage of digital to analog converter 644 when the analog to digital converter 640 is inactive. When analog to digital converter 640 is inactive, digital to analog converter 644 provides an output voltage to sample and hold circuit 650 based on the offset parameter. In one example, the controllable source 612 of FIG. 6 includes the digital to analog converter 644 of the analog to digital converter 640. In one example, with analog to digital converter 640 inactive, digital to analog converter 644 is controlled (e.g., by the offset parameter) such that the output of amplifier 622 (offset by VDAC) is within an operating range of analog to digital converter 640.
The switch 652 of sample and hold circuit 650 is controlled to be closed to charge the capacitor 654 to the output voltage of the digital to analog converter 644 when the analog to digital converter 640 is inactive (i.e., not converting the output of amplifier 622 to a digital value) and to be opened when the analog to digital converter 640 is active (i.e., when converting the output of amplifier 622 to a digital value). Therefore, the offset voltage VDAC on node 662 is maintained based on the offset parameter and offsets the voltage of the amplified sensor signal output by amplifier 622.
In one example, a sample and hold circuit (not shown) similar to sample and hold circuit 650 and controlled in a similar manner may be coupled between the output of amplifier 632 and the first input node 624 of amplifier 622 to sample and hold the V_OUT_D2SE signal until the digital to analog conversion is complete. By simultaneously sampling and holding both the offset voltage VDAC and V_OUT_D2SE, and continuing to hold them until the analog to digital conversion is complete, both of the held voltages drift similarly, which provides common mode rejection and nullifies the effect from signal drift, resulting in a more accurate sensor reading.
FIGS. 9A-9C are flow diagrams illustrating one example of a method 700 that may be carried out by a logic circuitry package, such as logic circuitry package 400 a-400 d, or by processing circuitry 424, 600, or 620. Method 700 may be carried out by a logic circuitry package for a replaceable print apparatus component, which includes a first at least one analog cell of a first type, a second at least one analog cell of a second type, an analog-digital converter (ADC), an interface to communicate with a print apparatus logic circuit, and at least one logic circuit. As illustrated in FIG. 9A at 702, the at least one logic circuit of the logic circuitry package may receive, via the interface, requests to perform measurements to selected ones of the at least one first and second analog cells. At 704, the at least one logic circuit selectively routes analog signals from the selected analog cells to the ADC based on the requests.
In some examples of method 700, one or both of the first and second at least one analog cells comprises an array with a plurality of analog cells. The array may include at least 20 analog cells. The array may include at least 100 analog cells. The logic circuitry package may further include at least one further analog cell of a third type.
In some examples of method 700, the ADC may include at least one of an analog to digital converter and a digital to analog converter. The ADC may include both an analog to digital converter and a digital to analog converter.
In some examples, the first at least one analog cell includes a first cell array with analog sensing cells of a first sensing type, and the second at least one analog cell includes a second cell array with analog sensing cells of a second sensing type, and, as illustrated in FIG. 9B, at 706, the at least one logic circuit may further receive, via the interface, requests to perform sensor measurements to selected ones of the analog sensing cells in the first and second arrays. At 708, the at least one logic circuit selectively routes analog sensor signals from the selected analog sensing cells to the ADC based on the requests.
In some examples of method 700, the first at least one analog cell is configured to sense print material level and the second at least one analog cell is configured to detect a pneumatic event applied to the replaceable print apparatus component. Each of the requests in method 700 may include a sensor ID corresponding to one of the analog cells. Each of the requests may include sensor ID parameters including the sensor ID and a sensor ID address, and the at least one logic circuit may be configured to: receive the sensor ID parameters; identify a sensor ID based on the sensor ID address; and select a cell type based on the sensor ID. The at least one logic circuit may be configured to: receive different sensor ID parameters including a sensor cell ID and a sensor cell ID address; identify a sensor cell ID based on the sensor cell ID address; and select a cell based on the sensor cell ID. The at least one logic circuit may be configured to output, via the interface, digital values corresponding to the analog signals from the analog cells corresponding to the sensor IDs.
In some examples, the logic circuitry package may further include at least one individual analog sensor, and the at least one logic circuit may be configured to selectively route analog sensor signals from the at least one individual analog sensor to the ADC. The at least one individual analog sensor may include at least two individual analog sensors. Each of the individual analog sensors may be of a different sensing type than the other individual analog sensors. The at least one individual analog sensor may include at least one of a crack detector sensor, a thermal diode sensor, and a global thermal sensor resistor sensor.
In some examples, the logic circuitry package may include a first analog amplification circuit and a second analog amplification circuit, and, as illustrated in FIG. 9C, at 710, the at least one logic circuit may further selectively route analog signals from the selected analog cells to an input of the first analog amplification circuit. At 712, the at least one logic circuit may further selectively route analog sensor signals from the at least one individual analog sensor to an input of the second analog amplification circuit. In some examples, an output of the first analog amplification circuit may be coupled to the input of the second analog amplification circuit, and an output of the second analog amplification circuit may be coupled to the ADC.
In some examples of method 700, the interface may be configured for digital data communications between the replaceable print apparatus component and the print apparatus logic circuit. The interface may be configured to communicate over an I2C multi-serial bus.
FIGS. 10A-10B are flow diagrams illustrating another example of a method 720 that may be carried out by a logic circuitry package, such as logic circuitry package 400 a-400 d, or by processing circuitry 424, 600, or 620. As illustrated in FIG. 10A, at 722, method 720 includes transmitting, via a print apparatus logic circuit to a logic circuitry package, requests to perform measurements by selected ones of a plurality of analog cells of a first type in a first cell array and a plurality of analog cells of a second type in a second cell array. At 724, method 720 includes selectively routing analog signals from the selected analog cells to an analog to digital converter (ADC), based on the requests, to generate digital values. At 726, method 720 includes transmitting, via the logic circuit package to the print apparatus logic circuit, the digital values.
As illustrated in FIG. 10B, at 728, method 720 includes transmitting, via the print apparatus logic circuit to the logic circuitry package, requests to perform measurements by selected ones of a plurality of individual analog sensors of different types. At 730, method 720 includes selectively routing analog signals from the selected individual analog sensors to the ADC to generate additional digital values. At 732, method 720 includes transmitting, via the logic circuit package to the print apparatus logic circuit, the additional digital values.
Some examples are directed to a logic circuitry package, which includes an I2C interface to receive requests to perform measurements. The logic circuitry package includes a first cell array with a plurality of analog cells of a first type, and a second cell array with a plurality of analog cells of a second type. The logic circuitry package includes an analog to digital converter (ADC), and multiplexing circuitry to selectively route analog signals from selected ones of the analog cells in the first cell array and the second cell array to the ADC based on the received requests to perform measurements.
In some examples of the logic circuitry package, the analog cells of the first cell array may be analog sensing cells of a first sensing type, and the analog cells of the second cell array may be analog sensing cells of a second sensing type. The logic circuitry package may also include at least one individual analog sensor, and the multiplexing circuitry may be configured to selectively route analog sensor signals from the at least one individual analog sensor to the ADC. In some examples, the at least one individual analog sensor may include at least two individual analog sensors, and each of the individual analog sensors may be of a different sensing type than the other individual analog sensors.
Some examples are directed to a replaceable print apparatus component which includes any of the logic circuitry packages described herein. The replaceable print apparatus component may also include a housing having a height, a width less than the height, and a length greater than the height, the height parallel to a vertical reference axis, and the width extending between two sides; a print liquid reservoir within the housing; a print liquid output; an air input above the print liquid output; and an interface comprising interface pads for communicating with a print apparatus logic circuit, the interface pads provided at an inner side of one of the sides facing a cut-out for a data interconnect to be inserted, the interface pads extending along a height direction near a top and front of the component above the air input, wherein the air input is provided at the front on the same vertical reference axis parallel to the height direction, and wherein the vertical reference axis is parallel to and distanced from an axis that intersects the interface pads.
FIG. 11 illustrates another example of a logic circuitry package 1000. FIG. 11 illustrates how the logic circuitry package 1000 may generate a digital output (e.g., sensor measurement data) based on inputs including parameters and/or requests (e.g., to request sensor measurements; to set a value of a sensor select register to control multiplexing circuitry; sensor IDs; etc.) sent digitally by the print apparatus. Logic circuitry package 1000 includes a logic circuit with a processor 1002 communicatively coupled to a memory 1004. Memory 1004 may store look up table(s) and/or list(s) 1006 and/or algorithm(s) 1008. Logic circuitry package 1000 may also include any of the features of logic circuitry packages 400 a-400 d or processing circuitry 424, 600, and/or 620 as previously described.
For example, the logic circuitry package 1000 may include at least one sensor 1010, or multiple sensors of different types, and an analog-digital converter (ADC) 1012. The logic circuit may be configured to consult a respective sensor 1010, in combination with the LUT(s)/list(s) 1006 and/or algorithm(s) 1008, based on a sensor ID and calibration parameters, to generate the digital output. The at least one sensor 1010 may include a sensor to detect an effect of a pneumatic actuation of the print apparatus upon the replaceable print component, and/or a sensor to detect an approximate temperature, and/or other sensors. The logic circuitry package 1000 may include a plurality of sensors of different types, for example, at least two sensors of different types, wherein the logic circuit may be configured to select and consult one of the sensors based on the sensor ID, and output a digital value based on a signal of the selected sensor.
The output values may be generated using the LUT(s) and or list(s) 1006 and/or algorithm(s) 1008 whereby the parameters may be used as input. In addition, a signal of at least one sensor 1010 may be consulted as input for the LUT.
The example logic circuitry package 1000 may be used as an alternative to the complex thin film sensor arrays addressed elsewhere in this disclosure. The example logic circuitry package 1000 may be configured to generate outputs that are validated by the same print apparatus logic circuit designed to be compatible with the complex sensor array packages. The alternative package 1000 may be cheaper or simpler to manufacture, or simply be used as an alternative to the earlier mentioned packages, for example to facilitate printing and validation by the print apparatus. The alternative package may be more robust, because fully or partially digitally generated/emulated signals may be more reliable than output that needs to rely on analog sensor signals that can be relatively difficult to control.
Logic circuitry package 1000 may be configured to output digital values indicating sensor measurement data in response to at least one request. Logic circuitry package 1000 may receive a first request to set a value in a sensor select register to configure multiplexing circuitry to facilitate routing of analog sensor signals to ADC 1012. Logic circuitry package 1000 may subsequently receive a second request to cause the at least one sensor 1010 to perform at least one sensor measurement. In response to the first and second requests, logic circuitry package 1000 may enable the at least one sensor 1010 to perform an analog sensor measurement, and route the analog sensor measurement signal to the ADC 1012 1012 with the multiplexing circuitry. The ADC 1012 may convert the received analog sensor measurement signal to digital sensor measurement data, which may be output from logic circuit 1000.
In one example, the logic circuitry packages described herein mainly include hardwired routings, connections, and interfaces between different components. In another example, the logic circuitry packages may also include at least one wireless connection, wireless communication path, or wireless interface, for internal and/or external signaling, whereby a wirelessly connected element may be considered as included in the logic circuitry package and/or replaceable component. For example, certain sensors may be wireless connected to communicate wirelessly to the logic circuit/sensor circuit. For example, sensors such as pressure sensors and/or print material level sensors may communicate wirelessly with other portions of the logic circuit. These elements, which communicate wirelessly with the rest of the logic circuit, may be considered part of the logic circuit or logic circuitry package. Also, the external interface of the logic circuitry package, to communicate with the print apparatus logic circuit, may include a wireless interface. Also, while reference may be made to power routings, power interfaces, or charging or powering certain cells, certain examples of this disclosure may include a power source such as a battery or a power harvesting source that may harvest power from data or clock signals.
Certain example circuits of this disclosure relate to outputs that vary in a certain way in response to certain commands, events and/or states. It is also explained that, unless calibrated in advance, responses to these same events and/or states may be “clipped”, for example so that they cannot be characterized or are not relatable to these commands, events and/or states. For these example circuits where the output needs to be calibrated to obtain the characterizable or relatable output, it should be understood that also before required calibration (or installation) occurred these circuits are in fact already “configured” to provide for the characterizable output, that is, all means are present to provide for the characterizable output, even where calibration is yet to occur. It may be a matter of choice to calibrate a logic circuit during manufacture and/or during customer installation and/or during printing, but this does not take away that the same circuit is already “configured” to function in the calibrated state. For example, when sensors are mounted to a reservoir wall, certain strains in that wall over the lifetime of the component may vary and may be difficult to predict while at the same time these unpredictable strains affect the output of the logic circuit. Different other circumstances such as conductivity of the print material, different packaging, in-assembly-line-mounting, etc. may also influence how the logic circuit responds to commands/events/states so that a choice may be made to calibrate at or after a first customer installation. In any of these and other examples, it is advantageous to determine (operational) calibration parameters in-situ, after first customer installation and/or between print jobs, whereby, again, these should be considered as already adapted to function in a calibrated state. Certain alternative (at least partly) “virtual” embodiments discussed in this disclosure may operate with LUTs or algorithms, which may similarly generate, before calibration or installation, clipped values, and after calibration or installation, characterizable values whereby such alternative embodiment, should also be considered as already configured or adapted to provide for the characterizable output, even before calibration/installation.
In one example, the logic circuitry package outputs count values in response to read requests. In many examples, the output of count values is discussed. In certain examples, each separate count value is output in response to each read request. In another example, a logic circuit is configured to output a series or plurality of count values in response to a single read request. In other examples, output may be generated without a read request.
Each of the logic circuitry packages 400 a-400 d, 1000 described herein may have any feature of any other logic circuitry packages 400 a-400 d, 1000 described herein or of the processing circuitry 424, 600, 620. Any logic circuitry packages 400 a-400 d, 1000 or the processing circuitry 424, 600, 620 may be configured to carry out at least one method block of the methods described herein. Any first logic circuit may have any attribute of any second logic circuit, and vice versa.
Examples in the present disclosure can be provided as methods, systems or machine readable instructions, such as any combination of software, hardware, firmware or the like. Such machine readable instructions may be included on a machine readable storage medium (including but not limited to disc storage, CD-ROM, optical storage, etc.) having machine readable program codes therein or thereon.
The present disclosure is described with reference to flow charts and block diagrams of the method, devices and systems according to examples of the present disclosure. Although the flow diagrams described above show a specific order of execution, the order of execution may differ from that which is depicted. Blocks described in relation to one flow chart may be combined with those of another flow chart. It shall be understood that at least some blocks in the flow charts and block diagrams, as well as combinations thereof can be realized by machine readable instructions.
The machine readable instructions may, for example, be executed by a general purpose computer, a special purpose computer, an embedded processor or processors of other programmable data processing devices to realize the functions described in the description and diagrams. In particular, a processor or processing circuitry may execute the machine readable instructions. Thus, functional modules of the apparatus and devices (for example, logic circuitry and/or controllers) may be implemented by a processor executing machine readable instructions stored in a memory, or a processor operating in accordance with instructions embedded in logic circuitry. The term ‘processor’ is to be interpreted broadly to include a CPU, processing unit, ASIC, logic unit, or programmable gate array etc. The methods and functional modules may all be performed by a single processor or divided amongst several processors.
Such machine readable instructions may also be stored in a machine readable storage (e.g., a tangible machine readable medium) that can guide the computer or other programmable data processing devices to operate in a specific mode.
Such machine readable instructions may also be loaded onto a computer or other programmable data processing devices, so that the computer or other programmable data processing devices perform a series of operations to produce computer-implemented processing, thus the instructions executed on the computer or other programmable devices realize functions specified by block(s) in the flow charts and/or in the block diagrams.
Further, the teachings herein may be implemented in the form of a computer software product, the computer software product being stored in a storage medium and comprising a plurality of instructions for making a computer device implement the methods recited in the examples of the present disclosure.
The word “comprising” does not exclude the presence of elements other than those listed in a claim, “a” or “an” does not exclude a plurality, and a single processor or other unit may fulfil the functions of several units recited in the claims.
Although specific examples have been illustrated and described herein, a variety of alternate and/or equivalent implementations may be substituted for the specific examples shown and described without departing from the scope of the present disclosure. This application is intended to cover any adaptations or variations of the specific examples discussed herein. Therefore, it is intended that this disclosure be limited only by the claims and the equivalents thereof.

Claims

1-29. (canceled)

30. A logic circuitry package for a replaceable print apparatus component comprising a first at least one analog cell of a first type, a second at least one analog cell of a second type, an analog-digital converter (ADC), an interface to communicate with a print apparatus logic circuit, and at least one logic circuit configured to:

receive, via the interface, requests to perform measurements to selected ones of the at least one first and second analog cells; and

selectively route analog signals from the selected analog cells to the ADC based on the requests.

31. The logic circuitry package of claim 30, wherein one or both of the first and second at least one analog cells comprises an array with a plurality of analog cells.

32. The logic circuitry package of claim 30, and further comprising at least one further analog cell of a third type.

33. The logic circuitry package of claim 30, wherein the ADC comprises at least one of an analog to digital converter and a digital to analog converter.

34. The logic circuitry package of claim 30, wherein the ADC comprises both an analog to digital converter and a digital to analog converter.

35. The logic circuitry package of claim 30, wherein the first at least one analog cell comprises a first cell array with analog sensing cells of a first sensing type, wherein the second at least one analog cell comprises a second cell array with analog sensing cells of a second sensing type, and wherein the at least one logic circuit is configured to:

receive, via the interface, requests to perform sensor measurements to selected ones of the analog sensing cells in the first and second arrays; and

selectively route analog sensor signals from the selected analog sensing cells to the ADC based on the requests.

36. The logic circuitry package of claim 30, wherein the first at least one analog cell is configured to sense print material level and the second at least one analog cell is configured to detect a pneumatic event applied to the replaceable print apparatus component.

37. The logic circuitry package of claim 30, wherein each of the requests includes a sensor ID corresponding to one of the analog cells.

38. The logic circuitry package of claim 37, wherein each of the requests includes sensor ID parameters including the sensor ID and a sensor ID address, and wherein the at least one logic circuit is configured to:

receive the sensor ID parameters;

identify a sensor ID based on the sensor ID address; and

select a cell type based on the sensor ID.

39. The logic circuitry package of claim 37, wherein the at least one logic circuit is configured to:

receive different sensor ID parameters including a sensor cell ID and a sensor cell ID address;

identify a sensor cell ID based on the sensor cell ID address; and

select a cell based on the sensor cell ID.

40. The logic circuitry package of claim 37, wherein the at least one logic circuit is configured to output, via the interface, digital values corresponding to the analog signals from the analog cells corresponding to the sensor IDs.

41. The logic circuitry package of claim 30, wherein the logic circuitry package further includes at least one individual analog sensor, and wherein the at least one logic circuit is configured to selectively route analog sensor signals from the at least one individual analog sensor to the ADC.

42. The logic circuitry package of claim 41, wherein the at least one individual analog sensor includes at least two individual analog sensors.

43. The logic circuitry package of claim 42, wherein each of the individual analog sensors is of a different sensing type than the other individual analog sensors.

44. The logic circuitry package of claim 41, wherein the at least one individual analog sensor includes at least one of a crack detector sensor, a thermal diode sensor, and a global thermal sensor resistor sensor.

45. The logic circuitry package of claim 41, wherein the logic circuitry package includes a first analog amplification circuit and a second analog amplification circuit, and wherein the at least one logic circuit is configured to:

selectively route analog signals from the selected analog cells to an input of the first analog amplification circuit; and

selectively route analog sensor signals from the at least one individual analog sensor to an input of the second analog amplification circuit.

46. The logic circuitry package of claim 45, wherein an output of the first analog amplification circuit is coupled to the input of the second analog amplification circuit, and wherein an output of the second analog amplification circuit is coupled to the ADC.

47. The logic circuitry package of claim 30, wherein the interface is configured for digital data communications between the replaceable print apparatus component and the print apparatus logic circuit, wherein the interface is configured to communicate over an I2C multi-serial bus.

48. A logic circuitry package, comprising:

an I2C interface to receive requests to perform measurements;

a first cell array with a plurality of analog cells of a first type;

a second cell array with a plurality of analog cells of a second type;

an analog to digital converter (ADC); and

multiplexing circuitry to selectively route analog signals from selected ones of the analog cells in the first cell array and the second cell array to the ADC based on the received requests to perform measurements.

49. The logic circuitry package of claim 48, wherein the analog cells of the first cell array are analog sensing cells of a first sensing type, and wherein the analog cells of the second cell array are analog sensing cells of a second sensing type.

50. The logic circuitry package of claim 48, and further comprising at least one individual analog sensor, and wherein the multiplexing circuitry is configured to selectively route analog sensor signals from the at least one individual analog sensor to the ADC.

51. The logic circuitry package of claim 50, wherein the at least one individual analog sensor includes at least two individual analog sensors, and wherein each of the individual analog sensors is of a different sensing type than the other individual analog sensors.