US20210098280A1 - Process for Making a Semiconductor System - Google Patents
Process for Making a Semiconductor System Download PDFInfo
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- US20210098280A1 US20210098280A1 US17/068,717 US202017068717A US2021098280A1 US 20210098280 A1 US20210098280 A1 US 20210098280A1 US 202017068717 A US202017068717 A US 202017068717A US 2021098280 A1 US2021098280 A1 US 2021098280A1
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- 239000004065 semiconductor Substances 0.000 title claims description 23
- 238000000034 method Methods 0.000 title claims 21
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000002184 metal Substances 0.000 claims description 6
- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 239000004020 conductor Substances 0.000 description 30
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 238000007792 addition Methods 0.000 description 1
- 239000011324 bead Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
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- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
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- H—ELECTRICITY
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- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
Definitions
- the embodiments disclosed herein relate to semiconductor devices, and in particular to point-to-point interconnection systems for stacked devices.
- the bare silicon die are typically given an overcoat of oxide to protect the die during handling.
- a redistribution layer (RDL) of metal may then be deposited on top of this oxide to form an external interconnection system. Holes or contacts are then etched in the oxide so the RDL metal can connect to the internal metal layers of the silicon die.
- the RDLs allow signals to pass through the stack.
- RDLs may be appropriate for bussed (multi-drop) connections, where all of the silicon die in a stack are coupled to the same bus.
- RDL systems are not well suited to point-to-point connections, where separate connections need to be made to individual die in the stack. This is because point-to-point connections typically require complex and custom RDLs on each die to properly route the signals through the stack.
- These custom RDLs on each silicon die are complex and costly to design and manufacture, particularly in the case in which all the silicon die are the same (e.g., memory die). Accordingly, a system that eliminates custom RDLs in a stacked system would be highly desirable.
- FIG. 1A is a schematic cross-sectional side view of a point-to-point interconnection system for stacked devices, according to an embodiment
- FIG. 1B is a schematic plan view of the system shown in FIG. 1A , as viewed along line 1 B- 1 B′ of FIG. 1A ;
- FIG. 2 is a schematic cross-sectional side view of one of the devices shown in FIGS. 1A and 1B ;
- FIG. 3 is a schematic cross-sectional side view of another device that may be used in the point-to-point interconnection system shown in FIGS. 1A and 1B , according to another embodiment;
- FIG. 4A is a schematic cross-sectional side view of yet another point-to-point interconnection system for stacked devices, as viewed along line 4 A- 4 A′ of FIG. 4C , according to yet another embodiment;
- FIG. 4B is a schematic cross-sectional side view of the point-to-point interconnection system of FIG. 4A , as viewed along line 4 B- 4 B′ of FIG. 4C ;
- FIG. 4C is a schematic plan view of the systems shown in FIGS. 4A and 4B .
- Point-to-point interconnect topology may be required for a number of reasons, such as (i) the die stack may connect to signals that are used by only one of the silicon die (e.g., a chip-select signal in the case of a memory die), (ii) point-to-point interconnect topology permits higher signaling rates than multi-drop topology, and/or (iii) point-to-point topology has fewer resource contention issues than a multi-drop topology (i.e., read-write turnaround and tri-state enable/disable delays).
- the die stack may connect to signals that are used by only one of the silicon die (e.g., a chip-select signal in the case of a memory die)
- point-to-point interconnect topology permits higher signaling rates than multi-drop topology
- point-to-point topology has fewer resource contention issues than a multi-drop topology (i.e., read-write turnaround and tri-state enable/disable delays).
- a point-to-point interconnection system includes a device having opposing first and second surfaces.
- the device includes operational circuitry, first, second and third electrical contacts, and a conductor.
- the first electrical contact is mechanically coupled to the first surface and electrically coupled to the operational circuitry.
- the second electrical contact is mechanically coupled to the first surface, while the third electrical contact is mechanically coupled to the second surface opposite, and aligned with, the first electrical contact.
- the conductor electrically couples the second electrical contact to the third electrical contact.
- the device may be an integrated circuit die or an integrated circuit package containing at least one die.
- a stacked device assembly includes a plurality of substantially identical devices stacked one on top of the other.
- Each device has a first surface and an opposing second surface, and includes operational circuitry, a first row of electrical contacts, a second row of electrical contacts, and a plurality of conductors.
- the first row of electrical contacts is arranged on the first surface such that each electrical contact is separated from an adjacent electrical contact by a predetermined distance.
- a first electrical contact of the first row of electrical contacts is electrically coupled to the operational circuitry.
- the second row of electrical contacts is arranged on the second surface, where each electrical contact is separated from an adjacent electrical contact by the predetermined distance.
- the second row is offset from the first row along the second surface by the predetermined distance.
- Each of the plurality of conductors is electrically coupled to a respective electrical contact in the first and second row.
- a stacked device assembly includes first and second devices each having a first surface and an opposing second surface.
- Each device includes operational circuitry, a first electrical contact, a second electrical contact, a third electrical contact, and a conductor.
- the first electrical contact is mechanically coupled to the first surface and electrically coupled to the operational circuitry.
- the second electrical contact is mechanically coupled to the first surface.
- the third electrical contact is mechanically coupled to the second surface opposite, and aligned with, the first electrical contact.
- the conductor electrically couples the second electrical contact to the third electrical contact.
- the second device is stacked adjacent the first device with the first surface of the second device located adjacent the second surface of the first device.
- the first electrical contact of the second device is aligned with and is electrically coupled to the third electrical contact of the first device.
- FIG. 1A is a schematic cross-sectional side view of a point-to-point interconnection system 100 for stacked devices (as viewed along line 1 A- 1 A′ of FIG. 1B ).
- multiple devices 102 ( 1 )- 102 ( 4 ) are stacked one on top of the other.
- the devices may be stacked symmetrically above one another, as shown, or they may be offset from one another, i.e., arranged in a stair-like manner.
- each of the multiple devices 102 ( 1 )- 102 ( 4 ) are identical.
- each of the multiple devices 102 ( 1 )- 102 ( 4 ) may have different operational circuitry, but may still have electrical contacts 104 located at the identical positions, e.g., may have identical RDLs.
- the stack of multiple devices 102 ( 1 )- 102 ( 4 ) is mechanically and electrically coupled to a substrate 101 , such as a motherboard.
- each of the multiple devices 102 ( 1 )- 102 ( 4 ) is an integrated circuit or die. In other embodiments, each of the multiple devices 102 ( 1 )- 102 ( 4 ) is a separate integrated circuit package containing at least one integrated circuit or die. In yet other embodiments, each device is a module containing one or more dies or packages. The devices in the stack may also be any combination of the aforesaid devices. For example, each of the multiple devices 102 ( 1 )- 102 ( 4 ) may be a single die or a package containing multiple die, such as a memory module or a System-in-Package (SIP).
- SIP System-in-Package
- one of the advantages of the point-to-point interconnection system 100 is that it facilitates point-to-point connections to any of the devices in a stack without requiring a custom RDL for each device, as all of the devices are either identical or the layout of their electrical contacts are identical.
- FIG. 2 is a schematic cross-sectional side view of one of the devices 102 shown in FIGS. 1A and 1B .
- the device 102 includes a substrate 110 , operational circuitry 112 , multiple electrical contacts or connectors 104 and multiple conductors 114 and 116 .
- the substrate 110 may be a silicon substrate.
- the substrate 110 may be a printed circuit board (PCB), ceramic substrate, or the like.
- the device 102 has opposing first and second sides 106 ( 1 ) and 106 ( 2 ), respectively.
- the substrate 110 is substantially planar, i.e., has substantially flat opposing first and second surfaces.
- the operational circuitry 112 may be embedded into, or internal to, the substrate 110 , as shown, or mounted on the substrate 110 , as shown in FIGS. 4A and 4B .
- the operational circuitry may include one or more transistors embedded into the die.
- the operational circuitry 112 may be an integrated circuit or die. In some embodiments, multiple discrete operational circuitry components 112 are provided per device, as shown in FIG. 1B .
- the multiple electrical contacts 104 include at least three electrical contacts 104 ( 1 ), 104 ( 2 ), and 104 ( 3 ). In other embodiments, the device may include as many electrical contacts 104 as is required. Some embodiments include an array 200 of multiple rows 202 ( a )- 202 ( d ) of electrical contacts 104 , as shown in FIG. 1B .
- the electrical contacts may take on any form such as metallic bumps or pads formed or etched onto the surface or RDL of the device 102 .
- each electrical contact 104 in a row 202 ( FIG. 1B ) on each side of the device is separated from an adjacent electrical contact in that row by the same predetermined pitch (p) ( FIG. 2 ).
- each electrical contact on the second surface 106 ( 2 ) of the device is aligned with a respective electrical contact on the first surface 106 ( 1 ) of the device, along an imaginary line 115 perpendicular to the surface of the device or parallel to the stacked direction.
- electrical contact 104 ( 3 ) is aligned (e.g., collinear) with electrical contact 104 ( 1 ) along an imaginary line 115 that is perpendicular to the first and second surfaces 106 ( 1 ) and 106 ( 2 ), respectively; and electrical contact 104 ( 1 ) is separated from electrical contact 104 ( 2 ) by a pitch (p).
- the electrical contact 104 ( 3 ) is arranged opposite the electrical contact 104 ( 1 ); the electrical contact 104 ( 5 ) is arranged opposite the electrical contact 104 ( 2 ); etc.
- the electrical conductors may be any suitable electrical conductors that electrically and/or mechanically couple components together, such as wires, redistribution layers, vias, any combination of the aforementioned, or the like.
- other electrical contacts are electrically coupled to one another via different electrical conductors.
- a fourth electrical contact 104 ( 4 ) which is mechanically coupled to the first surface 106 ( 1 ) of the device, is electrically coupled to a fifth electrical contact 104 ( 5 ), which is mechanically coupled to the second surface 106 ( 2 ) of the device, via a second electrical conductor 114 ( 2 ).
- a sixth electrical contact 104 ( 4 ) which is mechanically coupled to the first surface 106 ( 1 ) of the device 102 , may be electrically coupled to a seventh electrical contact 104 ( 5 ), which is mechanically coupled to the second surface 106 ( 2 ) of the device, via a second electrical conductor 114 ( 3 ). It should be appreciated that any number of electrical contacts may be provided.
- a signal to be routed to the operational circuitry 112 ( 1 ) of the first device 102 ( 1 ) is communicated to the first electrical contact 104 ( 1 ) of the first device 102 ( 1 ); and communicated from the first electrical contact 104 ( 1 ) to the operational circuitry 112 ( 1 ) of the device 102 ( 1 ) via the operational circuitry conductor 116 of the first device 102 ( 1 ).
- the signal is communicated to the electrical contact 104 ( 2 ) of the first device 102 ( 1 ); communicated through the first conductor 114 ( 1 ) to the third electrical contact 104 ( 3 ) of the first device 102 ( 1 ); communicated from the third electrical contact 104 ( 3 ) of the first device 102 ( 1 ) to the first electrical contact 104 ( 1 ) of the second device 102 ( 2 ); and communicated from the first electrical contact 104 ( 1 ) of the second device 102 ( 2 ) to the operational circuitry 112 ( 2 ) of the second device 102 ( 2 ) via the operational circuitry conductor 116 of the second device 102 ( 2 ).
- a signal to be routed to the operational circuitry 112 ( 3 ) of the third device 102 ( 3 ) is communicated to the fourth electrical contact 104 ( 4 ) of the first device 102 ( 1 ) and is routed through the first and second devices to the third device; and a signal to be routed to the operational circuitry 112 ( 4 ) of the fourth device 102 ( 4 ) is communicated to the sixth electrical contact 104 ( 6 ) of the first device 102 ( 1 ) and is routed through the first, second and third devices to the fourth device.
- the identical (or substantially similar) layout of electrical contacts and interconnecting conductors on the devices allows point-to-point connections to be made to all of the devices in the stack without requiring a customized RDL for one or more of the devices.
- FIG. 3 is a schematic cross-sectional side view of another point-to-point interconnection system 300 for stacked devices.
- a RDL is created that wraps around at least one edge of the device to route signals between corresponding electrical contacts.
- the RDL may include a first RDL 302 on the first surface of the device, a second RDL 304 on the second surface of the device, and a third RDL 306 at an edge of the device that couples the first RDL 302 to the second RDL 304 .
- corresponding electrical contacts may be electrically coupled by any suitable means, such as by a different RDL to that described above, by vias through the device, a combination of RDLS and vias, etc.
- the RDL may consist of any metal applied to the top and bottom (or front and back) of the silicon die, or it may alternatively consist of holes (vias) etched from the top surface to the bottom surface (or back surface to the front surface), with metal deposited in the holes.
- a flexible tape is used as a RDL substitute.
- FIG. 4A is a schematic cross-sectional side view of yet another point-to-point interconnection system 400 for stacked devices.
- three devices 402 are stacked on top of one another.
- each of the multiple devices 402 are identical.
- each of the multiple devices 402 have different operational circuitry, but still have identically located electrical contacts 408 .
- the stack of multiple devices is mechanically and electrically coupled to a substrate, such as a motherboard (not shown).
- Each device 402 includes a substrate 404 , operational circuitry 406 , multiple electrical contacts or connectors 408 and multiple conductors 410 , 412 , and 414 .
- the substrate 404 may include a silicon substrate.
- the substrate 404 may be a printed circuit board (PCB) or the like.
- the device 402 has opposing first and second sides 418 and 420 , respectively.
- the substrate 404 is substantially planar, i.e., has substantially flat opposing first and second sides.
- the operational circuitry 406 may be embedded into the substrate 404 or mounted on the substrate 404 , as shown.
- the operational circuitry may include one or more transistors embedded into the die.
- the operational circuitry may be an integrated circuit or die. In some embodiments, multiple discrete operational circuitry components are provided.
- the multiple electrical contacts 408 include at least four electrical contacts 408 ( 1 ), 408 ( 2 ), 408 ( 3 ), and 408 ( 4 ).
- the device may include as many electrical contacts as is required.
- Some embodiments include an array of multiple rows 428 and 430 of electrical contacts 408 , as shown in FIG. 4C .
- the electrical contacts may take on any form such as metallic bumps or pads formed or etched onto the surface of the device 402 .
- electrical contacts 408 ( 1 ) and 408 ( 2 ) are separated from one another by a predetermined pitch (q).
- electrical contacts 408 ( 3 ) and 408 ( 4 ) are separated from one another by a predetermined pitch (q).
- each electrical contact on the second surface 420 of the device is aligned with a respective electrical contact on the first surface 418 of the device.
- electrical contact 408 ( 3 ) is aligned or collinear with electrical contact 408 ( 1 ) along an imaginary line that is perpendicular to the first and second surfaces;
- electrical contact 408 ( 4 ) is aligned (e.g., collinear) with electrical contact 408 ( 2 ) along an imaginary line that is perpendicular to the first and second surfaces;
- electrical contact 408 ( 1 ) is separated from electrical contact 408 ( 2 ) by a pitch q; and contact 408 ( 3 ) is separated from electrical contact 408 ( 4 ) by the pitch q.
- the first electrical contact 408 ( 1 ) is electrically coupled to the operational circuitry 406 via an operational circuitry electrical conductor 410 .
- the second electrical contact 408 ( 2 ) is electrically coupled to the third electrical contact 408 ( 3 ), which is mechanically coupled to the second surface 420 of the device 402 , via a first electrical conductor 412 .
- the second electrical contact 408 ( 2 ) is also electrically coupled to the fourth electrical contact 408 ( 4 ), which is mechanically coupled to the second surface 420 of the device 402 , via a second electrical conductor 414 .
- the electrical conductors may be any suitable electrical conductors, such as wires, redistribution layers, vias, or the like.
- additional electrical contacts may be electrically coupled to one another via additional electrical conductors that are similar to those described above.
- an electrical connection is either formed between the third electrical contact 408 ( 3 ) of the first device 402 ( 1 ) and the first electrical contact 408 ( 1 ) of the second device 402 ( 2 ), or between the fourth electrical contact 408 ( 4 ) of the first device 402 ( 1 ) and the second electrical contact 408 ( 2 ) of the second device 402 ( 2 ).
- This electrical connection may be formed by a solder bead 416 or the like. As shown in FIG.
- an electrical connection is formed between the third electrical contact 408 ( 3 ) of the first device 402 ( 1 ) and the first electrical contact 408 ( 1 ) of the second device 402 ( 2 ). Accordingly, in use, a signal to be routed to the operational circuitry 406 of the first device 402 ( 1 ) is communicated to the first electrical contact 408 ( 1 ) of the first device 402 ( 1 ); and communicated from the first electrical contact 408 ( 1 ) to the operational circuitry 406 of the device 402 ( 1 ) via the operational circuitry conductor 410 of the first device 402 ( 2 ).
- the signal is communicated to the electrical contact 408 ( 2 ) of the first device 402 ( 1 ); communicated through the first conductor 412 to the third electrical contact of the first device 402 ( 1 ); communicated from the third electrical contact of the first device 402 ( 1 ) to the first electrical contact 408 ( 1 ) of the second device 402 ( 2 ); and communicated from the first electrical contact 408 ( 1 ) of the second device 402 ( 2 ) to the operational circuitry 406 of the second device 402 ( 2 ) via the operational circuitry conductor 410 of the second device 402 ( 2 ).
- FIG. 4B shows a schematic cross-sectional side view of the point-to-point interconnection system of FIG. 4A and 4C , as viewed along line 4 B- 4 B′ of FIG. 4C .
- an electrical connection is made between the fourth electrical contact of the first device 402 ( 1 ) and the second electrical contact of the second device 402 ( 2 ); and between the third electrical contact of the second device 402 ( 2 ) and the first electrical contact 408 ( 1 ) of the third device 402 ( 3 ).
- a signal routed to the first electrical contact of the first device 402 ( 1 ) is routed to the operational circuitry 406 of the first device, while a signal routed to the second electrical contact of the first device 402 ( 1 ) is routed to the operational circuitry of the third device 402 ( 3 ). Accordingly, by placing electrical connections between predetermined electrical contacts, signals can be communicated through the device along conductors 412 , 414 or routed to the operational circuitry of the device. Accordingly, the identical (or substantially similar) layout of electrical contacts and interconnecting conductors on the devices allows point-to-point connections to be made to all of the devices in the stack without requiring a customized RDL for one or more of the devices.
- each signal is also shifted one position laterally (in a direction perpendicular to the primary vertical direction of the stack). This permits a signal to be fed into the vertical stack at the bottom device, and be received at a device higher in the stack. This is facilitated by designing the identical pattern of electrical contacts (or RDLs) for all devices in the stack.
- the above mentioned embodiments permit a unique point-to-point signal (like a chip select for a memory die) to be driven to each device.
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- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
This application is directed to a system including a plurality of devices that are stacked one on top of another. Each device includes a substrate having two opposing surfaces. A first row of contacts is coupled on a first surface and includes a first contact and a second contact that are adjacent to each other. A second row of contacts is coupled on a respective second surface and includes a third contact. Each contact in the second row of contacts is physically aligned with an opposite contact in the first row. The third contact is disposed opposite and physically aligned with the first contact in the first row, and electrically coupled to the second contact in the first row. Operational circuitry is electrically coupled to at least the first contact on the first row, and at least two of the plurality of devices have distinct operational circuitry.
Description
- This application is a continuation application of and claims priority to U.S. Patent Application Serial No. U.S. patent application Ser. No. 15/824,762, filed on Nov. 28, 2017, which is a continuation application of U.S. Patent Application Serial No. U.S. patent application Ser. No. 14/272,295, filed on May 7, 2014, now U.S. Pat. No. 9,847,248, which is a continuation application of U.S. patent application Ser. No. 13/166,996, filed on Jun. 23, 2011, now U.S. Pat. No. 8,749,042, which is a continuation application of U.S. patent application Ser. No. 12/361,513, filed on Jan. 28, 2009, now U.S. Pat. No. 7,989,265, which is a continuation application of U.S. patent application Ser. No. 11/402,393, filed on Apr. 11, 2006, now U.S. Pat. No. 7,701,045, the entire contents of which applications are incorporated herein by reference.
- The embodiments disclosed herein relate to semiconductor devices, and in particular to point-to-point interconnection systems for stacked devices.
- As computer systems evolve, so does the demand for increased memory for such systems. To increase memory density, some memory modules stack integrated circuit (IC) dies one on top of the other. While memory subsystems commonly use die-stacking, System-in-Package (SIP) systems may also include stacked IC processor and controller die. These stacked systems permit high IC densities, thereby increasing the memory capacity of each module without requiring additional space on the underlying circuit board. Die stacking, however, does present a number of drawbacks, as described below.
- In these stacked systems, the bare silicon die are typically given an overcoat of oxide to protect the die during handling. A redistribution layer (RDL) of metal may then be deposited on top of this oxide to form an external interconnection system. Holes or contacts are then etched in the oxide so the RDL metal can connect to the internal metal layers of the silicon die. When the silicon die are assembled into a vertical stack, the RDLs allow signals to pass through the stack.
- Such RDLs may be appropriate for bussed (multi-drop) connections, where all of the silicon die in a stack are coupled to the same bus. However, such RDL systems are not well suited to point-to-point connections, where separate connections need to be made to individual die in the stack. This is because point-to-point connections typically require complex and custom RDLs on each die to properly route the signals through the stack. These custom RDLs on each silicon die are complex and costly to design and manufacture, particularly in the case in which all the silicon die are the same (e.g., memory die). Accordingly, a system that eliminates custom RDLs in a stacked system would be highly desirable.
- For a better understanding of the disclosure herein, reference should be made to the following detailed description taken in conjunction with the accompanying drawings, in which:
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FIG. 1A is a schematic cross-sectional side view of a point-to-point interconnection system for stacked devices, according to an embodiment; -
FIG. 1B is a schematic plan view of the system shown inFIG. 1A , as viewed alongline 1B-1B′ ofFIG. 1A ; -
FIG. 2 is a schematic cross-sectional side view of one of the devices shown inFIGS. 1A and 1B ; -
FIG. 3 is a schematic cross-sectional side view of another device that may be used in the point-to-point interconnection system shown inFIGS. 1A and 1B , according to another embodiment; -
FIG. 4A is a schematic cross-sectional side view of yet another point-to-point interconnection system for stacked devices, as viewed alongline 4A-4A′ ofFIG. 4C , according to yet another embodiment; -
FIG. 4B is a schematic cross-sectional side view of the point-to-point interconnection system ofFIG. 4A , as viewed alongline 4B-4B′ ofFIG. 4C ; and -
FIG. 4C is a schematic plan view of the systems shown inFIGS. 4A and 4B . - Like reference numerals refer to the same or similar components throughout the several views of the drawings.
- The following description describes various point-to-point interconnection systems. Point-to-point interconnect topology may be required for a number of reasons, such as (i) the die stack may connect to signals that are used by only one of the silicon die (e.g., a chip-select signal in the case of a memory die), (ii) point-to-point interconnect topology permits higher signaling rates than multi-drop topology, and/or (iii) point-to-point topology has fewer resource contention issues than a multi-drop topology (i.e., read-write turnaround and tri-state enable/disable delays).
- In some embodiments, a point-to-point interconnection system includes a device having opposing first and second surfaces. The device includes operational circuitry, first, second and third electrical contacts, and a conductor. The first electrical contact is mechanically coupled to the first surface and electrically coupled to the operational circuitry. The second electrical contact is mechanically coupled to the first surface, while the third electrical contact is mechanically coupled to the second surface opposite, and aligned with, the first electrical contact. The conductor electrically couples the second electrical contact to the third electrical contact. The device may be an integrated circuit die or an integrated circuit package containing at least one die.
- In other embodiments, a stacked device assembly includes a plurality of substantially identical devices stacked one on top of the other. Each device has a first surface and an opposing second surface, and includes operational circuitry, a first row of electrical contacts, a second row of electrical contacts, and a plurality of conductors. The first row of electrical contacts is arranged on the first surface such that each electrical contact is separated from an adjacent electrical contact by a predetermined distance. A first electrical contact of the first row of electrical contacts is electrically coupled to the operational circuitry. The second row of electrical contacts is arranged on the second surface, where each electrical contact is separated from an adjacent electrical contact by the predetermined distance. The second row is offset from the first row along the second surface by the predetermined distance. Each of the plurality of conductors is electrically coupled to a respective electrical contact in the first and second row.
- In yet other embodiments, a stacked device assembly includes first and second devices each having a first surface and an opposing second surface. Each device includes operational circuitry, a first electrical contact, a second electrical contact, a third electrical contact, and a conductor. The first electrical contact is mechanically coupled to the first surface and electrically coupled to the operational circuitry. The second electrical contact is mechanically coupled to the first surface. The third electrical contact is mechanically coupled to the second surface opposite, and aligned with, the first electrical contact. The conductor electrically couples the second electrical contact to the third electrical contact. The second device is stacked adjacent the first device with the first surface of the second device located adjacent the second surface of the first device. The first electrical contact of the second device is aligned with and is electrically coupled to the third electrical contact of the first device.
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FIG. 1A is a schematic cross-sectional side view of a point-to-point interconnection system 100 for stacked devices (as viewed alongline 1A-1A′ ofFIG. 1B ). As shown, multiple devices 102(1)-102(4) are stacked one on top of the other. The devices may be stacked symmetrically above one another, as shown, or they may be offset from one another, i.e., arranged in a stair-like manner. In some embodiments, each of the multiple devices 102(1)-102(4) are identical. In some embodiments, each of the multiple devices 102(1)-102(4) may have different operational circuitry, but may still haveelectrical contacts 104 located at the identical positions, e.g., may have identical RDLs. In use, the stack of multiple devices 102(1)-102(4) is mechanically and electrically coupled to asubstrate 101, such as a motherboard. - In some embodiments, each of the multiple devices 102(1)-102(4) is an integrated circuit or die. In other embodiments, each of the multiple devices 102(1)-102(4) is a separate integrated circuit package containing at least one integrated circuit or die. In yet other embodiments, each device is a module containing one or more dies or packages. The devices in the stack may also be any combination of the aforesaid devices. For example, each of the multiple devices 102(1)-102(4) may be a single die or a package containing multiple die, such as a memory module or a System-in-Package (SIP). As will be described in further detail below, one of the advantages of the point-to-
point interconnection system 100 is that it facilitates point-to-point connections to any of the devices in a stack without requiring a custom RDL for each device, as all of the devices are either identical or the layout of their electrical contacts are identical. -
FIG. 2 is a schematic cross-sectional side view of one of thedevices 102 shown inFIGS. 1A and 1B . Thedevice 102 includes asubstrate 110,operational circuitry 112, multiple electrical contacts orconnectors 104 andmultiple conductors substrate 110 may be a silicon substrate. In the embodiment where the device is a package or module containing multiple integrated circuits, thesubstrate 110 may be a printed circuit board (PCB), ceramic substrate, or the like. Thedevice 102 has opposing first and second sides 106(1) and 106(2), respectively. In some embodiments, thesubstrate 110 is substantially planar, i.e., has substantially flat opposing first and second surfaces. - The
operational circuitry 112 may be embedded into, or internal to, thesubstrate 110, as shown, or mounted on thesubstrate 110, as shown inFIGS. 4A and 4B . In the embodiments where the device is an integrated circuit, the operational circuitry may include one or more transistors embedded into the die. In the embodiment where the device is a package or module containing multiple integrated circuits, theoperational circuitry 112 may be an integrated circuit or die. In some embodiments, multiple discreteoperational circuitry components 112 are provided per device, as shown inFIG. 1B . - In some embodiments, the multiple
electrical contacts 104 include at least three electrical contacts 104(1), 104(2), and 104(3). In other embodiments, the device may include as manyelectrical contacts 104 as is required. Some embodiments include anarray 200 of multiple rows 202(a)-202(d) ofelectrical contacts 104, as shown inFIG. 1B . The electrical contacts may take on any form such as metallic bumps or pads formed or etched onto the surface or RDL of thedevice 102. In some embodiments, eachelectrical contact 104 in a row 202 (FIG. 1B ) on each side of the device is separated from an adjacent electrical contact in that row by the same predetermined pitch (p) (FIG. 2 ). Also in some embodiments, each electrical contact on the second surface 106(2) of the device is aligned with a respective electrical contact on the first surface 106(1) of the device, along animaginary line 115 perpendicular to the surface of the device or parallel to the stacked direction. For example, electrical contact 104(3) is aligned (e.g., collinear) with electrical contact 104(1) along animaginary line 115 that is perpendicular to the first and second surfaces 106(1) and 106(2), respectively; and electrical contact 104(1) is separated from electrical contact 104(2) by a pitch (p). In other words, in some embodiments, the electrical contact 104(3) is arranged opposite the electrical contact 104(1); the electrical contact 104(5) is arranged opposite the electrical contact 104(2); etc. - In some embodiments of the invention, the first electrical contact 104(1), which is mechanically coupled to the first surface 106(1) of the device, is electrically coupled to the
operational circuitry 112 via an operational circuitryelectrical conductor 116. The second electrical contact 104(2), which is mechanically coupled to the first surface 106(1) of the device, is electrically coupled to the third electrical contact 104(3), which is mechanically coupled to the second surface 106(2) of the device, via a first electrical conductor 114(1). The electrical conductors may be any suitable electrical conductors that electrically and/or mechanically couple components together, such as wires, redistribution layers, vias, any combination of the aforementioned, or the like. - In other embodiments of the invention, other electrical contacts are electrically coupled to one another via different electrical conductors. For example, a fourth electrical contact 104(4), which is mechanically coupled to the first surface 106(1) of the device, is electrically coupled to a fifth electrical contact 104(5), which is mechanically coupled to the second surface 106(2) of the device, via a second electrical conductor 114(2). Similarly, a sixth electrical contact 104(4), which is mechanically coupled to the first surface 106(1) of the
device 102, may be electrically coupled to a seventh electrical contact 104(5), which is mechanically coupled to the second surface 106(2) of the device, via a second electrical conductor 114(3). It should be appreciated that any number of electrical contacts may be provided. - Referring to
FIGS. 1A, 1B and 2 , in use, a signal to be routed to the operational circuitry 112(1) of the first device 102(1) is communicated to the first electrical contact 104(1) of the first device 102(1); and communicated from the first electrical contact 104(1) to the operational circuitry 112(1) of the device 102(1) via theoperational circuitry conductor 116 of the first device 102(1). However, to route a signal to the operational circuitry 112(2) of the second device 102(2) in the stack, the signal is communicated to the electrical contact 104(2) of the first device 102(1); communicated through the first conductor 114(1) to the third electrical contact 104(3) of the first device 102(1); communicated from the third electrical contact 104(3) of the first device 102(1) to the first electrical contact 104(1) of the second device 102(2); and communicated from the first electrical contact 104(1) of the second device 102(2) to the operational circuitry 112(2) of the second device 102(2) via theoperational circuitry conductor 116 of the second device 102(2). In a similar manner, a signal to be routed to the operational circuitry 112(3) of the third device 102(3) is communicated to the fourth electrical contact 104(4) of the first device 102(1) and is routed through the first and second devices to the third device; and a signal to be routed to the operational circuitry 112(4) of the fourth device 102(4) is communicated to the sixth electrical contact 104(6) of the first device 102(1) and is routed through the first, second and third devices to the fourth device. Accordingly, the identical (or substantially similar) layout of electrical contacts and interconnecting conductors on the devices allows point-to-point connections to be made to all of the devices in the stack without requiring a customized RDL for one or more of the devices. -
FIG. 3 is a schematic cross-sectional side view of another point-to-point interconnection system 300 for stacked devices. In this embodiment, a RDL is created that wraps around at least one edge of the device to route signals between corresponding electrical contacts. As shown, the RDL may include afirst RDL 302 on the first surface of the device, asecond RDL 304 on the second surface of the device, and athird RDL 306 at an edge of the device that couples thefirst RDL 302 to thesecond RDL 304. It should, however, be appreciated that corresponding electrical contacts may be electrically coupled by any suitable means, such as by a different RDL to that described above, by vias through the device, a combination of RDLS and vias, etc. For example, the RDL may consist of any metal applied to the top and bottom (or front and back) of the silicon die, or it may alternatively consist of holes (vias) etched from the top surface to the bottom surface (or back surface to the front surface), with metal deposited in the holes. In an alternative embodiment, a flexible tape is used as a RDL substitute. -
FIG. 4A is a schematic cross-sectional side view of yet another point-to-point interconnection system 400 for stacked devices. In this embodiment, threedevices 402 are stacked on top of one another. In some embodiments, each of themultiple devices 402 are identical. In other embodiments, each of themultiple devices 402 have different operational circuitry, but still have identically locatedelectrical contacts 408. In use, the stack of multiple devices is mechanically and electrically coupled to a substrate, such as a motherboard (not shown). - Each
device 402 includes asubstrate 404,operational circuitry 406, multiple electrical contacts orconnectors 408 andmultiple conductors device 402 is an integrated circuit, thesubstrate 404 may include a silicon substrate. In the embodiments where the device is a package or module containing multiple integrated circuits, thesubstrate 404 may be a printed circuit board (PCB) or the like. Thedevice 402 has opposing first andsecond sides substrate 404 is substantially planar, i.e., has substantially flat opposing first and second sides. - The
operational circuitry 406 may be embedded into thesubstrate 404 or mounted on thesubstrate 404, as shown. In the embodiments where the device is an integrated circuit, the operational circuitry may include one or more transistors embedded into the die. In the embodiment where the device is a package or module containing multiple integrated circuits, the operational circuitry may be an integrated circuit or die. In some embodiments, multiple discrete operational circuitry components are provided. - In some embodiments, the multiple
electrical contacts 408 include at least four electrical contacts 408(1), 408(2), 408(3), and 408(4). In other embodiments, the device may include as many electrical contacts as is required. Some embodiments include an array ofmultiple rows electrical contacts 408, as shown inFIG. 4C . The electrical contacts may take on any form such as metallic bumps or pads formed or etched onto the surface of thedevice 402. In some embodiments, electrical contacts 408(1) and 408(2) are separated from one another by a predetermined pitch (q). Similarly, electrical contacts 408(3) and 408(4) are separated from one another by a predetermined pitch (q). Also in some embodiments, each electrical contact on thesecond surface 420 of the device is aligned with a respective electrical contact on thefirst surface 418 of the device. For example, electrical contact 408(3) is aligned or collinear with electrical contact 408(1) along an imaginary line that is perpendicular to the first and second surfaces; electrical contact 408(4) is aligned (e.g., collinear) with electrical contact 408(2) along an imaginary line that is perpendicular to the first and second surfaces; electrical contact 408(1) is separated from electrical contact 408(2) by a pitch q; and contact 408(3) is separated from electrical contact 408(4) by the pitch q. - In some embodiments of the invention, the first electrical contact 408(1) is electrically coupled to the
operational circuitry 406 via an operational circuitryelectrical conductor 410. The second electrical contact 408(2) is electrically coupled to the third electrical contact 408(3), which is mechanically coupled to thesecond surface 420 of thedevice 402, via a firstelectrical conductor 412. The second electrical contact 408(2) is also electrically coupled to the fourth electrical contact 408(4), which is mechanically coupled to thesecond surface 420 of thedevice 402, via a secondelectrical conductor 414. The electrical conductors may be any suitable electrical conductors, such as wires, redistribution layers, vias, or the like. In other embodiments of the invention, additional electrical contacts may be electrically coupled to one another via additional electrical conductors that are similar to those described above. - As shown in
FIG. 4A , when the two devices 402(1) and 402(2) are arranged in a stack, an electrical connection is either formed between the third electrical contact 408(3) of the first device 402(1) and the first electrical contact 408(1) of the second device 402(2), or between the fourth electrical contact 408(4) of the first device 402(1) and the second electrical contact 408(2) of the second device 402(2). This electrical connection may be formed by asolder bead 416 or the like. As shown inFIG. 4A , an electrical connection is formed between the third electrical contact 408(3) of the first device 402(1) and the first electrical contact 408(1) of the second device 402(2). Accordingly, in use, a signal to be routed to theoperational circuitry 406 of the first device 402(1) is communicated to the first electrical contact 408(1) of the first device 402(1); and communicated from the first electrical contact 408(1) to theoperational circuitry 406 of the device 402(1) via theoperational circuitry conductor 410 of the first device 402(2). However, to route a signal to theoperational circuitry 406 of the second device 402(2) in the stack, the signal is communicated to the electrical contact 408(2) of the first device 402(1); communicated through thefirst conductor 412 to the third electrical contact of the first device 402(1); communicated from the third electrical contact of the first device 402(1) to the first electrical contact 408(1) of the second device 402(2); and communicated from the first electrical contact 408(1) of the second device 402(2) to theoperational circuitry 406 of the second device 402(2) via theoperational circuitry conductor 410 of the second device 402(2). - Similarly,
FIG. 4B shows a schematic cross-sectional side view of the point-to-point interconnection system ofFIG. 4A and 4C , as viewed alongline 4B-4B′ ofFIG. 4C . Here an electrical connection is made between the fourth electrical contact of the first device 402(1) and the second electrical contact of the second device 402(2); and between the third electrical contact of the second device 402(2) and the first electrical contact 408(1) of the third device 402(3). A signal routed to the first electrical contact of the first device 402(1) is routed to theoperational circuitry 406 of the first device, while a signal routed to the second electrical contact of the first device 402(1) is routed to the operational circuitry of the third device 402(3). Accordingly, by placing electrical connections between predetermined electrical contacts, signals can be communicated through the device alongconductors - The above described systems allow signals to be passed through the stack from one device to the next. In some embodiments, each signal is also shifted one position laterally (in a direction perpendicular to the primary vertical direction of the stack). This permits a signal to be fed into the vertical stack at the bottom device, and be received at a device higher in the stack. This is facilitated by designing the identical pattern of electrical contacts (or RDLs) for all devices in the stack. The above mentioned embodiments permit a unique point-to-point signal (like a chip select for a memory die) to be driven to each device.
- While the foregoing description and drawings represent the preferred embodiments of the present invention, it will be understood that various additions, modifications and substitutions may be made therein without departing from the spirit and scope of the present invention as defined in the accompanying claims. In particular, it will be clear to those skilled in the art that the present invention may be embodied in other specific forms, structures, arrangements, proportions, and with other elements, materials, and components, without departing from the spirit or essential characteristics thereof. The presently disclosed embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims, and not limited to the foregoing description.
Claims (20)
1. A method for making a point-to-point interconnection system, comprising:
providing a plurality of devices that are stacked one on top of another by, for each device that includes a respective substrate having a first surface and an opposing second surface:
(1) forming a first row of contacts on the respective first surface, wherein the first row of contacts includes a first contact and a second contact that are adjacent to each other;
(2) forming a second row of contacts on the second surface, wherein each contact in the second row of contacts is physically aligned with an opposite contact in the first row, and the second row of contacts includes a third contact disposed opposite and physically aligned with the first contact in the first row, and wherein the third contact in the second row of contacts is electrically coupled to the second contact in the first row; and
(3) forming respective operational circuitry electrically coupled to at least one contact on the first row;
wherein at least two of the plurality of devices have distinct operational circuitry.
2. The method of claim 1 , wherein at least a subset of the plurality of devices have identical contact layouts on each of the subset of the plurality of devices.
3. The method of claim 2 , wherein at least the subset of the plurality of devices have identical via layouts on each of the subset of the plurality of devices.
4. The method of claim 1 , further comprising stacking the plurality of devices above one another.
5. The method of claim 1 , wherein the plurality of devices include a first device and a second device stacked directly on top of the first device, further comprising:
electrically coupling the first and second devices via one or more contacts on the second row of the first device and one or more contacts on the first row of the second device.
6. The method of claim 5 , wherein the one or more contacts on the first row of the second device includes the at least one contact of the second device, and the corresponding one or more contacts on the second row of the first device includes the third contact of the first device that is electrically coupled to the second contact on the first row of the first device.
7. The method of claim 6 , wherein the operational circuitry of the second device is electrically coupled to the at least one contact of the second device, and further coupled to the first device via the at least one contact on the second device and the third contact on the first device.
8. The method of claim 1 , wherein at least one of the plurality of devices is selected from a group consisting of an integrated circuit, a semiconductor die, an integrated circuit package, and a module containing one or more dies or packages.
9. The method of claim 1 , wherein at least one of the plurality of devices further includes a RDL that wraps around a edge of the at least one of the plurality of devices and couples two electrical contacts located on the first and second surfaces of the at least one of the plurality of devices, respectively.
10. The method of claim 1 , wherein for each of the plurality of devices, the first row of contacts are evenly spaced on the first surface with a contact pitch, and the second row of contacts are also evenly spaced on the second surface.
11. The method of claim 10 , further comprising:
arranging at least two of the plurality of devices in a stair-like manner when the at least two of the plurality of devices are offset from one another by a spatial distance that is substantially equal to the contact pitch.
12. A method for making a semiconductor device, comprising:
for each of a plurality of semiconductor chips that each include a substrate having a first surface and an opposing second surface:
forming a first row of contacts on the first surface, wherein the first row of contacts includes a first contact and a second contact that are adjacent to each other;
forming a second row of contacts on the second surface, wherein each contact in the second row of contacts is physically aligned with an opposite contact in the first row, and the second row of contacts includes a third contact disposed opposite and physically aligned with the first contact in the first row, and wherein the third contact in the second row of contacts is electrically coupled to the second contact in the first row; and
forming operational circuitry electrically coupled to at least one contact on the first row; and
stacking the plurality of semiconductor chips one on top of the other, wherein at least two of the plurality of semiconductor chips have distinct operational circuitry.
13. The method of claim 12 , wherein the plurality of semiconductor chips are stacked symmetrically above one another.
14. The method of claim 12 , wherein the stacking comprises arranging at least two of the plurality of semiconductor chips in a stair-like manner when the at least two of the plurality of semiconductor chips are offset from one another.
15. The method of claim 12 , wherein, for each of the plurality of semiconductor chips, the first row of contacts are part of a first array of electrical contacts on the first surface of the substrate, and the second row of contacts are part of a second array of electrical contacts on the second surface of the substrate.
16. The method of claim 12 , wherein, for at least one of the plurality of semiconductor chips, at least one contact in the second row of contacts is electrically coupled to its opposite contact in the first row.
17. A method for making an electronic system, comprising:
forming each of a plurality of semiconductor chips by:
providing a substrate having a first surface and an opposing second surface;
forming a first row of contacts on the first surface, wherein the first row of contacts includes a first contact and a second contact that are adjacent to each other;
forming a second row of contacts on the second surface, wherein each contact in the second row of contacts is physically aligned with an opposite contact in the first row, and the second row of contacts includes a third contact disposed opposite and physically aligned with the first contact in the first row, and wherein the third contact in the second row of contacts is electrically coupled to the second contact in the first row; and
forming operational circuitry electrically coupled to at least one contact on the first row;
stacking a first set of the plurality of semiconductor chips to form a first semiconductor device, wherein at least two of the plurality of semiconductor chips in the first set have distinct operational circuitry; and
stacking a second set of the plurality of semiconductor chips to form a second semiconductor device, wherein at least two of the plurality of semiconductor chips in the second set have distinct operational circuitry.
18. The method of claim 17 , wherein for at least one of the first or second semiconductor devices, every two adjacent chips of the plurality of semiconductor chips are electrically coupled via at least one contact on each of corresponding opposing surfaces of the respective two adjacent chips.
19. The method of claim 18 , wherein the at least one contact on each of the corresponding opposing surfaces of every two adjacent chips is selected from a group consisting of a metal bump, a conductive pad, and a redistribution layer (RDL).
20. The method of claim 17 , wherein for at least one of the first or second semiconductor devices, the plurality of semiconductor chips includes a first chip and a second chip that are separated by one or more chips, and the operational circuitry electrically coupled to the first contact of the first chip is electrically coupled to the second chip via the at least one contact on each of the corresponding opposing surfaces of every two adjacent chips arranged between the first and second chips.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US17/068,717 US20210098280A1 (en) | 2006-04-11 | 2020-10-12 | Process for Making a Semiconductor System |
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/402,393 US7701045B2 (en) | 2006-04-11 | 2006-04-11 | Point-to-point connection topology for stacked devices |
US12/361,513 US7989265B2 (en) | 2006-04-11 | 2009-01-28 | Process for making a semiconductor system having devices that have contacts on top and bottom surfaces of each device |
US13/166,996 US8749042B2 (en) | 2006-04-11 | 2011-06-23 | Process for making a semiconductor system |
US14/272,295 US9847248B2 (en) | 2006-04-11 | 2014-05-07 | Method of making a stacked device assembly |
US15/824,762 US10804139B2 (en) | 2006-04-11 | 2017-11-28 | Semiconductor system |
US17/068,717 US20210098280A1 (en) | 2006-04-11 | 2020-10-12 | Process for Making a Semiconductor System |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/824,762 Continuation US10804139B2 (en) | 2006-04-11 | 2017-11-28 | Semiconductor system |
Publications (1)
Publication Number | Publication Date |
---|---|
US20210098280A1 true US20210098280A1 (en) | 2021-04-01 |
Family
ID=38574342
Family Applications (6)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/402,393 Active 2026-10-30 US7701045B2 (en) | 2006-04-11 | 2006-04-11 | Point-to-point connection topology for stacked devices |
US12/361,513 Expired - Fee Related US7989265B2 (en) | 2006-04-11 | 2009-01-28 | Process for making a semiconductor system having devices that have contacts on top and bottom surfaces of each device |
US13/166,996 Active 2026-09-19 US8749042B2 (en) | 2006-04-11 | 2011-06-23 | Process for making a semiconductor system |
US14/272,295 Active 2026-04-15 US9847248B2 (en) | 2006-04-11 | 2014-05-07 | Method of making a stacked device assembly |
US15/824,762 Active 2026-08-30 US10804139B2 (en) | 2006-04-11 | 2017-11-28 | Semiconductor system |
US17/068,717 Pending US20210098280A1 (en) | 2006-04-11 | 2020-10-12 | Process for Making a Semiconductor System |
Family Applications Before (5)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/402,393 Active 2026-10-30 US7701045B2 (en) | 2006-04-11 | 2006-04-11 | Point-to-point connection topology for stacked devices |
US12/361,513 Expired - Fee Related US7989265B2 (en) | 2006-04-11 | 2009-01-28 | Process for making a semiconductor system having devices that have contacts on top and bottom surfaces of each device |
US13/166,996 Active 2026-09-19 US8749042B2 (en) | 2006-04-11 | 2011-06-23 | Process for making a semiconductor system |
US14/272,295 Active 2026-04-15 US9847248B2 (en) | 2006-04-11 | 2014-05-07 | Method of making a stacked device assembly |
US15/824,762 Active 2026-08-30 US10804139B2 (en) | 2006-04-11 | 2017-11-28 | Semiconductor system |
Country Status (1)
Country | Link |
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US (6) | US7701045B2 (en) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
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Also Published As
Publication number | Publication date |
---|---|
US20180082884A1 (en) | 2018-03-22 |
US20090130798A1 (en) | 2009-05-21 |
US8749042B2 (en) | 2014-06-10 |
US20110248407A1 (en) | 2011-10-13 |
US20140329359A1 (en) | 2014-11-06 |
US7701045B2 (en) | 2010-04-20 |
US7989265B2 (en) | 2011-08-02 |
US20070235851A1 (en) | 2007-10-11 |
US9847248B2 (en) | 2017-12-19 |
US10804139B2 (en) | 2020-10-13 |
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