TWM648920U - Wiring carrier and electronic package - Google Patents

Abstract

A wiring carrier is suitable for mounting a plurality of chip components. The wiring carrier includes a plurality of wiring sub-boards, an encapsulant layer and a redistribution circuit structure. The encapsulant layer covers the wiring sub-boards and fills the gap between the wiring sub-boards. One side of the wiring layer exposes one side of each of the wiring sub-boards. The redistribution wiring structure is arranged on the side of the wiring layer farther away from the wiring sub-boards and is suitable for mounting the chip components thereon, so that the chip components are electrically connected to the wiring sub-boards through the redistribution wiring structure.

Description

Circuit carrier boards and electronic packages

The invention relates to an electronic component, and in particular to a circuit carrier board and an electronic package.

Circuit carriers for chip packaging are used to secure integrated circuit (IC) chips and serve as a medium for electrical connection to other electronic components. According to whether it has a dielectric core (dielectric core), circuit carrier boards can be divided into core types and coreless types. In the case of multi-chip packaging, a large size circuit carrier board is required. However, large-size circuit carrier boards have low layout utilization and yield during mass production, which increases production costs.

This new invention provides a circuit carrier board to reduce production costs.

This new creation provides an electronic package to reduce production costs.

A circuit carrier board according to an embodiment of the present invention is suitable for mounting multiple chip components. The circuit carrier board includes multiple circuit sub-boards, an adhesive layer and a redistribution circuit structure. The sealant layer covers these circuit sub-boards and fills the gaps between these circuit sub-boards. One side of the sealant layer exposes one side of each of these circuit daughter boards. The redistribution circuit structure is disposed on a side of the sealant layer that is far away from the circuit sub-boards and is suitable for mounting the chip components thereon, so that the chip components are electrically connected to the circuit sub-boards through the redistribution circuit structure.

An electronic package according to an embodiment of the present invention includes a plurality of chip components and a circuit carrier board. The circuit carrier board includes multiple circuit sub-boards, an adhesive layer and a redistribution circuit structure. The sealant layer covers these circuit sub-boards and fills the gaps between these circuit sub-boards. One side of the sealant layer exposes one side of each of these circuit daughter boards. The redistribution circuit structure is disposed on the side of the sealant layer that is far away from the circuit sub-boards and the chip components are mounted thereon, so that the chip components are electrically connected to the circuit sub-boards through the redistribution circuit structure.

Based on the above, multiple circuit sub-boards are covered with a sealant layer and a redistribution circuit structure is configured on the sealant layer to electrically connect these circuit sub-boards. Compared with large-sized circuit carrier boards traditionally used for chip packaging, small-sized circuit carrier boards have significantly higher layout utilization and yield rates. Therefore, in this case, a small-sized circuit carrier board is used as a circuit sub-board to form a large-sized circuit carrier board, which can also reduce production costs.

Please refer to FIG. 1 . In this embodiment, the electronic package 50 includes a plurality of chip components 51 and a circuit carrier board 100 . These chip components 51 are, for example, integrated circuit bare wafers or small chip packages (such as multi-chip packages, stacked chip packages, chip size packages, etc.). These chip components 51 are mounted to the circuit carrier board 100 , for example via conductive bumps 53 .

In this embodiment, the circuit carrier board 100 includes a plurality of circuit sub-boards 110, an adhesive layer 120 and a redistribution circuit structure 130. The sealant layer 120 covers the circuit sub-boards 110 and fills the gaps between the circuit sub-boards 110, that is, the circuit sub-boards 110 in the sealant layer 120 are insulated from each other. One side of the sealant layer 120 exposes one side of each of these circuit sub-boards 110 to connect to the next level of electronic components (such as a motherboard or a module board, etc.). The redistribution circuit structure 130 is disposed on the side of the sealant layer 120 that is far away from the circuit sub-boards 110 and the chip components 51 are mounted thereon, so that the chip components 51 are electrically connected to the circuit sub-boards 110 through the redistribution circuit structure 130 . Because the circuit sub-boards 110 in the sealant layer 120 are insulated from each other and cannot be directly electrically connected in the sealant layer 120 , the circuit sub-boards 110 can be electrically connected to each other through the redistribution circuit structure 130 . In addition, these circuit sub-boards 110 can be mounted to next-level electronic components, such as a motherboard or a module board, via a plurality of sub-board conductive balls 140 .

In this embodiment, each circuit sub-board 110 may include a plurality of sub-board dielectric layers 112 , a plurality of sub-board patterned conductive layers 114 and a plurality of sub-board conductive vias 116 . The sub-board patterned conductive layers 114 and the sub-board dielectric layers 112 are alternately laminated. The sub-board conductive vias 116 are respectively connected to the sub-board patterned conductive layers 114 . In addition, the redistribution circuit structure 130 may include a plurality of redistribution dielectric layers 132 , a plurality of redistribution patterned conductive layers 134 and a plurality of redistribution conductive vias 136 . The redistributed patterned conductive layers 134 and the redistributed dielectric layers 132 are alternately overlapped. The redistribution conductive channels 136 are respectively connected to the redistribution patterned conductive layers 134 . In one embodiment, the redistribution circuit structure 130 further includes a redistribution patterned conductive layer 134a, which can directly electrically connect at least two circuit sub-boards 110 to transmit signals. In addition, these chip components 51 can also be electrically connected to each other through the redistribution wiring structure 130 to transmit signals.

Please refer to FIG. 2A, FIG. 2B, and FIG. 2C. These chip components 51 and these circuit sub-boards 110 are arranged within the scope of the redistribution circuit structure 130. These circuit sub-boards 110 may be in a rectangular shape, and their lengths and widths may be equal or unequal. The rectangular dimensions of these circuit daughter boards 110 may vary. These circuit sub-boards 110 may be arranged in an area array or in a linear arrangement. In addition, some chip components 51 may be located on corresponding circuit sub-boards 110 respectively, and some chip components 51 may be located on multiple circuit sub-boards 110 at the same time, that is, at least spanning two adjacent circuit sub-boards 110 .

Please refer to FIG. 3. Compared with the electronic package 50 of FIG. 1, the circuit sub-board 110a of the electronic package 50 of FIG. There is no difference in the thickness of these circuit sub-boards 110 in 1, and they can be the same type of circuit sub-boards. Please refer to FIG. 4 . Compared with the electronic package 50 of FIG. 1 , the circuit sub-board 110 and the circuit sub-board 110 b of the electronic package 50 of FIG. 4 may be of different types. For example, the circuit sub-board 110 is a core-less circuit board, and the circuit sub-board 110b may be a core-based circuit board. In other words, in different embodiments, the thickness or type of circuit sub-boards can be selected and combined according to different requirements.

Please refer to FIG. 1 again. In this embodiment, the electronic package 50 may also include a protective cover 52 or other components with a heat dissipation function. The protective cover 52 may also have a heat dissipation function. A protective cover 52 is mounted on the redistribution structure 130 and covers the chip components 51 . In addition, please refer to FIG. 5. Compared with the embodiment of FIG. 1, the electronic package 50 of FIG. 51 , in one embodiment, the chip encapsulant 52 a will expose the backside (non-active side) of these chip components 51 . In addition, please refer to FIG. 6. Compared with the embodiment of FIG. 1, the circuit carrier board 100 of the electronic package 50 of FIG. The sub-board 110 may be mounted on the circuit substrate 150 via a plurality of sub-board conductive balls 140 . In addition, the circuit substrate 150 can be mounted to a next-level electronic component, such as a motherboard or a module board, via a plurality of substrate conductive balls 160 .

A manufacturing method of an electronic structure according to another embodiment of the present invention will be described below with reference to FIGS. 7A to 7F .

Referring to FIG. 7A , a plurality of circuit daughter boards 110 are fixed to a temporary carrier 204 via a temporary bonding layer 202 . In this embodiment, the circuit sub-board 110 has a plurality of conductive pads P. In one embodiment, the conductive pad P is made of copper and includes a bottom copper pad and an upper copper pillar.

Referring to FIG. 7B , a sealant layer 120 is formed to cover the temporary bonding layer 202 and the circuit sub-boards 110 . The sealant layer 120 fills the gaps between the circuit sub-boards 110 . In other words, the circuit sub-boards 110 in the sealant layer 120 are insulated from each other and cannot be directly electrically connected in the sealant layer 120 . In this embodiment, the sealant layer 120 also covers these conductive pads P.

Referring to FIG. 7C , a portion of the sealant layer 120 is removed to expose a portion of each of the conductive pads P, for example, the top surface of the conductive pad P is exposed. This step can flatten the surface of the electronic structure to facilitate subsequent steps.

Referring to FIG. 7D , a redistribution circuit structure 130 is formed on the sealant layer 120 , wherein the redistribution circuit structure 130 is electrically connected to the circuit sub-boards 110 . In this embodiment, a plurality of redistribution conductive channels 136 and a redistribution patterned conductive layer 134 of the redistribution circuit structure 130 are made from the top surfaces of the conductive pads P to electrically connect with the circuit sub-boards 110 . In one embodiment, the redistribution circuit structure 130 further includes a redistribution patterned conductive layer 134a, which can directly electrically connect at least two circuit sub-boards 110. In addition, pre-connection pads 53a may be formed on the redistribution patterned conductive layer 134 of the redistribution wiring structure 130, and may later be used to connect other components. In another embodiment not shown, the temporary bonding layer 202 and the temporary carrier 204 can be removed to form the circuit carrier board 100 of FIG. 8 . Then, these circuit sub-boards 110 can be mounted on the circuit substrate 150 of FIG. 6 to form the circuit carrier board 100 of FIG. 9 .

Referring to FIG. 7E , a plurality of chip components 51 are mounted on the redistribution circuit structure 130 so that the chip components 51 are electrically connected to the circuit daughter boards 110 through the redistribution circuit structure 130 . In addition, these chip components 51 may also be electrically connected to each other via the redistribution wiring structure 130 . In this embodiment, these chip components 51 can be connected to the pre-connection pads 53 a of the redistribution wiring structure 130 via a plurality of conductive bumps 53 . In another not-shown embodiment, a protective cover 52 as shown in FIG. 1 can be installed on the redistribution wiring structure 130 in FIG. 7E and cover the chip components 51 . In another not-shown embodiment, a chip encapsulant 52a as shown in FIG. 5 can be formed on the redistribution wiring structure 130 in FIG. 7E to cover the chip components 51 and expose the back surfaces of the chip components 51 .

Referring to FIG. 7F , the temporary bonding layer 202 and the temporary carrier 204 of FIG. 7E are removed to expose the circuit daughter boards 110 . In another not-shown embodiment, these circuit sub-boards 110 can be mounted on the circuit substrate 150 of FIG. 6 .

In summary, multiple circuit sub-boards are covered with a sealant layer and a redistributed circuit structure is configured on the sealant layer to electrically connect these circuit sub-boards. Compared with traditional large-size circuit carrier boards used for chip packaging, which have a lower yield rate, small-size circuit carrier boards have significantly higher layout utilization and yield rates. Therefore, in this case, a small-sized circuit carrier board is used as a circuit sub-board to form a large-sized circuit carrier board, which can reduce production costs.

50: Electronic package 51:Chip components 52:Protective cover 52a: Chip sealant 53: Conductive bumps 53a:Pre-connected pad 100: Line carrier board 110, 110a, 110b: circuit daughter board 112: Daughter board dielectric layer 114: Daughter board patterned conductive layer 116: Daughter board conductive via 120:Sealing layer 130:Rewiring the line structure 132:Redistribution of dielectric layer 134, 134a: Redistribution of patterned conductive layer 136:Redistribution of conductive channels 140: Daughter board conductive ball 150: Circuit substrate 160:Substrate conductive ball 202: Temporary joint layer 204:Temporary vehicle P: conductive pad

Figure 1 is a schematic cross-sectional view of an electronic package according to an embodiment of the present invention. FIG. 2A is a schematic top view of an arrangement of chip components, circuit sub-boards and redistribution circuit structures of the electronic package of FIG. 1 . FIG. 2B is a schematic top view of another arrangement of chip components, circuit sub-boards and redistribution circuit structures of the electronic package of FIG. 1 . FIG. 2C is a schematic top view of yet another arrangement of chip components, circuit sub-boards and redistribution circuit structures of the electronic package of FIG. 1 . Figure 3 is a schematic cross-sectional view of an electronic package according to another embodiment of the present invention. Figure 4 is a schematic cross-sectional view of an electronic package according to another embodiment of the present invention. Figure 5 is a schematic cross-sectional view of an electronic package according to another embodiment of the present invention. Figure 6 is a schematic cross-sectional view of an electronic package according to another embodiment of the present invention. 7A to 7F illustrate a method of manufacturing an electronic structure according to another embodiment of the present invention. Figure 8 is a schematic cross-sectional view of a circuit carrier board according to another embodiment of the present invention. Figure 9 is a schematic cross-sectional view of a circuit carrier board according to another embodiment of the present invention.

50: Electronic package

51:Chip components

52:Protective cover

53: Conductive bumps

100: Line carrier board

110: Circuit daughter board

112: Daughter board dielectric layer

114: Daughter board patterned conductive layer

116: Daughter board conductive via

120:Sealing layer

130:Rewiring the line structure

132:Redistribution of dielectric layer

134, 134a: Redistribution of patterned conductive layer

136:Redistribution of conductive channels

140: Daughter board conductive ball

Claims (21)

A circuit carrier board suitable for mounting multiple chip components. The circuit carrier board includes: Multiple circuit daughter boards; A sealant layer that covers the circuit sub-boards and fills the gaps between the circuit sub-boards, wherein one side of the sealant layer exposes one side of each of the circuit sub-boards; and A redistribution circuit structure is disposed on a side of the sealant layer farther away from the circuit daughter boards and is suitable for mounting the chip components thereon, so that the chip components are electrically connected to the circuits through the redistribution circuit structure daughter board. The circuit carrier board of claim 1, wherein the chip components are electrically connected to each other via the redistribution circuit structure. The circuit carrier board of claim 1, wherein the circuit sub-boards are electrically connected to each other via the redistribution circuit structure. The circuit carrier board of claim 3, wherein the redistribution circuit structure includes a redistribution patterned conductive layer, and the redistribution patterned conductive layer is directly electrically connected to at least two of the circuit sub-boards. The circuit carrier board according to claim 1, wherein the circuit sub-boards have different rectangular sizes. The circuit carrier board as described in claim 1, wherein the circuit sub-boards have different thicknesses. The circuit carrier board of claim 1, wherein the circuit sub-boards in the sealant layer are insulated from each other. The line carrier board as described in request item 1 further includes: A circuit substrate, the circuit sub-boards are installed on the circuit substrate to be electrically connected to the circuit substrate. An electronic package including: multiple chip components; and A line carrier board, including: Multiple circuit daughter boards; A sealant layer that covers the circuit sub-boards and fills the gaps between the circuit sub-boards, wherein one side of the sealant layer exposes one side of each of the circuit sub-boards; and A redistribution circuit structure is disposed on the side of the sealant layer farther away from the circuit daughter boards and the chip components are mounted thereon, so that the chip components are electrically connected to the circuit daughter boards through the redistribution circuit structure. . The electronic package of claim 9, wherein the chip components are electrically connected to each other via the redistribution wiring structure. The electronic package of claim 9, wherein one of the chip components is a bare chip or a chip package. The electronic package of claim 11, wherein the chip components are electrically connected to each other via the redistribution wiring structure. The electronic package of claim 9, wherein the circuit sub-boards are electrically connected to each other via the redistribution circuit structure. The electronic package of claim 13, wherein the redistribution circuit structure includes a redistribution patterned conductive layer, and the redistribution patterned conductive layer is directly electrically connected to at least two of the circuit sub-boards. The electronic package as claimed in claim 9, wherein the rectangular sizes of the circuit sub-boards are different. The electronic package as claimed in claim 9, wherein the circuit sub-boards have different thicknesses. The electronic package as claimed in claim 9, wherein the circuit sub-boards in the sealant layer are insulated from each other. The electronic package as described in claim 9 further includes: A protective cover is installed on the redistribution circuit structure and covers the chip components. The electronic package as claimed in claim 18, wherein the protective cover has a heat dissipation function. The electronic package as described in claim 9 further includes: A chip encapsulant is disposed on the redistribution wiring structure and fills the gaps between the chip components. The electronic package as claimed in claim 9, wherein the circuit carrier board further includes: A circuit substrate, the circuit sub-boards are installed on the circuit substrate.