US20210036098A1 - Capacitor - Google Patents
Capacitor Download PDFInfo
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- US20210036098A1 US20210036098A1 US16/741,691 US202016741691A US2021036098A1 US 20210036098 A1 US20210036098 A1 US 20210036098A1 US 202016741691 A US202016741691 A US 202016741691A US 2021036098 A1 US2021036098 A1 US 2021036098A1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G2/00—Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
- H01G2/02—Mountings
- H01G2/06—Mountings specially adapted for mounting on a printed-circuit support
- H01G2/065—Mountings specially adapted for mounting on a printed-circuit support for surface mounting, e.g. chip capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
- H05K1/0231—Capacitors or dielectric substances
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1205—Capacitor
Definitions
- the present invention relates to semiconductor technologies, and more particularly, to a semiconductor technology for massively producing capacitors from cutting.
- Current complete capacitor (such as MLCC) manufacturing process includes powder milling, foil casting, printing, stacking, laminating, cutting, BBO (binder burn out), sintering, dipping, curing, electroplating, testing, and taping, etc. This process is quite mature, though complicated, giving the capacitors in sufficient supply and stable production for long time.
- Recently with technological innovations such as Internet, 5G communications, artificial intelligence, electric cars and so on, and with functional improvements of various electronic products, there are more and more demands in types and numbers of components being adopted. Active components are required with increased quantities and higher precision, thus greatly raising the number of passive components that are to be used with the active components, especially MLCC (multi-layer ceramic chip) capacitors.
- the present invention uses different material, structure and manufacturing process so as to provide another option of capacitor for the market.
- the present invention also makes it easier to achieve area reduction of capacitors and thus improves product precision.
- the present invention further avoids a high temperature calcination procedure of the conventional MLCC manufacturing process, thereby in favor of energy saving, carbon reduction and cost decrease.
- a primary object of the present invention is to provide a capacitor, which is more easily made with reduced area, and simplify its manufacturing process and reduce its cost.
- Another primary object of the present invention is to provide a capacitor, which is manufactured by using current semiconductor equipment, to thereby simplify its manufacturing process and reduce its cost, and desirably provide another option of capacitor for the market.
- the first embodiment of the present invention provides a capacitor made by a wafer and for being bonded to a printed circuit board, the capacitor including: a first base layer; at least one first insulating elevation portion located above the first base layer; at least one first electrode layer located above the first insulating elevation portion and having first polarity, wherein the first electrode layer is extended along surface profiles of the first insulating elevation portion to increase its extension length; at least one second electrode layer located above the first electrode layer and having second polarity, wherein the second electrode layer is extended along surface profiles of the first electrode layer to increase its extension length; a first electrode pad electrically connected to the first electrode layer; and a second electrode pad electrically connected to the second electrode layer, wherein the first electrode pad and the second electrode pad are respectively for being bonded to the printed circuit board; and the first base layer is provided on the wafer.
- the at least one first electrode layer includes a plurality of first electrode layers
- the at least one second electrode layer includes a plurality of second electrode layers, wherein the first electrode layers and the second electrode layers are stacked in a staggered manner.
- the at least one first insulating elevation portion includes a plurality of first insulating elevation portions, and there is an insulating elevation recess situated between adjacent two of the first insulating elevation portions, wherein the first electrode layer is extended further along surface profiles of the insulating elevation recess to increase its extension length.
- a protection layer including a first exposed portion and a second exposed portion, wherein the first electrode pad is at least partly exposed from the first exposed portion, and the second electrode pad is at least partly exposed from the second exposed portion.
- the above capacitor further including: at least one dielectric layer located between the first electrode layer and the second electrode layer, for providing electrical isolation between the first electrode layer and the second electrode layer.
- the above capacitor further including: a first conductive channel extended from the first electrode pad to the first electrode layer, for electrically connecting the first electrode pad to the first electrode layer; and a second conductive channel extended from the second electrode pad to the second electrode layer, for electrically connecting the second electrode pad to the second electrode layer.
- the present invention provides a capacitor integrated structure made using a wafer.
- the capacitor integrated structure includes a first capacitor and a second capacitor.
- the first capacitor includes a first base layer, first insulating elevation portions, a first electrode layer and a second electrode layer.
- the first insulating elevation portions are located above the first base layer.
- the first electrode layer is located above the first insulating elevation portions and has first polarity, and is extended along surface profiles of the first insulating elevation portions to increase its extension length.
- the second electrode layer is located above the first electrode layer and has second polarity, and is extended along surface profiles of the first electrode layer to increase its extension length.
- the second capacitor includes a second base layer, second insulating elevation portions, a third electrode layer and a fourth electrode layer.
- the second insulating elevation portions are located above the second base layer.
- the third electrode layer is located above the second insulating elevation portions and has first polarity, and is extended along surface profiles of the second insulating elevation portions to increase its extension length.
- the fourth electrode layer is located above the third electrode layer and has second polarity, and is extended along surface profiles of the third electrode layer to increase its extension length.
- the first capacitor and the second capacitor are substantially identical in structure.
- the first base layer and the second base layer are respectively provided on the wafer.
- the present invention further provides a capacitor, a capacitor made by a wafer and for being bonded to a printed circuit board, the capacitor including: a first base layer; at least one first conductive elevation portion located above the first base layer and having second polarity; at least one first electrode layer located above the first conductive elevation portion and having first polarity, wherein the first electrode layer is extended along surface profiles of the first conductive elevation portion to increase its extension length; a first electrode pad electrically connected to the first electrode layer and having the first polarity; and a second electrode pad electrically connected to the first conductive elevation portion and having the second polarity, wherein the first electrode pad and the second electrode pad are respectively for being bonded to the printed circuit board.
- the above capacitor further including at least one second electrode layer located above the first electrode layer and electrically connected to the first conductive elevation portion to have the second polarity, wherein the second electrode layer is extended along surface profiles of the first electrode layer to increase its extension length.
- the at least one first electrode layer includes a plurality of first electrode layers
- the at least one second electrode layer includes a plurality of second electrode layers, wherein the first electrode layers and the second electrode layers are stacked in a staggered manner.
- the at least one first conductive elevation portion includes a plurality of first conductive elevation portions, and there is an conductive elevation recess situated between adjacent two of the first conductive elevation portions, wherein the first electrode layer is extended further along surface profiles of the conductive elevation recess to increase its extension length.
- a protection layer including a first exposed portion and a second exposed portion, wherein the first electrode pad is at least partly exposed from the first exposed portion, and the second electrode pad is at least partly exposed from the second exposed portion.
- the above capacitor further including: at least one dielectric layer located between the first electrode layer and the first conductive elevation portion, for providing electrical isolation between the first electrode layer and the first conductive elevation portion.
- the above capacitor further including: a first conductive channel extended from the first electrode pad to the first electrode layer, for electrically connecting the first electrode pad to the first electrode layer; and a second conductive channel extended from the second electrode pad to the first conductive elevation portion, for electrically connecting the second electrode pad to the first conductive elevation portion.
- the first base layer is silicon substrate, glass substrate or quartz substrate.
- the capacitor further including an etching stop layer located above the first base layer.
- the present invention also provides a capacitor integrated structure including a first capacitor and a second capacitor.
- the first capacitor includes a first base layer, first conductive elevation portions and a first electrode layer.
- the first conductive elevation portions are located above the first base layer and have second polarity.
- the first electrode layer is located above the first conductive elevation portions and has first polarity, and is extended along surface profiles of the first conductive elevation portions to increase its extension length.
- the second capacitor includes a second base layer, second conductive elevation portions and a third electrode layer.
- the second conductive elevation portions are located above the second base layer and have second polarity.
- the third electrode layer is located above the second conductive elevation portions and has first polarity, and is extended along surface profiles of the second conductive elevation portions to increase its extension length.
- the first capacitor and the second capacitor are substantially identical in structure.
- the present invention further provides a capacitor manufacturing method by which the above capacitor integrated structure is cut to separate the first capacitor and the second capacitor from each other.
- the present invention allows a capacitor integrated structure composed of a plurality of capacitors to be formed on a wafer, and cuts the capacitor integrated structure to separate the plurality of capacitors from each other so as to massively produce capacitors.
- the present invention simplifies the capacitor manufacturing process while avoids a high temperature calcination procedure of the conventional MLCC manufacturing process.
- the present invention also allows the capacitor integrated structure to be manufactured by current semiconductor equipment, thereby in favor of cost reduction.
- the capacitor in the present invention includes structural elevation portions, which increase an extension length of its electrode layer and thus reduce capacitor area.
- the structural elevation portions can be made of a metallic material, and with the metallic structural elevation portions serving as electrodes, the number of electrode layers is reduced in the capacitor, thereby simplifying the capacitor structure and lowering its manufacturing cost.
- FIG. 1 is a schematic diagram of a wafer used for manufacturing capacitors according to an embodiment of the present invention
- FIGS. 2 to 4 are structural schematic diagrams of a capacitor according to a first embodiment of the present invention.
- FIGS. 5 to 8 are structural schematic diagrams of a capacitor according to a second embodiment of the present invention.
- FIGS. 9A to 9C are schematic diagrams of a capacitor integrated structure according to the present invention.
- FIGS. 10A to 10B are schematic diagrams of capacitors according to the present invention.
- FIGS. 2 to 4 show a capacitor 11 according to a first embodiment of the present invention.
- the capacitor 11 includes a first base layer 111 , first insulating elevation portions 1121 , a first electrode layer 1131 , a second electrode layer 1132 , a first electrode pad 1141 and a second electrode pad 1142 .
- the first base layer 111 is mounted on the wafer 12 shown in FIG. 1 .
- an isolation layer 1111 is further formed on the first base layer 111 by depositing a base insulation layer on the first base layer 111 by means of, for example, chemical vapor deposition (CVD) or oxidation deposition.
- the first base layer 111 is, for example but not limited to, a silicon substrate used for producing integrated circuits, and can also be made of another material, such as glass substrate, quartz substrate and so on.
- the first insulating elevation portions 1121 are located above the first base layer 111 , and are formed by denting an insulation layer 1120 . Particularly, the insulation layer 1120 is provided above the isolation layer 1111 on the first base layer 111 , and is subjected to a denting procedure to obtain the first insulating elevation portions 1121 . In the embodiment shown in FIG.
- the insulation layer 1120 is dented to have two recesses and thus form three of the first insulating elevation portions 1121 , wherein there is an insulating elevation recess 1122 situated between any adjacent two of the first insulating elevation portions 1121 in a manner that, the first insulating elevation portions 1121 and the insulating elevation recesses 1122 are arranged in a staggered layout on the first base layer 111 .
- the first electrode layer 1131 is located above the first insulating elevation portions 1121 and has first polarity. It is applied and extended along surface profiles of the insulating elevation portions 1121 and insulating elevation recesses 1122 , making the first electrode layer 1131 entirely have a serpentine pattern with curved and twisted traces. This increases an extension length of the first electrode layer 1131 and thus enlarges capacity of the capacitor 11 .
- the second electrode layer 1132 is located above the first electrode layer 1131 and has second polarity. It is applied and extended along surface profiles of the first electrode layer 1131 , making the second electrode layer 1132 similarly have serpentine traces, thereby increasing an extension length of the second electrode layer 1132 and also enlarging capacity of the capacitor 11 .
- the capacitor 11 may include a plurality of first electrode layers 1131 and a plurality of second electrode layers 1132 , wherein the first electrode layers 1131 and the second electrode layers 1132 are stacked in a staggered manner, and a dielectric layer 1130 can further be formed between any adjacent the first electrode layer 1131 and the second electrode layer 1132 to provide electrical isolation for them.
- the first electrode pad 1141 and the second electrode pad 1142 are electrically connected to the first electrode layer 1131 and the second electrode layer 1132 respectively, such that the first electrode pad 1141 has first polarity, and the second electrode pad 1142 has second polarity.
- a metal layer 1140 is provided on the topmost first electrode layer 1131 or second electrode layer 1132 , and is etched to have recesses. Then, a protection layer 115 is applied over the metal layer 1140 and fills the recesses of the metal layer 1140 to form electrically isolated first electrode pad 1141 and second electrode pad 1142 .
- the protection layer 115 is then etched to form a first exposed portion 1151 and a second exposed portion 1152 , wherein the first electrode pad 1141 is at least partly exposed from the first exposed portion 1151 , and the second electrode pad 1142 is at least partly exposed from the second exposed portion 1152 , such that the first electrode pad 1141 and the second electrode pad 1142 can be respectively bonded to a printed circuit board (PCB).
- PCB printed circuit board
- the capacitor 11 further includes a first conductive channel 1161 and a second conductive channel 1162 , as shown in FIG. 4 .
- the first conductive channel 1161 is extended from the first electrode pad 1141 to the first electrode layer 1131 , and is used to electrically connect the first electrode pad 1141 to the first electrode layer 1131 .
- the second conductive channel 1162 is extended from the second electrode pad 1142 to the second electrode layer 1132 , and is used to electrically connect the second electrode pad 1142 to the second electrode layer 1132 .
- FIGS. 5 to 8 show a capacitor 11 according to a second embodiment of the present invention.
- This capacitor 11 is also made using the wafer 12 (shown in FIG. 1 ). It includes a first base layer 111 , first conductive elevation portions 1171 , a first electrode layer 1131 , a first electrode pad 1141 and a second electrode pad 1142 .
- the first base layer 111 is mounted on the wafer 12 .
- an isolation layer 1111 is further formed on the first base layer 111 by depositing a base insulation layer on the first base layer 111 by means of, for example, chemical vapor deposition (CVD) or oxidation deposition.
- the first base layer 111 is, for example but not limited to, a silicon substrate used for producing integrated circuits, and can also be made of another material, such as glass substrate, quartz substrate and so on.
- the first conductive elevation portions 1171 are located above the first base layer 111 and have second polarity.
- the first conductive elevation portions 1171 are formed by denting a metallic material layer 1170 .
- the metallic material layer 1170 is provided above an isolation layer 1111 on the first base layer 111 , and is subjected to a denting procedure to obtain the first conductive elevation portions 1171 .
- FIG. 1 In the embodiment shown in FIG. 1
- the metallic material layer 1170 there are three recesses formed in the metallic material layer 1170 to obtain four of the first conductive elevation portions 1171 , and there is a conductive elevation recess 1172 situated between any adjacent two of the first conductive elevation portions 1171 in a manner that, the first conductive elevation portions 1171 and the conductive elevation recesses 1172 are arranged in a staggered layout on the first base layer 111 .
- a conductive layer 1113 serving as an etching stop layer between the isolation layer 1111 and the metallic material layer 1170 .
- the metallic material layer 1170 can be replaced with a polycrystalline material layer 1170 ′, and there can further be formed an implant layer 1114 serving as an etching stop layer between the polycrystalline material layer 1170 ′ and the first base layer 111 .
- the first electrode layer 1131 is located above the first conductive elevation portions 1171 and has first polarity. It is applied and extended along surface profiles of the first conductive elevation portions 1171 and the conductive elevation recesses 1172 , making the first electrode layer 1131 entirely have serpentine traces and increase its extension length to thereby enlarge capacity of the capacitor 11 .
- the capacitor 11 further includes a second electrode layer 1132 located above the first electrode layer 1131 .
- the second electrode layer 1132 is electrically connected to the first conductive elevation portions 1171 and thus has the same second polarity as the first conductive elevation portions 1171 .
- the second electrode layer 1132 is applied and extended along surface profiles of the first electrode layer 1131 to similarly have serpentine traces, making the second electrode layer 1132 increase its extension length and thereby enlarging capacity of the capacitor 11 .
- the capacitor 11 may include a plurality of first electrode layers 1131 and a plurality of second electrode layers 1132 , wherein the first electrode layers 1131 and the second electrode layers 1132 are stacked in a staggered manner, and a dielectric layer 1130 can further be formed between any adjacent first electrode layer 1131 and the second electrode layer 1132 to provide electrical isolation for them.
- the first electrode pad 1141 and the second electrode pad 1142 are electrically connected to the first electrode layer 1131 and the first conductive elevation portions 1171 respectively, such that the first electrode pad 1141 has first polarity, and the second electrode pad 1142 has second polarity.
- a metal layer 1140 is provided on the topmost the first electrode layer 1131 or the second electrode layer 1132 , and is etched to have recesses. Then, a protection layer 115 is applied over the metal layer 1140 and fills the recesses of the metal layer 1140 to form electrically isolated the first electrode pad 1141 and the second electrode pad 1142 .
- the protection layer 115 is then etched to form first exposed portion 1151 and the second exposed portion 1152 , wherein the first electrode pad 1141 is at least partly exposed from the first exposed portion 1151 , and the second electrode pad 1142 is at least partly exposed from the second exposed portion 1152 , such that the first electrode pad 1141 and the second electrode pad 1142 can be respectively bonded to a printed circuit board (PCB).
- PCB printed circuit board
- the capacitor 11 further includes a first conductive channel 1161 and a second conductive channel 1162 , as shown in FIG. 7 or FIG. 8 .
- the first conductive channel 1161 is extended from the first electrode pad 1141 to the first electrode layer 1131 , and is used to electrically connect the first electrode pad 1141 to the first electrode layer 1131 .
- the second conductive channel 1162 is extended from the first electrode pad 1141 to the first conductive elevation portions 1171 , and is used to electrically connect the first conductive elevation portions 1171 to the second electrode pad 1142 .
- the present invention further provides a capacitor integrated structure 1 for the capacitors 11 in the first embodiment and the second embodiment, as shown in FIGS. 9A to 9C .
- the capacitor integrated structure 1 in the present invention mainly uses the wafer 12 to form the capacitor 11 according to the above first embodiment.
- the capacitor integrated structure 1 can form at least one first capacitor 11 A and at least one second capacitor 11 B through a cutting procedure, which are substantially identical in structure.
- the first capacitor 11 A includes a first base layer 111 , first insulating elevation portions 1121 , a first electrode layer 1131 and a second electrode layer 1132 .
- the first insulating elevation portions 1121 are located above the first base layer 111 .
- the first electrode layer 1131 is located above the first insulating elevation portions 1121 and has first polarity, and is extended along surface profiles of the first insulating elevation portions 1121 to have serpentine traces to thereby increase its extension length.
- the second electrode layer 1132 is located above the first electrode layer 1131 and has second polarity, and is extended along surface profiles of the first electrode layer 1131 to similarly have serpentine traces to thereby effectively increase its extension length.
- the second capacitor 11 B includes a second base layer 111 ′, second insulating elevation portions 1121 ′, a third electrode layer 1133 and a fourth electrode layer 1134 .
- the second insulating elevation portions 1121 ′ are located above the second base layer 111 ′.
- the third electrode layer 1133 is located above the second insulating elevation portions 1121 ′ and has first polarity, and is extended along surface profiles of the second insulating elevation portions 1121 ′ to have serpentine traces to thereby increase its extension length.
- the fourth electrode layer 1134 is located above the third electrode layer 1133 and has second polarity, and is extended along surface profiles of the third electrode layer 1133 to similarly have serpentine traces to thereby increase its extension length.
- first capacitor 11 A and the second capacitor 11 B are basically same as the capacitor 11 shown in FIGS. 2 to 4 , and are thus not to be further described here.
- the capacitor integrated structure 1 in the present invention mainly uses the wafer 12 to form the capacitor 11 according to the above second embodiment.
- the capacitor integrated structure 1 can form a first capacitor 11 A and a second capacitor 11 B through a cutting procedure, which are substantially identical in structure.
- the first capacitor 11 A includes a first base layer 111 , at least one first conductive elevation portions 1171 and at least one first electrode layer 1131 .
- the first conductive elevation portions 1171 are located above the first base layer 111 and has second polarity.
- the first electrode layer 1131 is located above the first conductive elevation portions 1171 and has first polarity, and is extended along surface profiles of the first conductive elevation portions 1171 to have serpentine traces to thereby increase its extension length.
- the second capacitor 11 B includes a second base layer 111 ′, at least one second conductive elevation portions 1171 ′ and at least one third electrode layer 1133 .
- the second conductive elevation portions 1171 ′ are located above the second base layer 111 ′ and has second polarity.
- the third electrode layer 1133 is located above the second conductive elevation portions 1171 ′ and has first polarity, and is extended along surface profiles of the second conductive elevation portions 1171 ′ to have serpentine traces to thereby increase its extension length.
- first capacitor 11 A and the second capacitor 11 B are basically same as the capacitor 11 shown in FIGS. 5 to 8 , and are thus not to be further described here.
- the first base layer 111 and the second base layer 111 ′ are respectively mounted on the wafer 12 , making the first capacitor 11 A and the second capacitor 11 B arranged in an array on the wafer 12 to form the capacitor integrated structure 1 , as shown in FIGS. 9A to 9B .
- the capacitor integrated structure 1 can thus be cut to separate the first capacitor 11 A and the second capacitor 11 B from each other and obtain individual the first capacitor 11 A and the second capacitor 11 B shown in FIGS. 10A and 10B .
- electrode contacts E of the first capacitor 11 A and the second capacitors 11 B are flexibly shaped as rectangular prism or hemisphere, as shown in FIGS. 10A and 10B .
- the present invention allows a plurality of capacitors to be formed on a wafer to construct a capacitor integrated structure composed of the plurality of capacitors.
- the capacitor integrated structure can be cut to separate the capacitors from each other so as to produce massive individual capacitors at a time, thereby simplifying the current capacitor manufacturing process while avoiding a high temperature calcination procedure of the conventional MLCC manufacturing process.
- the present invention also allows the capacitor integrated structure to be manufactured by current semiconductor manufacturing equipment, thereby in favor of cost reduction.
- the capacitor in the present invention includes structural elevation portions, making its electrode layer extended along surface profiles of the structural elevation portions to have serpentine traces. This desirably increases an extension length of the electrode layer, reduces capacitor area and enlarges capacitor capacity, thereby in favor of size miniaturization of electronic products.
- the present invention can also use a metallic material to form the structural elevation portions, and with the metallic structural elevation portions serving as conductive electrodes, the number of electrode layers is reduced in the capacitor, thereby simplifying the capacitor structure and lowering its manufacturing cost.
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Abstract
Description
- This application claims the priority of Taiwan Application No. 108127413 filed on Aug. 1, 2019, in the State Intellectual Property Office of the R.O.C., the disclosure of which is incorporated herein by reference.
- The present invention relates to semiconductor technologies, and more particularly, to a semiconductor technology for massively producing capacitors from cutting.
- Current complete capacitor (such as MLCC) manufacturing process includes powder milling, foil casting, printing, stacking, laminating, cutting, BBO (binder burn out), sintering, dipping, curing, electroplating, testing, and taping, etc. This process is quite mature, though complicated, giving the capacitors in sufficient supply and stable production for long time. Recently with technological innovations such as Internet, 5G communications, artificial intelligence, electric cars and so on, and with functional improvements of various electronic products, there are more and more demands in types and numbers of components being adopted. Active components are required with increased quantities and higher precision, thus greatly raising the number of passive components that are to be used with the active components, especially MLCC (multi-layer ceramic chip) capacitors. This thereby results in short supply of the passive components, while manufacturers thereof have not yet found a solution to massive production to meet the market demands for passive components. Moreover, another issue is about fitting all required components in a limited space in order to have a high density layout of components, which must be achieved by using compact components with reduced area and/or volume. This is however quite challenging to conventional capacitor manufacturing technique in terms of size reduction or product precision improvement.
- In view of this, compared to conventional MLCC production, the present invention uses different material, structure and manufacturing process so as to provide another option of capacitor for the market. The present invention also makes it easier to achieve area reduction of capacitors and thus improves product precision. The present invention further avoids a high temperature calcination procedure of the conventional MLCC manufacturing process, thereby in favor of energy saving, carbon reduction and cost decrease.
- In view of the above drawbacks in the prior art, a primary object of the present invention is to provide a capacitor, which is more easily made with reduced area, and simplify its manufacturing process and reduce its cost.
- Another primary object of the present invention is to provide a capacitor, which is manufactured by using current semiconductor equipment, to thereby simplify its manufacturing process and reduce its cost, and desirably provide another option of capacitor for the market.
- For the objects said above and for other objects, the first embodiment of the present invention provides a capacitor made by a wafer and for being bonded to a printed circuit board, the capacitor including: a first base layer; at least one first insulating elevation portion located above the first base layer; at least one first electrode layer located above the first insulating elevation portion and having first polarity, wherein the first electrode layer is extended along surface profiles of the first insulating elevation portion to increase its extension length; at least one second electrode layer located above the first electrode layer and having second polarity, wherein the second electrode layer is extended along surface profiles of the first electrode layer to increase its extension length; a first electrode pad electrically connected to the first electrode layer; and a second electrode pad electrically connected to the second electrode layer, wherein the first electrode pad and the second electrode pad are respectively for being bonded to the printed circuit board; and the first base layer is provided on the wafer.
- Preferably, in the above capacitor, wherein the at least one first electrode layer includes a plurality of first electrode layers, and the at least one second electrode layer includes a plurality of second electrode layers, wherein the first electrode layers and the second electrode layers are stacked in a staggered manner.
- Preferably, in the above capacitor, wherein the at least one first insulating elevation portion includes a plurality of first insulating elevation portions, and there is an insulating elevation recess situated between adjacent two of the first insulating elevation portions, wherein the first electrode layer is extended further along surface profiles of the insulating elevation recess to increase its extension length.
- Preferably, in the above capacitor, further including: a protection layer including a first exposed portion and a second exposed portion, wherein the first electrode pad is at least partly exposed from the first exposed portion, and the second electrode pad is at least partly exposed from the second exposed portion.
- Preferably, in the above capacitor, further including: at least one dielectric layer located between the first electrode layer and the second electrode layer, for providing electrical isolation between the first electrode layer and the second electrode layer.
- Preferably, in the above capacitor, further including: a first conductive channel extended from the first electrode pad to the first electrode layer, for electrically connecting the first electrode pad to the first electrode layer; and a second conductive channel extended from the second electrode pad to the second electrode layer, for electrically connecting the second electrode pad to the second electrode layer.
- The present invention provides a capacitor integrated structure made using a wafer. The capacitor integrated structure includes a first capacitor and a second capacitor. The first capacitor includes a first base layer, first insulating elevation portions, a first electrode layer and a second electrode layer. The first insulating elevation portions are located above the first base layer. The first electrode layer is located above the first insulating elevation portions and has first polarity, and is extended along surface profiles of the first insulating elevation portions to increase its extension length. The second electrode layer is located above the first electrode layer and has second polarity, and is extended along surface profiles of the first electrode layer to increase its extension length. The second capacitor includes a second base layer, second insulating elevation portions, a third electrode layer and a fourth electrode layer. The second insulating elevation portions are located above the second base layer. The third electrode layer is located above the second insulating elevation portions and has first polarity, and is extended along surface profiles of the second insulating elevation portions to increase its extension length. The fourth electrode layer is located above the third electrode layer and has second polarity, and is extended along surface profiles of the third electrode layer to increase its extension length. The first capacitor and the second capacitor are substantially identical in structure. The first base layer and the second base layer are respectively provided on the wafer.
- Furthermore, the present invention further provides a capacitor, a capacitor made by a wafer and for being bonded to a printed circuit board, the capacitor including: a first base layer; at least one first conductive elevation portion located above the first base layer and having second polarity; at least one first electrode layer located above the first conductive elevation portion and having first polarity, wherein the first electrode layer is extended along surface profiles of the first conductive elevation portion to increase its extension length; a first electrode pad electrically connected to the first electrode layer and having the first polarity; and a second electrode pad electrically connected to the first conductive elevation portion and having the second polarity, wherein the first electrode pad and the second electrode pad are respectively for being bonded to the printed circuit board.
- Preferably, in the above capacitor, further including at least one second electrode layer located above the first electrode layer and electrically connected to the first conductive elevation portion to have the second polarity, wherein the second electrode layer is extended along surface profiles of the first electrode layer to increase its extension length.
- Preferably, in the above capacitor, wherein the at least one first electrode layer includes a plurality of first electrode layers, and the at least one second electrode layer includes a plurality of second electrode layers, wherein the first electrode layers and the second electrode layers are stacked in a staggered manner.
- Preferably, in the above capacitor, wherein the at least one first conductive elevation portion includes a plurality of first conductive elevation portions, and there is an conductive elevation recess situated between adjacent two of the first conductive elevation portions, wherein the first electrode layer is extended further along surface profiles of the conductive elevation recess to increase its extension length.
- Preferably, in the above capacitor, further including: a protection layer including a first exposed portion and a second exposed portion, wherein the first electrode pad is at least partly exposed from the first exposed portion, and the second electrode pad is at least partly exposed from the second exposed portion.
- Preferably, in the above capacitor, further including: at least one dielectric layer located between the first electrode layer and the first conductive elevation portion, for providing electrical isolation between the first electrode layer and the first conductive elevation portion.
- Preferably, in the above capacitor, further including: a first conductive channel extended from the first electrode pad to the first electrode layer, for electrically connecting the first electrode pad to the first electrode layer; and a second conductive channel extended from the second electrode pad to the first conductive elevation portion, for electrically connecting the second electrode pad to the first conductive elevation portion.
- Preferably, in the above capacitor, wherein the first base layer is silicon substrate, glass substrate or quartz substrate.
- Preferably, in the above capacitor, wherein the capacitor further including an etching stop layer located above the first base layer.
- Moreover, the present invention also provides a capacitor integrated structure including a first capacitor and a second capacitor. The first capacitor includes a first base layer, first conductive elevation portions and a first electrode layer. The first conductive elevation portions are located above the first base layer and have second polarity. The first electrode layer is located above the first conductive elevation portions and has first polarity, and is extended along surface profiles of the first conductive elevation portions to increase its extension length. The second capacitor includes a second base layer, second conductive elevation portions and a third electrode layer. The second conductive elevation portions are located above the second base layer and have second polarity. The third electrode layer is located above the second conductive elevation portions and has first polarity, and is extended along surface profiles of the second conductive elevation portions to increase its extension length. The first capacitor and the second capacitor are substantially identical in structure.
- The present invention further provides a capacitor manufacturing method by which the above capacitor integrated structure is cut to separate the first capacitor and the second capacitor from each other.
- Therefore, the present invention allows a capacitor integrated structure composed of a plurality of capacitors to be formed on a wafer, and cuts the capacitor integrated structure to separate the plurality of capacitors from each other so as to massively produce capacitors. Compared to the conventional MLCC manufacturing process, the present invention simplifies the capacitor manufacturing process while avoids a high temperature calcination procedure of the conventional MLCC manufacturing process. The present invention also allows the capacitor integrated structure to be manufactured by current semiconductor equipment, thereby in favor of cost reduction.
- Moreover, the capacitor in the present invention includes structural elevation portions, which increase an extension length of its electrode layer and thus reduce capacitor area. Preferably, the structural elevation portions can be made of a metallic material, and with the metallic structural elevation portions serving as electrodes, the number of electrode layers is reduced in the capacitor, thereby simplifying the capacitor structure and lowering its manufacturing cost.
- The above and other aspects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
-
FIG. 1 is a schematic diagram of a wafer used for manufacturing capacitors according to an embodiment of the present invention; -
FIGS. 2 to 4 are structural schematic diagrams of a capacitor according to a first embodiment of the present invention; -
FIGS. 5 to 8 are structural schematic diagrams of a capacitor according to a second embodiment of the present invention; -
FIGS. 9A to 9C are schematic diagrams of a capacitor integrated structure according to the present invention; and -
FIGS. 10A to 10B are schematic diagrams of capacitors according to the present invention. - Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. The invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the shapes and dimensions of elements may be exaggerated for clarity, and the same reference numerals will be used throughout to designate the same or like components.
- In the following, elements with the same or similar functions will be described using the same reference numerals, and the description of the same or equivalent features will be omitted for the disclosed content to be more concise and easier to be understood.
- Referring to
FIG. 1 , the present invention provides capacitors made using awafer 12.FIGS. 2 to 4 show acapacitor 11 according to a first embodiment of the present invention. As shown, thecapacitor 11 includes afirst base layer 111, first insulating elevation portions 1121, afirst electrode layer 1131, asecond electrode layer 1132, afirst electrode pad 1141 and asecond electrode pad 1142. - The
first base layer 111 is mounted on thewafer 12 shown inFIG. 1 . In this embodiment, anisolation layer 1111 is further formed on thefirst base layer 111 by depositing a base insulation layer on thefirst base layer 111 by means of, for example, chemical vapor deposition (CVD) or oxidation deposition. Thefirst base layer 111 is, for example but not limited to, a silicon substrate used for producing integrated circuits, and can also be made of another material, such as glass substrate, quartz substrate and so on. - The first insulating elevation portions 1121 are located above the
first base layer 111, and are formed by denting aninsulation layer 1120. Particularly, theinsulation layer 1120 is provided above theisolation layer 1111 on thefirst base layer 111, and is subjected to a denting procedure to obtain the first insulating elevation portions 1121. In the embodiment shown inFIG. 2 , theinsulation layer 1120 is dented to have two recesses and thus form three of the first insulating elevation portions 1121, wherein there is aninsulating elevation recess 1122 situated between any adjacent two of the first insulating elevation portions 1121 in a manner that, the first insulating elevation portions 1121 and theinsulating elevation recesses 1122 are arranged in a staggered layout on thefirst base layer 111. Preferably, there can further be provided anetching stop layer 1112 between theisolation layer 1111 and theinsulation layer 1120. - The
first electrode layer 1131 is located above the first insulating elevation portions 1121 and has first polarity. It is applied and extended along surface profiles of the insulating elevation portions 1121 andinsulating elevation recesses 1122, making thefirst electrode layer 1131 entirely have a serpentine pattern with curved and twisted traces. This increases an extension length of thefirst electrode layer 1131 and thus enlarges capacity of thecapacitor 11. Thesecond electrode layer 1132 is located above thefirst electrode layer 1131 and has second polarity. It is applied and extended along surface profiles of thefirst electrode layer 1131, making thesecond electrode layer 1132 similarly have serpentine traces, thereby increasing an extension length of thesecond electrode layer 1132 and also enlarging capacity of thecapacitor 11. - As shown in
FIG. 3 , thecapacitor 11 may include a plurality offirst electrode layers 1131 and a plurality ofsecond electrode layers 1132, wherein thefirst electrode layers 1131 and thesecond electrode layers 1132 are stacked in a staggered manner, and adielectric layer 1130 can further be formed between any adjacent thefirst electrode layer 1131 and thesecond electrode layer 1132 to provide electrical isolation for them. - The
first electrode pad 1141 and thesecond electrode pad 1142 are electrically connected to thefirst electrode layer 1131 and thesecond electrode layer 1132 respectively, such that thefirst electrode pad 1141 has first polarity, and thesecond electrode pad 1142 has second polarity. Preferably, ametal layer 1140 is provided on the topmostfirst electrode layer 1131 orsecond electrode layer 1132, and is etched to have recesses. Then, aprotection layer 115 is applied over themetal layer 1140 and fills the recesses of themetal layer 1140 to form electrically isolatedfirst electrode pad 1141 andsecond electrode pad 1142. Theprotection layer 115 is then etched to form a first exposedportion 1151 and a second exposedportion 1152, wherein thefirst electrode pad 1141 is at least partly exposed from the first exposedportion 1151, and thesecond electrode pad 1142 is at least partly exposed from the second exposedportion 1152, such that thefirst electrode pad 1141 and thesecond electrode pad 1142 can be respectively bonded to a printed circuit board (PCB). - In another embodiment of the invention, the
capacitor 11 further includes a firstconductive channel 1161 and a secondconductive channel 1162, as shown inFIG. 4 . The firstconductive channel 1161 is extended from thefirst electrode pad 1141 to thefirst electrode layer 1131, and is used to electrically connect thefirst electrode pad 1141 to thefirst electrode layer 1131. The secondconductive channel 1162 is extended from thesecond electrode pad 1142 to thesecond electrode layer 1132, and is used to electrically connect thesecond electrode pad 1142 to thesecond electrode layer 1132. -
FIGS. 5 to 8 show acapacitor 11 according to a second embodiment of the present invention. Thiscapacitor 11 is also made using the wafer 12 (shown inFIG. 1 ). It includes afirst base layer 111, first conductive elevation portions 1171, afirst electrode layer 1131, afirst electrode pad 1141 and asecond electrode pad 1142. - The
first base layer 111 is mounted on thewafer 12. In this embodiment, anisolation layer 1111 is further formed on thefirst base layer 111 by depositing a base insulation layer on thefirst base layer 111 by means of, for example, chemical vapor deposition (CVD) or oxidation deposition. Thefirst base layer 111 is, for example but not limited to, a silicon substrate used for producing integrated circuits, and can also be made of another material, such as glass substrate, quartz substrate and so on. - The first conductive elevation portions 1171 are located above the
first base layer 111 and have second polarity. In this embodiment, the first conductive elevation portions 1171 are formed by denting ametallic material layer 1170. Particularly, themetallic material layer 1170 is provided above anisolation layer 1111 on thefirst base layer 111, and is subjected to a denting procedure to obtain the first conductive elevation portions 1171. In the embodiment shown inFIG. 5 , there are three recesses formed in themetallic material layer 1170 to obtain four of the first conductive elevation portions 1171, and there is aconductive elevation recess 1172 situated between any adjacent two of the first conductive elevation portions 1171 in a manner that, the first conductive elevation portions 1171 and theconductive elevation recesses 1172 are arranged in a staggered layout on thefirst base layer 111. Preferably, there can further be provided aconductive layer 1113 serving as an etching stop layer between theisolation layer 1111 and themetallic material layer 1170. - Referring to
FIG. 6 , preferably, themetallic material layer 1170 can be replaced with apolycrystalline material layer 1170′, and there can further be formed animplant layer 1114 serving as an etching stop layer between thepolycrystalline material layer 1170′ and thefirst base layer 111. - The
first electrode layer 1131 is located above the first conductive elevation portions 1171 and has first polarity. It is applied and extended along surface profiles of the first conductive elevation portions 1171 and the conductive elevation recesses 1172, making thefirst electrode layer 1131 entirely have serpentine traces and increase its extension length to thereby enlarge capacity of thecapacitor 11. - As shown in
FIGS. 7 and 8 , thecapacitor 11 further includes asecond electrode layer 1132 located above thefirst electrode layer 1131. Thesecond electrode layer 1132 is electrically connected to the first conductive elevation portions 1171 and thus has the same second polarity as the first conductive elevation portions 1171. Thesecond electrode layer 1132 is applied and extended along surface profiles of thefirst electrode layer 1131 to similarly have serpentine traces, making thesecond electrode layer 1132 increase its extension length and thereby enlarging capacity of thecapacitor 11. - In other embodiment, the
capacitor 11 may include a plurality offirst electrode layers 1131 and a plurality ofsecond electrode layers 1132, wherein thefirst electrode layers 1131 and thesecond electrode layers 1132 are stacked in a staggered manner, and adielectric layer 1130 can further be formed between any adjacentfirst electrode layer 1131 and thesecond electrode layer 1132 to provide electrical isolation for them. - The
first electrode pad 1141 and thesecond electrode pad 1142 are electrically connected to thefirst electrode layer 1131 and the first conductive elevation portions 1171 respectively, such that thefirst electrode pad 1141 has first polarity, and thesecond electrode pad 1142 has second polarity. Preferably, ametal layer 1140 is provided on the topmost thefirst electrode layer 1131 or thesecond electrode layer 1132, and is etched to have recesses. Then, aprotection layer 115 is applied over themetal layer 1140 and fills the recesses of themetal layer 1140 to form electrically isolated thefirst electrode pad 1141 and thesecond electrode pad 1142. Theprotection layer 115 is then etched to form first exposedportion 1151 and the second exposedportion 1152, wherein thefirst electrode pad 1141 is at least partly exposed from the first exposedportion 1151, and thesecond electrode pad 1142 is at least partly exposed from the second exposedportion 1152, such that thefirst electrode pad 1141 and thesecond electrode pad 1142 can be respectively bonded to a printed circuit board (PCB). - In another embodiment of the invention, the
capacitor 11 further includes a firstconductive channel 1161 and a secondconductive channel 1162, as shown inFIG. 7 orFIG. 8 . The firstconductive channel 1161 is extended from thefirst electrode pad 1141 to thefirst electrode layer 1131, and is used to electrically connect thefirst electrode pad 1141 to thefirst electrode layer 1131. The secondconductive channel 1162 is extended from thefirst electrode pad 1141 to the first conductive elevation portions 1171, and is used to electrically connect the first conductive elevation portions 1171 to thesecond electrode pad 1142. - Moreover, the present invention further provides a capacitor integrated
structure 1 for thecapacitors 11 in the first embodiment and the second embodiment, as shown inFIGS. 9A to 9C . - The capacitor integrated
structure 1 in the present invention mainly uses thewafer 12 to form thecapacitor 11 according to the above first embodiment. The capacitor integratedstructure 1 can form at least onefirst capacitor 11A and at least onesecond capacitor 11B through a cutting procedure, which are substantially identical in structure. - The
first capacitor 11A includes afirst base layer 111, first insulating elevation portions 1121, afirst electrode layer 1131 and asecond electrode layer 1132. The first insulating elevation portions 1121 are located above thefirst base layer 111. Thefirst electrode layer 1131 is located above the first insulating elevation portions 1121 and has first polarity, and is extended along surface profiles of the first insulating elevation portions 1121 to have serpentine traces to thereby increase its extension length. Thesecond electrode layer 1132 is located above thefirst electrode layer 1131 and has second polarity, and is extended along surface profiles of thefirst electrode layer 1131 to similarly have serpentine traces to thereby effectively increase its extension length. - The
second capacitor 11B includes asecond base layer 111′, second insulating elevation portions 1121′, athird electrode layer 1133 and a fourth electrode layer 1134. The second insulating elevation portions 1121′ are located above thesecond base layer 111′. Thethird electrode layer 1133 is located above the second insulating elevation portions 1121′ and has first polarity, and is extended along surface profiles of the second insulating elevation portions 1121′ to have serpentine traces to thereby increase its extension length. The fourth electrode layer 1134 is located above thethird electrode layer 1133 and has second polarity, and is extended along surface profiles of thethird electrode layer 1133 to similarly have serpentine traces to thereby increase its extension length. - Moreover, structural details and manufacturing procedures for the
first capacitor 11A and thesecond capacitor 11B are basically same as thecapacitor 11 shown inFIGS. 2 to 4 , and are thus not to be further described here. - The capacitor integrated
structure 1 in the present invention mainly uses thewafer 12 to form thecapacitor 11 according to the above second embodiment. The capacitor integratedstructure 1 can form afirst capacitor 11A and asecond capacitor 11B through a cutting procedure, which are substantially identical in structure. - The
first capacitor 11A includes afirst base layer 111, at least one first conductive elevation portions 1171 and at least onefirst electrode layer 1131. The first conductive elevation portions 1171 are located above thefirst base layer 111 and has second polarity. Thefirst electrode layer 1131 is located above the first conductive elevation portions 1171 and has first polarity, and is extended along surface profiles of the first conductive elevation portions 1171 to have serpentine traces to thereby increase its extension length. - The
second capacitor 11B includes asecond base layer 111′, at least one second conductive elevation portions 1171′ and at least onethird electrode layer 1133. The second conductive elevation portions 1171′ are located above thesecond base layer 111′ and has second polarity. Thethird electrode layer 1133 is located above the second conductive elevation portions 1171′ and has first polarity, and is extended along surface profiles of the second conductive elevation portions 1171′ to have serpentine traces to thereby increase its extension length. - Moreover, structural details and manufacturing procedures for the
first capacitor 11A and thesecond capacitor 11B are basically same as thecapacitor 11 shown inFIGS. 5 to 8 , and are thus not to be further described here. - In this invention, as shown in
FIG. 1 , thefirst base layer 111 and thesecond base layer 111′ are respectively mounted on thewafer 12, making thefirst capacitor 11A and thesecond capacitor 11B arranged in an array on thewafer 12 to form the capacitor integratedstructure 1, as shown inFIGS. 9A to 9B . The capacitor integratedstructure 1 can thus be cut to separate thefirst capacitor 11A and thesecond capacitor 11B from each other and obtain individual thefirst capacitor 11A and thesecond capacitor 11B shown inFIGS. 10A and 10B . This allows capacitors to be manufactured by current semiconductor equipment used for substrates, such that the capacitor manufacturing process is simplified and the capacitors can be massively produced. Preferably, electrode contacts E of thefirst capacitor 11A and thesecond capacitors 11B are flexibly shaped as rectangular prism or hemisphere, as shown inFIGS. 10A and 10B . - Therefore, the present invention allows a plurality of capacitors to be formed on a wafer to construct a capacitor integrated structure composed of the plurality of capacitors. The capacitor integrated structure can be cut to separate the capacitors from each other so as to produce massive individual capacitors at a time, thereby simplifying the current capacitor manufacturing process while avoiding a high temperature calcination procedure of the conventional MLCC manufacturing process. The present invention also allows the capacitor integrated structure to be manufactured by current semiconductor manufacturing equipment, thereby in favor of cost reduction.
- Moreover, the capacitor in the present invention includes structural elevation portions, making its electrode layer extended along surface profiles of the structural elevation portions to have serpentine traces. This desirably increases an extension length of the electrode layer, reduces capacitor area and enlarges capacitor capacity, thereby in favor of size miniaturization of electronic products. Further, the present invention can also use a metallic material to form the structural elevation portions, and with the metallic structural elevation portions serving as conductive electrodes, the number of electrode layers is reduced in the capacitor, thereby simplifying the capacitor structure and lowering its manufacturing cost.
- The examples above are only illustrative to explain principles and effects of the invention, but not to limit the invention. It will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the invention. Therefore, the protection range of the rights of the invention should be as defined by the appended claims.
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US20090309187A1 (en) * | 2005-08-24 | 2009-12-17 | Jae-Hyoung Choi | Semiconductor Device and Method of Fabricating the Same |
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US9048341B2 (en) * | 2011-03-16 | 2015-06-02 | Macronix International Co., Ltd. | Integrated circuit capacitor and method |
US9105759B2 (en) * | 2013-11-27 | 2015-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Capacitive device and method of making the same |
KR101912282B1 (en) * | 2016-08-05 | 2018-10-29 | 삼성전기 주식회사 | Thin-film ceramic capacitor |
US10468187B2 (en) * | 2016-08-05 | 2019-11-05 | Samsung Electro-Mechanics Co., Ltd. | Thin-film ceramic capacitor having capacitance forming portions separated by separation slit |
EP3780098A4 (en) * | 2019-04-24 | 2021-06-09 | Shenzhen Goodix Technology Co., Ltd. | Capacitor and preparation method therefor |
-
2019
- 2019-08-01 TW TW108127413A patent/TWI679662B/en active
- 2019-08-15 CN CN201910752390.0A patent/CN112310047B/en active Active
-
2020
- 2020-01-13 US US16/741,691 patent/US20210036098A1/en not_active Abandoned
-
2022
- 2022-08-22 US US17/892,665 patent/US11756989B2/en active Active
Also Published As
Publication number | Publication date |
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CN112310047B (en) | 2024-04-23 |
TWI679662B (en) | 2019-12-11 |
US20220399436A1 (en) | 2022-12-15 |
US11756989B2 (en) | 2023-09-12 |
CN112310047A (en) | 2021-02-02 |
TW202107499A (en) | 2021-02-16 |
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