TWI749983B - Metal-insulator-metal capacitor and method of manufacturing the same - Google Patents

Abstract

A metal-insulator-metal (MIM) capacitor is provided in the present invention, including an inter-metal dielectric (IMD) layer with a recess and a patterned first metal interconnect layer, and the recess exposes the patterned first metal interconnect layer, a plurality of stacked electrode layers in the recess and having vertically and upwardly extending edge portions, wherein the topmost electrode layer is top electrode, and the patterned first metal interconnect layer is bottom electrode, a plurality of stacked capacitor dielectric layers respectively between the electrode layers and having vertically and upwardly extending edge portions, and multiple vias respectively and electrically connecting the electrode layers and the bottom electrode.

Description

Metal-insulator-metal capacitor structure and manufacturing method thereof

The present invention is generally related to a metal-insulator-metal (metal-insulator-metal, MIM) capacitor structure, and more specifically, it relates to a metal-insulator-metal capacitor structure with multiple stacked electrode layers and its production method.

At present, capacitors in semiconductor components can be roughly divided into poly-insulator-poly (PIP) capacitors, metal-oxide-silicon substrate (Metal-Oxide-Silicon, MOS) structure, and metal- Insulator-metal (Metal-Insulator-Metal, MIM) capacitors, etc. In practical applications, these capacitors can be selectively used according to the characteristics of the semiconductor element. For example, MIM capacitors can be used in high-frequency semiconductor components.

In recent years, with the rapid development of wireless communication technology, the industry strongly hopes that capacitors suitable for system-on-chip (SoC) with high-performance decoupling and filtering functions can be implanted into the metal interconnection process of integrated circuits. Get a powerful radio frequency system. To achieve such a design, the implanted capacitor must have characteristics such as high capacitance density, ideal voltage linearity, precise capacitance value control, and high reliability. Traditional PIP capacitors or MOS capacitors have shortcomings such as large voltage linearity, large parasitic resistance and capacitance loss, etc., which cannot satisfy applications at gigahertz frequencies. Therefore, the use of MIM capacitors will be an inevitable choice for the development of radio frequency and analog/mixed-signal integrated circuits. Since MIM uses metal electrodes, its It can effectively reduce the parasitic capacitance and the contact resistance of the electrode, and greatly improve the performance of the component.

However, with the development of radio frequency technology, the requirements for the capacitance density of MIM capacitors will become higher and higher. Therefore, how to meet the requirements of MIM capacitors in this respect will be one of the key factors for the success of future wireless communication technology innovations.

In response to the aforementioned existing metal-insulator-metal (Metal-Insulator-Metal, MIM) capacitor needs to increase its capacitance density, the present invention hereby proposes a novel MIM capacitor structure and its manufacturing method, which is characterized in that multiple layers are formed in the structure. The stacked electrode layers and capacitor dielectric layers can greatly increase the capacitance density of MIM capacitors per unit layout area. Furthermore, the manufacturing method of the present invention only needs to use one photomask to complete the manufacturing of all the components of the capacitor structure, which can greatly reduce the manufacturing cost.

One aspect of the present invention is to provide a metal-insulator-metal capacitor structure including an intermetal dielectric layer, which has a groove and a patterned first metal interconnection layer, and the groove exposes the pattern The first metal interconnection layer is formed, a plurality of stacked electrode layers are located in the groove and have edge portions extending vertically upward, wherein the uppermost electrode layer is the upper electrode, and the patterned first metal interconnection layer is the lower The electrodes, a plurality of stacked capacitor dielectric layers are respectively located between the electrode layers and have edge portions extending vertically upward, and a plurality of contacts are electrically connected to the electrode layers and the bottom electrode, respectively.

Another aspect of the present invention is to provide a method for fabricating a metal-insulator-metal capacitor structure, including providing an intermetal dielectric layer having a patterned metal interconnection layer in the intermetallic A groove is formed in the electrical layer and the patterned metal interconnection layer is exposed, a conformal capacitor dielectric layer and an electrode layer are sequentially formed on the surface of the intermetal dielectric layer and the groove, on the electrode layer A filling layer is formed, the filling layer has a flat surface and fills the groove, and removes part of the capacitor dielectric layer and the electrode layer, so that the capacitor dielectric layer and the electrode layer have edge portions extending vertically upwards Position, remove the filling layer, repeat the steps of forming the capacitor dielectric layer and the electrode layer, forming the filling layer, removing part of the capacitor dielectric layer and the electrode layer, removing the filling layer, and respectively applying the steps to the electrodes Layer and a contact on the patterned metal interconnection layer.

Such objects and other objects of the present invention should become more apparent after readers have read the detailed description of the preferred embodiments described below with various illustrations and drawings.

100: Intermetal dielectric layer

102: Metal interconnection layer

102a: lower electrode

102b: circuit wiring

104: Groove

106: Electrode layer

106a: marginal part

108: Filling layer

110: Capacitor dielectric layer

110a: marginal part

112: Electrode layer

112a: marginal part

114: Filling layer

116: Capacitor dielectric layer

116a: marginal part

118: Electrode layer

118a: Edge part

120: Dielectric layer

122: Contact

124: Metal interconnection layer

This specification contains drawings and constitutes a part of this specification in the text, so that readers have a further understanding of the embodiments of the present invention. These figures depict some embodiments of the present invention and explain the principles together with the description herein. In these figures: Figures 1 to 10 are cross-sectional schematic diagrams of a manufacturing process of a metal-insulator-metal (Metal-Insulator-Metal, MIM) capacitor structure according to a preferred embodiment of the present invention; and 11 The figure is a schematic cross-sectional view of a MIM capacitor structure according to another embodiment of the present invention.

It should be noted that all the illustrations in this manual are illustrations in nature. For clarity and convenience of illustration, the parts in the illustrations may be exaggerated or reduced in size and proportion. Generally speaking, the figures The same reference symbols will be used to indicate corresponding or similar element features in modified or different embodiments.

Now, exemplary embodiments of the present invention will be described in detail below, which will illustrate the described features with reference to the accompanying drawings so that readers can understand and achieve technical effects. Readers will understand that the description in the text is only done by way of example, and is not intended to limit the case. The various embodiments of this case and the various features in the embodiments that do not conflict with each other can be combined or re-arranged in various ways. Without departing from the essence of the present invention In the case of God and category, the modification, equivalent or improvement of this case is understandable to those skilled in the art and is intended to be included in the scope of this case.

Readers should be able to easily understand that the meanings of "on", "on" and "above" in this case should be interpreted in a broad way, so that "on" not only means "directly on "Something is "on" but also includes something "on" with the meaning of intervening features or layers in between, and "on" or "on" not only means "on" or "on" something The meaning of "above" can also include the meaning of "above" or "above" something without intervening features or layers (that is, directly on something).

In addition, space-related terms such as "below", "below", "lower", "above", "upper" and other space-related terms may be used herein to describe one element or feature and another for convenience of description. The relationship of one or more elements or features is as shown in the drawings.

Readers can usually understand terms at least in part from their usage in the context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in the singular, or can be used to describe a feature, structure, or combination of characteristics in the plural. Similarly, depending at least in part on the context, terms such as "a", "an", "the" or "said" can also be understood as conveying singular usage or conveying plural usage. In addition, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors, but may allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least in part on the context.

As used herein, the term "layer" refers to a portion of a material that includes a region having a thickness. The layer may extend over the entirety of the lower or upper structure, or may have a range smaller than the range of the lower or upper structure. In addition, the layer may be a region of a homogeneous or non-homogeneous continuous structure whose thickness is less than that of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any horizontal faces at the top and bottom surfaces. The layers can extend horizontally, vertically, and/or along inclined surfaces. The substrate may be a layer, which may include one or more layers, and/or may be on, above, and/or below Has one or more layers. The layer may include multiple layers. For example, the interconnect layer may include one or more conductor and contact layers (where contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

Readers can better understand that when the words "include" and/or "contain" are used in this manual, they clearly define the existence of the stated features, regions, wholes, steps, operations, elements and/or components, but not The possibility of the existence or addition of one or more other features, regions, wholes, steps, operations, elements, components, and/or combinations thereof is not excluded.

Now the following embodiments will sequentially illustrate the manufacturing process of the capacitor structure of the present invention based on the cross-sectional structure of FIG. 1 to FIG. 11. It should be noted that although the structure and method proposed by the present invention are mainly based on metal-insulator-metal (Metal-Insulator-Metal, MIM) capacitors, those skilled in the art should be able to understand that the disclosed content does not violate logic. Under the premise of flexibility, method and structure, it can also be reasonably applied to other capacitor categories with similar composition. In addition, the MIM capacitor structure of the present invention is preferably constructed in an inter-metal dielectric (IMD) in the semiconductor back-end manufacturing process (BEOL). As for the structures and components generally found in the semiconductor front-end manufacturing process (FEOL), For example, active regions, transistors, etc., because they are not the focus of the present invention and have nothing to do with the features of the present invention, these elements are omitted in the figure for the sake of brevity of the illustration and the description.

First, referring to FIG. 1, an inter-metal dielectric layer 100 is provided, in which a metal interconnection layer 102 is formed. The intermetal dielectric layer 100 can be formed on a substrate that has completed the previous process or another intermetal dielectric layer by a spin coating process or a chemical vapor deposition process, and its material is preferably a low dielectric constant Material (k<3.0) or silicon oxide. The metal interconnection layer 102 can be a metal interconnection layer in a general back-end process, such as M1, M2, M3 and other metal interconnection layers. A vapor deposition (CVD) process is formed in the intermetal dielectric layer 100. The metal interconnection layer 102 may also be a composite structure including a lower titanium nitride layer-aluminum-copper alloy layer-upper titanium nitride layer. The upper and lower titanium nitride layers may also include a titanium layer, a tantalum layer, and a nitride layer. The tantalum layer or a combination thereof, and different metal interconnection layers can be electrically interconnected by vias. The metal interconnection layer 102 can be patterned in advance to form the power-off of the MIM capacitor structure The pole 102a may be used as a general circuit wiring 102b. Next, a photolithography process is performed to form a groove 104 in the intermetal dielectric layer 100 on the metal interconnection layer 102. The groove 104 is intended to form a space for the MIM capacitor structure of the present invention, which exposes the pattern The portion of the lower electrode 102a of the metal interconnect layer 102 after chemicalization.

Please refer to Figure 2 next. After the groove 104 is formed, a conformal electrode layer 106 is then formed on the surface of the intermetal dielectric layer 100 and the groove 104. The material of the electrode layer 106 can be titanium nitride, titanium, tantalum, or tantalum nitride, which can be formed by a physical vapor deposition process or various chemical vapor deposition processes. In the embodiment of the present invention, the electrode layer 106 is directly disposed on the surface of the lower electrode 102a and directly connected to it and connected to an external circuit via the lower electrode 102a.

Please refer to Figure 3 next. After the electrode layer 106 is formed, a filling layer 108 is then formed on the electrode layer 106 to have a flat surface and fill the groove 104. In the embodiment of the present invention, the filling layer 108 may be an organic planarization layer (OPL), and its material may be organosiloxane (organosiloxane) or spin-on-carbon (SOC). The spin coating method is formed on the electrode layer 106, so as to achieve a good groove filling effect and provide a flat surface for subsequent processes.

Please refer to Figure 4 next. After the filling layer 108 is formed, an etch-back process is then performed to remove the electrode layer 106 and the filling layer 108 above a certain height, and to remove part of the intermetal dielectric layer 100, and finally make the top of the electrode layer 106 and the filling layer 108 The surface is lower than the top surface of the intermetal dielectric layer 100. This etch-back step will completely remove the part of the electrode layer 106 on the intermetal dielectric layer 100 and partially remove the part of the electrode layer 106 on the sidewall of the groove 104, so that the electrode layer 106 will have on the sidewall of the groove 104 An edge portion 106a extending vertically upward. In the embodiment of the present invention, making the electrode layer 106 have a vertically extending edge portion 106a helps to increase the capacitance area of the capacitance structure. Furthermore, the design of making the entire electrode layer 106 lower than the surrounding intermetal dielectric layer 100 can realize the idea of multiple stacked electrode layers in a single-layer intermetal dielectric layer 100 space.

Please refer to Figure 5 next. After the etch-back process, the filling layer 108 is then removed, so that only the electrode layer 106 having a U-shaped cross-section and a vertically extending edge portion 106a remains in the groove 104 of the intermetal dielectric layer 100. The filling layer 108 can be removed by an ashing or wet etching process. Then, a conformal capacitor dielectric layer 110 and another electrode layer 112 are sequentially formed on the surfaces of the intermetal dielectric layer 100 and the electrode layer 106. In the embodiment of the present invention, the material of the capacitor dielectric layer 110 may include silicon nitride (SiN), aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), silicon _{oxide (SiO 2} ), and tantalum pentoxide. (Ta ₂ O ₅ ), tantalum oxynitride (TaON), titanium oxide (TiO ₂ ), zirconium oxide (ZrO ₂ ) and other high dielectric constant materials, or tetraethoxysilane (TEOS), spin-on glass (SOG) ), Fluorosilicate glass (ESG), etc., can also include a combination of the above materials, which can be formed by PVD, CVD, atomic layer deposition (ALD), or molecular beam epitaxy (MBE) and other processes. The electrode layer 112 can be made of the same material as the electrode layer 106, such as titanium nitride, titanium, tantalum, and tantalum nitride, which can be formed on the capacitor dielectric layer 110 by a physical vapor deposition process or various chemical vapor deposition processes.

Please refer to Figure 6 next. After the capacitor dielectric layer 110 and the electrode layer 112 are formed, another filling layer 114 is then formed on the electrode layer 112 to have a flat surface and fill the groove 104. Similarly, the filling layer 114 can be an organic flat layer, the material of which can be organosiloxane or carbon coating, and can be formed on the electrode layer 112 by spin coating, so as to achieve a good groove filling effect, and Provides a flat surface for subsequent processes.

Please refer to Figure 7 next. After the filling layer 114 is formed, an etch-back or chemical mechanical polishing process is performed again to remove the capacitor dielectric layer 110, the electrode layer 112, and the filling layer 114 on the top surface of the intermetal dielectric layer 100 (that is, outside the groove 104). In this way, the capacitor dielectric layer 110 and the electrode layer 112 are located in the grooves of the intermetal dielectric layer 100, and the capacitor dielectric layer 110 and the electrode layer 112 will also have vertically extending edge portions 110a and 112a, which helps to improve The capacitance area of the capacitance structure. This etch-back process has similar etch selectivity for the capacitor dielectric layer 110 and the intermetal dielectric layer 100. Therefore, after the etchback process, the top surface of the edge portion 110a of the capacitor dielectric layer and the top surface of the intermetal dielectric layer 100 are approximately It is flush, and the top surface of the edge portion 112a of the electrode layer is slightly lower (not shown). If the chemical mechanical polishing process is used instead of the etch-back process, the top surfaces of the intermetal dielectric layer 100, the edge portion 110a of the capacitor dielectric layer, and the edge portion 112a of the electrode layer are approximately flush, as shown in FIG. It should be noted that in the embodiment of the present invention, due to the lowermost electrode layer 106 Because the top surface of the edge portion 106a of the electrode layer 106 is designed to be lower than the top surface of the intermetal dielectric layer 100, the edge portion 110a of the subsequently formed capacitor dielectric layer 110 will be partially located on the top surface of the edge portion 106a of the electrode layer 106 , And the top surface of the edge portion 106a of the electrode layer 106 is completely covered by the edge portion 110a of the capacitor dielectric layer 110 above it. Similarly, the edge portion 112a of the electrode layer 112 will be partially located on the horizontal plane of the edge portion 110a of the capacitor dielectric layer 110.

Please refer to Figure 8 next. Repeat the steps in Figure 5 to remove the remaining filling layer 114, and form another conformal capacitor dielectric layer 116 and another conformal layer on the surfaces of the intermetal dielectric layer 100, the capacitor dielectric layer 110, and the electrode layer 112 in sequence. An electrode layer 118. The material and manufacturing method of the capacitor dielectric layer 116 may be the same as that of the capacitor dielectric layer 110, and the material and manufacturing method of the electrode layer 118 may be the same as those of the electrode layers 112 and 106, which will not be repeated here.

Please refer to Figure 9 next. After the capacitor dielectric layer 116 and the electrode layer 118 are formed, repeat the steps of FIGS. 6 and 7 to form another filling layer (not shown) on the electrode layer 118 to have a flat surface and fill the recesses.槽104. After that, an etch-back or chemical mechanical polishing process is performed again to remove the capacitor dielectric layer 116 and the electrode layer 118 on the top surface of the intermetal dielectric layer 100 (that is, outside the groove 104), so that the capacitor dielectric layer 116 and The electrode layer 118 is located in the groove of the intermetal dielectric layer 100, and the capacitor dielectric layer 116 and the electrode layer 118 also have vertically extending edge portions 116a and 118a, which help increase the capacitance area of the capacitor structure.

Then please refer to Figure 10. After a plurality of stacked capacitor dielectric layers 110, 116 and electrode layers 106, 112, 118 are formed, a dielectric layer 120 is then formed to cover the entire intermetal dielectric layer 100 and the capacitor structure. The material can be the same as that of the intermetal dielectric layer 100, such as Low dielectric constant material (k<3.0) or silicon oxide. Afterwards, perform a photolithography process to form a plurality of contact holes in the dielectric layer 120 and the intermetal dielectric layer 100, and fill the contact holes with conductive materials, such as metal materials such as copper, aluminum, titanium, and tungsten, In this way, the contact 122 is formed. Finally, another patterned metal interconnection layer 124 is formed above the dielectric layer 120 and the contact 122, such as the M2 metal interconnection layer located above the M1 metal interconnection layer, thus completing the manufacturing of the capacitor structure do.

It can be seen from Figure 10 that the capacitor structure manufactured by the manufacturing method of the present invention will have three stacked electrode layers 106, 112, 118 and two capacitor dielectric layers 110, 116 located between the electrode layers, and the most The top surface of the edge portion 106a of the lower electrode layer 106 will be completely covered by the edge portion 110a of the capacitor dielectric layer 110 above it. Different from the traditional MIM electrode layer (upper electrode layer and lower electrode layer) design with two upper and lower layers, the three-layer electrode layer design can stack two capacitor dielectric layers per unit area, so it can greatly increase the MIM capacitance. Capacitance area. For example, the electrode layers 106 and 118 in Figure 10 can be connected to a common metal interconnection layer 124 above through the contact 122, and connected to a ground terminal through the metal interconnection layer 124, sandwiched between the electrode layer 106 and The electrode layer 112 between the two is connected to another independent part of the metal interconnection layer 124 through the contact 122, and is connected to an operating voltage terminal through this part, so as to achieve the storage mechanism of the multilayer capacitor.

However, it should be noted that from a structural point of view, although only three electrode layers and two capacitor dielectric layers are shown in Figure 10, the method of the present invention can repeatedly form the capacitor dielectric layer and the electrode layer ( (Figure 5), forming a filling layer (Figure 6), performing etching back or chemical mechanical polishing (Figure 7), and removing the filling layer to produce a stacked electrode layer with more than three layers and a capacitor with more than two layers. The electrical layer further increases the number of capacitor dielectric layers to greatly increase the capacitance density of the MIM capacitor per unit layout area. Furthermore, since all the electrode layers and capacitor dielectric layers produced by the method of the present invention will have edge portions extending vertically upwards, which is different from the conventional two-dimensional MIM capacitor structure, these electrode layers and capacitor dielectric layers extend The edge part of the same also further increases the capacitance area and density on the three-dimensional level. On the other hand, from a method perspective, since the manufacturing method proposed by the present invention only requires a photomask to define the groove pattern, other parts of the capacitor structure can be achieved through simple deposition processes and etching back or chemical mechanical polishing. Compared with the conventional technology that requires more than two masks to define different electrode layers and capacitor dielectric layers, it can greatly reduce the manufacturing cost, which is another advantage.

Finally, please refer to FIG. 11, which is a schematic cross-sectional view of a MIM capacitor structure according to another embodiment of the present invention. The difference between the capacitor structure of this embodiment and the capacitor structure of the previous embodiment is that no additional electrode layer is formed on the surface of the lower electrode 102a. In this way, the formation of the first capacitor dielectric layer 110 can be started directly after the definition of the capacitor groove is completed, without forming an additional electrode layer (ie, the aforementioned electrode layer 106). Similarly, the electrode layer and the capacitor dielectric layer of this embodiment also have edge portions extending vertically.

The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: Intermetal dielectric layer

102a: lower electrode

106: Electrode layer

110: Capacitor dielectric layer

112: Electrode layer

116: Capacitor dielectric layer

118: Electrode layer

120: Dielectric layer

122: Contact

124: Metal interconnection layer

Claims (14)

A metal-insulator-metal capacitor structure, comprising: an intermetal dielectric layer, which has a groove and a patterned first metal interconnection layer, and the groove exposes the patterned first metal interconnection layer A plurality of stacked electrode layers are located in the groove and have an edge portion extending vertically upward, wherein the electrode layer of the uppermost layer is the upper electrode, the patterned first metal interconnection layer is the lower electrode, and the electrode layers The first electrode layer including the lowermost layer is directly disposed on the surface of the patterned first metal interconnection layer, and the first electrode layer has edge portions extending vertically upwards; a plurality of stacked capacitor dielectric layers are respectively located on the surface of the patterned first metal interconnection layer. The electrode layers have edge portions extending vertically upward; and a plurality of contacts are electrically connected to the electrode layers and the bottom electrode. The metal-insulator-metal capacitor structure described in the first item of the scope of patent application, wherein the top surface of the edge portion of the first electrode layer is lower than the top surface of the edge portions of the other electrode layers and the capacitor dielectric The top surface of the edge of the layer. In the metal-insulator-metal capacitor structure described in item 1 of the scope of patent application, the top surface of the edge portion of the first electrode layer is completely covered by the edge portion of the capacitor dielectric layer above it. In the metal-insulator-metal capacitor structure described in item 1 of the scope of patent application, the material of the patterned first metal interconnection layer is aluminum-copper alloy. The metal-insulator-metal capacitor structure described in item 1 of the scope of patent application, wherein the The contacts are electrically connected to the second metal interconnection layer disposed above the intermetal dielectric layer. In the metal-insulator-metal capacitor structure described in claim 5, the upper electrode and the lower electrode are respectively electrically connected to a common second metal interconnection layer through the contacts. In the metal-insulator-metal capacitor structure described in item 1 of the scope of patent application, the material of the electrode layer is titanium nitride. In the metal-insulator-metal capacitor structure described in item 1 of the scope of patent application, the material of the capacitor dielectric layer is silicon nitride. A manufacturing method of a metal-insulator-metal capacitor structure includes: providing an intermetal dielectric layer with a patterned metal interconnection layer; forming a groove in the intermetal dielectric layer And the patterned metal interconnection layer is exposed; a conformal first electrode layer is formed on the intermetal dielectric layer, the surface of the groove, and the exposed patterned metal interconnection layer; on the first electrode layer A conformal capacitor dielectric layer and an electrode layer are formed on the surface of the electrode layer in sequence; a filling layer is formed on the electrode layer, the filling layer has a flat surface and fills the groove; a part of the capacitor dielectric layer and the electrode layer are removed The electrode layer allows the capacitor dielectric layer and the electrode layer to have edge portions extending vertically upwards; remove the filling layer; repeat the above-mentioned forming the capacitor dielectric layer and the electrode layer, forming the filling layer, and removing part of the capacitor dielectric The steps of removing the electric layer and the electrode layer and removing the filling layer; and connecting the contacts on the electrode layers and the patterned metal interconnection layer respectively. According to the method for manufacturing the metal-insulator-metal capacitor structure described in claim 9, wherein the step of forming the first electrode layer includes: forming the intermetal dielectric layer, the patterned metal interconnection layer, and the concave A conformal electrode layer is formed on the surface of the groove; a filling layer is formed on the electrode layer, the filling layer has a flat surface and filling the groove; a part of the electrode layer and the filling layer are removed so that the electrode layer The top surface of the filling layer is lower than the top surface of the intermetal dielectric layer; and the filling layer is removed. The manufacturing method of the metal-insulator-metal capacitor structure as described in item 9 of the scope of patent application, wherein the first electrode layer has an edge portion extending vertically upward, and the top surface of the edge portion of the first electrode layer is lower than the other The top surface of the edge portion of the electrode layers and the top surface of the edge portion of the capacitor dielectric layer. According to the method for manufacturing a metal-insulator-metal capacitor structure described in item 9 of the scope of patent application, the step of connecting contacts on the electrode layers and the patterned metal interconnection layer includes: connecting the contacts on the intermetal dielectric layer Forming a dielectric layer on top; performing a photolithography process to form a plurality of contact holes in the dielectric layer; and forming the contacts in the contact holes to respectively connect the electrode layers and the patterned metal interconnection layer . According to the manufacturing method of the metal-insulator-metal capacitor structure described in item 9 of the scope of patent application, the filling layer is an organic planarization layer. According to the manufacturing method of the metal-insulator-metal capacitor structure described in claim 9, wherein the step of removing part of the capacitor dielectric layer and the electrode layer includes an etching back process or a chemical mechanical polishing process.

Images