TWI749983B - Metal-insulator-metal capacitor and method of manufacturing the same - Google Patents
Metal-insulator-metal capacitor and method of manufacturing the same Download PDFInfo
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Description
本發明大體上與一種金屬-絕緣體-金屬(metal-insulator-metal,MIM)電容結構有關,更具體言之,其係關於一種具有多層堆疊的電極層的金屬-絕緣體-金屬電容結構以及其製作方法。 The present invention is generally related to a metal-insulator-metal (metal-insulator-metal, MIM) capacitor structure, and more specifically, it relates to a metal-insulator-metal capacitor structure with multiple stacked electrode layers and its production method.
目前,半導體元件中的電容器按照結構大致可以分為多晶矽-絕緣體-多晶矽(Poly-Insulator-Poly,PIP)電容器、金屬-氧化層-矽基底(Metal-Oxide-Silicon,MOS)結構、以及金屬-絕緣體-金屬(Metal-Insulator-Metal,MIM)電容器等。在實際應用中,可以根據半導體元件的特性選擇性地使用這些電容器。例如在高頻半導體元件中可以選用MIM電容器。 At present, capacitors in semiconductor components can be roughly divided into poly-insulator-poly (PIP) capacitors, metal-oxide-silicon substrate (Metal-Oxide-Silicon, MOS) structure, and metal- Insulator-metal (Metal-Insulator-Metal, MIM) capacitors, etc. In practical applications, these capacitors can be selectively used according to the characteristics of the semiconductor element. For example, MIM capacitors can be used in high-frequency semiconductor components.
近年來,隨著無線通訊技術的快速發展,業界強烈希望將可適用於系統晶片(SoC)、具有高性能解耦與濾波功能的電容器植入到積體電路的金屬互連後段製程中,以獲得功能強勁的射頻系統。要達到這樣的設計所植入的電容必須具有高電容密度、理想的電壓線性值、精確的電容值控制以及高可靠性等特性。傳統的PIP電容或MOS電容因為具有很大的電壓線性值、較大的寄生電阻和電容損耗等缺點,其無法滿足千兆赫頻率下的應用。因此,採用MIM電容將是射頻和類比/混合信號積體電路發展的必然選擇。由於MIM採用金屬電極,其 可有效降低了寄生電容以及電極的接觸電阻,大大提高了元件的性能。 In recent years, with the rapid development of wireless communication technology, the industry strongly hopes that capacitors suitable for system-on-chip (SoC) with high-performance decoupling and filtering functions can be implanted into the metal interconnection process of integrated circuits. Get a powerful radio frequency system. To achieve such a design, the implanted capacitor must have characteristics such as high capacitance density, ideal voltage linearity, precise capacitance value control, and high reliability. Traditional PIP capacitors or MOS capacitors have shortcomings such as large voltage linearity, large parasitic resistance and capacitance loss, etc., which cannot satisfy applications at gigahertz frequencies. Therefore, the use of MIM capacitors will be an inevitable choice for the development of radio frequency and analog/mixed-signal integrated circuits. Since MIM uses metal electrodes, its It can effectively reduce the parasitic capacitance and the contact resistance of the electrode, and greatly improve the performance of the component.
然而,隨著射頻技術的發展,對於MIM電容的電容密度的要求將越來越高。因此,如何達到MIM電容在這方面的需求將是未來無線通訊技術革新是否成功的關鍵因素之一。 However, with the development of radio frequency technology, the requirements for the capacitance density of MIM capacitors will become higher and higher. Therefore, how to meet the requirements of MIM capacitors in this respect will be one of the key factors for the success of future wireless communication technology innovations.
針對前述現有金屬-絕緣體-金屬(Metal-Insulator-Metal,MIM)電容需要提高其電容密度的需求,本發明特此提出了一種新穎的MIM電容結構及其製作方法,其特點在於結構中形成有多層堆疊的電極層與電容介電層,可在單位佈局面積下大幅提升MIM電容的電容密度。再者,本發明的製作方法僅需使用一道光罩即可完成電容器結構的所有部件之製作,可大幅減少製作成本。 In response to the aforementioned existing metal-insulator-metal (Metal-Insulator-Metal, MIM) capacitor needs to increase its capacitance density, the present invention hereby proposes a novel MIM capacitor structure and its manufacturing method, which is characterized in that multiple layers are formed in the structure. The stacked electrode layers and capacitor dielectric layers can greatly increase the capacitance density of MIM capacitors per unit layout area. Furthermore, the manufacturing method of the present invention only needs to use one photomask to complete the manufacturing of all the components of the capacitor structure, which can greatly reduce the manufacturing cost.
本發明的面向之一在於提出一種金屬-絕緣體-金屬電容結構,包含一金屬間介電層,其中具有一凹槽以及一圖案化第一金屬互連層,並且該凹槽係暴露出該圖案化第一金屬互連層,複數個層疊的電極層位於該凹槽中且具有向上垂直延伸的邊緣部位,其中最上層的該電極層為上電極,該圖案化第一金屬互連層為下電極,複數個層疊的電容介電層分別位於該些電極層之間且具有向上垂直延伸的邊緣部位,以及多個接觸件,分別電連接該些電極層以及該下電極。 One aspect of the present invention is to provide a metal-insulator-metal capacitor structure including an intermetal dielectric layer, which has a groove and a patterned first metal interconnection layer, and the groove exposes the pattern The first metal interconnection layer is formed, a plurality of stacked electrode layers are located in the groove and have edge portions extending vertically upward, wherein the uppermost electrode layer is the upper electrode, and the patterned first metal interconnection layer is the lower The electrodes, a plurality of stacked capacitor dielectric layers are respectively located between the electrode layers and have edge portions extending vertically upward, and a plurality of contacts are electrically connected to the electrode layers and the bottom electrode, respectively.
本發明的另一面向在於提出一種金屬-絕緣體-金屬電容結構的製作方法,包含提供一金屬間介電層,該金屬間介電層中具有一圖案化金屬互連層、在該金屬間介電層中形成一凹槽並且暴露出該圖案化金屬互連層、在該金屬間介電層與該凹槽的表面依序形成一共形的電容介電層以及電極層、在該電極層上形成一填充層,該填充層具有平坦的表面並填滿該凹槽、移除部分的該電容介電層與該電極層,使得該電容介電層與該電極層具有垂直向上延伸的邊緣部 位、移除該填充層、重複上述形成電容介電層與電極層、形成填充層、移除部分的該電容介電層與該電極層、移除填充層的步驟、以及分別在該些電極層以及該圖案化金屬互連層上連接接觸件。 Another aspect of the present invention is to provide a method for fabricating a metal-insulator-metal capacitor structure, including providing an intermetal dielectric layer having a patterned metal interconnection layer in the intermetallic A groove is formed in the electrical layer and the patterned metal interconnection layer is exposed, a conformal capacitor dielectric layer and an electrode layer are sequentially formed on the surface of the intermetal dielectric layer and the groove, on the electrode layer A filling layer is formed, the filling layer has a flat surface and fills the groove, and removes part of the capacitor dielectric layer and the electrode layer, so that the capacitor dielectric layer and the electrode layer have edge portions extending vertically upwards Position, remove the filling layer, repeat the steps of forming the capacitor dielectric layer and the electrode layer, forming the filling layer, removing part of the capacitor dielectric layer and the electrode layer, removing the filling layer, and respectively applying the steps to the electrodes Layer and a contact on the patterned metal interconnection layer.
本發明的這類目的與其他目的在閱者讀過下文中以多種圖示與繪圖來描述的較佳實施例之細節說明後應可變得更為明瞭顯見。 Such objects and other objects of the present invention should become more apparent after readers have read the detailed description of the preferred embodiments described below with various illustrations and drawings.
100:金屬間介電層 100: Intermetal dielectric layer
102:金屬互連層 102: Metal interconnection layer
102a:下電極 102a: lower electrode
102b:電路佈線 102b: circuit wiring
104:凹槽 104: Groove
106:電極層 106: Electrode layer
106a:邊緣部位 106a: marginal part
108:填充層 108: Filling layer
110:電容介電層 110: Capacitor dielectric layer
110a:邊緣部位 110a: marginal part
112:電極層 112: Electrode layer
112a:邊緣部位 112a: marginal part
114:填充層 114: Filling layer
116:電容介電層 116: Capacitor dielectric layer
116a:邊緣部位 116a: marginal part
118:電極層 118: Electrode layer
118a:邊緣部位 118a: Edge part
120:介電層 120: Dielectric layer
122:接觸件 122: Contact
124:金屬互連層 124: Metal interconnection layer
本說明書含有附圖併於文中構成了本說明書之一部分,俾使閱者對本發明實施例有進一步的瞭解。該些圖示係描繪了本發明一些實施例並連同本文描述一起說明了其原理。在該些圖示中:第1圖至第10圖為根據本發明較佳實施例中一金屬-絕緣體-金屬(Metal-Insulator-Metal,MIM)電容結構的製作流程的截面示意圖;以及第11圖為根據本發明另一實施例中一MIM電容結構的截面示意圖。 This specification contains drawings and constitutes a part of this specification in the text, so that readers have a further understanding of the embodiments of the present invention. These figures depict some embodiments of the present invention and explain the principles together with the description herein. In these figures: Figures 1 to 10 are cross-sectional schematic diagrams of a manufacturing process of a metal-insulator-metal (Metal-Insulator-Metal, MIM) capacitor structure according to a preferred embodiment of the present invention; and 11 The figure is a schematic cross-sectional view of a MIM capacitor structure according to another embodiment of the present invention.
須注意本說明書中的所有圖示皆為圖例性質,為了清楚與方便圖示說明之故,圖示中的各部件在尺寸與比例上可能會被誇大或縮小地呈現,一般而言,圖中相同的參考符號會用來標示修改後或不同實施例中對應或類似的元件特徵。 It should be noted that all the illustrations in this manual are illustrations in nature. For clarity and convenience of illustration, the parts in the illustrations may be exaggerated or reduced in size and proportion. Generally speaking, the figures The same reference symbols will be used to indicate corresponding or similar element features in modified or different embodiments.
現在下文將詳細說明本發明的示例性實施例,其會參照附圖示出所描述之特徵以便閱者理解並實現技術效果。閱者將可理解文中之描述僅透過例示之方式來進行,而非意欲要限制本案。本案的各種實施例和實施例中彼此不衝突的各種特徵可以以各種方式來加以組合或重新設置。在不脫離本發明的精 神與範疇的情況下,對本案的修改、等同物或改進對於本領域技術人員來說是可以理解的,並且旨在包含在本案的範圍內。 Now, exemplary embodiments of the present invention will be described in detail below, which will illustrate the described features with reference to the accompanying drawings so that readers can understand and achieve technical effects. Readers will understand that the description in the text is only done by way of example, and is not intended to limit the case. The various embodiments of this case and the various features in the embodiments that do not conflict with each other can be combined or re-arranged in various ways. Without departing from the essence of the present invention In the case of God and category, the modification, equivalent or improvement of this case is understandable to those skilled in the art and is intended to be included in the scope of this case.
閱者應能容易理解,本案中的「在…上」、「在…之上」和「在…上方」的含義應當以廣義的方式被解讀,以使得「在…上」不僅表示「直接在」某物「上」而且還包括在某物「上」且其間有居間特徵或層的含義,並且「在…之上」或「在…上方」不僅表示「在」某物「之上」或「上方」的含義,而且還可以包括其「在」某物「之上」或「上方」且其間沒有居間特徵或層(即,直接在某物上)的含義。 Readers should be able to easily understand that the meanings of "on", "on" and "above" in this case should be interpreted in a broad way, so that "on" not only means "directly on "Something is "on" but also includes something "on" with the meaning of intervening features or layers in between, and "on" or "on" not only means "on" or "on" something The meaning of "above" can also include the meaning of "above" or "above" something without intervening features or layers (that is, directly on something).
此外,諸如「在…之下」、「在…下方」、「下部」、「在…之上」、「上部」等空間相關術語在本文中為了描述方便可以用於描述一個元件或特徵與另一個或多個元件或特徵的關係,如在附圖中示出的。 In addition, space-related terms such as "below", "below", "lower", "above", "upper" and other space-related terms may be used herein to describe one element or feature and another for convenience of description. The relationship of one or more elements or features is as shown in the drawings.
閱者通常可以至少部分地從上下文中的用法理解術語。例如,至少部分地取決於上下文,本文所使用的術語「一或多個」可以用於以單數意義描述任何特徵、結構或特性,或者可以用於以複數意義描述特徵、結構或特性的組合。類似地,至少部分地取決於上下文,諸如「一」、「一個」、「該」或「所述」之類的術語同樣可以被理解為傳達單數用法或者傳達複數用法。另外,術語「基於」可以被理解為不一定旨在傳達排他性的因素集合,而是可以允許存在不一定明確地描述的額外因素,這同樣至少部分地取決於上下文。 Readers can usually understand terms at least in part from their usage in the context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in the singular, or can be used to describe a feature, structure, or combination of characteristics in the plural. Similarly, depending at least in part on the context, terms such as "a", "an", "the" or "said" can also be understood as conveying singular usage or conveying plural usage. In addition, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors, but may allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least in part on the context.
如本文中使用的,術語「層」是指包括具有厚度的區域的材料部分。層可以在下方或上方結構的整體之上延伸,或者可以具有小於下方或上方結構範圍的範圍。此外,層可以是厚度小於連續結構的厚度的均質或非均質連續結構的區域。例如,層可以位於在連續結構的頂表面和底表面之間或在頂表面和底表面處的任何水平面對之間。層可以水準、豎直和/或沿傾斜表面延伸。基底可以是層,其中可以包括一個或多個層,和/或可以在其上、其上方和/或其下方 具有一個或多個層。層可以包括多個層。例如,互連層可以包括一個或多個導體和接觸層(其中形成觸點、互連線和/或通孔)和一個或多個介電層。 As used herein, the term "layer" refers to a portion of a material that includes a region having a thickness. The layer may extend over the entirety of the lower or upper structure, or may have a range smaller than the range of the lower or upper structure. In addition, the layer may be a region of a homogeneous or non-homogeneous continuous structure whose thickness is less than that of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any horizontal faces at the top and bottom surfaces. The layers can extend horizontally, vertically, and/or along inclined surfaces. The substrate may be a layer, which may include one or more layers, and/or may be on, above, and/or below Has one or more layers. The layer may include multiple layers. For example, the interconnect layer may include one or more conductor and contact layers (where contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.
閱者更能了解到,當「包含」與/或「含有」等詞用於本說明書時,其明定了所陳述特徵、區域、整體、步驟、操作、要素以及/或部件的存在,但並不排除一或多個其他的特徵、區域、整體、步驟、操作、要素、部件以及/或其組合的存在或添加的可能性。 Readers can better understand that when the words "include" and/or "contain" are used in this manual, they clearly define the existence of the stated features, regions, wholes, steps, operations, elements and/or components, but not The possibility of the existence or addition of one or more other features, regions, wholes, steps, operations, elements, components, and/or combinations thereof is not excluded.
現在下文的實施例將依序根據第1圖至第11圖的截面結構來說明本發明電容結構的製作流程。須注意,本發明所提出的結構與方法雖然是以金屬-絕緣體-金屬(Metal-Insulator-Metal,MIM)電容器為主,然而本領域的技術人士應能理解其所揭露之內容在不違反邏輯性、方法性以及結構性的前提下也能合理地應用到其他組成相似的電容器類別中。此外,本發明的MIM電容結構較佳建構在半導體後段製程(BEOL)中的金屬間介電層(inter-metal dielectric,IMD)中,至於半導體前段製程(FEOL)中一般所具有結構與元件,如主動區域、電晶體等,由於其並非本發明之重點且與本發明特徵沒有關係,為了圖示與說明書的簡明之故,圖中將省略這些元件。 Now the following embodiments will sequentially illustrate the manufacturing process of the capacitor structure of the present invention based on the cross-sectional structure of FIG. 1 to FIG. 11. It should be noted that although the structure and method proposed by the present invention are mainly based on metal-insulator-metal (Metal-Insulator-Metal, MIM) capacitors, those skilled in the art should be able to understand that the disclosed content does not violate logic. Under the premise of flexibility, method and structure, it can also be reasonably applied to other capacitor categories with similar composition. In addition, the MIM capacitor structure of the present invention is preferably constructed in an inter-metal dielectric (IMD) in the semiconductor back-end manufacturing process (BEOL). As for the structures and components generally found in the semiconductor front-end manufacturing process (FEOL), For example, active regions, transistors, etc., because they are not the focus of the present invention and have nothing to do with the features of the present invention, these elements are omitted in the figure for the sake of brevity of the illustration and the description.
首先請參照第1圖,提供一金屬間介電層100,其中形成有一金屬互連層102。金屬間介電層100可以旋轉塗佈製程或是化學氣相沉積製程等方式形成在一已經完成前段製程的基底上或是另一金屬間介電層上,其材質較佳為低介電常數材料(k<3.0)或是氧化矽。金屬互連層102可為一般後段製程中的金屬互連層,如M1,M2,M3等金屬互連層,其材質可為鋁銅合金,可以物理氣相沉積製程(PVD)或是各種化學氣相沉積(CVD)製程形成在金屬間介電層100中。金屬互連層102也可能是包含了下氮化鈦層-鋁銅合金層-上氮化鈦層的複層結構,其中上、下氮化鈦層亦可包含鈦層、鉭層、氮化鉭層或其組合,且不同的金屬互連層之間可以導孔件電性互連。金屬互連層102可先行圖案化形成MIM電容結構的下電
極102a或是做為一般電路佈線102b。接著,進行一光刻製程在金屬互連層102上的金屬間介電層100中形成一凹槽104,該凹槽104係預定用來形成本發明MIM電容結構的空間,其係暴露出圖案化後的金屬互連層102的下電極102a部位。
First, referring to FIG. 1, an inter-metal
接下來請參照第2圖。在凹槽104形成後,接著在金屬間介電層100與凹槽104的表面形成一共形的電極層106。電極層106的材料可為氮化鈦、鈦、鉭、氮化鉭,其可以物理氣相沉積製程或是各種化學氣相沉積製程形成。在本發明實施例中,電極層106直接設置於下電極102a表面與其直接連接並經由該下電極102a連接到外部電路。
Please refer to Figure 2 next. After the
接下來請參照第3圖。在電極層106形成後,接著在電極層106上形成一填充層108,使其具有平坦的表面並填滿凹槽104。在本發明實施例中,填充層108可為一有機平坦層(organic planarization layer,OPL),其材料可為有機矽氧烷(organosiloxane)或碳塗層(Spin-On-Carbon,SOC),可以旋轉塗佈的方式形成在電極層106上,如此達到良好的凹槽填充效果,並提供後續製程平坦的表面。
Please refer to Figure 3 next. After the
接下來請參照第4圖。在填充層108形成後,接著進行一回蝕刻製程來移除一定高度以上的電極層106與填充層108,並移除部分金屬間介電層100,最終使得電極層106與填充層108的頂面低於金屬間介電層100的頂面。此回蝕刻步驟會完全移除電極層106位於金屬間介電層100上的部位以及部分移除電極層106位於凹槽104側壁上的部位,如此電極層106在凹槽104的側壁上會具有垂直向上延伸的邊緣部位106a。在本發明實施例中,將電極層106做成具有垂直延伸的邊緣部位106a有助於提升電容結構的電容面積。再者,使得電極層106整體低於周圍的金屬間介電層100之設計可以在單層的金屬間介電層100空間中實現多層疊電極層的構想。
Please refer to Figure 4 next. After the
接下來請參照第5圖。在回蝕刻製程後,接著移除填充層108,使得金屬間介電層100的凹槽104中僅餘留具有U字形截面、垂直延伸的邊緣部位106a
的電極層106。填充層108可以採用一灰化或者濕蝕刻製程來移除。接著,在金屬間介電層100與電極層106的表面依序形成共形的一電容介電層110以及另一電極層112。在本發明實施例中,電容介電層110的材料可包含氮化矽(SiN)、氧化鋁(Al2O3)、氧化鉿(HfO2)、氧化矽(SiO2)、五氧化二鉭(Ta2O5)、氮氧化鉭(TaON)、氧化鈦(TiO2)、氧化鋯(ZrO2)等高介電常數材料、或者四乙氧基矽烷(TEOS)、旋塗式玻璃(SOG)、氟矽玻璃(ESG)等,亦可包含上述材料之組合,其可採用PVD、CVD、原子層沉積(ALD)、或是分子束磊晶(MBE)等製程來形成。電極層112的材料可與電極層106相同,例如氮化鈦、鈦、鉭、氮化鉭,其可以物理氣相沉積製程或是各種化學氣相沉積製程形成在電容介電層110上。
Please refer to Figure 5 next. After the etch-back process, the
接下來請參照第6圖。在電容介電層110與電極層112形成後,接著在電極層112上形成另一填充層114,使其具有平坦的表面並填滿凹槽104。同樣地,填充層114可為一有機平坦層,其材料可為有機矽氧烷或是碳塗層,可以旋轉塗佈的方式形成在電極層112上,如此達到良好的凹槽填充效果,並提供後續製程平坦的表面。
Please refer to Figure 6 next. After the
接下來請參照第7圖。在填充層114形成後,再次進行回蝕刻或者化學機械研磨製程移除金屬間介電層100頂面上(即凹槽104外的)的電容介電層110、電極層112以及填充層114,如此使得電容介電層110與電極層112位於金屬間介電層100的凹槽內,且該電容介電層110與電極層112同樣會具有垂直延伸的邊緣部位110a與112a,有助於提升電容結構的電容面積。此回蝕刻製程對於電容介電層110與金屬間介電層100有相近的蝕刻選擇性,故回蝕刻後會使電容介電層的邊緣部位110a頂面與金屬間介電層100頂面大致齊平,而電極層的邊緣部位112a頂面則略低(未圖示)。若採用化學機械研磨製程取代回蝕刻製程,則金屬間介電層100、電容介電層的邊緣部位110a、以及電極層的邊緣部位112a三者頂面大致齊平,如第7圖所示。須注意在本發明實施例中,由於最下層的電極層106
的邊緣部位106a的頂面被設計成低於金屬間介電層100頂面的緣故,後續形成的電容介電層110的邊緣部位110a會有部分位於該電極層106邊緣部位106a的頂面上,而電極層106的邊緣部位106a的頂面係完全被其上方的電容介電層110的邊緣部位110a覆蓋。同樣地,電極層112的邊緣部位112a會有部分位於電容介電層110的邊緣部位110a的水平面上。
Please refer to Figure 7 next. After the
接下來請參照第8圖。重複第5圖的步驟,移除剩餘的填充層114,並在金屬間介電層100、電容介電層110以及電極層112的表面依序形成共形的另一電容介電層116以及另一電極層118。電容介電層116的材質與製作方法可與電容介電層110相同,電極層118的材質與製作方法可與電極層112,106相同,於此不再贅述。
Please refer to Figure 8 next. Repeat the steps in Figure 5 to remove the remaining
接下來請參照第9圖。在電容介電層116與電極層118形成後,重複第6圖與第7圖的步驟,在電極層118上形成另一填充層(未圖示),使其具有平坦的表面並填滿凹槽104。之後,再次進行回蝕刻或者化學機械研磨製程移除位於金屬間介電層100頂面上(即凹槽104外的)的電容介電層116與電極層118,如此使得電容介電層116與電極層118位於金屬間介電層100的凹槽內,且電容介電層116與電極層118同樣會具有垂直延伸的邊緣部位116a與118a,有助於提升電容結構的電容面積。
Please refer to Figure 9 next. After the
接著請參照第10圖。在形成了多個層疊的電容介電層110,116與電極層106,112,118後,接著形成一介電層120覆蓋整個金屬間介電層100與電容結構,其材質可與金屬間介電層100相同,如低介電常數材料(k<3.0)或是氧化矽。之後,進行一光刻製程在介電層120與金屬間介電層100中形成多個接觸孔,並在該些接觸孔中填入導電材料,如銅、鋁、鈦、鎢等金屬材料,如此形成接觸件122。最後,再於介電層120與接觸件122的上方形成的圖案化的另一金屬互連層124,如位於M1金屬互連層上方的M2金屬互連層,如此即完成了電容結構之製
作。
Then please refer to Figure 10. After a plurality of stacked capacitor
從第10圖中可以看到,透過本發明製作方法所製成的電容結構,其會具有三層層疊的電極層106,112,118以及位於該些電極層之間的兩層電容介電層110,116,且最下層的電極層106的邊緣部位106a的頂面會完全被其上方的電容介電層110的邊緣部位110a覆蓋。有別於一般上下兩層的傳統MIM電極層(上電極層與下電極層)設計,三層的電極層設計由於可以在單位面積下堆疊兩層電容介電層,故可以大幅增加MIM電容的電容面積。例如,第10圖中的電極層106與118可透過接觸件122連接到上方一共同的金屬互連層124,並經由該金屬互連層124連接到一接地端,夾設在電極層106與108兩者之間的電極層112則透過接觸件122連接到金屬互連層124的另一獨立部分,並透過該部分連接到一操作電壓端,如此來達到多層疊電容的儲存機制。
It can be seen from Figure 10 that the capacitor structure manufactured by the manufacturing method of the present invention will have three stacked electrode layers 106, 112, 118 and two capacitor dielectric layers 110, 116 located between the electrode layers, and the most The top surface of the
然而,須注意從結構的角度來看,儘管第10圖中僅示出了三層電極層與兩層電容介電層,本發明方法可以透過不斷地重複上述形成電容介電層與電極層(第5圖)、形成填充層(第6圖)、進行回蝕刻或化學機械研磨(第7圖)以及移除填充層的步驟來製作出三層以上層疊的電極層與兩層以上的電容介電層,進一步增加電容介電層數目,以在單位佈局面積下大幅提升MIM電容的電容密度。再者,由於本發明方法所製作出的所有電極層與電容介電層都會具有垂直向上延伸的邊緣部位,有別於一般傳統設計的二維MIM電容結構,這些電極層與電容介電層延伸的邊緣部位也同樣在三維層面上進一步增加了電容面積與密度。另一方面,從方法的角度來看,由於本發明所提出的製造方法僅需要一道光罩來界定出凹槽圖案,電容結構的其他部分皆可以透過簡單的沉積製程與回蝕刻或化學機械研磨製程來形成,相較於習知技術需要兩道光罩以上來界定不同的電極層與電容介電層的做法,其可大幅減少製作成本,是其另一優點所在。 However, it should be noted that from a structural point of view, although only three electrode layers and two capacitor dielectric layers are shown in Figure 10, the method of the present invention can repeatedly form the capacitor dielectric layer and the electrode layer ( (Figure 5), forming a filling layer (Figure 6), performing etching back or chemical mechanical polishing (Figure 7), and removing the filling layer to produce a stacked electrode layer with more than three layers and a capacitor with more than two layers. The electrical layer further increases the number of capacitor dielectric layers to greatly increase the capacitance density of the MIM capacitor per unit layout area. Furthermore, since all the electrode layers and capacitor dielectric layers produced by the method of the present invention will have edge portions extending vertically upwards, which is different from the conventional two-dimensional MIM capacitor structure, these electrode layers and capacitor dielectric layers extend The edge part of the same also further increases the capacitance area and density on the three-dimensional level. On the other hand, from a method perspective, since the manufacturing method proposed by the present invention only requires a photomask to define the groove pattern, other parts of the capacitor structure can be achieved through simple deposition processes and etching back or chemical mechanical polishing. Compared with the conventional technology that requires more than two masks to define different electrode layers and capacitor dielectric layers, it can greatly reduce the manufacturing cost, which is another advantage.
最後,請參照第11圖,其為根據本發明另一實施例中一MIM電容結構的截面示意圖。此實施例的電容結構與前述實施例的電容結構的差異在於下電極102a表面不另外形成電極層。如此在電容凹槽界定完成後可以直接開始形成第一層電容介電層110,不需形成額外的電極層(即前述的電極層106)。同樣地,此實施例的電極層與電容介電層同樣都具有垂直延伸的邊緣部位。
Finally, please refer to FIG. 11, which is a schematic cross-sectional view of a MIM capacitor structure according to another embodiment of the present invention. The difference between the capacitor structure of this embodiment and the capacitor structure of the previous embodiment is that no additional electrode layer is formed on the surface of the
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。 The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.
100:金屬間介電層 100: Intermetal dielectric layer
102a:下電極 102a: lower electrode
106:電極層 106: Electrode layer
110:電容介電層 110: Capacitor dielectric layer
112:電極層 112: Electrode layer
116:電容介電層 116: Capacitor dielectric layer
118:電極層 118: Electrode layer
120:介電層 120: Dielectric layer
122:接觸件 122: Contact
124:金屬互連層 124: Metal interconnection layer
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US20200066922A1 (en) * | 2018-08-27 | 2020-02-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Film scheme for a high density trench capacitor |
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US20200066922A1 (en) * | 2018-08-27 | 2020-02-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Film scheme for a high density trench capacitor |
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