TWI755679B - Capacitor structure and method of fabricating the same - Google Patents

Abstract

A capacitor structure including a bottom electrode plate on a substrate, wherein the bottom electrode plate is provided with multiple recesses. A capacitor dielectric layer on the bottom electrode plate and the recesses, and a top electrode plate on the capacitor dielectric layer, wherein the edges of capacitor dielectric layer and top electrode plate are provided with vertically extending portions extending in a direction perpendicular to the top surface of bottom electrode plate.

Description

Capacitor structure and method of making the same

The present invention generally relates to a capacitor structure, and more particularly, it relates to a metal-insulator-metal (MIM) capacitor structure having a plurality of vertically extending portions of grooves and edges to increase its capacitance value.

At present, capacitors in semiconductor devices can be roughly divided into polysilicon-insulator-polysilicon (Poly-Insulator-Poly, PIP) capacitors, metal-oxide layer-silicon substrate (Metal-Oxide-Silicon, MOS) structure according to the structure, and metal- Insulator-Metal (Metal-Insulator-Metal, MIM) capacitors. In practical applications, these capacitors can be selectively used according to the characteristics of the semiconductor element. For example, MIM capacitors can be used in high-frequency semiconductor components.

In recent years, with the rapid development of wireless communication technology, the industry strongly hopes to implant capacitors suitable for system-on-chip (SoC) with high-performance decoupling and filtering functions into the back-end process of metal interconnection of integrated circuits. Get a powerful RF system. To achieve such a design, the implanted capacitor must have high capacitance density, ideal voltage linearity, precise capacitance control, and high reliability. Traditional PIP capacitors or MOS capacitors cannot meet applications at gigahertz frequencies due to their large voltage linearity value, large parasitic resistance, and capacitance loss. Therefore, the use of MIM capacitors will be an inevitable choice for the development of RF and analog/mixed-signal integrated circuits. Since the MIM uses metal electrodes, it can effectively reduce the parasitic capacitance and the contact resistance of the electrodes, and greatly improve the performance of the element.

However, with the development of radio frequency technology, the requirements for the capacitance density of MIM capacitors will become higher and higher, while maintaining a small voltage linearity value and good insulation performance. Therefore, how to meet the needs of MIM capacitors in this regard will be one of the key factors for the success of future wireless communication technology innovations.

In response to the above-mentioned requirements of increasing the capacitance density and providing good insulation performance of the existing MIM capacitors, the present invention hereby proposes a novel capacitor structure, which utilizes the inherent micro loading effect of the etching process to form a special groove, and The surface area of the groove can be increased through an additional pull-back process, thereby increasing the overall capacitance of the capacitor structure. In addition, the additional process treatment enables the formed MIM capacitor to have good insulating properties.

One aspect of the present invention is to provide a capacitor structure comprising a substrate and a lower electrode plate on the substrate, wherein the lower electrode plate has a plurality of grooves and a capacitor dielectric layer on the lower electrode plate and The grooves and an upper electrode plate are located on the capacitor dielectric layer, wherein the capacitor dielectric layer and the edge of the upper electrode plate have vertical extensions extending in a direction perpendicular to the top surface of the lower electrode plate part.

Another aspect of the present invention is to provide a method for fabricating a capacitor structure, comprising forming a lower electrode material layer on a substrate, performing a first photolithography process to pattern the lower electrode material layer to form a lower electrode plate, wherein the first The photolithography process simultaneously forms a plurality of grooves on the lower electrode plate, forms an oxide layer on the lower electrode plate, and performs a second photolithography process to remove a portion of the oxide layer to form a groove including the grooves Capacitor grooves, the capacitor grooves expose the grooves, a capacitor dielectric layer and an upper electrode plate are sequentially formed on the surfaces of the capacitor grooves and the oxide layer, and the top surface of the oxide layer is removed the capacitor dielectric layer and the upper electrode plate on the upper electrode plate, so that the edges of the capacitor dielectric layer and the upper electrode plate have vertical extension parts located on the sidewall of the oxide layer.

These and other objects of the present invention should become more apparent to the reader after reading the following detailed description of the preferred embodiment described in the various figures and drawings.

100: Substrate/Dielectric Layer

102: Lower electrode material layer

104: Titanium nitride layer

106: Aluminum layer

108: Titanium nitride layer

110: Photoresist

112: Lower electrode plate

114a, 114b: grooves

116: Dielectric layer

118: Photoresist

120: Capacitor groove

122: Capacitive dielectric layer

122a: Vertical extension

124: Upper electrode plate

124a: Vertical extension

124b: Oxidation site

126: organic flat layer

128: Dielectric layer

130: Contacts

132: metal layer

134: lower electrode layer

134a: Vertical extension

134b: Oxidation site

136: Sidewall

This specification contains accompanying drawings, which constitute a part of this specification, so as to enable readers to have a further understanding of the embodiments of the present invention. The drawings depict some embodiments of the invention and together with the description herein explain the principles thereof. Among these figures: Figures 1 to 8 are schematic cross-sectional views of a manufacturing process of a capacitor structure according to a preferred embodiment of the present invention; Figures 9 and 10 are a schematic diagram of a capacitor structure according to another embodiment of the present invention A schematic cross-sectional view of a capacitor structure and its fabrication steps; FIG. 11 is a cross-sectional schematic view of a fabrication step of a capacitor structure according to yet another embodiment of the present invention; FIG. 12 is a fabrication step of a capacitor structure according to yet another embodiment of the present invention ; and FIG. 13 and FIG. 14 are enlarged schematic views of a capacitor structure according to yet another embodiment of the present invention.

It should be noted that all the illustrations in this specification are of the nature of illustrations. For the sake of clarity and convenience of illustration, the sizes and proportions of the components in the illustrations may be exaggerated or reduced. The same reference characters will be used to designate corresponding or similar element features in modified or different embodiments.

Exemplary embodiments of the present invention will now be described in detail below, which will illustrate the described features with reference to the accompanying drawings to facilitate the reader's understanding and to achieve technical effects. The reader will understand that the description in the text is only by way of example to proceed in the manner indicated, and is not intended to limit the case. The various embodiments of the present invention and various features of the embodiments that do not conflict with each other may be combined or rearranged in various ways. Modifications, equivalents or improvements to the present invention will be understood by those skilled in the art without departing from the spirit and scope of the present invention, and are intended to be included within the scope of the present invention.

Readers should be able to easily understand that the meanings of "on", "on" and "above" in this case should be interpreted in a broad sense, so that "on" not only means "directly on" "on" something but also includes the meaning of "on" something with intervening features or layers, and "on" or "over" means not only "on" something "on" or The meaning of "above", but can also include its meaning "on" or "over" something without intervening features or layers (ie, directly on something).

Furthermore, spatially relative terms such as "below", "below", "lower", "above", "upper" and the like may be used herein for descriptive convenience to describe one element or feature with another The relationship of one or more elements or features as illustrated in the accompanying drawings.

As used herein, the term "substrate" refers to a material upon which subsequent materials are added. The substrate itself can be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Additionally, the substrate may comprise a wide variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic or sapphire wafer.

As used herein, the term "layer" refers to a portion of a material that includes a region having a thickness. A layer may extend over the entirety of the underlying or overlying structure, or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any horizontal faces at the top and bottom surfaces. Layers can extend horizontally, vertically and/or along inclined surfaces. The substrate may be a layer, may include one or more layers, and/or may be on, over and/or under have one or more layers. Layers may include multiple layers. For example, the interconnect layer may include one or more conductor and contact layers (in which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

Now, the following embodiments will sequentially illustrate the fabrication process of the capacitor structure of the present invention according to the cross-sectional structures shown in FIG. 1 to FIG. 8 . It should be noted that although the structure and method proposed in the present invention are mainly metal-insulator-metal (MIM) capacitors, those skilled in the art should understand that the disclosed content does not violate the logic It can also be reasonably applied to other capacitor categories with similar composition under the premise of nature, method and structure.

Please refer to Figure 1 first. The capacitor structure of the present invention can be constructed on a semiconductor substrate, such as a P-type silicon substrate, on which a shallow trench isolation structure (STI) may be formed to define an active area, and various active elements and passive components may be further formed on the active area. Components, such as field effect transistors, diodes, memories and other components. Since the capacitor structure of the present invention is preferably formed in the back end of the process (BEOL), the structures and components in the front end of the process (FEOL) are not the focus of the present invention and have nothing to do with the features of the present invention, for the sake of simplicity of illustration and description For this reason, these elements are omitted from the drawings, and only a dielectric layer 100 formed on the semiconductor substrate is used to represent the substrate, such as an intermetal dielectric (IMD). In the embodiment of the present invention, the material of the dielectric layer 100 is preferably a low dielectric constant material (k<3.0) or silicon oxide, which can be formed on the substrate by processes such as spin coating or chemical vapor deposition.

Refer back to Figure 1. The lower electrode material layer 102 of the capacitor structure is formed on the dielectric layer 100 . In the embodiment of the present invention, the lower electrode material layer 102 may be a three-layer composite structure, which may include a lower titanium nitride layer 104 - an aluminum layer 106 - an upper titanium nitride layer 108 , wherein the upper and lower titanium nitride layers 104 and 108 will be much smaller than the middle aluminum layer 106 . The lower electrode material layer 102 in the multi-layer configuration helps to reduce the series resistance of the capacitor and improve its quality factor. In other embodiments, the aluminum layer may also be a copper-aluminum alloy layer, and the titanium nitride layer may also be titanium, tantalum or tantalum nitride. In some embodiments, the lower electrode material layer 102 can be one of the metal layers in the back-end process, preferably the metal layer before the top metal layer, which can be physical vapor deposition (PVD) or various chemical vapor deposition processes (CVD) process is formed on the dielectric layer 100 .

Next please refer to Figure 2. After the lower electrode material layer 102 is formed, a photolithography process is then performed to form a patterned photoresist 110 on the lower electrode material layer 102, and the photoresist 110 is used as an etching mask to perform dry etching to pattern the lower electrode material layer 102 to form a patterned photoresist 110. the lower electrode plate 112, and at the same time a plurality of grooves 114a are formed thereon. It should be noted that in the embodiment of the present invention, the width of the groove 114a on the lower electrode plate 112 is significantly smaller than the width of the groove 114b around the lower electrode plate 112. The depth of the grooves 114a may be less than the depth of the grooves 114b. As shown in FIG. 2, the grooves 114a on the lower electrode plate 112 extend downward through the upper titanium nitride layer 108 to the aluminum layer 106, and the grooves 114b around the lower electrode plate 112 further penetrate through the lower nitride layer The titanium layer 104 exposes the dielectric layer 100 and even extends into the dielectric layer 100 , thereby separating the lower electrode plate 112 from the surrounding lower electrode material layer 102 . The above-mentioned embodiments of the present invention utilize the inherent micro-loading effect of the etching process to define the lower electrode plate 112 and simultaneously form the desired groove 114a structure on the lower electrode plate 112 in the same etching process. The advantage of this method compared with the general practice is that it can reduce the cost of a mask and an etching process, and increase the production capacity.

In other embodiments, as shown in FIG. 11 , the grooves 114 a on the lower electrode plate 112 may also pass through the aluminum layer 106 to expose the lower titanium nitride layer 104 . The advantage of this embodiment is that a more consistent depth of the groove 114a can be obtained, because in a general etching process, the etching process will have different etching rates for the parts near the center of the wafer and near the edge of the wafer. The depth of the groove 114a at the center of the wafer is too different from the depth of the groove 114a at the edge of the wafer. This embodiment utilizes the different etching speed of titanium nitride and aluminum. The lower titanium nitride layer 104 is used as an etch stop layer, so that the grooves 114a on the lower electrode plate 112 can be controlled to extend uniformly to the lower nitride layer. The surface of the titanium layer 104 , and the grooves 114 b around the lower electrode plate 112 can be controlled to extend through the titanium nitride layer 104 into the underlying dielectric layer 100 by using the micro-loading effect to define the lower electrode plate 112 .

Next please refer to Figure 3. After the lower electrode plate 112 is formed, an ashing process and a cleaning process are performed to remove the photoresist 110 , and then another dielectric layer 116 is formed to cover the lower electrode plate 112 . Like the underlying dielectric layer 100, the dielectric layer 116 may be an intermetal dielectric layer, preferably made of a low dielectric constant material The material (k<3.0) or silicon oxide can be formed on the substrate by processes such as spin coating or chemical vapor deposition. In this step, a chemical mechanical polishing (CMP) process may be performed after the first deposition of the dielectric layer to planarize the surface of the dielectric layer 116 , and then a second deposition may be performed to achieve a predetermined thickness of the dielectric layer 116 .

Next please refer to Figure 4. After the dielectric layer 116 is formed, a photolithography process is then performed to form a patterned photoresist 118 on the dielectric layer 116 , and the photoresist 118 is used as an etching mask to etch the dielectric layer 116 to form the lower electrode plate 112 Capacitor groove 120 on it. In the embodiment of the present invention, the etching process may be sputter etching, ion beam etching, or plasma etching, etc. The formed capacitor groove 120 includes all the grooves previously formed on the lower electrode plate 112 114a.

Next please refer to Figure 5. After the capacitor groove 120 is formed, an ashing process and a cleaning process are performed to remove the photoresist 118, and then a conformal capacitor dielectric layer 122 and An upper electrode plate 124 . As shown, the upper electrode plate 124 fills the space in the groove 114a. In other embodiments, voids may be formed in the upper electrode plate 124 filled in the groove 114a. In the embodiment of the present invention, the material of the capacitor dielectric layer 122 may be a high dielectric constant material, including aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), silicon oxide (SiO ₂ ), silicon nitride ( SiN), tantalum pentoxide (Ta ₂ O ₅ ), tantalum oxynitride (TaON), titanium oxide (TiO ₂ ), zirconium oxide (ZrO ₂ ), tetraethoxysilane (TEOS), spin-on glass (SOG) ), or fluorosilicate glass (FSG), etc., which can be formed by PVD, CVD, atomic layer deposition (ALD), or molecular beam epitaxy (MBE) processes. The material of the upper electrode plate 124 can be titanium nitride, titanium, tantalum, tantalum nitride or tungsten, which can be formed on the capacitor dielectric layer 122 by a physical vapor deposition process or various chemical vapor deposition processes. As can be seen from the figure, in the embodiment of the present invention, due to the existence of the groove 114a, the electrode area of the capacitor under the unit area of the wafer can be significantly improved. The greater the number of the grooves 114a, the more the area of the electrodes is increased, thereby increasing the overall capacitance of the capacitor structure.

Next, please refer to Figure 6. After the capacitor dielectric layer 122 and the upper electrode plate 124 are formed, an organic planarization layer (OPL) 126 is then formed on the upper electrode plate 124 . It can be seen from the figure that the organic flat layer 126 covers the entire substrate and fills the capacitor groove 120, and its function is to provide a flat surface for subsequent processes. The material of the organic planarization layer 126 can be organosiloxane or carbon coating (Spin-On-Carbon, SOC), which can be formed on the upper electrode plate 124 by spin coating and provide good groove filling Effect.

Next please refer to Figure 7. After the organic planarization layer 126 is formed, an etching back process or a chemical mechanical polishing process is performed to remove the layer structure with a certain thickness. This removal step removes the organic planar layer 126 , the upper electrode plate 124 , and the capacitive dielectric layer 122 on the top surface of the dielectric layer 116 , thus defining each capacitive structure in isolation. Therefore, due to the steps, the edges of the capacitor dielectric layer 122 and the upper electrode plate 124 have vertically extending portions 122 a and 124 a extending in a direction perpendicular to the top surface of the lower electrode plate 112 .

Finally, please refer to Figure 8. After separating the individual capacitive structures, the remaining organic planarization layer 126 is then removed and another dielectric layer 128 is covered over the entire substrate. The related process of the dielectric layer 128 is as described in the dielectric layer 116 in FIG. 3 , and will not be repeated here. Then, contact members 130 are formed in the dielectric layers 116 and 128 to connect the upper electrode plate 124 and the lower electrode plate 112 of the capacitor structure, respectively. The steps may include: performing photolithography on the upper electrode plate 124 and the lower electrode plate 112 as an etch stop layer. The process forms via holes in the dielectric layers 116 , 128 , and then fills the via holes with metal materials such as copper, aluminum, titanium, tungsten, etc. to form the contacts 130 . After the contact member 130 is formed, a patterned metal layer 132 is then formed on the dielectric layer 128 to be connected thereto, thus completing the fabrication of the capacitor structure.

The above embodiment is an illustration of the manufacturing process of the capacitor structure of the present invention. According to the above manufacturing process, the present invention also proposes a capacitor structure, as shown in FIG. 8 , which includes a substrate 100 and a lower electrode plate 112 on the substrate 100 , wherein the lower electrode plate 112 has a plurality of grooves 114a, a capacitor dielectric layer 122, located on the lower electrode plate 112 and the grooves 114a, and an upper electrode plate 124, located on the capacitor dielectric layer 122, wherein the capacitor dielectric layer 122 and the upper electrode plate 124 The edge has vertically extending portions 122 a and 124 a extending in a direction perpendicular to the top surface of the lower electrode plate 112 .

Next, please refer to FIG. 9 and FIG. 10 , which are schematic cross-sectional views of a capacitor structure and its fabrication steps according to another embodiment of the present invention. In the embodiment of the present invention, the electrodes on the lower electrode plate 112 may be After the groove 114a is formed, an additional pullback process is applied to change the shape of the groove 114a to further increase the electrode area. The pullback process may use solutions with different etch selectivity ratios for aluminum and titanium nitride, such as dilute sulfur peroxide (DSP), to etch the sidewalls 136 of the recess 114a so that they arc outwardly bulge. Such arcuate convex groove sidewalls 136 can provide more electrode area than the conventional straight groove sidewalls shown in FIG. 4 .

Next, please refer to FIG. 12 , which is a schematic cross-sectional view of a manufacturing step of a capacitor structure according to yet another embodiment of the present invention. In the embodiment of the present invention, after the capacitor groove 120 is formed in FIG. 4 and before the capacitor dielectric layer 122 is formed, an additional lower electrode layer 134 may be formed on the surface of the capacitor groove 120 first. The material of the lower electrode layer 134 can be titanium nitride, titanium, tantalum, tantalum nitride or tungsten, which can be formed by physical vapor deposition process or various chemical vapor deposition processes. Thus, as shown in FIG. 12 , like the capacitor dielectric layer 122 and the upper electrode plate 124 , the lower electrode layer 134 also has a vertically extending portion located on the sidewall of the dielectric layer 116 . Compared with the foregoing embodiments, due to the existence of the vertically extending portion of the lower electrode layer 134, the vertically extending portion can also provide an effective electrode area, thereby further increasing the capacitance value of the overall capacitor structure.

Next, please refer to FIG. 13 , which is an enlarged schematic view of a capacitor structure according to yet another embodiment of the present invention. According to the embodiment of FIG. 12, in the case where the lower electrode layer 134 is additionally formed, an additional etching process may be performed in the step stage after separating each capacitor structure in FIG. 7 to remove part of the upper electrode plate 124 and the lower electrode plate 124. For the electrode layer 134, the length of the vertically extending parts 124a and 134a is smaller than the length of the vertically extending part 122a of the capacitor dielectric layer 122, as shown in FIG. 13, so that the vertical extending parts of the upper electrode plate 124 and the lower electrode layer 134 can be ensured The edges will not cause component failure due to contact.

Next, please refer to FIG. 14 , which is an enlarged schematic diagram of a capacitor structure according to yet another embodiment of the present invention. According to the embodiment shown in FIG. 12 , in the case where the lower electrode layer 134 is additionally formed, an additional oxidation process may be performed in the steps after the capacitor structures are separated in FIG. 7 , so that the upper electrode plate 124 and the lower electrode layer 134 are formed. The tops of the vertically extending parts 124a, 134a are oxidized to become oxidized parts 124b, 134b, As shown in FIG. 14 , this can ensure that the upper electrode plate 124 and the edge of the vertically extending portion of the lower electrode layer 134 are insulated without causing device failure.

According to the capacitor structure and the manufacturing method thereof according to the above-mentioned embodiments of the present invention, the special groove is formed by utilizing the inherent micro-loading effect of the etching process, and the surface area of the groove can be increased through an additional pull-back process, thereby increasing the overall capacitor structure. capacitance value. In addition, the additional etching or oxidation process enables the formed MIM capacitor to have good insulating properties, which is an invention with both distinctive and functional features.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: Substrate/Dielectric Layer

102: Lower electrode material layer

104: Titanium nitride layer

106: Aluminum layer

108: Titanium nitride layer

112: Lower electrode plate

114a: groove

116: Dielectric layer

122: Capacitive dielectric layer

122a: Vertical extension

124: Upper electrode plate

124a: Vertical extension

128: Dielectric layer

130: Contacts

132: metal layer

Claims (18)

A capacitor structure, comprising: a substrate; a lower electrode plate on the substrate, wherein the lower electrode plate has a plurality of grooves; a capacitor dielectric layer on the lower electrode plate; an upper electrode plate on the capacitor on the dielectric layer and extending into the grooves, wherein the capacitor dielectric layer and the upper electrode plate have a vertical extension part perpendicular to the top surface of the lower electrode plate; and a lower electrode layer, arranged on the lower electrode plate , and the capacitor dielectric layer is arranged between the lower electrode layer and the upper electrode plate. The capacitor structure according to claim 1, wherein the lower electrode plate is a multi-layer structure of a titanium nitride layer-aluminum layer-titanium nitride layer, and the grooves extend through the titanium nitride layer to the aluminum layer. According to the capacitor structure described in claim 1, the sidewalls of the grooves protrude outwardly in an arc shape. The capacitor structure according to claim 1, wherein the lower electrode layer has a vertically extending portion perpendicular to the top surface of the lower electrode plate. The capacitor structure according to claim 4, wherein the length of the vertically extending portion of the lower electrode layer is smaller than the length of the vertically extending portion of the capacitor dielectric layer. The capacitor structure according to claim 4, wherein the top of the vertically extending portion of the lower electrode layer has an oxidized portion. According to the capacitor structure described in claim 1, the material of the lower electrode layer is titanium nitride or titanium. The capacitor structure according to claim 1, wherein the length of the vertically extending portion of the upper electrode plate is smaller than the length of the vertically extending portion of the capacitor dielectric layer. The capacitor structure according to claim 1, wherein the top of the vertically extending portion of the upper electrode plate has an oxidized portion. According to the capacitor structure described in claim 1, the material of the capacitor dielectric layer comprises a high dielectric constant material or silicon nitride. According to the capacitor structure described in claim 1, the material of the upper electrode plate is titanium nitride or titanium. A method for fabricating a capacitor structure, comprising: forming a lower electrode material layer on a substrate; patterning the lower electrode material layer by a first photolithography process to form a lower electrode plate, wherein the first photolithography process is simultaneously performed on the lower electrode plate. forming a plurality of grooves on the electrode plate; forming a dielectric layer on the lower electrode plate; performing a second photolithography process to remove part of the dielectric layer to expose the part of the lower electrode including the grooves plate; sequentially form a capacitor dielectric layer and an upper electrode plate on the surface of the lower electrode plate and the dielectric layer; to and removing the capacitor dielectric layer and the upper electrode plate on the top surface of the dielectric layer, so that the edges of the capacitor dielectric layer and the upper electrode plate have vertically extending portions on the sidewalls of the dielectric layer . According to the manufacturing method of the capacitor structure described in claim 12, wherein the step of removing the capacitor dielectric layer and the upper electrode plate on the top surface of the dielectric layer comprises: forming on the upper electrode plate an organic planarization layer; and performing an etch-back process to remove a portion of the organic planarization layer, the upper electrode plate on the top surface of the dielectric layer, and the capacitor dielectric layer. According to the manufacturing method of the capacitor structure described in claim 12, wherein the step of removing the capacitor dielectric layer and the upper electrode plate on the top surface of the dielectric layer comprises: forming on the upper electrode plate an organic planarization layer; and a chemical mechanical polishing process to remove a portion of the organic planarization layer, the upper electrode plate on the top surface of the dielectric layer, and the capacitor dielectric layer. According to the method for fabricating the capacitor structure described in claim 12, the method further includes performing a pulling process after forming the grooves, so that the sidewalls of the grooves protrude outward in an arc shape. According to the method for fabricating the capacitor structure described in claim 12, before forming the capacitor dielectric layer, a lower electrode layer is formed on the surface of the dielectric layer and the lower electrode plate, and the bottom electrode layer is removed on the surface of the lower electrode plate. The steps of the capacitor dielectric layer and the upper electrode plate on the top surface of the dielectric layer also simultaneously remove the lower electrode layer on the top surface of the dielectric layer, so that the edge of the lower electrode layer has Vertical extensions on the sidewalls of the dielectric layer. According to the method for fabricating the capacitor structure described in claim 17, the method further comprises performing an oxidation process to oxidize the tops of the vertically extending portions of the upper electrode plate and the lower electrode layer to form oxide portions. According to the method for fabricating the capacitor structure described in claim 17, the method further comprises performing an etching process to remove part of the vertically extending portion of the upper electrode plate and the lower electrode layer, so that the upper electrode plate and the lower electrode The length of the vertically extending portion of the layer is less than the length of the vertically extending portion of the capacitive dielectric layer.

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