US20200396465A1

US20200396465A1 - Interaction between ibc and affine

Info

Publication number: US20200396465A1
Application number: US17/005,521
Authority: US
Inventors: Kai Zhang; Li Zhang; Hongbin Liu; Yue Wang
Original assignee: Beijing ByteDance Network Technology Co Ltd; ByteDance Inc
Current assignee: Beijing ByteDance Network Technology Co Ltd; ByteDance Inc
Priority date: 2018-06-05
Filing date: 2020-08-28
Publication date: 2020-12-17
Also published as: TW202002644A; US20210006780A1; TW202005390A; US20200404255A1; CN110572669B; WO2019234606A1; CN110572647A; CN110572669A; WO2019234607A1; GB2588317B; CN110572648B; US20200413048A1; JP7104186B2; GB2588003B; GB2588023A; GB202018255D0; WO2019234600A1; CN110572646A; TWI708504B; TW202002643A

Abstract

Devices, systems and methods for applying intra-block copy (IBC) in video coding are described. In general, methods for integrating IBC with existing motion compensation algorithms for video encoding and decoding are described. In a representative aspect, a method for video encoding using IBC includes determining whether a current block of the current picture is to be encoded using a motion compensation algorithm, and encoding, based on the determining, the current block by selectively applying an intra-block copy to the current block. In a representative aspect, another method for video encoding using IBC includes determining whether a current block of the current picture is to be encoded using an intra-block copy, and encoding, based on the determining, the current block by selectively applying a motion compensation algorithm to the current block.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of International Application No. PCT/IB2019/054612, filed on Jun. 4, 2019, which claims the priority to and benefits of International Patent Application No. PCT/CN2018/089920, filed on Jun. 5, 2018. All the aforementioned patent applications are hereby incorporated by reference in their entireties.

TECHNICAL FIELD

This patent document is directed generally to video coding technologies.

BACKGROUND

Motion compensation is a technique in video processing to predict a frame in a video, given the previous and/or future frames by accounting for motion of the camera and/or objects in the video. Motion compensation can be used in the encoding and decoding of video data for video compression.

SUMMARY

Devices, systems and methods related to intra-block copy for motion compensation are described.
In one representative aspect, the disclosed technology may be used to provide a method for video encoding using intra-block copy. This method includes determining whether a current block of the current picture is to be encoded using a motion compensation algorithm, and encoding, based on the determining, the current block by selectively applying an intra-block copy to the current block.
In another representative aspect, the disclosed technology may be used to provide another method for video encoding using intra-block copy. This method includes determining whether a current block of the current picture is to be encoded using an intra-block copy, and encoding, based on the determining, the current block by selectively applying a motion compensation algorithm to the current block.
In yet another representative aspect, the disclosed technology may be used to provide a method for video decoding using intra-block copy. This method includes determining whether a current block of the current picture is to be decoded using a motion compensation algorithm, and decoding, based on the determining, the current block by selectively applying an intra-block copy to the current block.
In yet another representative aspect, the disclosed technology may be used to provide another method for video decoding using intra-block copy. This method includes determining whether a current block of the current picture is to be decoded using an intra-block copy, and decoding, based on the determining, the current block by selectively applying a motion compensation algorithm to the current block.
In yet another example aspect, a method of video processing is disclosed. The method includes determining that a block being decoded representing a portion of the visual information is coded using a first coding technique; and decoding the coded representation by using a first decoding technique corresponding to the first coding technique and by excluding use of a second decoding technique corresponding to a second coding technique; wherein one of the first and second coding techniques corresponds to an intra-block copy (IBC) technique that uses a second block of a same video picture for coding the block being decoded and the other corresponds to an affine coding technique that uses an affine motion model for coding the block being decoded.
In yet another example aspect, a method of visual information processing is disclosed. The method includes determining that a block being decoded representing a portion of an encoded picture of visual information is coded using an intra-block copy (IBC) technique that uses a second block of the picture for coding the block being decoded and an affine coding technique that uses an affine motion model for coding the block being decoded; and decoding the coded representation by using an IBC decoding technique corresponding to the IBC decoding technique and an affine decoding technique corresponding to the affine coding technique.
In yet another representative aspect, the above-described method is embodied in the form of processor-executable code and stored in a computer-readable program medium.
In yet another representative aspect, a device that is configured or operable to perform the above-described method is disclosed. The device may include a processor that is programmed to implement this method.
In yet another representative aspect, a video decoder apparatus may implement a method as described herein.
The above and other aspects and features of the disclosed technology are described in greater detail in the drawings, the description and the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows an example of an intra-block copy technique.

FIG. 2 shows an example of a simplified affine motion model.

FIG. 3 shows an example of an affine motion vector field (MVF) per sub-block.

FIG. 4 shows an example of motion vector prediction (MVP) for the AF_INTER affine motion mode.

FIGS. 5A and 5B show example candidates for the AF_MERGE affine motion mode.

FIG. 6 shows a flowchart of an example method for video encoding using intra-block copy in accordance with the disclosed technology.

FIG. 7 shows a flowchart of another example method for video encoding using intra-block copy in accordance with the disclosed technology.

FIG. 8 shows a flowchart of an example method for video decoding using intra-block copy in accordance with the disclosed technology.

FIG. 9 shows a flowchart of another example method for video decoding using intra-block copy in accordance with the disclosed technology.

FIG. 10 is a block diagram illustrating an example of the architecture for a computer system or other control device that can be utilized to implement various portions of the presently disclosed technology.

FIG. 11 shows a block diagram of an example embodiment of a mobile device that can be utilized to implement various portions of the presently disclosed technology.

FIG. 12 shows a flowchart for an example method of visual information processing.

FIG. 13 shows a flowchart for an example method of visual information processing.

DETAILED DESCRIPTION

Section headings are used in the present document for the ease of understanding and do not limit scope of the technologies and embodiments discussed in each section to just that section.
Due to the increasing demand of higher resolution visual information, such as video, images, three-dimensional scenes, etc., video coding methods and techniques are ubiquitous in modern technology. The techniques described in this application can apply to various visual information including video, images, three-dimensional scenes, etc. A picture of the visual information can be a frame in a video, a portion of an image, an object in a three-dimensional scene, a portion of the three-dimensional scene, etc. A block can be portion of the picture of the visual information such as a coding unit (CU), a largest coding unit (LCU), a sample, a prediction unit (PU) etc. as described in this application. A sub-block of the visual information can be a PU such as a sub-CU, a sample, etc. The PU can be a pixel, a voxel, or a smallest quantum of resolution of the visual information. Video codecs typically include an electronic circuit or software that compresses or decompresses digital video, and are continually being improved to provide higher coding efficiency. A video codec converts uncompressed video to a compressed format or vice versa. There are complex relationships between the video quality, the amount of data used to represent the video (determined by the bit rate), the complexity of the encoding and decoding algorithms, sensitivity to data losses and errors, ease of editing, random access, and end-to-end delay (latency). The compressed format usually conforms to a standard video compression specification, e.g., the High Efficiency Video Coding (HEVC) standard (also known as H.265 or MPEG-H Part 2), the Versatile Video Coding standard to be finalized, or other current and/or future video coding standards.
Embodiments of the disclosed technology may be applied to existing video coding standards (e.g., HEVC, H.265) and future standards to improve runtime performance. Section headings are used in the present document to improve readability of the description and do not in any way limit the discussion or the embodiments (and/or implementations) to the respective sections only.

1. Examples of Reference Pictures and Reference Picture Lists

In HEVC, there are two types of reference pictures, short-term and long-term. A reference picture may be marked as “unused for reference” when it becomes no longer needed for prediction reference. A completely new approach for reference picture management, referred to as reference picture set (RPS) or buffer description has been introduced by HEVC.
The process of marking pictures as “used for short-term reference”, “used for long-term reference”, or “unused for reference” is done using the RPS concept. An RPS is a set of picture indicators that is signaled in each slice header and consists of one set of short-term pictures and one set of long-term pictures. After the first slice header of a picture has been decoded, the pictures in the DPB are marked as specified by the RPS. The pictures in the DPB that are indicated in the short-term picture part of the RPS are kept as short-term pictures. The short-term or long-term pictures in the DPB that are indicated in the long-term picture part in the RPS are converted to or kept as long-term pictures. And finally, pictures in the DPB for which there is no indicator in the RPS are marked as unused for reference. Thus, all pictures that have been decoded that may be used as references for prediction of any subsequent pictures in decoding order must be included in the RPS.
An RPS consists of a set of picture order count (POC) values that are used for identifying the pictures in the DPB. Besides signaling POC information, the RPS also signals one flag for each picture. Each flag indicates whether the corresponding picture is available or unavailable for reference for the current picture. Note that even though a reference picture is signaled as unavailable for the current picture, it is still kept in the DPB and may be made available for reference later on and used for decoding future pictures.
From the POC information and the availability flag, five lists of reference pictures as shown in Table 1 can be created. The list RefPicSetStCurrBefore consists of short-term pictures that are available for reference for the current picture and have POC values that are lower than the POC value of the current picture. RefPicSetStCurrAfter consist of available short-term pictures with a POC value that is higher than the POC value of the current picture. RefPicSetStFoll is a list that contains all short-term pictures that are made unavailable for the current picture but may be used as reference pictures for decoding subsequent pictures in decoding order. Finally, the lists RefPicSetLtCurr and RefPicSetLtFoll contain long-term pictures that are available and unavailable for reference for the current picture, respectively.

TABLE 1

List of Reference Picture lists

	Long-term or	Availability
List name	short-term	flag	POC

RefPicSetStCurrBefore	Short-term	Available	Lower
RefPicSetStCurrAfter	Short-term	Available	Higher
RefPicSetStFoll	Short-term	Unavailable	—
RefPicSetLtCurr	Long-term	Available	—
RefPicSetLtFoll	Long-term	Unavailable	—

1.1 Examples of Short-Term and Long-Term Reference Pictures

The syntax for the general sequence parameter set is shown below:


	Descriptor

seq_parameter_set_rbsp( ) {

	sps_video_parameter_set_id	u(4)
	sps_max_sub_layers_minus1	u(3)
	sps_temporal_id_nesting_flag	u(1)
	profile_tier_level( 1, sps_max_sub_layers_minus1 )
	sps_seq_parameter_set_id	ue(v)
	chroma_format_idc	ue(v)
	if( chroma_format_idc = = 3 )
	...
	}

...

	amp_enabled_flag	u(1)
	sample_adaptive_offset_enabled_flag	u(1)
	pcm_enabled_flag	u(1)
	if( pcm_enabled_flag ) {
	...
	}
	num_short_term_ref_pic_sets	ue(v)
	for( i = 0; i < num_short_term_ref_pic_sets; i++)

st_ref_pic_set( i )

	long_term_ref_pics_present_flag	u(1)
	if( long_term_ref_pics_present_flag ) {

	num_long_term_ref_pics_sps	ue(v)
	for( i = 0; i < num_long_term_ref_pics_sps; i++ ) {

	lt_ref_pic_poc_lsb_sps[ i ]	u(v)
	used_by_curr_pic_lt_sps_flag[ i ]	u(1)

}

	}
	sps_temporal_mvp_enabled_flag	u(1)

...

}

The syntax for the general slice segment header is shown below:


	Descriptor

slice_segment_header( ) {

	first_slice_segment_in_pic_flag	u(1)
	if( nal_unit_type >= BLA_W_LP && nal_unit_type <=

RSV_IRAP_VCL23 )

no_output_of_prior_pics_flag

u(1)

	slice_pic_parameter_set_id	ue(v)
	if( !first_slice_segment_in_pic_flag ) {

if( dependent_slice_segments_enabled_flag )

dependent_slice_segment_flag

u(1)

slice_segment_address

u(v)

	}
	if( !dependent_slice_segment_flag ) {

for( i = 0; i < num_extra_slice_header_bits; i++ )

slice_reserved_flag[ i ]

u(1)

	slice_type	ue(v)
	if( output_flag_present_flag )

pic_output_flag

u(1)

if( separate_colour_plane_flag = = 1 )

colour_plane_id

u(2)

if( nal_unit_type != IDR_W_RADL && nal_unit_type !=

IDR_N_LP ) {

	slice_pic_order_cnt_lsb	u(v)
	short_term_ref_pic_set_sps_flag	u(1)
	if( !short_term_ref_pic_set_sps_flag )

st_ref_pic_set( num_short_term_ref_pic_sets )

else if( num_short_term_ref_pic_sets > 1 )

short_term_ref_pic_set_idx

u(v)

if( long_term_ref_pics_present_flag ) {

if( num_long_term_ref_pics_sps > 0 )

num_long_term_sps

ue(v)

	num_long_term_pics	ue(v)
	for( i = 0; i < num_long_term_sps + num_long_term_pics; i++ ) {

if( i < num_long_term_sps ) {

if( num_long_term_ref_pics_sps > 1 )

lt_idx_sps[ i ]

u(v)

} else {

	poc_lsb_lt[ i ]	u(v)
	used_by_curr_pic_lt_flag[ i ]	u(1)

	}
	delta_poc_msb_present_flag[ i ]	u(1)
	if( delta_poc_msb_present_flag[ i ] )

delta_poc_msb_cycle_lt[ i ]

ue(v)

}

...

The semantics used in the syntax tables above are defined as:
num_short_term_ref_pic_sets specifies the number of st_ref_pic_set( ) syntax structures included in the SPS. The value of num_short_term_ref_pic_sets shall be in the range of 0 to 64, inclusive.
In some embodiments, a decoder may allocate memory for a total number of num_short_term_ref_pic_sets+1 st_ref_pic_set( ) syntax structures since there may be a st_ref_pic_set( ) syntax structure directly signaled in the slice headers of a current picture. A st_ref_pic_set( ) syntax structure directly signaled in the slice headers of a current picture has an index equal to num_short_term_ref_pic_sets.
long_term_ref_pies_present_flag equal to 0 specifies that no long-term reference picture is used for inter prediction of any coded picture in the CVS. long_term_ref_pics_present_flag equal to 1 specifies that long-term reference pictures may be used for inter prediction of one or more coded pictures in the CVS.
num_long_term_ref_pics_sps specifies the number of candidate long-term reference pictures that are specified in the SPS. The value of num_long_term_ref_pics_sps shall be in the range of 0 to 32, inclusive.
lt_ref_pic_poc_lsb_sps[i] specifies the picture order count modulo MaxPicOrderCntLsb of the i-th candidate long-term reference picture specified in the SPS. The number of bits used to represent lt_ref_pic_poc_lsb_sps[i] is equal to log_2_max_pic_order_cnt_lsb_minus4+4.
used_by_curr_pic_lt_sps_flag[i] equal to 0 specifies that the i-th candidate long-term reference picture specified in the SPS is not used for reference by a picture that includes in its long-term reference picture set (RPS) the i-th candidate long-term reference picture specified in the SPS.
short_term_ref_pic_set_sps_flag equal to 1 specifies that the short-term RPS of the current picture is derived based on one of the st_ref_pic_set( ) syntax structures in the active SPS that is identified by the syntax element short_term_ref_pic_set_idx in the slice header. short_term_ref_pic_set_sps_flag equal to 0 specifies that the short-term RPS of the current picture is derived based on the st_ref_pic_set( ) syntax structure that is directly included in the slice headers of the current picture. When num_short_term_ref_pic_sets is equal to 0, the value of short_term_ref_pic_set_sps_flag shall be equal to 0.
short_term_ref_pic_set_idx specifies the index, into the list of the st_ref_pic_set( ) syntax structures included in the active SPS, of the st_ref_pic_set( ) syntax structure that is used for derivation of the short-term RPS of the current picture. The syntax element short_term_ref_pic_set_idx is represented by Ceil(Log 2(num_short_term_ref_pic_sets)) bits. When not present, the value of short_term_ref_pic_set_idx is inferred to be equal to 0. The value of short_term_ref_pic_set_idx shall be in the range of 0 to num_short_term_ref_pic_sets−1, inclusive.
In some embodiments, the variable CurrRpsldx is derived as follows:

- If short_term_ref_pic_set_sps_flag is equal to 1, CurrRpsldx is set equal to short_term_ref_pic_set_idx.
- Otherwise, CurrRpsldx is set equal to num_short_term_ref_pic_sets.

num_long_term_sps specifies the number of entries in the long-term RPS of the current picture that are derived based on the candidate long-term reference pictures specified in the active SPS. The value of num_long_term_sps shall be in the range of 0 to num_long_term_ref_pics_sps, inclusive. When not present, the value of num_long_term_sps is inferred to be equal to 0.
num_long_term_pics specifies the number of entries in the long-term RPS of the current picture that are directly signaled in the slice header. When not present, the value of num_long_term_pics is inferred to be equal to 0.
In some embodiments, when nuh_layer_id is equal to 0, the value of num_long_term_pics shall be less than or equal to sps_max_dec_pic_buffering_minus1[Temporand]-NumNegativePics[CurrRpsIdx]-NumPositivePics[CurrRpsIdx]-num_long_term_sps-TwoVersionsOfCurrDecPicFlag.
lt_idx_sps[i] specifies an index, into the list of candidate long-term reference pictures specified in the active SPS, of the i-th entry in the long-term RPS of the current picture. The number of bits used to represent lt_idx_sps[i] is equal to Ceil(Log 2(num_long_term_ref_pics_sps)). When not present, the value of lt_idx_sps[i] is inferred to be equal to 0. The value of lt_idx_sps[i] shall be in the range of 0 to num_long_term_ref_pics_sps−1, inclusive.
poc_lsb_lt[i] specifies the value of the picture order count modulo MaxPicOrderCntLsb of the i-th entry in the long-term RPS of the current picture. The length of the poc_lsb_lt[i] syntax element is log_2_max_pic_order_cnt_lsb_minus4+4 bits.
used_by_curr_pic_lt_flag[i] equal to 0 specifies that the i-th entry in the long-term RPS of the current picture is not used for reference by the current picture.
In some embodiments, the variables PocLsbLt[i] and UsedByCurrPicLt[i] are derived as follows:

- If i is less than num_long_term_sps, PocLsbLt[i] is set equal to lt_ref_pic_poc_lsb_sps[lt_idx_sps[i]] and UsedByCurrPicLt[i] is set equal to used_by_curr_pic_lt_sps_flag[lt_idx_sps[i]].
- Otherwise, PocLsbLt[i] is set equal to poc_lsb_lt[i] and UsedByCurrPicLt[i] is set equal to used_by_curr_pic_lt_flag[i].

delta_poc_msb_present_flag[i] equal to 1 specifies that delta_poc_msb_cycle_lt[i] is present. delta_poc_msb_present_flag[i] equal to 0 specifies that delta_poc_msb_cycle_lt[i] is not present.
In some embodiments, let prevTid0Pic be the previous picture in decoding order that has TemporalId equal to 0 and is not a RASL, RADL or SLNR picture. Let setOfPrevPocVals be a set consisting of the following:

- the PicOrderCntVal of prevTid0Pic,
- the PicOrderCntVal of each picture in the RPS of prevTid0Pic,
- the PicOrderCntVal of each picture that follows prevTid0Pic in decoding order and precedes the current picture in decoding order.

In some embodiments, when there is more than one value in setOfPrevPocVals for which the value modulo MaxPicOrderCntLsb is equal to PocLsbLt[i], delta_poc_msb_present_flag[i] shall be equal to 1.
delta_poc_msb_cycle_lt[i] is used to determine the value of the most significant bits of the picture order count value of the i-th entry in the long-term RPS of the current picture. When delta_poc_msb_cycle_lt[i] is not present, it is inferred to be equal to 0.
In some embodiments, the variable DeltaPocMsbCycleLt[i] is derived as follows:
if(i==0∥i==num_long_term_sps) DeltaPocMsbCycleLt[i]=delta_poc_msb_cycle_lt[i] else DeltaPocMsbCycleLt[i]=delta_poc_msb_cycle_lt[i]+DeltaPocMsbCycleLt[i−1]

1.2 Examples of Motion Vector Prediction (MVP) Between Short-Term and Long-Term Reference Pictures

In some embodiments, the motion vector prediction is only allowed if the target reference picture type and the predicted reference picture type is the same. In other words, when the types are different, motion vector prediction is disallowed.
Advanced Motion Vector Prediction (AMVP) is an example of motion vector prediction that includes an existing implementation. The relevant portion of the existing AMVP implementation is detailed below.
The motion vector mvLXA and the availability flag availableFlagLXA are derived in the following ordered steps:
(1) The sample location (xNbA0, yNbA0) is set equal to (xPb−1, yPb+nPbH) and the sample location (xNbA1, yNbA1) is set equal to (xNbA0, yNbA0−1).
(7) When availableFlagLXA is equal to 0, the following applies for (xNbAk, yNbAk) from (xNbA0, yNbA0) to (xNbA1, yNbA1) or until availableFlagLXA is equal to 1:

- When availableAk is equal to TRUE and availableFlagLXA is equal to 0, the following applies:

If PredFlagLX[xNbAk][yNbAk] is equal to 1 and LongTermRefPic(currPic, currPb, refIdxLX, RefPicListX) is equal to LongTermRefPic(currPic, currPb, RefldxLX[xNbAk][yNbAk], RefPicListX), availableFlagLXA is set equal to 1 and the following assignments are made:

- mvLXA=MvLX[xNbAk][yNbAk]
- refIdxA=RefldxLX[xNbAk][yNbAk]
- refPicListA=RefPicListX

Otherwise, when PredFlagLY[xNbAk][yNbAk] (with Y=!X) is equal to 1 and LongTermRefPic(currPic, currPb, refIdxLX, RefPicListX) is equal to LongTermRefPic(currPic, currPb, RefldxLY[xNbAk][yNbAk], RefPicListY), availableFlagLXA is set to 1.
The motion vector mvLXB and the availability flag availableFlagLXB are derived in the following ordered steps:
(1) The sample locations (xNbB0, yNbB0), (xNbB1, yNbB1) and (xNbB2, yNbB2) are set equal to (xPb+nPbW, yPb−1), (xPb+nPbW−1, yPb−1) and (xPb−1, yPb−1), respectively.
(5) When isScaledFlagLX is equal to 0, availableFlagLXB is set equal to 0 and the following applies for (xNbBk, yNbBk) from (xNbB0, yNbB0) to (xNbB2, yNbB2) or until availableFlagLXB is equal to 1:

- The availability derivation process for a prediction block as specified in clause 6.4.2 is invoked with the luma location (xCb, yCb), the current luma coding block size nCbS, the luma location (xPb, yPb), the luma prediction block width nPbW, the luma prediction block height nPbH, the luma location (xNbY, yNbY) set equal to (xNbBk, yNbBk) and the partition index partIdx as inputs, and the output is assigned to the prediction block availability flag availableBk.
- When availableBk is equal to TRUE and availableFlagLXB is equal to 0, the following applies:

If PredFlagLX[xNbBk][yNbBk] is equal to 1 and LongTermRefPic(currPic, currPb, refIdxLX, RefPicListX) is equal to LongTermRefPic(currPic, currPb, RefIdxLX[xNbBk][yNbBk], RefPicListX), availableFlagLXB is set equal to 1 and the following assignments are made:

- mvLXB=MvLX[xNbBk][yNbBk]
- refIdxB=RefIdxLX[xNbBk][yNbBk]
- refPicListB=RefPicListX

Otherwise, when PredFlagLY[xNbBk][yNbBk] (with Y=!X) is equal to 1 and LongTermRefPic(currPic, currPb, refIdxLX, RefPicListX) is equal to LongTermRefPic(currPic, currPb, RefldxLY[xNbBk][yNbBk], RefPicListY), availableFlagLXB is set equal to 1 and the following assignments are made:

- mvLXB=MvLY[xNbBk][yNbBk].

Temporal Motion Vector Prediction (TMVP) is another example of motion vector prediction that includes an existing implementation. The relevant portion of the existing TMVP implementation is detailed below.
The variables mvLXCol and availableFlagLXCol are derived as follows:
If LongTermRefPic(currPic, currPb, refIdxLX, LX) is not equal to LongTermRefPic(ColPic, colPb, refIdxCol, listCol), both components of mvLXCol are set equal to 0 and availableFlagLXCol is set equal to 0.
Otherwise, the variable availableFlagLXCol is set equal to 1, refPicListCol[refIdxCol] is set to be the picture with reference index refIdxCol in the reference picture list listCol of the slice containing prediction block colPb in the collocated picture specified by ColPic.

2. Example Embodiments of Intra-Block Copy (IBC)

Intra-block copy (IBC) has been extends the concept of motion compensation from inter-frame coding to intra-frame coding. As shown in FIG. 1, the current block is predicted by a reference block in the same picture when IBC is applied. The samples in the reference block must have been already reconstructed before the current block is coded or decoded. Although IBC is not so efficient for most camera-captured sequences, it shows significant coding gains for screen content. The reason is that there are lots of reduplicated patterns, such as icons and text characters in a screen content picture. IBC can remove the redundancy between these reduplicated patterns effectively.
In HEVC-SCC, an inter-coded coding unit (CU) can apply IBC if it chooses the current picture as its reference picture. The MV is renamed as block vector (BV) in this case, and a BV always has an integer-pixel precision. To be compatible with main profile HEVC, the current picture is marked as a “long-term” reference picture in the Decoded Picture Buffer (DPB). It should be noted that similarly, in multiple view/3D video coding standards, the inter-view reference picture is also marked as a “long-term” reference picture.
2.1 Embodiments of Picture Marking when IBC is Enabled
Semantics related to IBC in PPS. pps_curr_pic_ref_enabled_flag equal to 1 specifies that a picture referring to the PPS may be included in a reference picture list of a slice of the picture itself. pps_curr_pic_ref_enabled_flag equal to 0 specifies that a picture referring to the PPS is never included in a reference picture list of a slice of the picture itself. When not present, the value of pps_curr_pic_ref_enabled_flag is inferred to be equal to 0.
It is a requirement of bitstream conformance that when sps_curr_pic_ref_enabled_flag is equal to 0, the value of pps_curr_pic_ref_enabled_flag shall be equal to 0.
The variable TwoVersionsOfCurrDecPicFlag is derived as follows:
TwoVersionsOfCurrDecPicFlag=pps_curr_pic_ref_enabled_flag && (sample_adaptive_offset_enabled_flag∥!pps_deblocking_filter_disabled_flag∥deblocking_filter_override_enabled_flag)
When sps_max_dec_pic_buffering_minus1[TemporalId] is equal to 0, the value of TwoVersionsOfCurrDecPicFlag shall be equal to 0.
Decoding process. The current decoded picture after the invocation of the in-loop filter process is stored in the DPB in an empty picture storage buffer, the DPB fullness is incremented by one and this picture is marked as “used for short-term reference”.
When TwoVersionsOfCurrDecPicFlag is equal to 1, the current decoded picture before the invocation of the in-loop filter process as specified in clause F.8.7 [1] is stored in the DPB in an empty picture storage buffer, the DPB fullness is incremented by one, and this picture is marked as “used for long-term reference”.

3. Examples of the Joint Exploration Model (JEM)

In some embodiments, future video coding technologies are explored using a reference software known as the Joint Exploration Model (JEM). In JEM, sub-block based prediction is adopted in several coding tools, such as affine prediction, alternative temporal motion vector prediction (ATMVP), spatial-temporal motion vector prediction (STMVP), bi-directional optical flow (BIO), Frame-Rate Up Conversion (FRUC), Locally Adaptive Motion Vector Resolution (LAMVR), Overlapped Block Motion Compensation (OBMC), Local Illumination Compensation (LIC), and Decoder-side Motion Vector Refinement (DMVR).

3.1 Examples of Affine Prediction

In HEVC, only a translation motion model is applied for motion compensation prediction (MCP). However, the camera and objects may have many kinds of motion, e.g. zoom in/out, rotation, perspective motions, and/or other irregular motions. JEM, on the other hand, applies a simplified affine transform motion compensation prediction. FIG. 2 shows an example of an affine motion field of a block 200 described by two control point motion vectors V₀and Vi. The motion vector field (MVF) of the block 200 can be described by the following equation:
$\begin{matrix} {\begin{matrix} v_{x} = \frac{(v_{1 x} - v_{0 x})}{w} x - \frac{(v_{1 y} - v_{0 y})}{w} y + v_{0 x} \\ v_{y} = \frac{(v_{1 y} - v_{0 y})}{w} x + \frac{(v_{1 x} - v_{0 x})}{w} y + v_{0 y} \end{matrix} & Eq . (1) \end{matrix}$
As shown in FIG. 2, (v_0x, v_0y) is motion vector of the top-left corner control point, and (v_1x, v_1y) is motion vector of the top-right corner control point. To simplify the motion compensation prediction, sub-block based affine transform prediction can be applied. The sub-block size M×N is derived as follows:
$\begin{matrix} {\begin{matrix} M = clip 3 (4, w, \frac{w \times MvPre}{\max (abs (v_{1 x} - v_{0 x}), abs (v_{1 y} - v_{0 y}))}) \\ N = clip 3 (4, h, \frac{h \times MvPre}{\max (abs (v_{2 x} - v_{0 x}), abs (v_{2 y} - v_{0 y}))}) \end{matrix} & Eq . (2) \end{matrix}$
Here, MvPre is the motion vector fraction accuracy (e.g., 1/16 in JEM). (v_2x, v_2y) is motion vector of the bottom-left control point, calculated according to Eq. (1). M and N can be adjusted downward if necessary to make it a divisor of w and h, respectively.
FIG. 3 shows an example of affine MVF per sub-block for a block 300. To derive motion vector of each M×N sub-block, the motion vector of the center sample of each sub-block can be calculated according to Eq. (1), and rounded to the motion vector fraction accuracy (e.g., 1/16 in JEM). Then the motion compensation interpolation filters can be applied to generate the prediction of each sub-block with derived motion vector. After the MCP, the high accuracy motion vector of each sub-block is rounded and saved as the same accuracy as the normal motion vector.
In the JEM, there are two affine motion modes: AF_INTER mode and AF_MERGE mode. For CUs with both width and height larger than 8, AF_INTER mode can be applied. An affine flag in CU level is signaled in the bitstream to indicate whether AF_INTER mode is used. In the AF_INTER mode, a candidate list with motion vector pair {(v₀, v₁)|v₀={v_A, v_B,v_C}, v₁={v_D,v_E}} is constructed using the neighboring blocks.
FIG. 4 shows an example of motion vector prediction (MVP) for a block 400 in the AF_INTER mode. As shown in FIG. 4, v₀is selected from the motion vectors of the sub-block A, B, or C. The motion vectors from the neighboring blocks can be scaled according to the reference list. The motion vectors can also be scaled according to the relationship among the Picture Order Count (POC) of the reference for the neighboring block, the POC of the reference for the current CU, and the POC of the current CU. The approach to select v₁from the neighboring sub-block D and E is similar. If the number of candidate list is smaller than 2, the list is padded by the motion vector pair composed by duplicating each of the AMVP candidates. When the candidate list is larger than 2, the candidates can be firstly sorted according to the neighboring motion vectors (e.g., based on the similarity of the two motion vectors in a pair candidate). In some implementations, the first two candidates are kept. In some embodiments, a Rate Distortion (RD) cost check is used to determine which motion vector pair candidate is selected as the control point motion vector prediction (CPMVP) of the current CU. An index indicating the position of the CPMVP in the candidate list can be signaled in the bitstream. After the CPMVP of the current affine CU is determined, affine motion estimation is applied and the control point motion vector (CPMV) is found. Then the difference of the CPMV and the CPMVP is signaled in the bitstream.
When a CU is applied in AF_MERGE mode, it gets the first block coded with an affine mode from the valid neighboring reconstructed blocks. FIG. 5A shows an example of the selection order of candidate blocks for a current CU 500. As shown in FIG. 5A, the selection order can be from left (501), above (502), above right (503), left bottom (504) to above left (505) of the current CU 500. FIG. 5B shows another example of candidate blocks for a current CU 500 in the AF_MERGE mode. If the neighboring left bottom block 501 is coded in affine mode, as shown in FIG. 5B, the motion vectors v₂, v₃and v₄of the top left corner, above right corner, and left bottom corner of the CU containing the sub-block 501 are derived. The motion vector v₀of the top left corner on the current CU 500 is calculated based on v2, v3 and v4. The motion vector v1 of the above right of the current CU can be calculated accordingly.
After the CPMV of the current CU v0 and v1 are computed according to the affine motion model in Eq. (1), the MVF of the current CU can be generated. In order to identify whether the current CU is coded with AF_MERGE mode, an affine flag can be signaled in the bitstream when there is at least one neighboring block is coded in affine mode.

4. Exemplary Methods for IBC in Video Coding

FIG. 6 shows a flowchart of an exemplary method for video encoding using intra-block copy. The method 600 includes, at step 610, determining whether a current block of the current picture is to be encoded using a motion compensation algorithm. The method 600 includes, in step 620, encoding, based on the determining, the current block by selectively applying an intra-block copy to the current block. More generally, whether or not to apply the intra-block copy to the current block is based on whether the current block is to be encoded using a specific motion compensation algorithm.
FIG. 7 shows a flowchart of another exemplary method video encoding using intra-block copy. The method 700 includes, at step 710, determining whether a current block of the current picture is to be encoded using an intra-block copy. The method 700 includes, in step 720, encoding, based on the determining, the current block by selectively applying a motion compensation algorithm to the current block. More generally, whether or not to encode the current block using the motion compensation algorithm is based on whether the current block is to be encoded using the intra-block copy.
FIG. 8 shows a flowchart of an exemplary method for video decoding using intra-block copy. The method 800 includes, at step 810, determining whether a current block of the current picture is to be decoded using a motion compensation algorithm. The method 800 includes, in step 820, decoding, based on the determining, the current block by selectively applying an intra-block copy to the current block. More generally, whether or not to apply the intra-block copy to the current block is based on whether the current block is to be decoded using a specific motion compensation algorithm.
FIG. 9 shows a flowchart of another exemplary method video decoding using intra-block copy. The method 900 includes, at step 910, determining whether a current block of the current picture is to be decoded using an intra-block copy. The method 900 includes, in step 920, decoding, based on the determining, the current block by selectively applying a motion compensation algorithm to the current block. More generally, whether or not to decode the current block using the motion compensation algorithm is based on whether the current block is to be decoded using the intra-block copy.
The methods 600, 700, 800 and 900, described in the context of FIGS. 6-9, may further include are further the step of determining whether the motion compensation algorithm is compatible with the intra-block copy. The compatibility of the intra-block copy and the motion compensation algorithms are elucidated in the following examples described for different specific motion compensation algorithms.
Example 1. After determining that the current picture must be stored in the buffer for a duration corresponding to the duration of a long-term reference picture, the current picture is not marked as a “long-term” reference picture in a buffer (e.g., a decoded picture buffer). Instead, it is marked as a new type of reference picture different from “short-term” or “long-term”. For example, it may be marked as a “current” reference picture, a “self” reference picture, an “instant” reference picture, an “intra block copy” reference picture, and so on.
(a) Similarly, prediction (e.g., motion information prediction) between pictures with the new picture type and short-term pictures, and/or prediction (e.g., motion information prediction) between pictures with the new picture type and long-term pictures are disallowed.
(b) When the prediction between pictures with the new picture type and short/long-term pictures is allowed, scaling process of motion vectors may be skipped.
Example 2. It is proposed that affine prediction cannot be applied for IBC coded blocks. In this case, when a block is coded with IBC mode, the signaling of indications of affine prediction is skipped.
(a) In an example, if at least one reference picture of the current block in a reference picture list is the current picture, the flag indicating whether affine prediction is used (a. k. a. affine_flag) is not signaled and inferred to be 0.
(b) Alternatively, if the two reference pictures for the two reference lists are both the current picture, affine_flag is not signaled and inferred to be 0.
(c) Alternatively, if a block is associated with M sets of motion information (M>2), and all the associated reference pictures are the current picture, affine_flag is not signaled and inferred to be 0.
(d) Alternatively, if reference pictures of the current block includes both the current picture and other reference pictures, affine_flag may be signaled. In this case, affine_flag only controls whether the affine prediction is used for the non-IBC inter-prediction, i.e., inter-prediction which is not from the current picture. Some examples of this case are as following:

- (i) In an example, the current block is associated with two reference pictures, and only one reference picture is the current picture.
- (ii) In an example, the current block is associated with more than two reference pictures from, and at least one of the reference pictures is the current picture and at least one of the reference pictures is not the current picture.
- (iii) Even if affine_flag is equal to 1, affine prediction is not used for the IBC prediction with the reference picture identical to the current picture.
- (iv) Alternatively, furthermore, even if affine_flag is equal to 1, affine prediction is not used for the reference list wherein the IBC prediction is enabled with the reference picture identical to the current picture.

(e) In an example, whether and how to apply affine prediction for IBC coded blocks can be transmitted from the encoder to the decoder at sequence level, picture level, slice level, Coding Tree Unit (CTU) a. k. a. Largest Coding Unit (LCU) level, region level, CU level, or PU level. The information can be signaled in Sequence Parameter Set (SPS), Picture Parameter Set (PPS), Slice Header (SH), CTU (a. k. a. LCU), region, CU or PU.
Example 3. It is proposed that IBC cannot be applied for a block with affine prediction. In this case, when a block is coded with affine mode, the signaling of indications of IBC is skipped.
(a) In an example, if affine_flag is 1 for a block, any reference picture of the current block cannot be the current picture. In another example, if affine_flag is 1 for a block, at least one reference picture of the current block is not identical to the current picture.
(b) Alternatively, whether and how to apply IBC for a block with affine prediction can be transmitted from the encoder to the decoder at sequence level, picture level, slice level, Coding Tree Unit (CTU) (e.g., Largest Coding Unit (LCU) level, region level, CU level, or PU level). The information can be signaled in Sequence Parameter Set (SPS), Picture Parameter Set (PPS), Slice Header (SH), CTU (a. k. a. LCU), region, CU or PU.
Example 4. Alternatively, it is proposed that affine prediction can be applied for IBC coded blocks. In this case, the indications of affine and IBC may be both signaled. When affine prediction is applied for a IBC coded block, the following may further apply:
(a) In an example, the MV Prediction (MVP) for control points (such as {right arrow over (v₀)} and {right arrow over (v₁)}) can only be derived from previously decoded MVs with the current picture as the reference picture. MV scaling is disabled for MVP derivation. Vice versa, MVP for control points of a block with an affine prediction but not IBC-coded, can only be derived from previously decoded MVs with reference pictures not identical to the current picture.
(b) In an example, MVs at control points explained in “Examples of affine prediction” section are signaled in the integer precision. MVPs for them should be truncated or rounded to the integer-pixel precision.
(c) In an example, if MVs at control points (such as {right arrow over (v₀)} and {right arrow over (v₁)}) are derived from neighboring MVs, such as in the affine-merge mode, the derived MVs are truncated or rounded to the integer-pixel precision.
(d) In an example, a MV inside the block derived from MVs at the control points, such as (v_x, v_y) in eq. (1) are truncated or rounded to the integer-pixel precision.
(e) In an example, OBMC is not applied.
(f) In an example, the y component of the MV at control points (e.g., {right arrow over (v₁)}) is not signaled and is always considered as zero.
Listed below are some examples of the technology described in this application. A block, as used in this application, can be a contiguous or a noncontiguous collection of pixels, voxels, sub-pixels, and/or sub-voxels. For example, a block can be rectilinear, such as a 4×4 square, 6×4 rectangle, or curvilinear, such as an ellipse.
A portion of the visual information, as used in this application, can be a subset of visual information. A coded representation, as used in this application, can be a bitstream representing the visual information that has been encoded using one of the techniques described in this application. An indicator, as used in this application, can be a flag or a field in the coded representation or can be multiple separate flags or fields.
A decoding technique, as used in this application can be applied by a decoder and can be implemented in hardware or software. The decoding technique can undo in reverse sequence everything a coder does. When an appropriate decoding technique is applied to an encoded representation, a visual information can be obtained as a result.
An initial block in the plurality of blocks, as used in this application, is a block occurring before the first block in the coded representation. A predetermined component, as used in this application, can be an x-axis, a y-axis or a z-axis component of a motion vector.

EXAMPLES

1. As depicted in FIG. 13, A visual information decoding method (1300), comprising: determining (1302) that a block being decoded representing a portion of the visual information is coded using a first coding technique; and decoding (1304) the coded representation by using a first decoding technique corresponding to the first coding technique and by excluding use of a second decoding technique corresponding to a second coding technique; wherein one of the first and second coding techniques corresponds to an intra-block copy (IBC) technique that uses a second block of a same video picture for coding the block being decoded and the other corresponds to an affine coding technique that uses an affine motion model for coding the block being decoded.
2. As depicted in FIG. 12, a visual information processing method (1200) comprising: determining (1202) that a block being decoded representing a portion of an encoded picture of visual information is coded using an intra-block copy (IBC) technique that uses a second block of the picture for coding the block being decoded and an affine coding technique that uses an affine motion model for coding the block being decoded; and decoding (1204) the coded representation by using an IBC decoding technique corresponding to the IBC decoding technique and an affine decoding technique corresponding to the affine coding technique.
3. The method of examples 1-2, the IBC decoding technique comprising: obtaining a plurality of blocks representing the encoded picture and an indicator of use of the IBC technique; decoding a plurality of initial blocks in the encoded picture; and after decoding the plurality of initial blocks, decoding a first block in the remaining of the plurality of blocks based on the decoded initial blocks.
4. The method of example 1, comprising: deciding, based on the determining, that a coded representation of the block being decoded excludes an indicator of use of a second coding technique; and parsing the coded representation based on the deciding. For example, in this parsing process, the decoder is successfully able to parse coded bitstream with the knowledge that fields related to the excluded coding technique will not be present in the bitstream.
5. A method of video processing, comprising: determining that an indicator associated with an encoded picture comprises an alternate type of reference picture indicator signaling an encoding technique applied to the encoded picture is an IBC technique, wherein the alternate type of reference picture indicator is different from a long-term reference picture indicator and a short-term reference picture indicator, wherein a picture comprising the long-term reference picture indicator is stored in a memory for a first duration, and wherein a picture comprising the short-term reference picture indicator is stored in the memory for a second duration that is shorter than the first duration.
6. The method of example 5, comprising: obtaining a first indicator comprising the long-term reference picture indicator or the long-term reference picture indicator associated with a first picture; obtaining a second indicator comprising the alternate type of reference picture indicator associated with a second picture; avoiding decoding the second picture based on the first picture; avoiding decoding the first picture based on the second picture.
7. The method of example 6, comprising: obtaining a first indicator comprising the long-term reference picture indicator or the long-term reference picture indicator associated with a first picture; obtaining a second indicator comprising the alternate type of reference picture indicator associated with a second picture; skipping a scaling process of motion vectors associated with the first picture when decoding the second picture; and skipping the scaling process of motion vectors associated with the second picture when decoding the first picture.
8. The method of examples 1-7, comprising: when an indicator associated with a block of the encoded picture signals a use of the IBC technique, decoding the block without applying the affine decoding technique.
9. The method of example 8, comprising: obtaining a plurality of reference pictures used to decode a block of the encoded picture comprising a plurality of blocks; when at least one reference picture in the plurality of reference pictures comprises the encoded picture, decoding the block without applying the affine decoding technique.
10. The method of example 8, comprising: obtaining a plurality of reference pictures used to decode a block of the encoded picture comprising a plurality of blocks; in case that a block is associated with multiple sets of motion information, wherein the multiple sets of motion information comprise more than two sets of motion information, and each reference picture in the plurality of reference pictures is the encoded picture, decoding the block without applying the affine decoding technique.
11. The method of example 8, comprising: obtaining a plurality of reference pictures used to decode a block of the encoded picture comprising a plurality of blocks, the plurality of reference pictures comprising the encoded picture and another picture in the visual information; obtaining a first indicator signaling that the affine coding technique is applied to the block; decoding the block using the affine decoding technique and the another picture in the visual information.
12. The method of example 11, wherein the encoded picture and the another picture in the visual information are identical, the method comprising: avoiding decoding the block using the affine decoding technique and the encoded picture. For example, avoiding may be performed by disabling the affine decoding technique and the encoded picture during the decoding process.
13. The method of examples 1-12, comprising: determining that an indicator associated with the encoded picture signals that the affine coding technique is applied to the encoded picture; and in case that the indicator associated with the encoded picture signals that the affine coding technique is applied to the encoded picture, decoding the encoded picture without applying the IBC decoding technique.
14. The method of example 13, comprising: obtaining one or more reference pictures used to decode a block of the encoded picture comprising a plurality of blocks and the indicator associated with the encoded picture; in case that the indicator associated with the encoded picture signals that the affine coding technique is applied to the encoded picture, assuming that the one or more reference pictures do not contain the encoded picture.
15. The method of example 13, comprising: obtaining one or more reference pictures used to decode a block of the encoded picture comprising a plurality of blocks and the indicator associated with the encoded picture; in case that the indicator associated with the encoded picture signals that the affine coding technique is applied to the encoded picture, assuming that at least one reference picture in the one or more reference pictures is different from the encoded picture.
16. The method of examples 1-7, comprising: obtaining a first indicator associated with the encoded picture and a second indicator associated with the encoded picture, the first indicator signaling that the affine coding technique is applied to the block, the second indicator signaling that the IBC technique is applied to the block; and decoding the block of the encoded picture comprising a plurality of blocks by applying the affine decoding technique and the IBC decoding technique to the block.
17. The method of example 16, comprising: obtaining an initial block in a plurality of blocks representing the encoded picture; decoding an initial motion vector of an initial control point associated with the initial block; obtaining a first block in the plurality of blocks representing the encoded picture, and a first indicator signaling that the IBC technique is applied to the first block; disabling motion vector scaling; and upon disabling motion vector scaling, creating a motion vector prediction (MVP) of a first control point associated with the first block based on the initial motion vector of the initial control point associated with initial block.
18. The method of examples 16-17, comprising: obtaining a first block in the plurality of blocks representing the encoded picture, and a first indicator signaling that the affine coding technique is applied to the first block; creating the MVP of the first control point associated with the first block based on a motion vector of a control point associated with the block belonging to a picture different from the encoded picture.
19. The method of examples 16-17, comprising: obtaining a plurality of blocks representing the encoded picture; obtaining a motion vector of a control point associated with a block in the plurality of blocks, wherein the motion vector is signaled in an integer precision; making a motion vector prediction based on the motion vector; and rounding the motion vector prediction to an integer-pixel precision.
20. The method of examples 16-17, comprising: obtaining a block in a plurality of blocks representing the encoded picture; deriving a motion vector at a control point associated with the block from a neighboring motion vector at a neighboring control point; and rounding the motion vector to an integer-pixel precision.
21. The method of examples 16-20, comprising: avoiding to conduct an Overlapped Block Motion Compensation (OBMC).
22. The method of examples 16-20, comprising: assuming that a predetermined component of a motion vector at a control point is a constant integer.
23. A method for encoding a visual information, comprising: encoding the visual information into a plurality of encoded pictures and a plurality of indicators signaling one or more encoding techniques applied, the plurality of indicators comprising an intra-block copy (IBC) technique indicator and an affine coding technique indicator, wherein a first block of a first picture associated with the visual information is encoded using the IBC technique and a second block of a second picture associated with the visual information is encoded using the affine coding technique, wherein the IBC technique uses a different block of the first picture to encode the first block of the first picture and the affine coding technique uses a third picture associated with the visual information to encode the second block.
24. The method of example 23, the IBC technique comprising: dividing the first picture into a plurality of blocks; encoding an initial block in the plurality of blocks; and upon encoding the initial block, encoding a first block in the plurality of blocks based on the initial block.
25. The method comprising: encoding an indicator in a plurality of indicators associated with an encoded picture in a plurality of encoded pictures, the indicator comprising an alternate type of reference picture indicator signaling an encoding technique applied to the encoded picture is an IBC technique, wherein the alternate type of reference picture indicator is different from a long-term reference picture indicator and a short-term reference picture indicator, wherein a picture comprising the long-term reference picture indicator is stored in a memory for a first duration, and wherein a picture comprising the short-term reference picture indicator is stored in the memory for a second duration that is shorter than the first duration.
26. The method of example 25, comprising: obtaining a first indicator comprising the long-term reference picture indicator or the long-term reference picture indicator associated with a first picture; obtaining a second indicator comprising the alternate type of reference picture indicator associated with a second picture; avoiding encoding the second picture based on the first picture; and avoiding encoding the first picture based on the second picture.
27. The method of example 25, comprising: encoding a first indicator comprising the long-term reference picture indicator or the long-term reference picture indicator associated with a first picture; encoding a second indicator comprising the alternate type of reference picture indicator associated with a second picture; skipping a scaling process of motion vectors associated with the first picture when encoding the second picture; and skipping the scaling process of motion vectors associated with the second picture when encoding the first picture.
28. The method of examples 23-27, comprising: applying IBC technique to a block of the first picture in the visual information to obtain an encoded block; encoding an indicator associated with the encoded picture as the IBC technique and skipping encoding the encoded block using the affine coding technique and encoding an indicator signaling the affine coding technique.
29. The method of example 28, comprising: encoding a plurality of reference pictures used to encode the block of the first picture; in case that at least one reference picture in the plurality of reference pictures comprises the first picture, skipping encoding an indicator of use of the affine coding technique.
30. The method of example 28, comprising: encoding a plurality of reference pictures used to encode a block of the first picture; when a block is associated with multiple sets of motion information, wherein the multiple sets of motion information comprise more than two sets of motion information, and each reference picture in the plurality of reference pictures is the first picture, skipping encoding an indicator signaling the affine coding technique.
31. The method of example 28, comprising: encoding a plurality of reference pictures used to encode a block of the first picture, the plurality of reference pictures comprising the first picture and another picture in the visual information; encoding a first indicator signaling that the affine coding technique is applied to the block; and applying the affine coding technique to the block of the first picture and the another picture in the visual information.
32. The method of example 31, wherein the encoded picture and the another picture in the visual information are identical, the method comprising: skipping applying the affine coding technique to the block of the first picture and the another picture in the visual information.
33. The method of examples 23-32, comprising: applying the affine coding technique to the second picture associated with the visual information; and skipping encoding an indicator comprising the IBC technique.
34. The method of example 33, comprising: encoding one or more reference pictures used to encode a block of the second picture, wherein the one or more reference pictures excludes the second picture; and encoding an indicator in the plurality of indicators to signal that the affine coding technique is used to encode the second picture.
35. The method of example 33, comprising: encoding one or more reference pictures used to encode a block of the second picture, wherein at least one reference picture in the one or more reference pictures is different from the second picture; and encoding an indicator in the plurality of indicators to signal that the affine coding technique is used to encode the second picture.
36. The method of examples 23-27, comprising: encoding a block of the first picture using the IBC technique and the affine coding technique; encoding a first indicator and a second indicator associated with the block of the first picture, the first indicator to signal that the IBC technique is used to encode the block and the second indicator to signal that the affine coding technique is used to encode the block.
37. The method of example 36, comprising: dividing the first picture into a plurality of blocks; encoding a motion vector of a control point associated with an initial block in the plurality of blocks; and encoding a motion vector of a control point associated with a first block in the plurality of blocks based on the motion vector of the control point associated with the initial block; and disabling motion vector scaling.
38. The method of examples 36-37, comprising: dividing the second picture into a second plurality of blocks and a third picture in the visual information into a third plurality of blocks, wherein the third picture is different from the second picture; encoding a motion vector of a control point associated with a second block in second the plurality of blocks; and encoding a motion vector of a control point associated with a third block in the third plurality of blocks based on the motion vector of the control point associated with the second block.
39. The method of examples 36-37, comprising: dividing the first picture into a plurality of blocks; encoding a block in the plurality of blocks using the affine coding technique; encoding a motion vector of a control point associated with the block in the plurality of blocks using an integer precision; encoding a motion vector prediction based on the motion vector by rounding the motion vector prediction to an integer-pixel precision.
40. The method of examples 36-39, comprising: dividing the first picture into a plurality of blocks; encoding a block in the plurality of blocks using the affine coding technique; encoding a motion vector of a control point associated with the block in the plurality of blocks using an integer precision; encoding a motion vector of a point inside the block based on the motion vector of the control point associated with the block by rounding the motion vector of the point inside the block to the integer-pixel precision.
41. The method of examples 36-40, comprising: avoiding applying an Overlapped Block Motion Compensation (OBMC).
42. The method of examples 36-40, comprising: skipping encoding of a predetermined component of a motion vector at a control point.
43. The method of examples 1-42, comprising: transmitting an indicator between an encoder and a decoder, the indicator signaling whether and how to apply the affine coding technique for IBC technique coded blocks at a sequence level, a picture level, a slice level, a Coding Tree Unit (CTU), a region level, a CU level, or a PU level.
44. The method of example 43, comprising: transmitting the indicator at a Sequence Parameter Set (SPS), Picture Parameter Set (PPS), a Slice Header (SH), a tile group header, a CTU, a region, a CU or a PU.
45. A video processing apparatus comprising a processor configured to implement a method recited in any one or more of examples 1 to 44. In some embodiments, the video processing apparatus may be a video encoder. In some embodiments, the video processing apparatus may be a video decoder. In some embodiments, the video processing apparatus may be a video transcoder.
46. A computer readable medium having processor-executable code stored thereon, the code, upon execution, causing a processor to implement a method recited in any one or more of examples 1 to 44.

5. Example Implementations of the Disclosed Technology

FIG. 10 is a block diagram illustrating an example of the architecture for a computer system or other control device 1000 that can be utilized to implement various portions of the presently disclosed technology, including (but not limited to) methods 600, 700, 800, 900, 1200 and 1300. In FIG. 10, the computer system 1000 includes one or more processors 1005 and memory 1010 connected via an interconnect 1025. The interconnect 1025 may represent any one or more separate physical buses, point to point connections, or both, connected by appropriate bridges, adapters, or controllers. The interconnect 1025, therefore, may include, for example, a system bus, a Peripheral Component Interconnect (PCI) bus, a HyperTransport or industry standard architecture (ISA) bus, a small computer system interface (SCSI) bus, a universal serial bus (USB), IIC (I2C) bus, or an Institute of Electrical and Electronics Engineers (IEEE) standard 674 bus, sometimes referred to as “Firewire.”
The processor(s) 1005 may include central processing units (CPUs) to control the overall operation of, for example, the host computer. In certain embodiments, the processor(s) 1005 accomplish this by executing software or firmware stored in memory 1010. The processor(s) 1005 may be, or may include, one or more programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application specific integrated circuits (ASICs), programmable logic devices (PLDs), or the like, or a combination of such devices.
The memory 1010 can be or include the main memory of the computer system. The memory 1010 represents any suitable form of random access memory (RAM), read-only memory (ROM), flash memory, or the like, or a combination of such devices. In use, the memory 1010 may contain, among other things, a set of machine instructions which, when executed by processor 1005, causes the processor 1005 to perform operations to implement embodiments of the presently disclosed technology.
Also connected to the processor(s) 1005 through the interconnect 1025 is a (optional) network adapter 1015. The network adapter 1015 provides the computer system 1000 with the ability to communicate with remote devices, such as the storage clients, and/or other storage servers, and may be, for example, an Ethernet adapter or Fiber Channel adapter.
FIG. 11 shows a block diagram of an example embodiment of a mobile device 1100 that can be utilized to implement various portions of the presently disclosed technology, including (but not limited to) methods 600, 700, 800 and 900. The mobile device 1100 can be a laptop, a smartphone, a tablet, a camcorder, or other types of devices that are capable of processing videos. The mobile device 1100 includes a processor or controller 1101 to process data, and memory 1102 in communication with the processor 1101 to store and/or buffer data. For example, the processor 1101 can include a central processing unit (CPU) or a microcontroller unit (MCU). In some implementations, the processor 1101 can include a field-programmable gate-array (FPGA). In some implementations, the mobile device 1100 includes or is in communication with a graphics processing unit (GPU), video processing unit (VPU) and/or wireless communications unit for various visual and/or communications data processing functions of the smartphone device. For example, the memory 1102 can include and store processor-executable code, which when executed by the processor 1101, configures the mobile device 1100 to perform various operations, e.g., such as receiving information, commands, and/or data, processing information and data, and transmitting or providing processed information/data to another device, such as an actuator or external display.
To support various functions of the mobile device 1100, the memory 1102 can store information and data, such as instructions, software, values, images, and other data processed or referenced by the processor 1101. For example, various types of Random Access Memory (RAM) devices, Read Only Memory (ROM) devices, Flash Memory devices, and other suitable storage media can be used to implement storage functions of the memory 1102. In some implementations, the mobile device 1100 includes an input/output (I/O) unit 1103 to interface the processor 1101 and/or memory 1102 to other modules, units or devices. For example, the I/O unit 1103 can interface the processor 1101 and memory 1102 with to utilize various types of wireless interfaces compatible with typical data communication standards, e.g., such as between the one or more computers in the cloud and the user device. In some implementations, the mobile device 1100 can interface with other devices using a wired connection via the I/O unit 1103. The mobile device 1100 can also interface with other external interfaces, such as data storage, and/or visual or audio display devices 1104, to retrieve and transfer data and information that can be processed by the processor, stored in the memory, or exhibited on an output unit of a display device 1104 or an external device. For example, the display device 1104 can display a video frame that includes a block (a CU, PU or TU) that applies the intra-block copy based on whether the block is encoded using a motion compensation algorithm, and in accordance with the disclosed technology.
In some embodiments, a video decoder apparatus may implement a method of video decoding in which the intra-block copy as described herein is used for video decoding. The method may be similar to the above-described methods 600, 700, 800, 900, 1200 and 1300.
In some embodiments, a decoder-side method of video decoding may use the intra-block copy for improving video quality by determining whether a current block of the current picture is to be decoded using a motion compensation algorithm, and decoding, based on the determining, the current block by selectively applying an intra-block copy to the current block.
In other embodiments, a decoder-side method of video decoding may use the intra-block copy for improving video quality by determining whether a current block of the current picture is to be decoded using an intra-block copy, and decoding, based on the determining, the current block by selectively applying a motion compensation algorithm to the current block.
In some embodiments, the video decoding methods may be implemented using a decoding apparatus that is implemented on a hardware platform as described with respect to FIG. 10 and FIG. 11.
Below are improvements measured by incorporating IBC into VTM-1.0, which is a reference software for the video coding standard named Versatile Video Coding (VVC). VTM stands for VVC Test Model.


	Over VTM-1.0

	Y	U	V	EncT	DecT

Class Al	−0.33%	−0.50%	−0.49%	162%	100%
Class A2	−0.96%	−1.17%	−0.77%	159%	98%
Class B	−0.94%	−1.14%	−1.34%	162%	102%
Class C	−1.03%	−1.58%	−1.92%	160%	101%
Class E	−1.48%	−1.46%	−1.80%	160%	104%
Overall	−0.95%	−1.19%	−1.31%	161%	101%
Class D	−0.57%	−0.73%	−0.91%	161%	100%
Class F	−20.25%	−20.15%	−20.93%	194%	95%
(optional)
Class SCC	−52.94%	−53.26%	−53.37%	217%	74%
1080p

In the above table, “Y”, “U”, “V” represent colors in the YUV color encoding system which encodes a color image or video taking human perception into account. The EncT and DecT represent a ratio of the encoding and decoding time using the IBC compared to the encoding and decoding time without the IBC, respectively. Specifically,

- EncT=TestEncodingTime/anchorEncodingTime
- DecT=TestEncodingTime/anchorEncodingTime.

The various classes, such as Class A1, Class A2, etc., represent a grouping of standard video sequences used in testing performance of various video coding techniques. The negative percentages under the “Y”, “U”, “V” columns represent bit-rate savings when IBC is added to VTM-1.0. The percentages under the EncT and DecT columns that are over 100% show how much the encoding/decoding with IBC is slower than encoding/decoding without IBC. For example, a percentage of 150% means that the encoding/decoding with IBC is 50% slower than the encoding/decoding without the IBC. The percentage below 100% shows how much the encoding/decoding with IBC is faster than encoding/decoding without the IBC. Two classes, class F and class SCC, highlighted in green in the table above, show that bit-rate savings exceed 3%.
From the foregoing, it will be appreciated that specific embodiments of the presently disclosed technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the scope of the invention. Accordingly, the presently disclosed technology is not limited except as by the appended claims.
Implementations of the subject matter and the functional operations described in this patent document can be implemented in various systems, digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Implementations of the subject matter described in this specification can be implemented as one or more computer program products, i.e., one or more modules of computer program instructions encoded on a tangible and non-transitory computer readable medium for execution by, or to control the operation of, data processing apparatus. The computer readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, a composition of matter effecting a machine-readable propagated signal, or a combination of one or more of them. The term “data processing unit” or “data processing apparatus” encompasses all apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. The apparatus can include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.
A computer program (also known as a program, software, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub programs, or portions of code). A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication network.
The processes and logic flows described in this specification can be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).
Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read only memory or a random access memory or both. The essential elements of a computer are a processor for performing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto optical disks, or optical disks. However, a computer need not have such devices. Computer readable media suitable for storing computer program instructions and data include all forms of nonvolatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.
It is intended that the specification, together with the drawings, be considered exemplary only, where exemplary means an example. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Additionally, the use of “or” is intended to include “and/or”, unless the context clearly indicates otherwise.
While this patent document contains many specifics, these should not be construed as limitations on the scope of any invention or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this patent document in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Moreover, the separation of various system components in the embodiments described in this patent document should not be understood as requiring such separation in all embodiments.
Only a few implementations and examples are described and other implementations, enhancements and variations can be made based on what is described and illustrated in this patent document.

Claims

What is claimed is:

1. A method of coding video data, comprising:

determining, for a conversion between a current video block of a video and a bitstream representation of the video, that the current video block is coded with a first technique; and

performing the conversion by using the first technique and by excluding use of a second technique;

wherein one of the first and second techniques corresponds to an intra-block copy (IBC) technique that uses sample values of a same video slice for coding the current video block and the other corresponds to an affine technique that uses an affine motion model for coding the current video block.

2. The method of claim 1, comprising:

deciding that an indicator of use of the second technique is excluded from the bitstream representation of the video in response to the first technique being used.

3. The method of claim 1, comprising:

in response to an indicator associated with the current video block signaling a use of the IBC technique, perform the conversion without applying the affine technique.

4. The method of claim 1, comprising:

in response to an indicator associated with the current video block signaling a use of the affine technique, perform the conversion without applying the IBC technique.

5. The method of claim 1, wherein the first technique corresponds to the IBC technique, and the second technique corresponds to the affine technique.

6. The method of claim 1, wherein the first technique corresponds to the affine technique, and the second technique corresponds to the IBC technique.

7. The method of claim 1, wherein the conversion generates the current video block from the bitstream representation.

8. The method of claim 1, wherein the conversion generates the bitstream representation from the current video block.

9. An apparatus for coding video data comprising a processor and a non-transitory memory with instructions thereon, wherein the instructions upon execution by the processor, cause the processor to:

10. The apparatus of claim 9, comprising:

deciding that an indicator of use of the second technique is excluded from the bitstream representation of the video in response to the first technique is used.

11. The apparatus of claim 9, comprising:

12. The apparatus of claim 9, comprising:

13. The apparatus of claim 9, wherein the first technique corresponds to the IBC technique, and the second technique corresponds to the affine technique.

14. The apparatus of claim 9, wherein the first technique corresponds to the affine technique, and the second technique corresponds to the IBC technique.

15. The apparatus of claim 9, wherein the conversion generates the current video block from the bitstream representation.

16. The apparatus of claim 9, wherein the conversion generates the bitstream representation from the current video block.

17. A non-transitory computer-readable storage medium storing instructions that cause a processor to:

determining, for a conversion between a current video block of a video and a bitstream representation of the video, that the current video block being decoded representing a portion of the visual information is coded using a first technique; and