US20200245456A1 - Ceramic Substrate Component/Assembly with Raised Thermal Metal Pad, and Method for Fabricating the Component - Google Patents
Ceramic Substrate Component/Assembly with Raised Thermal Metal Pad, and Method for Fabricating the Component Download PDFInfo
- Publication number
- US20200245456A1 US20200245456A1 US16/737,288 US202016737288A US2020245456A1 US 20200245456 A1 US20200245456 A1 US 20200245456A1 US 202016737288 A US202016737288 A US 202016737288A US 2020245456 A1 US2020245456 A1 US 2020245456A1
- Authority
- US
- United States
- Prior art keywords
- ceramic substrate
- base portion
- substrate body
- layer
- top layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 120
- 239000000919 ceramic Substances 0.000 title claims abstract description 109
- 238000000034 method Methods 0.000 title claims description 25
- 229910052751 metal Inorganic materials 0.000 claims abstract description 53
- 239000002184 metal Substances 0.000 claims abstract description 53
- 230000008646 thermal stress Effects 0.000 claims abstract description 14
- 239000010410 layer Substances 0.000 claims description 120
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 22
- 229910052802 copper Inorganic materials 0.000 claims description 21
- 239000010949 copper Substances 0.000 claims description 21
- 239000011241 protective layer Substances 0.000 claims description 5
- 229910000679 solder Inorganic materials 0.000 claims description 5
- 238000004544 sputter deposition Methods 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 238000005476 soldering Methods 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 238000005219 brazing Methods 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 238000007789 sealing Methods 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 description 5
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000009713 electroplating Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000005855 radiation Effects 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- -1 aluminum nitrides Chemical class 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical class [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
- H05K1/0209—External configuration of printed circuit board adapted for heat dissipation, e.g. lay-out of conductors, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
- H05K3/4015—Surface contacts, e.g. bumps using auxiliary conductive elements, e.g. pieces of metal foil, metallic spheres
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0338—Layered conductor, e.g. layered metal substrate, layered finish layer, layered thin film adhesion layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4076—Through-connections; Vertical interconnect access [VIA] connections by thin-film techniques
Definitions
- the present invention relates to a ceramic substrate and, more particularly, to a ceramic substrate component/assembly, and a method for fabricating the component.
- Ceramic substrates are excellent in heat dissipation, temperature resistance, reliability, and capable of being made into a thin, small-sized circuit board, and thus they are suitable for high-power chips or dies in electronic products.
- DBC direct bounded copper
- DBA direct bounded aluminum
- Al 2 O 3 aluminum oxide
- the electrical circuit including pads, traces and conductive layers, on a ceramic substrate need to be thickened.
- the thermal expansion coefficients of a metal layer and a ceramic substrate For example, the linear thermal expansion coefficients of copper and aluminum are about 16.5 and 23 ppm/K (at 20 degree C.) respectively, while the liner thermal expansion coefficients of aluminum oxide, aluminum nitride, silicon nitride are about 7, 4.5, 3.5 ppm/K (at 20 degree C.) respectively.
- the significant difference of thermal expansion coefficients often causes thermal stress at the interface of the circuit layer and the substrate. Under these circumstances, the circuit board easily suffers interfacial breaks, bending or deformation.
- a technical solution is provided in the present invention, which employs at least one raised or thickened pad of a metal circuit layer on a ceramic substrate for installing a high-power chip, so that most of the temperature difference between the chip and the ceramic substrate is applied across the thickened pad, so that the temperature difference per unit height can be reduced, and thus the thermal stress occurring at the interface between the metal circuit layer and the substrate can be mitigated.
- the pad can be configured with various thicknesses according to customers' demands.
- One object of the present invention is to provide a ceramic substrate component, which includes a ceramic substrate body provided thereon with a metal circuit layer containing a raised thermal metal pad composed of a top layer and a thinner base portion, wherein the top layer has an area less than the thinner base portion, so that breaks caused at the interface between the metal circuit layer and the ceramic substrate body can be mitigated.
- Another object of the present invention is to provide a ceramic substrate component with a raised thermal metal pad so that the component is suitable for installing a high-power chip or die.
- a further object of the present invention is to provide a ceramic substrate assembly, which includes a high-power chip or die installed on a ceramic substrate component, which allows the heat produced by the chip to be dissipated properly.
- a still further object of the present invention is to provide a method for fabricating a ceramic substrate assembly, whereby a high-power chip can be installed onto a ceramic substrate body so that interfacial damages between pads and the ceramic substrate body can be mitigated while the chips works.
- the ceramic substrate component is adapted for installing thereon at least one chip that produces a lot of heat, which generally comprises a ceramic substrate body and at least one raised metal pad.
- the ceramic substrate body has an upper surface and a lower surface opposite to the upper surface.
- the raised metal pad includes a base portion and a top layer.
- the base portion which is attached to the upper surface of the ceramic substrate body, has a thickness between 10 and 300 micrometers and has a thermal expansion coefficient greater than the ceramic substrate body.
- the top layer which is formed on the base portion and adapted to solder or braze a high-power chip thereon, extends an area less than the base portion but greater than the chip.
- the top layer has a thermal expansion coefficient greater than the ceramic substrate body. As such, damages due to thermal stress occurring at the interface between the base portion and the ceramic substrate body can be mitigated.
- the ceramic substrate assembly is obtained by installing a high-power chip onto the ceramic substrate component.
- the ceramic substrate assembly comprises at least one chip that produces a lot heat, a ceramic substrate body, and at least one raised metal pad.
- the ceramic substrate body has an upper surface and a lower surface opposite to the upper surface.
- the raised metal pad includes a base portion and a top layer.
- the base portion which is attached to the upper surface of the ceramic substrate body, has a thickness between 10 and 300 micrometers and has a thermal expansion coefficient greater than the ceramic substrate body.
- the top layer is formed on the base portion, and the chip is placed on the top layer and soldered or brazed in place.
- the top layer extends an area less than the base portion but greater than the chip, and has a thermal expansion coefficient greater than the ceramic substrate body. As such, damages due to thermal stress occurring at the interface between the base portion and the ceramic substrate body can be mitigated.
- the present invention is featured in a raised thermal metal pad, including a thinner base portion and a thicker top layer, on a ceramic substrate body, wherein the base portion has an area greater than the top layer. Therefore, the temperature difference per unit thickness of the metal pad can be reduced, while the extensibility of the base portion can be increased, so that the ceramic substrate body is suitable for a high-power chip, and damages caused by thermal stress occurring at the interface of the pad and the ceramic substrate body can be mitigated.
- FIG. 1 shows a side view of a first embodiment of a ceramic substrate component according to the present invention.
- FIG. 2 shows a side view of an embodiment of a ceramic substrate assembly according the present invention, wherein a high-power chip is installed on a ceramic substrate component.
- FIGS. 3A through 3K show side views of temporary products during fabrication of the ceramic substrate assembly according to the present invention.
- FIG. 4 shows a side view of a second embodiment of the ceramic substrate component according to the present invention.
- FIG. 1 shows a first embodiment of a ceramic substrate component according to the present invention.
- the ceramic substrate component indicated by reference numeral 10 , comprises a ceramic substrate body 11 and a raised metal pad 12 , wherein the ceramic substrate body 11 has an upper surface 111 and a second surface 112 opposite to the upper surface 111 ; the raised metal pad 12 includes a base portion 13 and a top layer 14 .
- the base portion 13 can be formed by sputtering copper onto the upper surface 111 of the ceramic substrate body and subsequently performing an electroplating process to reach a thickness of copper between 10 and 300 micrometers.
- the substrate product can be coated with a photo-resist (a photo-sensitive material) and then exposed with proper radiation so that unwanted portion of the photo-resist can be removed to expose part of the base portion 13 , which can be further electroplated thereon with copper to form the top layer 14 that is thicker and extends an area less than the base portion 13 .
- a high-power chip can be soldered or brazed.
- the thicker top layer can take a significant portion of the temperature difference existing between the chip and the substrate, while the extensible base portion 13 can keep contact with the ceramic substrate body without being damaged caused by thermal stress.
- the base portion and the top layer can be further processed by general routines to form a metal circuit according to a design pattern.
- the raised metal pad can work as a solder pad or a land for attachment of an electronic component.
- other ways of providing copper, such as evaporation or electroless plating, and/or other metals suitable for the base portion and the top layer can also be used.
- FIG. 2 shows one embodiment of a ceramic substrate assembly or package according the present invention.
- a high-power chip 25 which can produce a lot of heat, refers to an IGBT (insulated gate bipolar transistor) device.
- the high-power chip 25 can be soldered on the raised metal pad 22 via SMT (surface-mount technology).
- the raised metal pad 22 includes a base potion 23 and a top layer 24 .
- the base portion 23 is composed of a first thin layer 232 (seed layer), and a second thin layer 231 (build-up layer).
- the first thin layer 232 formed of titanium/copper and having thickness less than 0.5 micrometer is firstly attached on the upper surface of the ceramic substrate body by sputtering technique.
- the second thin layer 231 can be formed on the first thin layer 232 by electroplating technique.
- the top layer 24 can be formed on the second thin layer 231 by electroplating to reach a thickness suitable for the high-power chip 25 according to the specification thereof. Generally, the thickness of the top layer 24 is greater than that of the base portion 23 .
- metal wires 26 can be connected between bond pads (not shown) of the chip 25 and corresponding metal pads 27 , so that the chip 25 can work properly (in FIG. 2 , only one metal wire is shown).
- IGBT devices are often used in electrical equipment that performs heavy work, such as air conditioners, refrigerators, stereos, and motor drives. In operation of such equipment, the IGBT devices can produce a lot of heat. With the thicker top layer 24 , the raised metal pad 22 can take more heat than ordinary pads. Also, since the thermal expansion coefficients of the top layer 24 and the second thin layer 231 are approximately equal, thermal stress resulting from different thermal expansion coefficients is low, and thus does not cause damages between the two layers.
- the base portion 23 composed of the first thin layer 232 and the second thin layer 231 , has a thinner thickness than the top layer 24 and extends an area greater than the top layer 24 , which leads the base portion 23 to have better extensibility or ductility than the top layer 24 . Even though the base portion 23 has a different thermal expansion coefficient than the substrate body 21 , the base portion 23 allows to be extended over the substrate body 21 more freely to reduce the thermal stress caused by thermal expansion, thus reducing interface breaks.
- FIGS. 3A through 3K show a method for fabricating a ceramic substrate assembly or package.
- the method is based on a process the technique of DPC (direct plating copper), which is superior over the technique of DBC (direct bonding copper) in designing a stable substrate assembly.
- DPC direct plating copper
- DBC direct bonding copper
- FIG. 3A shows a ceramic substrate body 30 made of Aluminum Oxide (Al 2 O 3 ) or Aluminum Nitride (AlN).
- the ceramic substrate body 30 can be drilled to form a through hole 31 , as shown in FIG. 3B .
- the ceramic substrate body 30 can be sputtered with titanium/copper to form a first thin layer 32 thereon, as shown in FIG. 3C .
- a first layer 33 of photo-resist can be applied on the first thin layer 32 , as shown in FIG. 3D , and then the photo-resist can be exposed under a radiation lamp and then treated with a development process to remove unwanted photo-resist and thus to form a first remained photo-resist layer 33 , as shown in FIG. 3E .
- the first thin layer 32 can be electroplated with copper to form a second thin layer 34 , as shown in FIG. 3F , wherein the first and second thin layers 32 , 34 will constitute a base portion of the raised metal pad.
- a second layer 35 of photo resist can be applied on top of the second thin layer 34 and the first remained photo resist layer 33 , as shown in FIG. 3G
- the second photo-resist layer 35 can be exposed under a radiation lamp and then treated with a development process to remove unwanted photo resist, thus forming a second remained photo-resist layer and exposing the second thin layer 34 , as shown in FIG. 3H .
- a top layer 36 of copper can formed on the second thin layer 34 by electroplating and extends an area less than the second thin layer 34 , as shown in FIG. 3I .
- a high-power chip 37 can be installed on to the ceramic substrate component, wherein the chip's back (ground) can be soldered or brazed onto the top layer 36 and fixed in place; a metal wire 38 is soldered or brazed between one bond pad of the chip (not shown) and a metal pad 39 of the circuit layer, as shown in FIG. 3K .
- a sealing or encapsulation process can be performed so as to protect the chip and metal wire on the ceramic substrate component.
- the first and second thin layers on the ceramic substrate body can be replaced by a piece of copper foil.
- the ceramic substrate body can be electroplated with copper so that an initial copper layer having a thickness equal to the total thickness of a top layer and a base portion is formed on the substrate, and then unwanted portions of the initial copper layer can be removed through imaging (light exposure), developing and etching process to obtain a raised metal pad.
- FIG. 4 shows a second embodiment of the ceramic substrate component, which is the same as the one shown in FIG. 3J except for the base portion and/or the top layer being coated with a protective layer 42 , which protects the copper of the raised metal pad 41 and other pads from oxidation, thus improving solderability and conductivity of the pads.
- the protective layer 42 can be formed of gold, silver, palladium, or nickel by using hot gas over a layer of solder paste containing protective metals (reflow technique), organic coating technique, or electroless plating technique.
- the ceramic substrate component/assembly of the present invention employs a raised thermal metal pad including a thicker top layer to take a significant portion of temperature difference existing between a high-power chip and a ceramic substrate body, and a thinner base portion under the top layer.
- the thickness of the top layer depends on the power or heat generation of the chip.
- the base portion which has an area greater than the top layer, can be extended more easily than the top layer to reduce the thermal stress caused by different thermal expansions of the base portion and the ceramic substrate body, thus reducing interfacial breaks.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Materials Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
- The present invention relates to a ceramic substrate and, more particularly, to a ceramic substrate component/assembly, and a method for fabricating the component.
- Compared with traditional substrates for circuit boards, ceramic substrates are excellent in heat dissipation, temperature resistance, reliability, and capable of being made into a thin, small-sized circuit board, and thus they are suitable for high-power chips or dies in electronic products. Both DBC (direct bounded copper) and DBA (direct bounded aluminum) substrates, made of aluminum oxide (Al2O3), are the most commonly used ceramic substrates, wherein the thickness of copper or aluminum layer is generally between 200 and 300 micrometers; when the thickness of copper or aluminum layer is greater than 300 micrometers, because the substrates are easy to suffer interfacial breaks.
- With increasing power of chips or dies, the electrical circuit, including pads, traces and conductive layers, on a ceramic substrate need to be thickened. Generally, there is a significant difference between the thermal expansion coefficients of a metal layer and a ceramic substrate. For example, the linear thermal expansion coefficients of copper and aluminum are about 16.5 and 23 ppm/K (at 20 degree C.) respectively, while the liner thermal expansion coefficients of aluminum oxide, aluminum nitride, silicon nitride are about 7, 4.5, 3.5 ppm/K (at 20 degree C.) respectively. The significant difference of thermal expansion coefficients often causes thermal stress at the interface of the circuit layer and the substrate. Under these circumstances, the circuit board easily suffers interfacial breaks, bending or deformation.
- To alleviate the problem of existing circuit boards, a technical solution is provided in the present invention, which employs at least one raised or thickened pad of a metal circuit layer on a ceramic substrate for installing a high-power chip, so that most of the temperature difference between the chip and the ceramic substrate is applied across the thickened pad, so that the temperature difference per unit height can be reduced, and thus the thermal stress occurring at the interface between the metal circuit layer and the substrate can be mitigated. Also, the pad can be configured with various thicknesses according to customers' demands.
- One object of the present invention is to provide a ceramic substrate component, which includes a ceramic substrate body provided thereon with a metal circuit layer containing a raised thermal metal pad composed of a top layer and a thinner base portion, wherein the top layer has an area less than the thinner base portion, so that breaks caused at the interface between the metal circuit layer and the ceramic substrate body can be mitigated.
- Another object of the present invention is to provide a ceramic substrate component with a raised thermal metal pad so that the component is suitable for installing a high-power chip or die.
- A further object of the present invention is to provide a ceramic substrate assembly, which includes a high-power chip or die installed on a ceramic substrate component, which allows the heat produced by the chip to be dissipated properly.
- A still further object of the present invention is to provide a method for fabricating a ceramic substrate assembly, whereby a high-power chip can be installed onto a ceramic substrate body so that interfacial damages between pads and the ceramic substrate body can be mitigated while the chips works.
- The ceramic substrate component is adapted for installing thereon at least one chip that produces a lot of heat, which generally comprises a ceramic substrate body and at least one raised metal pad. The ceramic substrate body has an upper surface and a lower surface opposite to the upper surface. The raised metal pad includes a base portion and a top layer. The base portion, which is attached to the upper surface of the ceramic substrate body, has a thickness between 10 and 300 micrometers and has a thermal expansion coefficient greater than the ceramic substrate body. The top layer, which is formed on the base portion and adapted to solder or braze a high-power chip thereon, extends an area less than the base portion but greater than the chip. The top layer has a thermal expansion coefficient greater than the ceramic substrate body. As such, damages due to thermal stress occurring at the interface between the base portion and the ceramic substrate body can be mitigated.
- The ceramic substrate assembly is obtained by installing a high-power chip onto the ceramic substrate component. Accordingly, the ceramic substrate assembly comprises at least one chip that produces a lot heat, a ceramic substrate body, and at least one raised metal pad. The ceramic substrate body has an upper surface and a lower surface opposite to the upper surface. The raised metal pad includes a base portion and a top layer. The base portion, which is attached to the upper surface of the ceramic substrate body, has a thickness between 10 and 300 micrometers and has a thermal expansion coefficient greater than the ceramic substrate body. The top layer is formed on the base portion, and the chip is placed on the top layer and soldered or brazed in place. The top layer extends an area less than the base portion but greater than the chip, and has a thermal expansion coefficient greater than the ceramic substrate body. As such, damages due to thermal stress occurring at the interface between the base portion and the ceramic substrate body can be mitigated.
- The method for fabricating a ceramic substrate component that includes a ceramic substrate body having an upper surface and a lower surface and provided with a raised metal pad for soldering at least one high-power chip thereon comprises the steps of: (a) forming a seed layer by sputtering a target metal onto the upper surface of the ceramic substrate body such that the seed layer has a thickness less than 1 micrometer; (b) forming a build-up layer of metal on the seed layer such that the seed layer and the build-up layer constitute a base portion having a thickness between 10 and 300 micrometers, and having a thermal expansion coefficient greater than the ceramic substrate body, so as to reduce damages caused by thermal stress occurring between the base portion and the ceramic substrate body; and (c) forming a top layer of metal on the base portion to extend an area less than the base portion such that the top layer and the base portion constituting the raised metal pad, the top layer having a thermal expansion coefficient greater than the ceramic substrate body.
- Compared with conventional technology, the present invention is featured in a raised thermal metal pad, including a thinner base portion and a thicker top layer, on a ceramic substrate body, wherein the base portion has an area greater than the top layer. Therefore, the temperature difference per unit thickness of the metal pad can be reduced, while the extensibility of the base portion can be increased, so that the ceramic substrate body is suitable for a high-power chip, and damages caused by thermal stress occurring at the interface of the pad and the ceramic substrate body can be mitigated.
-
FIG. 1 shows a side view of a first embodiment of a ceramic substrate component according to the present invention. -
FIG. 2 shows a side view of an embodiment of a ceramic substrate assembly according the present invention, wherein a high-power chip is installed on a ceramic substrate component. -
FIGS. 3A through 3K show side views of temporary products during fabrication of the ceramic substrate assembly according to the present invention. -
FIG. 4 shows a side view of a second embodiment of the ceramic substrate component according to the present invention. - The foregoing and other features and advantages of illustrated embodiments of the present invention will be more readily apparent from the following detailed description, which proceeds with reference to the accompanying drawings.
- The foregoing and other technical contents, features and advantages of the present invention will be illustrated in detail by way of exemplary embodiments in the following paragraphs with reference to the accompanying drawings.
- The drawings accompanying with the specification show the structural features of elements used in the present invention, which may be depicted in a size or proportion to be easily understood by those skilled in the art without changing the subject matter of the present invention.
-
FIG. 1 shows a first embodiment of a ceramic substrate component according to the present invention. The ceramic substrate component, indicated byreference numeral 10, comprises aceramic substrate body 11 and a raisedmetal pad 12, wherein theceramic substrate body 11 has anupper surface 111 and asecond surface 112 opposite to theupper surface 111; the raisedmetal pad 12 includes abase portion 13 and atop layer 14. Thebase portion 13 can be formed by sputtering copper onto theupper surface 111 of the ceramic substrate body and subsequently performing an electroplating process to reach a thickness of copper between 10 and 300 micrometers. Since copper has a linear thermal expansion coefficient of about 17 ppm/K while general ceramic substrates, such as aluminum oxides, aluminum nitrides or silicon nitrides, have a thermal expansion coefficient of 4 to 7 ppm/K, the use of thethinner base portion 13 leads to better extensibility or ductility. Thereafter, the substrate product can be coated with a photo-resist (a photo-sensitive material) and then exposed with proper radiation so that unwanted portion of the photo-resist can be removed to expose part of thebase portion 13, which can be further electroplated thereon with copper to form thetop layer 14 that is thicker and extends an area less than thebase portion 13. On the top layer, a high-power chip can be soldered or brazed. As such, the thicker top layer can take a significant portion of the temperature difference existing between the chip and the substrate, while theextensible base portion 13 can keep contact with the ceramic substrate body without being damaged caused by thermal stress. - The base portion and the top layer can be further processed by general routines to form a metal circuit according to a design pattern. The raised metal pad can work as a solder pad or a land for attachment of an electronic component. Of course, other ways of providing copper, such as evaporation or electroless plating, and/or other metals suitable for the base portion and the top layer can also be used.
-
FIG. 2 shows one embodiment of a ceramic substrate assembly or package according the present invention. In this embodiment, a high-power chip 25, which can produce a lot of heat, refers to an IGBT (insulated gate bipolar transistor) device. The high-power chip 25 can be soldered on the raisedmetal pad 22 via SMT (surface-mount technology). As show, the raisedmetal pad 22 includes abase potion 23 and atop layer 24. Thebase portion 23 is composed of a first thin layer 232 (seed layer), and a second thin layer 231 (build-up layer). The firstthin layer 232 formed of titanium/copper and having thickness less than 0.5 micrometer is firstly attached on the upper surface of the ceramic substrate body by sputtering technique. The secondthin layer 231 can be formed on the firstthin layer 232 by electroplating technique. Thetop layer 24 can be formed on the secondthin layer 231 by electroplating to reach a thickness suitable for the high-power chip 25 according to the specification thereof. Generally, the thickness of thetop layer 24 is greater than that of thebase portion 23. After the high-power chip 25 has been fixed onto thetop layer 24 by soldering or brazing,metal wires 26 can be connected between bond pads (not shown) of thechip 25 and correspondingmetal pads 27, so that thechip 25 can work properly (inFIG. 2 , only one metal wire is shown). - Due to various advantages, such as high efficiency and fast switching capability, IGBT devices are often used in electrical equipment that performs heavy work, such as air conditioners, refrigerators, stereos, and motor drives. In operation of such equipment, the IGBT devices can produce a lot of heat. With the thicker
top layer 24, the raisedmetal pad 22 can take more heat than ordinary pads. Also, since the thermal expansion coefficients of thetop layer 24 and the secondthin layer 231 are approximately equal, thermal stress resulting from different thermal expansion coefficients is low, and thus does not cause damages between the two layers. On the other hand, thebase portion 23, composed of the firstthin layer 232 and the secondthin layer 231, has a thinner thickness than thetop layer 24 and extends an area greater than thetop layer 24, which leads thebase portion 23 to have better extensibility or ductility than thetop layer 24. Even though thebase portion 23 has a different thermal expansion coefficient than thesubstrate body 21, thebase portion 23 allows to be extended over thesubstrate body 21 more freely to reduce the thermal stress caused by thermal expansion, thus reducing interface breaks. -
FIGS. 3A through 3K show a method for fabricating a ceramic substrate assembly or package. The method is based on a process the technique of DPC (direct plating copper), which is superior over the technique of DBC (direct bonding copper) in designing a stable substrate assembly. With the DPC technique, the flexibility of designing a ceramic substrate assembly and the bonding strength between the metal and the ceramic substrate body can be increased, while the ratio of gaps existing between the metal and the ceramic substrate body can be reduced. -
FIG. 3A shows aceramic substrate body 30 made of Aluminum Oxide (Al2O3) or Aluminum Nitride (AlN). Firstly, theceramic substrate body 30 can be drilled to form a throughhole 31, as shown inFIG. 3B . Secondly, theceramic substrate body 30 can be sputtered with titanium/copper to form a firstthin layer 32 thereon, as shown inFIG. 3C . Thirdly, afirst layer 33 of photo-resist can be applied on the firstthin layer 32, as shown inFIG. 3D , and then the photo-resist can be exposed under a radiation lamp and then treated with a development process to remove unwanted photo-resist and thus to form a first remained photo-resistlayer 33, as shown inFIG. 3E . Fourthly, the firstthin layer 32 can be electroplated with copper to form a secondthin layer 34, as shown inFIG. 3F , wherein the first and secondthin layers - Fifthly, a
second layer 35 of photo resist can be applied on top of the secondthin layer 34 and the first remained photo resistlayer 33, as shown inFIG. 3G Sixthly, the second photo-resistlayer 35 can be exposed under a radiation lamp and then treated with a development process to remove unwanted photo resist, thus forming a second remained photo-resist layer and exposing the secondthin layer 34, as shown inFIG. 3H . Seventhly, atop layer 36 of copper can formed on the secondthin layer 34 by electroplating and extends an area less than the secondthin layer 34, as shown inFIG. 3I . Eighthly, all of the remained photo resist can be removed from the ceramic substrate body, and then portions of the first thin layer 32 (uncovered by the second thin layer 34) can be etched away, thus obtaining a ceramic substrate component containing a circuit layer according to a design pattern, as shown inFIG. 3J . Ninthly, a high-power chip 37 can be installed on to the ceramic substrate component, wherein the chip's back (ground) can be soldered or brazed onto thetop layer 36 and fixed in place; a metal wire 38 is soldered or brazed between one bond pad of the chip (not shown) and ametal pad 39 of the circuit layer, as shown inFIG. 3K . Finally, a sealing or encapsulation process can be performed so as to protect the chip and metal wire on the ceramic substrate component. - Of course, those skilled in the art can understand that alternative steps can be performed to fabricate the ceramic substrate assembly of the present invention. For example, the first and second thin layers on the ceramic substrate body can be replaced by a piece of copper foil. Alternatively, the ceramic substrate body can be electroplated with copper so that an initial copper layer having a thickness equal to the total thickness of a top layer and a base portion is formed on the substrate, and then unwanted portions of the initial copper layer can be removed through imaging (light exposure), developing and etching process to obtain a raised metal pad.
-
FIG. 4 shows a second embodiment of the ceramic substrate component, which is the same as the one shown inFIG. 3J except for the base portion and/or the top layer being coated with aprotective layer 42, which protects the copper of the raisedmetal pad 41 and other pads from oxidation, thus improving solderability and conductivity of the pads. Theprotective layer 42 can be formed of gold, silver, palladium, or nickel by using hot gas over a layer of solder paste containing protective metals (reflow technique), organic coating technique, or electroless plating technique. - As a summary, the ceramic substrate component/assembly of the present invention employs a raised thermal metal pad including a thicker top layer to take a significant portion of temperature difference existing between a high-power chip and a ceramic substrate body, and a thinner base portion under the top layer. The thickness of the top layer depends on the power or heat generation of the chip. The base portion, which has an area greater than the top layer, can be extended more easily than the top layer to reduce the thermal stress caused by different thermal expansions of the base portion and the ceramic substrate body, thus reducing interfacial breaks.
- While the invention has been described with reference to the preferred embodiments above, it should be recognized that the preferred embodiments are given for the purpose of illustration only and are not intended to limit the scope of the present invention and that various modifications and changes, which will be apparent to those skilled in the relevant art, may be made without departing from the scope of the invention.
Claims (10)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW108103286A TWI706857B (en) | 2019-01-29 | 2019-01-29 | Ceramic substrate assembly and element with metal thermal conductive bump pads and manufacturing method thereof |
TW108103286 | 2019-01-29 | ||
TW108103286A | 2019-01-29 |
Publications (2)
Publication Number | Publication Date |
---|---|
US20200245456A1 true US20200245456A1 (en) | 2020-07-30 |
US10743411B1 US10743411B1 (en) | 2020-08-11 |
Family
ID=71732936
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/737,288 Active US10743411B1 (en) | 2019-01-29 | 2020-01-08 | Ceramic substrate component/assembly with raised thermal metal pad, and method for fabricating the component |
Country Status (2)
Country | Link |
---|---|
US (1) | US10743411B1 (en) |
TW (1) | TWI706857B (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI762290B (en) * | 2021-04-28 | 2022-04-21 | 璦司柏電子股份有限公司 | Interval Pressurization Combination Method for Power Modules with Multiple Power Components |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09148523A (en) * | 1995-11-21 | 1997-06-06 | Toshiba Corp | Semiconductor device |
WO2013061727A1 (en) * | 2011-10-28 | 2013-05-02 | 京セラ株式会社 | Circuit board and electronic apparatus provided with same |
JP2018085705A (en) * | 2016-11-25 | 2018-05-31 | 太陽誘電株式会社 | Electronic component and manufacturing method of the same |
-
2019
- 2019-01-29 TW TW108103286A patent/TWI706857B/en active
-
2020
- 2020-01-08 US US16/737,288 patent/US10743411B1/en active Active
Also Published As
Publication number | Publication date |
---|---|
TW202027988A (en) | 2020-08-01 |
US10743411B1 (en) | 2020-08-11 |
TWI706857B (en) | 2020-10-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5413707B2 (en) | Metal-ceramic composite substrate and manufacturing method thereof | |
CN101609826B (en) | Power semiconductor module | |
US6373131B1 (en) | TBGA semiconductor package | |
JP2967697B2 (en) | Lead frame manufacturing method and semiconductor device manufacturing method | |
US5760465A (en) | Electronic package with strain relief means | |
JPH04137551A (en) | Semiconductor device | |
KR20020020169A (en) | Semiconductor device and method of manufacturing the same | |
US10743411B1 (en) | Ceramic substrate component/assembly with raised thermal metal pad, and method for fabricating the component | |
TWI775075B (en) | Ceramic substrate assemblies and components with metal thermally conductive bump pads | |
US20210407874A1 (en) | System and Method for a Device Package | |
CN110838475A (en) | Chip assembly and manufacturing method thereof | |
JPS5819385B2 (en) | Rouzukehouhou | |
JPH07297320A (en) | Bga type semiconductor device | |
JPH10242330A (en) | Substrate for power module and manufacture thereof | |
US20230335459A1 (en) | Thermal mismatch reduction in semiconductor device modules | |
JP2002324873A (en) | Semiconductor device and its manufacturing method | |
SE517916C2 (en) | Chip carriers, systems and procedures in the manufacture of chip carriers | |
JP2003060129A (en) | Circuit board and method for partially plating circuit board | |
JP3210503B2 (en) | Multi-chip module and manufacturing method thereof | |
JP4175339B2 (en) | Manufacturing method of semiconductor device | |
CN111490018A (en) | Ceramic substrate element with metal heat conduction bump pad, assembly and manufacturing method | |
JP2822506B2 (en) | Method for manufacturing semiconductor device | |
JPH08172142A (en) | Semiconductor package, its manufacturing method, and semiconductor device | |
JP3506788B2 (en) | Semiconductor package | |
JP2968704B2 (en) | Semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YU, HO-CHIEH;LIAO, CHEN-CHENG-LUNG;LIN, CHUN-YU;AND OTHERS;SIGNING DATES FROM 20191121 TO 20191127;REEL/FRAME:051452/0320 Owner name: ICP TECHNOLOGY CO., LTD., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YU, HO-CHIEH;LIAO, CHEN-CHENG-LUNG;LIN, CHUN-YU;AND OTHERS;SIGNING DATES FROM 20191121 TO 20191127;REEL/FRAME:051452/0320 |
|
FEPP | Fee payment procedure |
Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |