US20200006361A1 - Erasable programmable non-volatile memory - Google Patents
Erasable programmable non-volatile memory Download PDFInfo
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- US20200006361A1 US20200006361A1 US16/397,143 US201916397143A US2020006361A1 US 20200006361 A1 US20200006361 A1 US 20200006361A1 US 201916397143 A US201916397143 A US 201916397143A US 2020006361 A1 US2020006361 A1 US 2020006361A1
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- 230000015556 catabolic process Effects 0.000 description 9
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- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
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- H01L27/11517—
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- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
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- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
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- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
- G11C16/045—Floating gate memory cells with both P and N channel memory transistors, usually sharing a common floating gate
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- G11C16/12—Programming voltage switching circuits
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- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
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- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
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- G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
- G11C2216/02—Structural aspects of erasable programmable read-only memories
- G11C2216/04—Nonvolatile memory cell provided with a separate control gate for erasing the cells, i.e. erase gate, independent of the normal read control gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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Definitions
- the present invention relates to a non-volatile memory, and more particularly to an erasable programmable non-volatile memory.
- FIGS. 1A ?? 1 D schematically illustrate the structure and the equivalent circuit of a conventional erasable programmable non-volatile memory.
- the conventional erasable programmable non-volatile memory is disclosed in U.S. Pat. No. 8,941,167.
- FIG. 1A is a schematic top view of a conventional non-volatile memory.
- FIG. 1B is a schematic cross-sectional view illustrating the conventional non-volatile memory of FIG. 1A and taken along a first direction (a 1 -a 2 ).
- FIG. 1C is a schematic cross-sectional view illustrating the non-volatile memory of FIG. 1A and taken along a second direction (b 1 -b 2 ).
- FIG. 1D is a schematic equivalent circuit diagram of the conventional non-volatile memory.
- the conventional non-volatile memory comprises two serially-connected p-type transistors. These two p-type transistors are constructed in an n-type well region (NW). Three p-type doped regions 31 , 32 and 33 are formed in the n-type well region (NW). In addition, two polysilicon gates 34 and 36 are spanned over the areas between the three p-type doped regions 31 , 32 and 33 .
- the first p-type transistor is used as a select transistor, and the polysilicon gate 34 (also referred as a select gate) of the first p-type transistor is connected to a select gate voltage V SG .
- the p-type doped region 31 is connected to a source line voltage V SL .
- the p-type doped region 32 is a combination of a p-type doped drain region of the first p-type transistor and a p-type doped region of the second p-type transistor.
- the second p-type transistor is a floating gate transistor.
- the polysilicon gate 36 (also referred as a floating gate) is disposed over the second p-type transistor.
- the p-type doped region 33 is connected to a bit line voltage V BL .
- the n-type well region (NW) is connected to an n-well voltage V NW .
- the conventional non-volatile memory further comprises an n-type transistor.
- the n-type transistor is composed of the floating gate 36 and an erase gate region 35 .
- the n-type transistor is constructed in a p-type well region (PW).
- An n-type doped region 38 is formed in the p-type well region (PW). That is, the erase gate region 35 contains the p-type well region (PW) and the n-type doped region 38 .
- the floating gate 36 is extended externally and located near the erase gate region 35 . Consequently, the floating gate 36 is also the gate terminal of the n-type transistor.
- the n-type doped region 38 may be considered as a combination of an n-type doped source region and an n-type doped drain region.
- the n-type doped region 38 is connected to an erase line voltage V EL .
- the p-type well region (PW) is connected to a p-well voltage V PW .
- the erase gate region 35 and the n-type well region (NW) are isolated from each other by a shallow trench isolation (STI) structure 39 .
- STI shallow trench isolation
- the non-volatile memory comprises a select transistor, a floating gate transistor and an n-type transistor.
- the select transistor and the floating gate transistor are p-type transistors and constructed in the n-type well region (NW).
- the n-type well region (NW) receives the n-well voltage V NW .
- the n-type transistor is constructed in the p-type well region (PW).
- the p-type well region (PW) receives the p-well voltage V PW .
- the select gate of the select transistor receives the select gate voltage V SG .
- the first source/drain terminal of the select transistor receives the source line voltage V SL .
- the first source/drain terminal of the floating gate transistor is connected with the second source/drain terminal of the select transistor.
- the second source/drain terminal of the floating gate transistor receives the bit line voltage V BL .
- the gate terminal of the n-type transistor and the floating gate of the floating gate transistor are connected with each other.
- the first source/drain terminal of the n-type transistor and the second source/drain terminal of the n-type transistor are connected with each other to receive the erase line voltage V EL .
- the present invention provides an erasable programmable non-volatile memory with a novel structure.
- An embodiment of the present invention provides an erasable programmable non-volatile memory.
- the erasable programmable non-volatile memory includes a first select transistor, a first floating gate transistor, a second select transistor and a second floating gate transistor.
- the first select transistor includes a select gate, a first source/drain terminal and a second source/drain terminal.
- the select gate of the first select transistor receives a select gate voltage.
- the first source/drain terminal of the first select transistor receives a first source line voltage.
- the first floating gate transistor includes a floating gate, a first source/drain terminal and a second source/drain terminal. The first source/drain terminal of the first floating gate transistor is connected with the second source/drain terminal of the first select transistor.
- the second source/drain terminal of the first floating gate transistor receives a first bit line voltage.
- the second select transistor includes the select gate, a first source/drain terminal and a second source/drain terminal.
- the first source/drain terminal of the second select transistor receives a second source line voltage.
- the second floating gate transistor includes the floating gate, a first source/drain terminal and a second source/drain terminal.
- the first source/drain terminal of the second floating gate transistor is connected with the second source/drain terminal of the second select transistor.
- the second source/drain terminal of the second floating gate transistor receives a second bit line voltage.
- the first select transistor and the first floating gate transistor are constructed in a first well region
- the second select transistor and the second floating gate transistor are constructed in a second well region.
- the first well region and the second well region have different types.
- the erasable programmable non-volatile memory includes a semiconductor layer, a first well region, a first doped region, a second doped region, a third doped region, a second well region, a fourth doped region, a fifth doped region, a sixth doped region, a select gate, a floating gate and an isolation structure.
- the first well region is formed in the semiconductor layer.
- the first doped region, the second doped region and the third doped region are formed in a surface of the first well region.
- the first doped region receives a first source line voltage.
- the third doped region receives a first bit line voltage.
- the second well region is formed in the semiconductor layer.
- the fourth doped region, the fifth doped region and the sixth doped region are formed in a surface of the second well region.
- the fourth doped region receives a second source line voltage.
- the sixth doped region receives a second bit line voltage.
- the select gate is spanned over an area between the first doped region and the second doped region and an area between the fourth doped region and the fifth doped region.
- the select gate receives a select gate voltage.
- the floating gate is spanned over an area between the second doped region and the third doped region and an area between the fifth doped region and the sixth doped region.
- the isolation structure is formed in the semiconductor layer and arranged between the first well region and the second well region.
- FIGS. 1A ⁇ 1 D (prior art) schematically illustrate the structure and the equivalent circuit of a conventional erasable programmable non-volatile memory
- FIG. 2A is a schematic top view illustrating an erasable programmable non-volatile memory according to a first embodiment of the present invention
- FIG. 2B is a schematic cross-sectional view illustrating the non-volatile memory as shown in FIG. 2A and taken along the dotted line a-b;
- FIG. 2C is a schematic equivalent circuit diagram of the erasable programmable non-volatile memory of FIG. 2A ;
- FIGS. 3A ⁇ 3 D schematically illustrate the bias voltages and the operations of the erasable programmable non-volatile memory according to the first embodiment of the present invention
- FIG. 4A is a schematic top view illustrating an erasable programmable non-volatile memory according to a second embodiment of the present invention.
- FIG. 4B is a schematic cross-sectional view illustrating the non-volatile memory as shown in FIG. 4A and taken along the dotted line c-d.
- FIG. 2A is a schematic top view illustrating an erasable programmable non-volatile memory according to a first embodiment of the present invention.
- FIG. 2B is a schematic cross-sectional view illustrating the non-volatile memory as shown in FIG. 2A and taken along the dotted line a-b.
- FIG. 2C is a schematic equivalent circuit diagram of the erasable programmable non-volatile memory of FIG. 2A .
- the erasable programmable non-volatile memory 20 comprises two serially-connected p-type transistors and two serially-connected n-type transistors. These two p-type transistors are constructed in an n-type well region (NW). The two serially-connected n-type transistors are constructed in a p-type well region (PW). The n-type well region (NW) and the p-type well region (PW) are separated from each other by an isolation structure 29 .
- the isolation structure 29 is a shallow trench isolation (STI) structure.
- the isolation structure 29 , the n-type well region (NW) and the p-type well region (PW) are formed in a p-type substrate (p_sub).
- the isolation structure 29 , the n-type well region (NW) and the p-type well region (PW) are formed in another semiconductor layer such as an n-type substrate, an n-type buried layer (NBL) or a deep n-well (DNW) region.
- Three p-type doped regions 21 , 22 and 23 are formed in the n-type well region (NW).
- a polysilicon gate SG is spanned over the area between the p-type doped regions 21 and 22
- a polysilicon gate FG is spanned over the area between the p-type doped regions 22 and 23 .
- the first p-type transistor is used as a first select transistor, and the polysilicon gate SG (also referred as a select gate) of the first p-type transistor is connected to a select gate voltage V SG .
- the p-type doped region 21 is connected to a first source line voltage V SL1 .
- the p-type doped region 22 is a combination of a p-type doped drain region of the first p-type transistor and a p-type doped region of the second p-type transistor.
- the second p-type transistor is used as a first floating gate transistor.
- the polysilicon gate FG (also referred as a floating gate) is disposed over the second p-type transistor.
- the p-type doped region 23 is connected to a first bit line voltage V BL1 .
- the n-type well region (NW) is connected to an n-well voltage V NW .
- n-type doped regions 25 , 26 and 27 are formed in the p-type well region (PW).
- PW p-type well region
- two polysilicon gates SG and FG are spanned over the areas between the three n-type doped regions 25 , 26 and 27 .
- the first n-type transistor is used as a second select transistor, and the polysilicon gate SG (also referred as a select gate) of the second n-type transistor is connected to the select gate voltage V SG .
- the n-type doped region 25 is connected to a second source line voltage V SL2 .
- the n-type doped region 26 is a combination of an n-type doped drain region of the first n-type transistor and an n-type doped region of the second n-type transistor.
- the second n-type transistor is used as a second floating gate transistor.
- the polysilicon gate FG i.e., the floating gate
- the n-type doped region 27 is connected to a second bit line voltage V BL2 .
- the p-type well region (PW) is connected to a p-well voltage V PW .
- the select gate SG of the first select transistor and the select gate SG of the second select transistor are formed of the same polysilicon gate. That is, the select gate SG of the first select transistor and the select gate SG of the second select transistor are connected with each other.
- the floating gate FG of the first floating gate transistor and the floating gate FG of the second floating gate transistor are formed of the same polysilicon gate. That is, the floating gate FG of the first floating gate transistor and the floating gate FG of the second floating gate transistor are connected with each other.
- the channel length L 1 of the first floating gate transistor is smaller than the channel length L 2 of the second floating gate transistor
- the channel width w 1 of the first floating gate transistor is smaller than the channel width w 2 of the second floating gate transistor.
- the erasable programmable non-volatile memory 20 comprises a first select transistor, a second select transistor, a first floating gate transistor and a second floating gate transistor. That is, the four transistors constitute a memory cell of the erasable programmable non-volatile memory 20 .
- the memory cell is connected with two bit lines, two source lines and two select lines connected with each other (i.e., the select gate SG of the first select transistor and the select gate SG of the second select transistor are connected with each other).
- the first select transistor and the first floating gate transistor are p-type transistors and constructed in the n-type well region (NW).
- the n-type well region (NW) receives the n-well voltage V NW .
- the second select transistor and the second floating gate transistor are n-type transistors and constructed in the p-type well region (PW).
- the p-type well region (PW) receives the p-well voltage V PW .
- the select gate SG of the first select transistor receives the select gate voltage V SG .
- the first source/drain terminal of the first select transistor receives the first source line voltage V SL1 .
- the first source/drain terminal of the first floating gate transistor is connected with the second source/drain terminal of the first select transistor.
- the second source/drain terminal of the first floating gate transistor receives the first bit line voltage V BL1 .
- the select gate SG of the second select transistor receives the select gate voltage V SG .
- the first source/drain terminal of the second select transistor receives the second source line voltage V SL2 .
- the first source/drain terminal of the second floating gate transistor is connected with the second source/drain terminal of the second select transistor.
- the second source/drain terminal of the second floating gate transistor receives the second bit line voltage V BL2 .
- the first select transistor and the first floating gate transistor are activated. Consequently, hot carriers (e.g. electrons) are transferred through a channel region of the first floating gate transistor and injected into the floating gate FG.
- hot carriers e.g. electrons
- the first select transistor and the first floating gate transistor are activated. Consequently, the electrons are ejected from the floating gate FG through the channel region of the first floating gate transistor.
- the second select transistor and the second floating gate transistor are activated. According to the amount of electrons in the floating gate FG, the second floating gate transistor generates a read current. According to the magnitude of the read current, the storage state of the non-volatile memory 20 is determined.
- FIGS. 3A ⁇ 3 D schematically illustrate the bias voltages and the operations of the erasable programmable non-volatile memory according to the first embodiment of the present invention.
- the program cycle is divided into two time periods.
- the program cycle needs 50 ⁇ s
- the first time period (or an earlier stage) of the program cycle is 20 ⁇ s
- the second time period (or a later stage) of the program cycle is 30 ⁇ s.
- the select gate voltage V SG , the second source line voltage V SL2 , the second bit line voltage V BL2 and the p-well voltage V PW are all 0V. Consequently, the second select transistor is turned off.
- the select gate voltage V SG is 0V
- the first source line voltage V SL1 is 5V
- the first bit line voltage V BL1 is ⁇ 2V
- the n-well voltage V NW is 5V.
- the first select transistor is turned on, and a program current Ipgm flows through the first select transistor. Consequently, electrons are injected into the floating gate FG through the channel region of the first floating gate transistor.
- the second source line voltage V SL2 , the second bit line voltage V BL2 and the p-well voltage V PW are all increased to 5V while the select gate voltage V SG is 0V. Consequently, the floating gate FG of the second floating gate transistor is coupled to have the voltage of about 5V. Under this circumstance, more electrons are injected into the floating gate FG of the first floating gate transistor. Consequently, the program efficiency of the non-volatile memory 20 is enhanced.
- the second source line voltage V SL2 , the second bit line voltage V BL2 and the p-well voltage V PW are all ⁇ 7.5V.
- the first source line voltage V SL1 , the first bit line voltage V BL1 and the n-well voltage V NW are all 7.5V while the select gate voltage V SG is 0V. Consequently, the first select transistor and the second select transistor are turned off.
- the floating gate FG of the second floating gate transistor is coupled to have the voltage of about ⁇ 7.5V and both of the first bit line voltage V BL1 and the n-well voltage V NW are 7.5V, a voltage difference between the floating gate FG of the first floating gate transistor and the n-well voltage V NW is 15V. Consequently, the electrons are ejected from the floating gate FG of the first floating gate transistor to the n-type well region (NW).
- the select gate voltage V SG , the first source line voltage V SL1 , the first bit line voltage V BL1 and the n-well voltage V NW are all 2.5V. Consequently, the first select transistor is turned off.
- the select gate voltage V SG is 2.5V
- the second source line voltage V SL2 is 0V
- the second bit line voltage V BL2 is 2.5V
- the p-well voltage V PW is 0V. Consequently, the second select transistor is turned on, and the second floating gate transistor generates a read current Iread.
- the magnitude of the read current Iread is determined according to the amount of electrons stored in the floating gate FG of the second floating gate transistor. For example, in case that electrons are stored in the floating gate FG of the second floating gate transistor, the second floating gate transistor is turned off and the magnitude of the generated read current Iread is very low (e.g., nearly zero). Whereas, in case that no electrons are stored in the floating gate FG of the second floating gate transistor, the second floating gate transistor is turned on and the magnitude of the generated read current Iread is higher. Consequently, the storage state of the non-volatile memory 20 is determined according to the magnitude of the read current Iread.
- the channel length L 1 of the first floating gate transistor is smaller than the channel length L 2 of the second floating gate transistor, and the channel width w 1 of the first floating gate transistor is smaller than the channel width w 2 of the second floating gate transistor. Consequently, the program efficiency of the first floating gate transistor is enhanced, and the read efficiency of the second floating gate transistor is enhanced.
- the n-type well region (NW) and the p-type well region (PW) of the non-volatile memory 20 have high doping concentrations.
- the n-well voltage V NW is 7.5V and the p-well voltage V PW is ⁇ 7.5V. That is, the voltage difference between the n-type well region (NW) and the p-type well region (PW) is 15V. If the n-type well region (NW) and the p-type well region (PW) of the non-volatile memory 20 are in contact with each other, the junction breakdown voltage is not enough for sustaining during the erase action. Under this circumstance, a junction breakdown problem occurs.
- a wider isolation structure 29 is formed in the p-type substrate (p_sub) to separate the n-type well region (NW) from the p-type well region (PW).
- the width of the isolation structure 29 is larger than 1 ⁇ m. Because of the wider isolation structure 29 , after the n-type well region (NW) and the p-type well region (PW) are produced, the n-type well region (NW) and the p-type well region (PW) are not in contact with each other and separated from each other by the p-type substrate (p_sub). Consequently, the junction breakdown problem of the non-volatile memory 20 is avoided.
- the doping concentration of the p-type substrate (p_sub) is low, the junction breakdown voltage between the n-type well region (NW) and the p-type substrate (p_sub) is higher than conventional one. Consequently, during the erase cycle of the non-volatile memory 20 , the junction breakdown problem is avoided. However, since the wider isolation structure 29 is formed in the p-type substrate (p_sub), the memory cell of the non-volatile memory 20 has a larger area.
- FIG. 4A is a schematic top view illustrating an erasable programmable non-volatile memory according to a second embodiment of the present invention.
- FIG. 4B is a schematic cross-sectional view illustrating the non-volatile memory as shown in FIG. 4A and taken along the dotted line c-d.
- the bias voltages and the equivalent circuit of the non-volatile memory of this embodiment are similar to those of the first embodiment, and are not redundantly described herein.
- the structures of the well regions of the second embodiment are distinguished.
- the n-type well region comprises plural n-type sub-well regions
- the p-type well region comprises plural p-type sub-well regions.
- the n-type well region comprises three n-type sub-well regions NW 1 ⁇ NW 3
- the p-type well region comprises three p-type sub-well regions PW 1 ⁇ PW 3 .
- the n-type well region may comprise two n-type sub-well regions or more than three n-type sub-well regions
- the p-type well region may comprise two p-type sub-well regions or more than three p-type sub-well regions.
- the erasable programmable non-volatile memory 40 comprises two serially-connected p-type transistors and two serially-connected n-type transistors. These two p-type transistors are constructed in the first n-type sub-well region (NW 1 ). The two serially-connected n-type transistors are constructed in a first p-type sub-well region (PW 1 ). The first n-type sub-well region (NW 1 ) and the first p-type sub-well region (PW 1 ) are separated from each other by an isolation structure 49 .
- the second n-type sub-well region (NW 2 ) and the second p-type sub-well region (PW 2 ) are also separated from each other by the isolation structure 49 .
- the third n-type sub-well region (NW 3 ) and the third p-type sub-well region (PW 3 ) are in direct contact with each other.
- the isolation structure 49 is a shallow trench isolation (STI) structure.
- the isolation structure 49 , the n-type well region and the p-type well region are formed in a p-type substrate (p_sub).
- the isolation structure 49 , the n-type well region and the p-type well region are formed in another semiconductor layer such as an n-type substrate, an n-type buried layer (NBL) or a deep n-well (DNW) region.
- NBL n-type buried layer
- DNS deep n-well
- Three p-type doped regions 41 , 42 and 43 are formed in the first n-type sub-well region (NW 1 ).
- a polysilicon gate SG is spanned over the area between the p-type doped regions 41 and 42
- a polysilicon gate FG is spanned over the area between the p-type doped regions 42 and 43 .
- the first p-type transistor is used as a first select transistor
- the polysilicon gate SG (also referred as a select gate) of the first p-type transistor is connected to a select gate voltage V SG .
- the p-type doped region 41 is connected to a first source line voltage V SL1 .
- the p-type doped region 42 is a combination of a p-type doped drain region of the first p-type transistor and a p-type doped region of the second p-type transistor.
- the second p-type transistor is used as a first floating gate transistor.
- the polysilicon gate FG (also referred as a floating gate) is disposed over the second p-type transistor.
- the p-type doped region 43 is connected to a first bit line voltage V BL1 .
- the n-type well region is connected to an n-well voltage V NW .
- n-type doped regions 45 , 46 and 47 are formed in the first p-type sub-well region (PW 1 ).
- two polysilicon gates SG and FG are spanned over the areas between the three n-type doped regions 45 , 46 and 47 .
- the first n-type transistor is used as a second select transistor, and the polysilicon gate SG (also referred as a select gate) of the second n-type transistor is connected to the select gate voltage V SG .
- the n-type doped region 45 is connected to a second source line voltage V SL2 .
- the n-type doped region 46 is a combination of an n-type doped drain region of the first n-type transistor and an n-type doped region of the second n-type transistor.
- the second n-type transistor is used as a second floating gate transistor.
- the polysilicon gate FG i.e., the floating gate
- the n-type doped region 47 is connected to a second bit line voltage V BL2 .
- the p-type well region is connected to a p-well voltage V PW .
- the n-type well region in the p-type substrate (p_sub) comprises the first n-type sub-well region (NW 1 ), the second n-type sub-well region (NW 2 ) and the third n-type sub-well region (NW 3 ) sequentially.
- the n-type well region in the p-type substrate (p_sub) comprises the first p-type sub-well region (PW 1 ), the second p-type sub-well region (PW 2 ) and the third p-type sub-well region (PW 3 ) sequentially.
- the doping concentration of the second n-type sub-well region (NW 2 ) is higher than the doping concentration of the third n-type sub-well region (NW 3 ).
- the doping concentration of the second p-type sub-well region (PW 2 ) is higher than the doping concentration of the third p-type sub-well region (PW 3 ).
- the junction breakdown voltage between the third n-type sub-well region (NW 3 ) and the third p-type sub-well region (PW 3 ) is very high. Consequently, during the erase cycle, the junction breakdown problem of the non-volatile memory 40 is not generated.
- the isolation structure 49 in the p-type substrate (p_sub) may be narrower.
- the width of the isolation structure 49 is smaller than 0.5 ⁇ m.
- the doping concentration of the second n-type sub-well region (NW 2 ) is higher than the doping concentration of the third n-type sub-well region (NW 3 ), and the doping concentration of the second p-type sub-well region (PW 2 ) is higher than the doping concentration of the third p-type sub-well region (PW 3 ). Consequently, the punch through effect between the third n-type sub-well region (NW 3 ) to n-type doped regions 45 , 46 , and 47 is not generated during the erase cycle.
- the isolation structure 49 of the non-volatile memory 40 is narrower, the area of the memory cell can be effectively reduced.
- the threshold voltage of the first select transistor is determined according to the doping concentration of the first n-type sub-well region (NW 1 ), and the threshold voltage of the second select transistor is determined according to the doping concentration of the first p-type sub-well region (PW 1 ). Consequently, the doping concentration of the first n-type sub-well region (NW 1 ) and the doping concentration of the first p-type sub-well region (PW 1 ) are not restricted.
- the doping concentration of the first n-type sub-well region (NW 1 ) and the doping concentration of the first p-type sub-well region (PW 1 ) may be determined according to the practical requirements.
- the p-type select transistor and the p-type floating gate transistor are responsible for the program action and the erase action, and the n-type select transistor and the n-type floating gate transistor are responsible for the read action. It is noted that numerous modifications and alterations may be made while retaining the teachings of the invention.
- the n-type select transistor and the n-type floating gate transistor constructed in the p-type well region are responsible for the program action and the erase action, and the p-type select transistor and the p-type floating gate transistor constructed in the n-type well region are responsible for the read action.
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Abstract
Description
- This application claims the benefit of U.S. provisional application Ser. No. 62/690,894, filed Jun. 27, 2018, the subject matter of which is incorporated herein by reference.
- The present invention relates to a non-volatile memory, and more particularly to an erasable programmable non-volatile memory.
-
FIGS. 1A ˜1D schematically illustrate the structure and the equivalent circuit of a conventional erasable programmable non-volatile memory. For example, the conventional erasable programmable non-volatile memory is disclosed in U.S. Pat. No. 8,941,167.FIG. 1A is a schematic top view of a conventional non-volatile memory.FIG. 1B is a schematic cross-sectional view illustrating the conventional non-volatile memory ofFIG. 1A and taken along a first direction (a1-a2).FIG. 1C is a schematic cross-sectional view illustrating the non-volatile memory ofFIG. 1A and taken along a second direction (b1-b2).FIG. 1D is a schematic equivalent circuit diagram of the conventional non-volatile memory. - As shown in
FIGS. 1A and 1B , the conventional non-volatile memory comprises two serially-connected p-type transistors. These two p-type transistors are constructed in an n-type well region (NW). Three p-type dopedregions polysilicon gates regions - The first p-type transistor is used as a select transistor, and the polysilicon gate 34 (also referred as a select gate) of the first p-type transistor is connected to a select gate voltage VSG. The p-type doped
region 31 is connected to a source line voltage VSL. The p-type dopedregion 32 is a combination of a p-type doped drain region of the first p-type transistor and a p-type doped region of the second p-type transistor. The second p-type transistor is a floating gate transistor. The polysilicon gate 36 (also referred as a floating gate) is disposed over the second p-type transistor. The p-type dopedregion 33 is connected to a bit line voltage VBL. Moreover, the n-type well region (NW) is connected to an n-well voltage VNW. - As shown in
FIGS. 1A and 1C , the conventional non-volatile memory further comprises an n-type transistor. The n-type transistor is composed of thefloating gate 36 and anerase gate region 35. The n-type transistor is constructed in a p-type well region (PW). An n-type dopedregion 38 is formed in the p-type well region (PW). That is, theerase gate region 35 contains the p-type well region (PW) and the n-type dopedregion 38. - As shown in
FIG. 1A , thefloating gate 36 is extended externally and located near theerase gate region 35. Consequently, thefloating gate 36 is also the gate terminal of the n-type transistor. Moreover, the n-type dopedregion 38 may be considered as a combination of an n-type doped source region and an n-type doped drain region. The n-type dopedregion 38 is connected to an erase line voltage VEL. In addition, the p-type well region (PW) is connected to a p-well voltage VPW. As shown inFIG. 1C , theerase gate region 35 and the n-type well region (NW) are isolated from each other by a shallow trench isolation (STI)structure 39. - As shown in the equivalent circuit of
FIG. 1D , the non-volatile memory comprises a select transistor, a floating gate transistor and an n-type transistor. The select transistor and the floating gate transistor are p-type transistors and constructed in the n-type well region (NW). The n-type well region (NW) receives the n-well voltage VNW. The n-type transistor is constructed in the p-type well region (PW). In addition, the p-type well region (PW) receives the p-well voltage VPW. - The select gate of the select transistor receives the select gate voltage VSG. The first source/drain terminal of the select transistor receives the source line voltage VSL. The first source/drain terminal of the floating gate transistor is connected with the second source/drain terminal of the select transistor. The second source/drain terminal of the floating gate transistor receives the bit line voltage VBL. The gate terminal of the n-type transistor and the floating gate of the floating gate transistor are connected with each other. The first source/drain terminal of the n-type transistor and the second source/drain terminal of the n-type transistor are connected with each other to receive the erase line voltage VEL.
- The present invention provides an erasable programmable non-volatile memory with a novel structure.
- An embodiment of the present invention provides an erasable programmable non-volatile memory. The erasable programmable non-volatile memory includes a first select transistor, a first floating gate transistor, a second select transistor and a second floating gate transistor. The first select transistor includes a select gate, a first source/drain terminal and a second source/drain terminal. The select gate of the first select transistor receives a select gate voltage. The first source/drain terminal of the first select transistor receives a first source line voltage. The first floating gate transistor includes a floating gate, a first source/drain terminal and a second source/drain terminal. The first source/drain terminal of the first floating gate transistor is connected with the second source/drain terminal of the first select transistor. The second source/drain terminal of the first floating gate transistor receives a first bit line voltage. The second select transistor includes the select gate, a first source/drain terminal and a second source/drain terminal. The first source/drain terminal of the second select transistor receives a second source line voltage. The second floating gate transistor includes the floating gate, a first source/drain terminal and a second source/drain terminal. The first source/drain terminal of the second floating gate transistor is connected with the second source/drain terminal of the second select transistor. The second source/drain terminal of the second floating gate transistor receives a second bit line voltage. The first select transistor and the first floating gate transistor are constructed in a first well region, the second select transistor and the second floating gate transistor are constructed in a second well region. The first well region and the second well region have different types.
- Another embodiment of the present invention provides an erasable programmable non-volatile memory. The erasable programmable non-volatile memory includes a semiconductor layer, a first well region, a first doped region, a second doped region, a third doped region, a second well region, a fourth doped region, a fifth doped region, a sixth doped region, a select gate, a floating gate and an isolation structure. The first well region is formed in the semiconductor layer. The first doped region, the second doped region and the third doped region are formed in a surface of the first well region. The first doped region receives a first source line voltage. The third doped region receives a first bit line voltage. The second well region is formed in the semiconductor layer. The fourth doped region, the fifth doped region and the sixth doped region are formed in a surface of the second well region. The fourth doped region receives a second source line voltage. The sixth doped region receives a second bit line voltage. The select gate is spanned over an area between the first doped region and the second doped region and an area between the fourth doped region and the fifth doped region. The select gate receives a select gate voltage. The floating gate is spanned over an area between the second doped region and the third doped region and an area between the fifth doped region and the sixth doped region. The isolation structure is formed in the semiconductor layer and arranged between the first well region and the second well region.
- Numerous objects, features and advantages of the present invention will be readily apparent upon a reading of the following detailed description of embodiments of the present invention when taken in conjunction with the accompanying drawings. However, the drawings employed herein are for the purpose of descriptions and should not be regarded as limiting.
- The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:
-
FIGS. 1A ˜1D (prior art) schematically illustrate the structure and the equivalent circuit of a conventional erasable programmable non-volatile memory; -
FIG. 2A is a schematic top view illustrating an erasable programmable non-volatile memory according to a first embodiment of the present invention; -
FIG. 2B is a schematic cross-sectional view illustrating the non-volatile memory as shown inFIG. 2A and taken along the dotted line a-b; -
FIG. 2C is a schematic equivalent circuit diagram of the erasable programmable non-volatile memory ofFIG. 2A ; -
FIGS. 3A ˜3D schematically illustrate the bias voltages and the operations of the erasable programmable non-volatile memory according to the first embodiment of the present invention; -
FIG. 4A is a schematic top view illustrating an erasable programmable non-volatile memory according to a second embodiment of the present invention; and -
FIG. 4B is a schematic cross-sectional view illustrating the non-volatile memory as shown inFIG. 4A and taken along the dotted line c-d. -
FIG. 2A is a schematic top view illustrating an erasable programmable non-volatile memory according to a first embodiment of the present invention.FIG. 2B is a schematic cross-sectional view illustrating the non-volatile memory as shown inFIG. 2A and taken along the dotted line a-b.FIG. 2C is a schematic equivalent circuit diagram of the erasable programmable non-volatile memory ofFIG. 2A . - As shown in
FIGS. 2A and 2B , the erasable programmablenon-volatile memory 20 comprises two serially-connected p-type transistors and two serially-connected n-type transistors. These two p-type transistors are constructed in an n-type well region (NW). The two serially-connected n-type transistors are constructed in a p-type well region (PW). The n-type well region (NW) and the p-type well region (PW) are separated from each other by anisolation structure 29. For example, theisolation structure 29 is a shallow trench isolation (STI) structure. In this embodiment, theisolation structure 29, the n-type well region (NW) and the p-type well region (PW) are formed in a p-type substrate (p_sub). Alternatively, theisolation structure 29, the n-type well region (NW) and the p-type well region (PW) are formed in another semiconductor layer such as an n-type substrate, an n-type buried layer (NBL) or a deep n-well (DNW) region. - Three p-type doped
regions regions regions region 21 is connected to a first source line voltage VSL1. The p-type dopedregion 22 is a combination of a p-type doped drain region of the first p-type transistor and a p-type doped region of the second p-type transistor. The second p-type transistor is used as a first floating gate transistor. The polysilicon gate FG (also referred as a floating gate) is disposed over the second p-type transistor. The p-type dopedregion 23 is connected to a first bit line voltage VBL1. Moreover, the n-type well region (NW) is connected to an n-well voltage VNW. - Three n-type doped
regions regions region 25 is connected to a second source line voltage VSL2. The n-type dopedregion 26 is a combination of an n-type doped drain region of the first n-type transistor and an n-type doped region of the second n-type transistor. The second n-type transistor is used as a second floating gate transistor. The polysilicon gate FG (i.e., the floating gate) is disposed over the second n-type transistor. The n-type dopedregion 27 is connected to a second bit line voltage VBL2. Moreover, the p-type well region (PW) is connected to a p-well voltage VPW. - In this embodiment, the select gate SG of the first select transistor and the select gate SG of the second select transistor are formed of the same polysilicon gate. That is, the select gate SG of the first select transistor and the select gate SG of the second select transistor are connected with each other. Moreover, the floating gate FG of the first floating gate transistor and the floating gate FG of the second floating gate transistor are formed of the same polysilicon gate. That is, the floating gate FG of the first floating gate transistor and the floating gate FG of the second floating gate transistor are connected with each other. Moreover, the channel length L1 of the first floating gate transistor is smaller than the channel length L2 of the second floating gate transistor, and the channel width w1 of the first floating gate transistor is smaller than the channel width w2 of the second floating gate transistor.
- As shown in the equivalent circuit of
FIG. 2C , the erasable programmablenon-volatile memory 20 comprises a first select transistor, a second select transistor, a first floating gate transistor and a second floating gate transistor. That is, the four transistors constitute a memory cell of the erasable programmablenon-volatile memory 20. The memory cell is connected with two bit lines, two source lines and two select lines connected with each other (i.e., the select gate SG of the first select transistor and the select gate SG of the second select transistor are connected with each other). - The first select transistor and the first floating gate transistor are p-type transistors and constructed in the n-type well region (NW). The n-type well region (NW) receives the n-well voltage VNW. The second select transistor and the second floating gate transistor are n-type transistors and constructed in the p-type well region (PW). In addition, the p-type well region (PW) receives the p-well voltage VPW.
- The select gate SG of the first select transistor receives the select gate voltage VSG. The first source/drain terminal of the first select transistor receives the first source line voltage VSL1. The first source/drain terminal of the first floating gate transistor is connected with the second source/drain terminal of the first select transistor. The second source/drain terminal of the first floating gate transistor receives the first bit line voltage VBL1.
- The select gate SG of the second select transistor receives the select gate voltage VSG. The first source/drain terminal of the second select transistor receives the second source line voltage VSL2. The first source/drain terminal of the second floating gate transistor is connected with the second source/drain terminal of the second select transistor. The second source/drain terminal of the second floating gate transistor receives the second bit line voltage VBL2.
- The operations of the erasable programmable
non-volatile memory 20 will be described as follows. - During a program cycle of the
non-volatile memory 20, the first select transistor and the first floating gate transistor are activated. Consequently, hot carriers (e.g. electrons) are transferred through a channel region of the first floating gate transistor and injected into the floating gate FG. - During an erase cycle of the
non-volatile memory 20, the first select transistor and the first floating gate transistor are activated. Consequently, the electrons are ejected from the floating gate FG through the channel region of the first floating gate transistor. - In a read cycle of the
non-volatile memory 20, the second select transistor and the second floating gate transistor are activated. According to the amount of electrons in the floating gate FG, the second floating gate transistor generates a read current. According to the magnitude of the read current, the storage state of thenon-volatile memory 20 is determined. -
FIGS. 3A ˜3D schematically illustrate the bias voltages and the operations of the erasable programmable non-volatile memory according to the first embodiment of the present invention. - As shown in
FIGS. 3A and 3B , the program cycle is divided into two time periods. For example, the program cycle needs 50 μs, the first time period (or an earlier stage) of the program cycle is 20 μs, and the second time period (or a later stage) of the program cycle is 30 μs. - In the earlier stage of the program cycle, the select gate voltage VSG, the second source line voltage VSL2, the second bit line voltage VBL2 and the p-well voltage VPW are all 0V. Consequently, the second select transistor is turned off. Moreover, the select gate voltage VSG is 0V, the first source line voltage VSL1 is 5V, the first bit line voltage VBL1 is −2V, and the n-well voltage VNW is 5V. In this situation, the first select transistor is turned on, and a program current Ipgm flows through the first select transistor. Consequently, electrons are injected into the floating gate FG through the channel region of the first floating gate transistor.
- In the later stage of the program cycle, the second source line voltage VSL2, the second bit line voltage VBL2 and the p-well voltage VPW are all increased to 5V while the select gate voltage VSG is 0V. Consequently, the floating gate FG of the second floating gate transistor is coupled to have the voltage of about 5V. Under this circumstance, more electrons are injected into the floating gate FG of the first floating gate transistor. Consequently, the program efficiency of the
non-volatile memory 20 is enhanced. - Please refer to
FIGS. 3A and 3C . During the erase cycle, the second source line voltage VSL2, the second bit line voltage VBL2 and the p-well voltage VPW are all −7.5V. In addition, the first source line voltage VSL1, the first bit line voltage VBL1 and the n-well voltage VNW are all 7.5V while the select gate voltage VSG is 0V. Consequently, the first select transistor and the second select transistor are turned off. - Since the floating gate FG of the second floating gate transistor is coupled to have the voltage of about −7.5V and both of the first bit line voltage VBL1 and the n-well voltage VNW are 7.5V, a voltage difference between the floating gate FG of the first floating gate transistor and the n-well voltage VNW is 15V. Consequently, the electrons are ejected from the floating gate FG of the first floating gate transistor to the n-type well region (NW).
- Please refer to
FIGS. 3A and 3D . During the read cycle, the select gate voltage VSG, the first source line voltage VSL1, the first bit line voltage VBL1 and the n-well voltage VNW are all 2.5V. Consequently, the first select transistor is turned off. In addition, the select gate voltage VSG is 2.5V, the second source line voltage VSL2 is 0V, the second bit line voltage VBL2 is 2.5V, and the p-well voltage VPW is 0V. Consequently, the second select transistor is turned on, and the second floating gate transistor generates a read current Iread. - Generally, the magnitude of the read current Iread is determined according to the amount of electrons stored in the floating gate FG of the second floating gate transistor. For example, in case that electrons are stored in the floating gate FG of the second floating gate transistor, the second floating gate transistor is turned off and the magnitude of the generated read current Iread is very low (e.g., nearly zero). Whereas, in case that no electrons are stored in the floating gate FG of the second floating gate transistor, the second floating gate transistor is turned on and the magnitude of the generated read current Iread is higher. Consequently, the storage state of the
non-volatile memory 20 is determined according to the magnitude of the read current Iread. - As mentioned above, the channel length L1 of the first floating gate transistor is smaller than the channel length L2 of the second floating gate transistor, and the channel width w1 of the first floating gate transistor is smaller than the channel width w2 of the second floating gate transistor. Consequently, the program efficiency of the first floating gate transistor is enhanced, and the read efficiency of the second floating gate transistor is enhanced.
- Generally, the n-type well region (NW) and the p-type well region (PW) of the
non-volatile memory 20 have high doping concentrations. During the erase cycle of thenon-volatile memory 20, the n-well voltage VNW is 7.5V and the p-well voltage VPW is −7.5V. That is, the voltage difference between the n-type well region (NW) and the p-type well region (PW) is 15V. If the n-type well region (NW) and the p-type well region (PW) of thenon-volatile memory 20 are in contact with each other, the junction breakdown voltage is not enough for sustaining during the erase action. Under this circumstance, a junction breakdown problem occurs. - As shown in
FIG. 2B , awider isolation structure 29 is formed in the p-type substrate (p_sub) to separate the n-type well region (NW) from the p-type well region (PW). For example, the width of theisolation structure 29 is larger than 1 μm. Because of thewider isolation structure 29, after the n-type well region (NW) and the p-type well region (PW) are produced, the n-type well region (NW) and the p-type well region (PW) are not in contact with each other and separated from each other by the p-type substrate (p_sub). Consequently, the junction breakdown problem of thenon-volatile memory 20 is avoided. - Since the doping concentration of the p-type substrate (p_sub) is low, the junction breakdown voltage between the n-type well region (NW) and the p-type substrate (p_sub) is higher than conventional one. Consequently, during the erase cycle of the
non-volatile memory 20, the junction breakdown problem is avoided. However, since thewider isolation structure 29 is formed in the p-type substrate (p_sub), the memory cell of thenon-volatile memory 20 has a larger area. -
FIG. 4A is a schematic top view illustrating an erasable programmable non-volatile memory according to a second embodiment of the present invention.FIG. 4B is a schematic cross-sectional view illustrating the non-volatile memory as shown inFIG. 4A and taken along the dotted line c-d. The bias voltages and the equivalent circuit of the non-volatile memory of this embodiment are similar to those of the first embodiment, and are not redundantly described herein. - In comparison with the first embodiment, the structures of the well regions of the second embodiment are distinguished. In this embodiment, the n-type well region comprises plural n-type sub-well regions, and the p-type well region comprises plural p-type sub-well regions. For example, the n-type well region comprises three n-type sub-well regions NW1˜NW3, and the p-type well region comprises three p-type sub-well regions PW1˜PW3. In other embodiments, the n-type well region may comprise two n-type sub-well regions or more than three n-type sub-well regions, and the p-type well region may comprise two p-type sub-well regions or more than three p-type sub-well regions.
- As shown in
FIGS. 4A and 4B , the erasable programmablenon-volatile memory 40 comprises two serially-connected p-type transistors and two serially-connected n-type transistors. These two p-type transistors are constructed in the first n-type sub-well region (NW1). The two serially-connected n-type transistors are constructed in a first p-type sub-well region (PW1). The first n-type sub-well region (NW1) and the first p-type sub-well region (PW1) are separated from each other by anisolation structure 49. The second n-type sub-well region (NW2) and the second p-type sub-well region (PW2) are also separated from each other by theisolation structure 49. The third n-type sub-well region (NW3) and the third p-type sub-well region (PW3) are in direct contact with each other. For example, theisolation structure 49 is a shallow trench isolation (STI) structure. In this embodiment, theisolation structure 49, the n-type well region and the p-type well region are formed in a p-type substrate (p_sub). Alternatively, theisolation structure 49, the n-type well region and the p-type well region are formed in another semiconductor layer such as an n-type substrate, an n-type buried layer (NBL) or a deep n-well (DNW) region. - Three p-type doped
regions regions regions region 41 is connected to a first source line voltage VSL1. The p-type dopedregion 42 is a combination of a p-type doped drain region of the first p-type transistor and a p-type doped region of the second p-type transistor. The second p-type transistor is used as a first floating gate transistor. The polysilicon gate FG (also referred as a floating gate) is disposed over the second p-type transistor. The p-type dopedregion 43 is connected to a first bit line voltage VBL1. Moreover, the n-type well region is connected to an n-well voltage VNW. - Three n-type doped
regions regions region 45 is connected to a second source line voltage VSL2. The n-type dopedregion 46 is a combination of an n-type doped drain region of the first n-type transistor and an n-type doped region of the second n-type transistor. The second n-type transistor is used as a second floating gate transistor. The polysilicon gate FG (i.e., the floating gate) is disposed over the second n-type transistor. The n-type dopedregion 47 is connected to a second bit line voltage VBL2. Moreover, the p-type well region is connected to a p-well voltage VPW. - During the formation of the well regions, plural ion implantation steps are performed according to different depths. Consequently, the plural n-type sub-well regions and the plural p-type sub-well regions are formed.
- Please refer to
FIG. 4B . From the shallower to the deeper, the n-type well region in the p-type substrate (p_sub) comprises the first n-type sub-well region (NW1), the second n-type sub-well region (NW2) and the third n-type sub-well region (NW3) sequentially. Similarly, from the shallower to the deeper, the n-type well region in the p-type substrate (p_sub) comprises the first p-type sub-well region (PW1), the second p-type sub-well region (PW2) and the third p-type sub-well region (PW3) sequentially. The doping concentration of the second n-type sub-well region (NW2) is higher than the doping concentration of the third n-type sub-well region (NW3). The doping concentration of the second p-type sub-well region (PW2) is higher than the doping concentration of the third p-type sub-well region (PW3). - Since the doping concentration of the third n-type sub-well region (NW3) and the doping concentration of the third p-type sub-well region (PW3) are low, the junction breakdown voltage between the third n-type sub-well region (NW3) and the third p-type sub-well region (PW3) is very high. Consequently, during the erase cycle, the junction breakdown problem of the
non-volatile memory 40 is not generated. - Since the
non-volatile memory 40 is not suffered from the junction breakdown problem, theisolation structure 49 in the p-type substrate (p_sub) may be narrower. For example, the width of theisolation structure 49 is smaller than 0.5 μm. After the n-type well region and the p-type well region are formed, the third n-type sub-well region (NW3) and the third p-type sub-well region (PW3) are in direct contact with each other and the junction breakdown problem of thenon-volatile memory 40 is avoided. - As mentioned above, the doping concentration of the second n-type sub-well region (NW2) is higher than the doping concentration of the third n-type sub-well region (NW3), and the doping concentration of the second p-type sub-well region (PW2) is higher than the doping concentration of the third p-type sub-well region (PW3). Consequently, the punch through effect between the third n-type sub-well region (NW3) to n-type doped
regions - Since the
isolation structure 49 of thenon-volatile memory 40 is narrower, the area of the memory cell can be effectively reduced. - Moreover, the threshold voltage of the first select transistor is determined according to the doping concentration of the first n-type sub-well region (NW1), and the threshold voltage of the second select transistor is determined according to the doping concentration of the first p-type sub-well region (PW1). Consequently, the doping concentration of the first n-type sub-well region (NW1) and the doping concentration of the first p-type sub-well region (PW1) are not restricted. The doping concentration of the first n-type sub-well region (NW1) and the doping concentration of the first p-type sub-well region (PW1) may be determined according to the practical requirements.
- In the above embodiments, the p-type select transistor and the p-type floating gate transistor are responsible for the program action and the erase action, and the n-type select transistor and the n-type floating gate transistor are responsible for the read action. It is noted that numerous modifications and alterations may be made while retaining the teachings of the invention. For example, in another embodiment, the n-type select transistor and the n-type floating gate transistor constructed in the p-type well region are responsible for the program action and the erase action, and the p-type select transistor and the p-type floating gate transistor constructed in the n-type well region are responsible for the read action.
- While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.
Claims (21)
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CN201910422754.9A CN110649102B (en) | 2018-06-27 | 2019-05-21 | Programmable erasable nonvolatile memory |
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US11189356B2 (en) * | 2020-02-27 | 2021-11-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | One-time-programmable memory |
US11139006B1 (en) * | 2020-03-12 | 2021-10-05 | Ememory Technology Inc. | Self-biased sense amplification circuit |
US11690221B2 (en) | 2020-08-14 | 2023-06-27 | Ememory Technology Inc. | Charge pump circuit capable of generating voltages in erasing operation, program operation and read operation |
TWI819457B (en) * | 2021-02-18 | 2023-10-21 | 力旺電子股份有限公司 | Memory cell array of multi-time programmable non-volatile memory |
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