CN108695337B - Programmable erasable non-volatile memory - Google Patents

Programmable erasable non-volatile memory Download PDF

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Publication number
CN108695337B
CN108695337B CN201710521061.6A CN201710521061A CN108695337B CN 108695337 B CN108695337 B CN 108695337B CN 201710521061 A CN201710521061 A CN 201710521061A CN 108695337 B CN108695337 B CN 108695337B
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floating gate
line
transistor
voltage
erase
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CN108695337A (en
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黎俊霄
陈纬仁
陈学威
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eMemory Technology Inc
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eMemory Technology Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/60—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell

Abstract

The invention discloses a programmable erasable nonvolatile memory, comprising: a first transistor, a second transistor, an erasing gate region and a metal layer. The first transistor includes: a select gate, a first doped region and a second doped region. The select gate is connected to a word line. The first doped region is connected to a source line. The second transistor includes: the second doped region, a third doped region and a floating gate. The third doped region is connected to a bit line. The erase gate region is connected to an erase line. The floating gate extends to the upper part of the erasing gate region and is adjacent to the erasing gate region. A metal layer is over the floating gate and connected to the bit line.

Description

Programmable erasable non-volatile memory
Technical Field
The present invention relates to non-volatile memories, and more particularly to programmable and erasable non-volatile memories.
Background
Referring to fig. 1A to 1D, a conventional programmable and erasable nonvolatile memory is shown. Such programmable and erasable non-volatile memory is disclosed in US patent 8941167. FIG. 1A is a top view of a programmable erasable non-volatile memory; FIG. 1B is a first direction (a1a2 direction) cross-sectional view of a programmable erasable nonvolatile memory; FIG. 1C is a second direction (b1b2 direction) cross-sectional view of the programmable erasable nonvolatile memory; FIG. 1D is an equivalent circuit diagram of a programmable erasable nonvolatile memory.
As shown in fig. 1A and 1B, the conventional programmable/erasable nonvolatile memory includes two serially connected p-type transistors fabricated in an N-well (NW). The N-well NW includes three p-type doped regions 31, 32, 33, and two gates 34, 36 made of polysilicon (polysilicon) are disposed above the surface between the three p-type doped regions 31, 32, 33.
The first p-type transistor is used as a select transistor with the select gate 34 connected to a select gate Voltage (VSG) and the p-doped region 31 connected to the source line Voltage (VSL). Furthermore, the p-type doped region 32 can be regarded as a p-type drain doped region of the first p-type transistor and a p-type doped region of the second p-type transistor connected to each other. The second p-type transistor is a floating gate transistor that includes a floating gate 36 above it, and the p-doped region 33 is connected to the bit line Voltage (VBL). The N Well (NW) is connected to an N well Voltage (VNW).
As shown in fig. 1A and fig. 1C, the conventional programmable and erasable nonvolatile memory further includes an n-type transistor, or an element formed by combining a floating gate 36 and an erase gate region 35. The n-type transistor is fabricated in a P-type well (PW). An n-doped region 38 is included in the P-well region (PW). In other words, the erase gate region 35 includes a P-well (PW) and an n-doped region 38.
As shown in FIG. 1A, the floating gate 36 extends outward and is adjacent to the erase gate region 35. Thus, the floating gate 36 may be considered to be the gate of an n-type transistor, while the n-doped region 38 may be considered to be an interconnection of an n-type source doped region and an n-type drain doped region. Furthermore, the n-type doped region 38 is connected to an erase line Voltage (VEL). The P Well (PW) is connected to a P well Voltage (VPW). Furthermore, as shown in FIG. 1C, the erase gate region 35 and the N-well (NW) are separated by a Shallow Trench Isolation (STI) 39.
The operation principle of the conventional programmable and erasable nonvolatile memory is described as follows.
During programming, appropriate bias voltages are provided to the respective terminals. When electrons (otherwise known as hot carriers) are caused to pass through the corresponding channel region of the floating gate transistor, the electrons are injected into the floating gate 36 and stored in the floating gate 36 to complete the programming operation.
During an erase operation, electrons stored on the floating gate 36 are removed from the floating gate 36 and leave the nonvolatile memory through the n-type doped region 38 after appropriate biasing of the terminals is provided. Thus, after the erase state, there will be no stored electrons in the floating gate 36.
During the read operation, each terminal is provided with an appropriate bias. Depending on whether there are any stored electrons on the floating gate 36, a different read current (IR) will be generated to flow to the bit line. That is, the storage state of the non-volatile memory can be known according to the magnitude of the read current (IR) during the read-like operation.
The conventional programmable erasable nonvolatile memory has a twin-well structure (twin-well structure), so the total design size of the conventional programmable erasable nonvolatile memory is large. During the programming operation, according to the channel electron injection (CHE) effect, electrons are injected into the floating gate 36 and stored in the floating gate 36 to complete the programming operation.
Disclosure of Invention
The invention aims to provide a programmable erasable nonvolatile memory with a completely new architecture. The programmable erasable nonvolatile memory of the invention is composed of n-type transistors. In addition, a program assisted metal layer (program assisted metal layer) is designed in the programmable erasable non-volatile memory and is positioned above the floating grid. During the programming operation, a bias voltage is provided on the programming auxiliary metal layer to increase electrons injected into the floating gate and effectively improve the programming capability.
The invention is a programmable erasable nonvolatile memory, comprising: a first transistor having a select gate connected to a word line, a first doped region connected to a source line and a second doped region; a second transistor having the second doped region, a third doped region connected to a bit line, and a floating gate; an erasing gate region connected to an erasing line, wherein the floating gate extends to above the erasing gate region and is adjacent to the erasing gate region; and a metal layer located above the floating gate and connected to the bit line.
The invention is a programmable erasable nonvolatile memory, comprising: a select transistor having a gate terminal connected to a word line, a first drain/source terminal connected to a source line, and a second drain/source terminal; a floating gate transistor having a first drain/source terminal connected to the second drain/source terminal of the select transistor, a second drain/source terminal connected to a bit line, and a floating gate; a first capacitor connected between the floating gate and an erase line; and a second capacitor connected between the floating gate and the bit line.
In order that the manner in which the above recited and other aspects of the present invention are obtained can be understood in detail, a more particular description of the invention, briefly summarized below, may be had by reference to the appended drawings, in which:
drawings
FIGS. 1A-1D are schematic diagrams of a conventional programmable and erasable nonvolatile memory;
FIGS. 2A-2H are schematic diagrams illustrating a process, an equivalent circuit and an operating bias voltage of the programmable erasable nonvolatile memory according to the present invention;
FIG. 3 is a diagram of another embodiment of the present invention.
Description of the symbols
31. 32, 33: p-type doped region
34: selection grid
35: erase gate region
36: floating gate
38: n-type doped region
39. 42: isolation structure
44. 46: grid oxide layer
SL: source line
WL: character line
BL1, BL 2: bit line
EL1, EL 2: erase line
Ms, Mf: transistor with a metal gate electrode
SG: selection grid
FG: floating gate
PAM: programming assist metal layer
Ct, Cp: capacitor with a capacitor element
n +: n-type doped region
PW: p-type well region
P-sub: p-type substrate
DNW: deep n-type well region
Detailed Description
Fig. 2A to fig. 2H are schematic diagrams illustrating a manufacturing process, an equivalent circuit and an operating bias voltage of the programmable and erasable nonvolatile memory according to the present invention. The manufacturing process is a process for manufacturing two memory cells, but the invention is not limited thereto.
FIG. 2A shows a shallow trench isolation structure and a well region formation step. First, after a Shallow Trench Isolation (STI) formation step is performed on a p-type substrate (p-substrate), an isolation structure 42 is formed on the surface of the p-type substrate (p-sub) to define an a region and a B region. In the following manufacturing process, two n-type transistors connected in series are formed in the region A, and an erase gate region is formed in the region B. Then, the B region is covered and a p-type well region forming step is performed. Thus, as shown in fig. 2A, a p-type well region (PW) is formed below the surface a region of the p-type substrate (p-sub).
Fig. 2B shows a gate structure forming step and a doped region forming step. First, two gate oxide layers 44 and 46 are formed on the surface of a p-type substrate (p-sub). Then, a polysilicon gate (polysilicon gate) FG, SG is formed to cover the two gate oxide layers 44, 46, so as to form two gate structures.
In fig. 2B, two gate structures divide the a-region surface area into three portions. And one of the gate structures extends outward and is adjacent to the B region. In addition, the polysilicon gate FG of the gate structure adjacent to the B region is a Floating Gate (FG). The polysilicon gate SG in the other gate structure is a Select Gate (SG) which can be used as a word line (word line).
As shown in fig. 2B, the p-type substrate is doped with two gate structures as masks. Therefore, three parts of the A region which are not covered by the two gate structures form three n-type doped regions n +; and the part of the B region which is not covered by the gate structure forms an n-type doped region n +.
In the region a, the n-type doped region n + at both sides of the select gate SG forms a select transistor (select transistor) with the select gate SG; the n-type doped regions n + on both sides of the floating gate FG form a floating gate transistor (floating gate transistor) with the floating gate FG. The floating gate transistor and the selection transistor are n-type transistors and are manufactured in the p-type well region PW, and the floating gate transistor and the selection transistor are connected in series.
Furthermore, the n + doped region in the region B is an erase gate region, and the floating gate FG extends outward and is adjacent to the erase gate region. Thus, the erase gate region and the floating gate FG are combined into a tunneling capacitor.
In fig. 2B, a first portion (a1) of the floating gate FG covers over area B and a second portion (a2) of the floating gate FG covers over area a, according to an embodiment of the present invention. The area ratio A1/A2 of the first portion (A1) to the second portion (A2) is approximately between 1/4 and 2/3, and better performance is obtained when the area ratio A1/A2 is equal to 3/7. The region a2 is the channel area (channel area) of the floating gate transistor.
Fig. 2C shows a metal layer formation step in a first direction. In the metal layer forming step in the first direction (X direction), source lines SL in the first direction are formed, and the source lines SL are connected to one n-type doped region n + of the selection transistor via the through holes.
In addition, in the metal layer forming step in the first direction, a metal island (metal island) is also formed as a program assisted metal layer (PAM). The programming auxiliary metal layer PAM is located above the floating gate FG, and an Interlayer dielectric (ILD) is disposed between the programming auxiliary metal layer PAM and the floating gate FG for separating the programming auxiliary metal layer PAM and the floating gate FG, so that the programming auxiliary metal layer PAM is not in contact with the floating gate FG. In addition, the program assist metal layer PAM is connected to an n-doped region n + of the floating gate transistor via a through hole. Furthermore, the program assistant metal layer PAM and the floating gate FG are combined to form a program assisted capacitor (program assisted capacitor).
According to a preferred embodiment of the present invention, the area of the program assist metal layer PAM is larger than the area of the floating gate FG, and the floating gate FG is completely covered by the program assist metal layer PAM.
As shown in fig. 2D, in a cross-sectional view along the ab-dashed line in the second direction (Y direction), the program assist metal layer PAM is located above the floating gate FG, and the source line SL is in contact with the n-type doped region n + via a through hole.
Fig. 2E shows a metal layer forming step in a second direction. In the metal layer forming step in the second direction (Y direction), the bit lines BL1, BL2 in the second direction are formed, and the bit lines BL1, BL2 contact the corresponding program assist metal layer PAM through the through holes and contact one n-type doped region n + of the floating gate transistor.
In addition, in the step of forming the metal layer in the second direction, erase lines (EL 1, EL2) in the second direction are formed, and the erase lines EL1, EL2 contact the corresponding n-type doped region n + through the through holes. That is, the erase lines EL1, EL2 contact the corresponding erase gate regions.
As shown in fig. 2F, in a cross-sectional view along the dashed line cd in the second direction (Y direction), the bit line BL1 contacts the program assist metal layer PAM through a through hole and contacts an n-type doped region n + of the floating gate transistor.
Furthermore, in the manufacturing process of another embodiment, the P-well (PW) may be enlarged such that the n + doped region under the a-region and the B-region is surrounded by the P-well (PW). In other words, in another embodiment, the floating gate transistor, the select transistor and the erase gate region are all constructed in a single P-well (PW). Thus, the memory cell size of the programmable erasable non-volatile memory of the present invention will be effectively reduced and will not be limited by the well area fabrication process rule of the semiconductor manufacturer.
FIG. 2G is an equivalent circuit of the programmable erasable nonvolatile memory of the present invention. The memory cells 1 and 2 have the same structure, and only the memory cell1 is described below.
The memory cell1 includes: a selection transistor Ms, a floating gate transistor Mf, a tunneling capacitor Ct and a programming auxiliary capacitor Cp. A first drain/source terminal of the selection transistor Ms is connected to a source line SL, and a selection gate SG is connected to a word line WL. The floating gate transistor Mf has a first drain/source terminal connected to the second drain/source terminal of the selection transistor Ms, and the second drain/source terminal connected to the bit line BL 1. The tunneling capacitor Ct is connected between the erase line EL1 and the floating gate FG of the floating gate transistor Mf. The program assist capacitor Cp is connected between the bit line BL1 and the floating gate FG of the floating gate transistor Mf.
FIG. 2H is a schematic diagram of the bias voltages during the program operation, erase operation and read operation of the programmable and erasable nonvolatile memory according to the present invention.
In the program operation (PGM), a ground voltage (0V) is applied to the p-well PW and the source line SL, a program voltage VPP is applied to the bit line BL and the erase line EL, and a turn-on voltage Von is applied to the word line WL. Wherein the programming voltage VPP is about 6-8V, and the turn-on voltage Von is about 0.5-1.5V.
Therefore, the selection transistor Ms is turned on, and a programming current (program current) is generated in the memory cell from the bit line BL to the source line SL through the floating gate transistor Mf and the selection transistor Ms. Furthermore, since the programming voltage VPP is supplied to the bit line BL and the erase line EL, when electrons (or called hot carriers) pass through the channel region (channel area) of the floating gate transistor Mf, the electrons are attracted and injected into the floating gate FG and stored in the floating gate FG according to the channel electron injection effect (CHE effect) to complete the programming operation.
During an erase operation (ERS), a ground voltage (0V) is applied to the p-well PW, the source line SL and the bit line BL, an erase voltage VEE is applied to the erase line EL, and an off voltage Voff is applied to the word line WL. The erase voltage VEE is about 12V, and the off-voltage Voff is about 0V.
Therefore, the selection transistor Ms is turned off. Electrons stored in the floating gate FG in the memory cell are ejected (project) from the floating gate FG by FN Tunneling, and leave the programmable and erasable nonvolatile memory cell through the penetrating capacitor Ct to the erase line EL. Therefore, after the erase state, there will be no stored electrons in the floating gate FG.
In the Read operation (Read), a ground voltage (0V) is applied to the p-well PW, the source line SL and the erase line EL, a Read voltage Vread is applied to the bit line BL, and a turn-on voltage Von is applied to the word line WL. Where the read voltage Vread is about 1V.
Therefore, the selection transistor Ms is turned on, and a read current (read current) generated in the memory cell flows from the bit line BL to the source line SL through the floating gate transistor Mf and the selection transistor Ms. Furthermore, the storage state of the programmable erasable nonvolatile memory can be known according to the magnitude of the reading current.
Referring to FIG. 3, another embodiment of the present invention is shown in a programmable erasable nonvolatile memory. The difference between FIG. 2E and the deep N-well (DNW) is that the detailed structure is not repeated. That is, in the non-volatile memory of this embodiment, the select transistor and the floating gate transistor are formed in the p-type well PW, and the deep n-type well DNW is included between the p-type well PW and the p-type substrate (p-sub).
Similarly, in the manufacturing process of other embodiments, the P-well (PW) may also be enlarged such that the n + doped region under the a region and the B region is surrounded by the P-well (PW). In other words, in other embodiments, the floating gate transistor, the select transistor and the erase gate region are all constructed in a single P-well (PW). Thus, the memory cell size of the programmable erasable non-volatile memory of the present invention will be effectively reduced and will not be limited by the well area fabrication process rule of the semiconductor manufacturer.
From the above description, the present invention provides a new architecture of programmable and erasable non-volatile memory. The select transistor and the floating gate transistor in the memory cell are composed of n-type transistors. Since the mobility of the memory cell of the present invention is higher than that of the memory cell of the p-type transistor, the memory cell of the present invention has a better margin. In addition, a programming auxiliary metal layer is further designed in the memory unit, and a programming auxiliary capacitor is formed by the programming auxiliary metal layer and the floating grid. During the programming operation, the bias voltage provided on the programming auxiliary metal layer can increase the number of electrons injected into the floating gate and effectively improve the programming capability.
In summary, although the present invention is disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the definition of the appended claims.

Claims (14)

1. A programmable erasable non-volatile memory comprising:
a first transistor having a select gate connected to a word line, a first doped region connected to a source line, and a second doped region;
a second transistor having the second doped region; a third doped region connected to a bit line; and a floating gate;
an erase gate region connected to an erase line, wherein the floating gate extends above the erase gate region; and
a metal layer located above the floating gate and between the floating gate and a bit line;
wherein the bit line contacts the metal layer and the third doped region through a via hole.
2. The non-volatile memory as claimed in claim 1, wherein the first transistor and the second transistor are n-type transistors, and the first doped region, the second doped region and the third doped region are n-type doped regions.
3. The non-volatile memory as claimed in claim 2, wherein the first n-type transistor and the second n-type transistor are formed in a p-type well region, and the p-type well region is located on a p-type substrate.
4. The non-volatile memory as claimed in claim 2, wherein the first n-type transistor and the second n-type transistor are formed in a p-type well region, and a deep n-type well region is included between the p-type well region and a p-type substrate.
5. The non-volatile memory of claim 3, wherein during a programming operation, a first voltage is applied to the p-well, the source line, a programming voltage is applied to the bit line and the erase line, and a turn-on voltage is applied to the word line to inject electrons into the floating gate.
6. The non-volatile memory as in claim 3, wherein during an erase operation, a first voltage is applied to the p-well, the source line and the bit line, an erase voltage is applied to the erase line, and a turn-off voltage is applied to the word line to cause electrons to exit the floating gate.
7. The non-volatile memory of claim 3, wherein during a read operation, a first voltage is applied to the p-well, the source line and the erase line, a read voltage is applied to the bit line, and a turn-on voltage is applied to the word line to cause a read current to flow to the source line.
8. The non-volatile memory of claim 1, wherein a first portion of the floating gate overlies the erase gate region, a second portion of the floating gate overlies a channel region of the second transistor, and a ratio of an area of the first portion to an area of the second portion is between 1/4 and 2/3.
9. The non-volatile memory as in claim 1, wherein the area of the metal layer is larger than the area of the floating gate.
10. A programmable erasable non-volatile memory comprising:
a selection transistor having a gate terminal connected to a word line, a first drain/source terminal connected to a source line, and a second drain/source terminal;
a floating gate transistor having a first drain/source terminal connected to the second drain/source terminal of the select transistor, a second drain/source terminal connected to a bit line, and a floating gate;
a first capacitor connected between the floating gate and an erase line; and
a metal layer;
the metal layer and the floating gate form a second capacitor, and the bit line contacts the metal layer and the second drain/source terminal of the floating gate transistor through a through hole.
11. The non-volatile memory of claim 10, wherein said select transistor and said floating gate transistor are both n-type transistors and are formed in a p-type well region.
12. The memory of claim 11, wherein during a programming operation, a first voltage is applied to the p-well, the source line, a programming voltage is applied to the bit line and the erase line, and a turn-on voltage is applied to the word line to inject electrons into the floating gate.
13. The memory of claim 11, wherein during an erase operation, a first voltage is applied to the p-well, the source line and the bit line, an erase voltage is applied to the erase line, and a turn-off voltage is applied to the word line to cause electrons to exit the floating gate.
14. The memory of claim 11, wherein during a read operation, a first voltage is applied to the p-well, the source line and the erase line, a read voltage is applied to the bit line, and a turn-on voltage is applied to the word line to cause a read current to flow to the source line.
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110007895B (en) * 2019-04-15 2021-08-06 恒烁半导体(合肥)股份有限公司 Analog multiplication circuit, analog multiplication method and application thereof
CN110008440B (en) * 2019-04-15 2021-07-27 恒烁半导体(合肥)股份有限公司 Convolution operation based on analog matrix operation unit and application thereof
US10763212B1 (en) * 2019-04-18 2020-09-01 Nanya Technology Corporation Semiconductor structure
US11521980B2 (en) * 2019-11-14 2022-12-06 Ememory Technology Inc. Read-only memory cell and associated memory cell array
US11139006B1 (en) * 2020-03-12 2021-10-05 Ememory Technology Inc. Self-biased sense amplification circuit

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5512505A (en) * 1990-12-18 1996-04-30 Sandisk Corporation Method of making dense vertical programmable read only memory cell structure
US6426893B1 (en) * 2000-02-17 2002-07-30 Sandisk Corporation Flash eeprom system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks
TW536818B (en) * 2002-05-03 2003-06-11 Ememory Technology Inc Single-poly EEPROM
US8344443B2 (en) * 2008-04-25 2013-01-01 Freescale Semiconductor, Inc. Single poly NVM devices and arrays
US8743591B2 (en) * 2011-04-26 2014-06-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor memory device and method for driving the same
US8384147B2 (en) * 2011-04-29 2013-02-26 Silicon Storage Technology, Inc. High endurance non-volatile memory cell and array
US9293468B2 (en) * 2012-11-30 2016-03-22 SK Hynix Inc. Nonvolatile memory device
TWI521683B (en) * 2013-05-13 2016-02-11 力旺電子股份有限公司 Erasable programmable single-poly nonvolatile memory
US9508396B2 (en) * 2014-04-02 2016-11-29 Ememory Technology Inc. Array structure of single-ploy nonvolatile memory

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