JP2014239137A - Erasable programmable single-poly nonvolatile memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electrically erasable programmable single-poly nonvolatile memory.SOLUTION: An erasable programmable single-poly nonvolatile memory includes: a floating gate transistor including a floating gate 36, a gate oxide layer under the floating gate 36, and a channel region formed in an N-well region; and an erase gate region adjacent to the floating gate 36 that is extended thereto and including an n-type source/drain region 38 connected to an erase line voltage and a P-well region PW. The N-well region NW and the P-well region PW are formed in the substrate structure, the gate oxide layer includes a first portion above the channel region of the floating gate 36 and a second portion above the erase gate region, and a thickness of the first portion of the gate oxide layer is different from that of the second portion of the gate oxide layer.

Description

  The present invention relates to non-volatile memory, and more particularly to an erasable programmable single poly non-volatile memory.

  FIG. 1 is a schematic cross-sectional view illustrating a conventional programmable dual poly nonvolatile memory. Programmable dual poly non-volatile memory is also referred to as a floating gate transistor. As shown in FIG. 1, the nonvolatile memory includes two stacked separate gates. The upper gate is the control gate 12 and is connected to the control line C. The lower gate is a floating gate 14. In addition, an n-type doped source region and an n-type doped drain region are formed in the P-type substrate. The n-type doped source region is connected to the source line S. The n-type doped drain region is connected to the drain line D.

  When the nonvolatile memory is in the programmed state, a high voltage (for example, + 16V) is supplied by the drain line D, a ground voltage is supplied by the source line S, and a control voltage (for example, + 25V) is supplied by the control line C. The As a result, hot carriers (for example, hot electrons) are attracted to the control voltage of the control gate 12 and injected into the floating gate 14 while electrons move from the source line S to the drain line D through the n-channel region. . Under this environment, many carriers are accumulated in the floating gate 14. As a result, the program state can be considered as the first storage state (eg, “0”).

  In the non-volatile memory, carriers are not injected into the floating gate in the non-programmed state. Therefore, the non-programmed state can be considered as the second storage state (for example, “1”).

  In other words, the drain current (id) and gate-source voltage (Vgs) characteristic curve (for example, id-Vgs characteristic curve) in the first memory state is different from the id-Vgs characteristic curve in the second memory state. . As a result, the memory state of the floating gate transistor can be realized by changing the id-Vgs characteristic curve.

  However, since the programmable dual poly nonvolatile memory floating gate 14 and control gate 12 need to be manufactured separately, the manufacturing process of the programmable dual poly nonvolatile memory requires more processes, and It is not compatible with general CMOS manufacturing processes.

  US Pat. No. 6,678,190 discloses a programmable single poly non-volatile memory. FIG. 2A is a schematic cross-sectional view illustrating a conventional programmable single poly non-volatile memory disclosed in US Pat. No. 6,678,190. FIG. 2B is a schematic top view of the conventional programmable single poly non-volatile memory of FIG. 2A. 2C is a schematic circuit diagram illustrating the conventional programmable single poly non-volatile memory of FIG. 2A.

Refer to Figures 2A-2C. A programmable single poly nonvolatile memory consists of two sequentially connected p-type metal oxide semiconductor (PMOS) transistors. The 1PMOS transistor is used as a selection transistor, the selection gate 24 of the 1PMOS transistor is connected to the select gate voltage _{V SG.} The first source / drain region 21 is connected to the source line voltage _VSL . Further, the second source / drain region 22 can be considered as a combination of the p-type drain region of the first PMOS transistor and the first p-type source region of the second PMOS transistor. The floating gate 26 is disposed on the second PMOS transistor. The third source / drain region 23 of the second PMOS transistor is connected to the bit line voltage _VBL . Further, these PMOS transistors are formed in an N-type well region (NW). The N-type well region is connected to the N-type well voltage V _NW . The second PMOS transistor is used as a floating gate transistor.

Programmable single poly nonvolatile memory can operate in a programmed state or a read state by appropriately controlling the selection gate voltage V _SG , the source line voltage V _SL , the bit line voltage V _BL and the N-type well voltage V _NW Can do.

  The two PMOS transistors of a conventional programmable single poly non-volatile memory have gates 24 and 26, respectively, and the conventional programmable single poly non-volatile memory manufacturing process is compatible with a typical CMOS manufacturing process. There is sex.

  As described in FIGS. 1 and 2, the non-volatile memory is programmable. The electrical characteristics of the nonvolatile memory are only used for injecting many hot carriers into the floating gate. However, electrical properties cannot be used to remove carriers from the floating gate. That is, in order to realize the data erasing function, carriers stored in the floating gate can be removed from the floating gate by irradiating the nonvolatile memory with ultraviolet (UV) light. These non-volatile memories are named as one time programming (OTP) memories.

  Therefore, there is a need to provide an erasable programmable single poly non-volatile memory for multi-times programming (MTP) memory designs.

  The present invention provides an erasable programmable single poly non-volatile memory to eliminate the obstacles faced by the prior art.

  An erasable programmable single poly nonvolatile memory of the present invention comprises a substrate structure, a floating gate transistor having a floating gate, a gate oxide layer under the floating gate, and a channel region formed in an N-type well region. An erasing gate region having a P-type well region and an n-type source / drain region connected to an erasing line voltage, the floating gate extending adjacently, and the N-type well region and the P-type well region Formed in the substrate structure, wherein the gate oxide layer has a first portion on the channel region of the floating gate and a second portion on the erase gate region, and the gate oxide layer The thickness of the first portion is different from the thickness of the second portion of the gate oxide layer.

  Many objects, features and advantages of the present invention will become readily apparent from the following detailed description of embodiments of the invention when read in conjunction with the accompanying drawings. However, the drawings used here are for illustrative purposes and should not be considered limiting.

  The above objects and advantages of the present invention will become more readily apparent to those of ordinary skill in the art after reviewing the following detailed description and accompanying drawings.

(Prior Art) FIG. 1 is a schematic cross-sectional view for explaining a conventional programmable dual poly nonvolatile memory.

FIG. 1 is a schematic cross-sectional view of a conventional programmable single poly non-volatile memory disclosed in US Pat. No. 6,678,190.

FIG. 2B is a schematic top view of the conventional programmable single poly non-volatile memory of FIG. 2A.

FIG. 2B is a schematic circuit diagram illustrating the conventional programmable single poly non-volatile memory of FIG. 2A.

1 schematically illustrates an erasable programmable single poly non-volatile memory according to a first embodiment of the present invention; FIG. 1 schematically illustrates an erasable programmable single poly non-volatile memory according to a first embodiment of the present invention; FIG. 1 schematically illustrates an erasable programmable single poly non-volatile memory according to a first embodiment of the present invention; FIG. 1 schematically illustrates an erasable programmable single poly non-volatile memory according to a first embodiment of the present invention; FIG.

It is a figure which shows roughly a different board | substrate structure and P type well area | region (PW) applied to 1st Embodiment of this invention. It is a figure which shows roughly a different board | substrate structure and P type well area | region (PW) applied to 1st Embodiment of this invention.

It is a figure which shows roughly the other erase gate area | region which can be substituted for the erase gate area | region shown in 1st Embodiment. It is a figure which shows roughly the other erase gate area | region which can be substituted for the erase gate area | region shown in 1st Embodiment.

FIG. 2 schematically illustrates different substrate structures and P-type well regions (PW) applied to embodiments of the present invention. FIG. 2 schematically illustrates different substrate structures and P-type well regions (PW) applied to embodiments of the present invention.

It is a figure which shows two voltage bias methods in an erased state.

  3A-3D schematically illustrate an erasable programmable single poly non-volatile memory according to a first embodiment of the present invention. FIG. 3A is a schematic top view illustrating an erasable programmable single poly non-volatile memory according to a first embodiment of the present invention. 3B is a schematic cross-sectional view along the first direction (a1-a2) illustrating the erasable programmable single poly non-volatile memory of FIG. 3A. 3C is a schematic cross-sectional view along the second direction (b1-b2) showing the erasable programmable single poly non-volatile memory of FIG. 3A. FIG. 3D is a schematic equivalent circuit diagram showing an erasable programmable single-poly nonvolatile memory according to the first embodiment of the present invention. Furthermore, the non-volatile memory of the present invention is manufactured using a single poly process that is logically compatible with the CMOS manufacturing process.

  As shown in FIGS. 3A and 3B, the erasable programmable single poly nonvolatile memory of the first embodiment comprises two sequentially connected p-type metal oxide semiconductors (PMOS). These two PMOS transistors are formed in an N-type well region (NW). Three p-type source / drain regions 31, 32 and 33 are formed in an N-type well region (NW). In addition, two polysilicon gates 34 and 36 extend over the region between the three p-type source / drain regions 31, 32 and 33, and the gate oxide layers 342 and 362 are connected to the two polysilicon gates 34 and 36. 36 and the upper surface of the semiconductor. Furthermore, the two polysilicon gates 34 and 36 on the N-type well region (NW) are P-type doped polysilicon gates 34 and 36.

The first PMOS transistor is used as a selection transistor, and a polysilicon gate 34 (also referred to as a selection gate) of the first PMOS transistor is connected to a selection gate voltage _VSG . The first source / drain region 31 is a p-type source region and is connected to the source line voltage _VSL . The second source / drain region 32 is a p-type drain region. The p-type source / drain region 32 can be considered as a combination of the p-type drain region of the first PMOS transistor and the p-type source region of the second PMOS transistor. A polysilicon gate 36 (also referred to as a floating gate) is disposed on the second PMOS transistor. The third source / drain region 33 is a p-type drain region of the second PMOS transistor and is connected to the bit line voltage _VBL . Furthermore, the second PMOS transistor includes a channel region formed in the N-type well region (NW), and the N-type well region (NW) is connected to the N-type well voltage V _NW . The second PMOS transistor is used as a floating gate transistor.

  As shown in FIGS. 3A and 3C, the erasable programmable single poly nonvolatile memory of the first embodiment is an n-type metal oxide semiconductor (NMOS) transistor or floating gate 36, a gate oxide layer 362 and an erase. A combination of gate regions 35 is provided. The NMOS transistor is formed in the P-type well region (PW). The n-type source / drain region 38 is formed in the P-type well region (PW). In other words, the erase gate region 35 includes a P-type well region (PW) and an n-type source / drain region 38. Furthermore, the floating gate 36 on the P-type well region (PW) is an N-type doped polysilicon gate. The P-type well region (PW) can be a P-type doped well region, and the N-type well region can be an N-type doped well region.

As shown in FIG. 3A, the floating gate 36 extends to and is adjacent to the erase gate region 35. Furthermore, the n-type source / drain region 38 can be considered as a combination of the n-type source region and the n-type drain region of the NMOS transistor, and the floating gate 36 can be considered as the gate of the NMOS transistor. N-type source / drain region 38 is connected to erase line voltage V _EL . In addition, the P-type well region (PW) is connected to the P-type well voltage V _PW . As shown in FIG. 3C, the gate oxide layer 362 is formed under the floating gate 36, and the gate oxide layer 362 includes two portions 362a and 362b. The first portion 362a of the gate oxide layer 362 is formed in the floating gate transistor (second PMOS transistor), and the second portion 362b of the gate oxide layer 362 is formed in the NMOS transistor (or on the erase gate region 35). The According to the first embodiment of the invention, an etch back process is employed to etch the second portion of the gate oxide layer. Thus, the thickness of the first portion 362a of the gate oxide layer 362 is greater than the thickness of the second portion 362b of the gate oxide layer 362. Further, one isolation structure 39 is formed between the P-type well region (PW) and the N-type well region (NW). For example, the isolation structure 39 is an STI (Shallow Trench Isolation) structure.

  As shown in FIG. 3D, the erase gate region 35 can also be viewed as a tunnel capacitance for storage carriers that are emitted from the floating gate 36 out of the non-volatile memory through the tunnel capacitance.

Furthermore, different substrate structures and P-type well regions (PW) applied to the first embodiment of the present invention are shown in more detail below. As shown in FIG. 4, the substrate structure includes a deep N-type well region (DNW) and a P-type substrate. The deep N-type well region (DNW) is formed in the P-type substrate, and the deep N-type well region (DNW) is connected to the deep N-type well voltage V _DNW .

  The N-type well region (NW) and P-type well region (PW) of the first embodiment are formed in a deep N-type well region (DNW) having a substrate structure. The P-type well region (PW) further includes a first p-type region (p1), two second p-type regions (p2), and a third p-type region (p3). The injection amount of the second p-type region (p2) is higher than or equal to the injection amount of the first p-type region (p1). Further, the implantation amount of the third p-type region (p3) is higher than or equal to the implantation amount of the first p-type region (p1).

  In addition, the first p-type region (p1) is formed below the surface of the P-type substrate, is in contact with the n-type source / drain region 38, and the third p-type region (p3) is below the first p-type region (p1). Formed. Furthermore, the first p-type region (p1) and the third p-type region (p3) are disposed between the two second p-type regions (p2), and the second p-type region (p2) is below the two isolation structures 39. It is formed.

  According to FIG. 4 of the present invention, the junction breakdown voltage between the n-type source / drain region 38 and the first p-type region (p1) is increased, so the erase efficiency of the erasable programmable single poly nonvolatile memory is Improved. Furthermore, the two second p-type regions (p2) can improve the lateral punch-through effect between the n-type source / drain region 38 and the N-type well region (NW), and the third p-type region (p3 ) Can improve the vertical punch-through effect between the n-type source / drain region 38 and the deep N-type well region (DNW), particularly in a high temperature environment.

  As shown in FIG. 5, the substrate structure includes a fourth p-type region (p4), an n-type barrier layer (NBL: N-type barrier layer, ie, second n-type region), and a P-type substrate. The n-type barrier layer (NBL) is formed on the P-type substrate, and the fourth p-type region (p4) is formed on the n-type barrier layer (NBL) and in contact with the n-type barrier layer (NBL).

  The N-type well region (NW) and the P-type well region (PW) of the first embodiment are formed in the fourth p-type region (p4) of the substrate structure. The P-type well region (PW) further includes a first p-type region (p1), two second p-type regions (p2), and a third p-type region (p3). The injection amount of the second p-type region (p2) is higher than or equal to the injection amount of the first p-type region (p1). Further, the implantation amount of the third p-type region (p3) is higher than or equal to the implantation amount of the first p-type region (p1). In addition, the implantation amount of the fourth p-type region (p4) is equal to the implantation amount in the P-type substrate. Alternatively, the injection amount of the fourth p-type region (p4) is higher than or equal to the injection amount of the third p-type region (p3), and the fourth p-type region (p4) is the second p-type region (p2). It is lower than or equal to the amount injected into.

  In addition, the first p-type region (p1) is formed below the surface of the substrate structure, is in contact with the n-type source / drain region 38, and the third p-type region (p3) is below the first p-type region (p1). It is formed. Furthermore, the first p-type region (p1) and the third p-type region (p3) are disposed between the two second p-type regions (p2), and the second p-type region (p2) is below the two isolation structures 39. It is formed.

  According to FIG. 5 of the present invention, the junction breakdown voltage between the n-type source / drain region 38 and the first p-type region (p1) is increased, and thus the erase efficiency of the erasable programmable single-poly nonvolatile memory. Is improved. Furthermore, the two second p-type regions (p2) can improve the lateral punch-through effect between the n-type source / drain region 38 and the N-type well region (NW) at a higher temperature. The type region (p3) can improve the vertical punch-through effect between the n-type source / drain region 38 and the N-type barrier layer (NBL) at a higher temperature. In addition, the N-type well region (NW) of the first embodiment is separated by the fourth p-type region (p4) and the P-type well region (PW). Therefore, an independent bias voltage is separated from the floating gate 36. The voltage stress between the N-type well region (NW) can be reduced.

  6A to 6B schematically show other erase gate regions that can be replaced with the erase gate region 35 shown in the first embodiment. The structures of the first PMOS transistor (selection transistor) and the second PMOS transistor (floating gate transistor) are the same as in FIG. 3B, and are not shown redundantly here.

As shown in FIGS. 6A and 6B, compared to FIG. 3C, the erase gate region 65 has a double diffusion drain (between the n-type source / drain region 62 and the P-type well region (PW)). DDD) region 64 (ie, the first n-type region (n1)). In order to achieve a lower erase line voltage (V _EL ), the thickness of the second portion 362b of the gate oxide layer 362 is thinner than the thickness of the first portion 362a of the gate oxide layer 362.

  FIG. 6B shows a schematic equivalent circuit diagram of an erasable programmable single poly non-volatile memory including a first PMOS transistor, a second PMOS transistor and an erase gate region 65.

Furthermore, the different substrate structures and P-type well regions (PW) applied to the embodiment shown in FIG. 6A are shown in more detail below. As shown in FIG. 7, the substrate structure includes a deep N-type well region (DNW) and a P-type substrate. The deep N-type well region (DNW) is formed in the P-type substrate, and the deep N-type well region (DNW) is connected to the deep N-type well voltage V _DNW .

  The N-type well region (NW) and the P-type well region (PW) of the embodiment are formed in the substrate structure. The P-type well region (PW) further includes a first p-type region (p1), two second p-type regions (p2), and a third p-type region (p3). The injection amount of the second p-type region (p2) is higher than or equal to the injection amount of the first p-type region (p1). Further, the implantation amount of the third p-type region (p3) is higher than or equal to the implantation amount of the first p-type region (p1). The implantation amount of the N-type well region (NW) is higher than or equal to the implantation amount of the first n-type region (n1, that is, the double diffusion drain (DDD) region). The implantation amount of the first p-type region (p1) is higher than or the same as the implantation amount of the first n-type region (n1).

  In addition, the first p-type region (p1) is formed under the surface of the substrate structure and is in contact with the double diffusion drain (DDD) region 64, and the third p-type region (p3) is the first p-type region (p1). Formed below. Furthermore, the first p-type region (p1) and the third p-type region (p3) are disposed between the second p-type regions (p2) formed under the two isolation structures 39.

  According to FIG. 7 of the present invention, the junction breakdown voltage between the first n-type region (n1, ie, double diffused drain (DDD) region 64) and the first p-type region (p1) is increased, and therefore erased. The erase efficiency of the programmable programmable single poly non-volatile memory is improved. Furthermore, the second p-type region (p2) can improve the lateral punch-through effect between the double diffused drain (DDD) region 64 and the N-type well region (NW) at a higher temperature. The mold region (p3) can improve the vertical punch-through effect between the double diffused drain (DDD) region 64 and the deep N-type well region (DNW) at higher temperatures.

  As shown in FIG. 8, the substrate structure includes a fourth p-type region (p4), an n-type barrier layer (NBL, ie, a second n-type region), and a P-type substrate. The n-type barrier layer (NBL) is formed in the substrate structure, and the fourth p-type region (p4) is in contact with the n-type barrier layer (NBL).

  The N-type well region (NW) and the P-type well region (PW) of the embodiment are formed in the substrate structure. The P-type well region (PW) further includes a first p-type region (p1), two second p-type regions (p2), and a third p-type region (p3). The injection amount of the second p-type region (p2) is higher than or equal to the injection amount of the first p-type region (p1). Further, the implantation amount of the third p-type region (p3) is higher than or equal to the implantation amount of the first p-type region (p1). In addition, the implantation amount of the fourth p-type region (p4) is equal to the implantation amount in the P-type substrate. Alternatively, the injection amount of the fourth p-type region (p4) is higher than or equal to the injection amount of the third p-type region (p3), and the fourth p-type region (p4) is the second p-type region (p2). It is lower than or equal to the amount injected into.

  In addition, the first p-type region (p1) is formed under the surface of the substrate structure and is in contact with the double diffusion drain (DDD) region 64, and the third p-type region (p3) is the first p-type region (p1). Formed below. Furthermore, the first p-type region (p1) and the third p-type region (p3) are disposed between the two second p-type regions (p2) formed under the two isolation structures 39.

  According to FIG. 8 of the present invention, the junction breakdown voltage between the first n-type region (n1) (ie, the double diffusion drain (DDD) region 64) and the first p-type region (p1) is increased, and therefore The erase efficiency of an erasable programmable single poly non-volatile memory is improved. Furthermore, the second p-type region (p2) can improve the lateral punch-through effect between the double diffused drain (DDD) region 94 and the N-type well region (NW) at a higher temperature. The type region (p3) improves the vertical penetration effect between the double diffusion drain (DDD) region 64 (ie, the first n-type region: n1) and the n-type barrier layer (DBL) at a higher temperature. be able to. In addition, the N-type well region (NW) of the first embodiment is separated by the fourth p-type region (p4) and the P-type well region (PW). Therefore, an independent bias voltage is separated from the floating gate 36. The voltage stress between the N-type well region (NW) can be reduced.

In accordance with the present invention, some bias voltage may be provided to an embodiment formed in the deep N-type well region (DNW) of the substrate structure as shown in FIGS. 4 and 7 in the erased state. FIG. 9 shows two voltage bias methods in the erased state. As shown in FIG. 9, when Method 1 is used in the erased state, the source line voltage V _SL and the bit line voltage are in the range of 0 V to the positive voltage V _EE and the N-type well voltage V _NW and the word The line voltage V _WL and the deep N-type well voltage V _DNW are equal to the positive voltage (V _EE ). However, the erase line voltage V _EL and the P-type well voltage V _PW are equal to the negative voltage −V _ee . The positive voltage _{V EE} in the range of + 18V from + 6.5V, the negative voltage _{-V ee} is in the range of -18V from -6.5 V. Thus, the release of memory carriers is achieved using the Fowler-Nordhiem (FN) effect.

As shown in FIG. 9, when Method 2 is used in the erased state, the source line voltage V _SL is floating, the bit line voltage is the ground voltage (0 V), the N-type well voltage V _NW , the word The line voltage V _WL and the deep N-type well voltage V _DNW are equal to the positive voltage (V _EE ). However, the erase line voltage V _EL and the P-type well voltage (V _PW ) are equal to the negative voltage −V _ee . The positive voltage _{V EE} in the range of + 18V from + 6.5V, the negative voltage _{-V ee} is in the range of -18V from -6.5 V. As described above, the release of memory carriers is caused by band-to-band hot holes (BBHH), substrate hot holes (SHH), and drain avalanche hot holes (DAHH). Such a hot hole (HH) effect is used.

As described above, the erasable programmable single poly nonvolatile memory of the present invention can reduce the erase line voltage (V _EL ). In other words, the storage state of the nonvolatile memory of the present invention can be changed by supplying a lower erase line voltage _VEL .

  Although the invention has been described with respect to what are presently considered to be the most practical and preferred embodiments, it is to be understood that the invention need not be limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar changes that fall within the spirit and scope of the appended claims consistent with the broadest interpretation, and includes all such modifications and similar structures.

Claims (14)

A substrate structure;
A floating gate transistor having a floating gate, a gate oxide layer under the floating gate, and a channel region formed in an N-type well region;
An erase gate region extending adjacent to the floating gate and having a P-type well region and an n-type source / drain region connected to an erase line voltage;
The N-type well region and the P-type well region are formed in the substrate structure, and the gate oxide layer includes a first portion on the channel region of the floating gate and a second portion on the erase gate region. And the thickness of the first portion of the gate oxide layer is different from the thickness of the second portion of the gate oxide layer. Sex memory. An erasable programmable single poly non-volatile memory according to claim 1, comprising:
The erasable programmable single poly, further comprising a first n-type region formed between the n-type source / drain region and the P-type well region. Non-volatile memory. An erasable programmable single poly non-volatile memory according to claim 2,
An erasable programmable single poly non-volatile memory wherein the first n-type region is a double diffused drain region. An erasable programmable single poly non-volatile memory according to claim 3,
The P-type well region is
A first p-type region formed under the surface of the substrate structure and connected to the first n-type region;
A plurality of second p-type regions;
A third p-type region formed below the first p-type region,
An erasable programmable single-poly nonvolatile memory, wherein the first p-type region and the third p-type region are disposed between the plurality of second p-type regions. An erasable programmable single poly non-volatile memory according to claim 4,
The implantation amount of the second p-type region is higher than or equal to the implantation amount of the first p-type region, and the implantation amount of the third p-type region is higher than or the same as the implantation amount of the first p-type region. Erasable programmable single poly non-volatile memory featuring. An erasable programmable single poly non-volatile memory according to claim 4,
The substrate structure is
A P-type substrate;
A deep N-type well region formed on the P-type substrate, connected to the N-type well region, the second p-type region, and the third p-type region, and connected to a deep N-type well voltage. An erasable programmable single poly non-volatile memory. An erasable programmable single poly non-volatile memory according to claim 6, comprising:
An erasable programmable single-poly non-volatile memory, wherein the implantation amount of the first p-type region is higher than or equal to the implantation amount of the first n-type region. An erasable programmable single poly non-volatile memory according to claim 4,
The substrate structure is
A P-type substrate;
A second n-type region formed in the P-type substrate;
And a fourth p-type region connected to the N-type well region, the second p-type region, and the third p-type region. The fourth p-type region is formed on and connected to the n-type barrier layer. Erasable programmable single poly non-volatile memory. An erasable programmable single poly non-volatile memory according to claim 8, comprising:
The implantation amount of the fourth p-type region is higher than or equal to the implantation amount of the P-type substrate, and the implantation amount of the fourth p-type region is higher than or equal to the implantation amount of the third p-type region, An erasable programmable single-poly non-volatile memory, wherein the implantation amount of the fourth p-type region is lower or the same as the implantation amount of the second p-type region. An erasable programmable single poly non-volatile memory according to claim 1, comprising:
The P-type well region is
A first p-type region formed under the surface of the substrate structure and connected to the n-type source / drain region;
A plurality of second p-type regions;
A third p-type region formed under the first p-type region,
The erasable programmable single-poly nonvolatile memory, wherein the first p-type region and the third p-type region are disposed between the plurality of second p-type regions. An erasable programmable single poly non-volatile memory according to claim 10,
The implantation amount of the second p-type region is higher than or equal to the implantation amount of the first p-type region, and the implantation amount of the third p-type region is higher than or the same as the implantation amount of the first p-type region. An erasable programmable single poly non-volatile memory characterized in that. An erasable programmable single poly non-volatile memory according to claim 10,
The substrate structure is
A P-type substrate;
An erasable programmable single circuit comprising: a deep N-type well region formed on the P-type substrate and connected to the N-type well region, the second p-type region, and the third p-type region. One poly non-volatile memory. An erasable programmable single poly non-volatile memory according to claim 10,
The substrate structure is
A P-type substrate;
A second n-type region formed in the P-type substrate;
And a fourth p-type region connected to the N-type well region, the second p-type region, and the third p-type region. The fourth p-type region is formed on and connected to the n-type barrier layer. Erasable programmable single poly non-volatile memory. An erasable programmable single poly non-volatile memory according to claim 13,
The implantation amount of the fourth p-type region is higher than or equal to the implantation amount of the P-type substrate, and the implantation amount of the fourth p-type region is higher than or equal to the implantation amount of the third p-type region, An erasable programmable single-poly non-volatile memory, wherein the implantation amount of the fourth p-type region is lower or the same as the implantation amount of the second p-type region.

Images