CN104157307B - Flash memory and its read method - Google Patents
Flash memory and its read method Download PDFInfo
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- CN104157307B CN104157307B CN201410398312.2A CN201410398312A CN104157307B CN 104157307 B CN104157307 B CN 104157307B CN 201410398312 A CN201410398312 A CN 201410398312A CN 104157307 B CN104157307 B CN 104157307B
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Abstract
The present invention relates to semiconductor devices, a kind of flash memory and its read method are disclosed.In the present invention, each flash cell in the flash memory includes a selection grid PMOS transistor, a control gate PMOS transistor and a reading selection grid PMOS transistor, and selection grid PMOS transistor, control gate PMOS transistor and reading selection grid PMOS transistor are connect by first electrode and second electrode series winding；The absolute value for reading electrical thickness of gate oxide, channel length and the threshold voltage of selection grid PMOS transistor is respectively less than the respective value of selection grid PMOS transistor.The 3T PMOS flash memories of the present invention have the reading selection grid PMOS transistor for being exclusively used in reading, the reading efficiency of flash memory can be improved on the whole, effectively reduce and read power consumption, overcome the shortcomings of existing 2T PMOS flash memories discharge and recharge overlong time, dynamic current in read operation are too high, reading power consumption is too high.
Description
Technical field
The present invention relates to semiconductor devices, more particularly to flash memory and its read method.
Background technology
Existing inserted 2 T pMOS flash arrays are made up of the 2T pMOS flash cells of repeated arrangement, flash cell
Basic structure is as shown in Figure 1.2T PMOS flash cells by selection grid PMOS transistor (grid line SG-1 controls its grid potential) and
Control gate PMOS transistor (wordline WL-1 controls its grid potential) series connection is formed.Selection grid PMOS transistor main technologic parameters
It is as follows：" electrical thickness of gate oxide 8nm~11nm, channel length 100nm~300nm ".The main work of control gate PMOS transistor
Skill parameter is as follows：Electrical thickness of gate oxide 8nm~11nm is (synchronous with selecting the gate oxide of gate transistor to be formed therefore thick
Degree it is identical), ono dielectric layer (silicon oxide-silicon nitride-silica membrane) electrical thickness 10nm~20nm, multi-crystal silicon floating bar
Thickness 20nm~100nm (doping concentrations 1020/cm-3More than), channel length 100nm~300nm.Wherein, internal node knot
(Internal-Node Junction, IN) is shared by two PMOS transistors.When SL-1 connects high potential, BL-1 connects low potential
When, IN is equivalent to the drain electrode of gate transistor is controlled, while being also the source electrode for selecting gate transistor.
Existing inserted 2 T pMOS flash arrays use NOR-type architecture (as shown in Figure 2).BL in figure is Bit
Line abbreviation, commonly referred to as " bit line ", for the current potential of controlling transistor drain terminal.WL is Word Line abbreviation, commonly referred to as
For " wordline ", for the current potential of controlling transistor gate terminal.SL is Source Line abbreviation, commonly referred to as " source line ", is used for
The current potential of controlling transistor source.Under NOR-type circuit framework, it can be set, realized by SG/BL/WL/SL different biass
Reading to any one flash cell.By taking the internal storage location 1 of circles mark in scheming as an example, we open selection by SG-1
Grid pMOS, gives control gate pMOS mono- suitable grid voltage, by being between BL-1 and SL-1 during read operation by WL-1
No to have electric current to judge " 0 "/" 1 ", the bias of specific read operation is set referring to table 1.
Table 1.2T pMOS flash memories read operation bias sets table
Wherein, VCC represents supply voltage.
The erasing-programming of existing inserted 2 T pMOS flash arrays is operated as read operation, it is necessary to pass through SG/
BL/WL/SL different biass are set to be operated to choose the flash cell of particular address (scope), and specific bias sets ginseng
It is shown in Table 2 and table 3.
Table 2.2T pMOS flash memories erasing operation bias sets table
Table 3.2T pMOS flash memory programmings operation bias sets table
Existing inserted 2 T PMOS flash arrays are made up of the flash cell of 2T cascaded structures.Wiped, programmed
During read operation, it is necessary to which horizontal selection is carried out by selecting gate transistor (SG), and (it is vertical generally to define BL directions
To).
With reference to table 1-3, it can be seen that device is being wiped or during programming operation, can applied respectively positively or negatively on SG
High pressure.In order to be resistant to above-mentioned high pressure, the electrical thickness of gate oxide of selection grid PMOS transistor can not be excessively thin, therefore has to
Gate oxide is used as using tunnel oxide.Due to the limitation of 2T cascaded structures, the blocked up gate oxide for selecting gate transistor
Selected flash cell can be caused when being read, SG voltage must sufficiently low (such as -2V) can just obtain foot
Enough big reading electric currents.From the perspective of circuit design, too low SG biass can cause during read operation " SG " that chooses and
" pressure difference between unchecked SG " is excessive (such as VCC+2V), so that discharge and recharge time when switching SG addresses in read operation
Long, dynamic current is excessive, it is too high to read power consumption.
Further, since to transmit high pressure in erase and program operations to SG, peripheral circuit related SG (such as decodes electricity
Road, drive circuit) the pressure-resistant high tension apparatus beyond 10V must be used.And for reading circuit, the threshold value electricity of high tension apparatus
Press through that high, driving current is too small, switching speed is excessively slow, these shortcomings all to flash memory reading speed and can read power consumption and cause unfavorable
Influence.
Above-mentioned embedded flash memory (Embedded Flash Memory), is generally integrated into system-level core in the form of IP
SIM-card (client identification module card) chip of piece, such as mobile phone, Intelligent Bank the core of the card piece etc..Due to this characteristic, therefore
Referred to as " embedded ", to be different from the product (Stand-alone Flash Memory, free-standing flash memory) of independent flash memory formation；
PMOS (FET)-P-type mos FET, MOS=MOSFET, are the bases of modern super large-scale integration
This composition device, PMOS has four control ends, is gate terminal (Gate), drain terminal (Drain), source (Source) and substrate respectively
Hold (Bulk), pass through the control of Electric potentials at this four end, it is possible to achieve the opening and closing of transistor (conducting of corresponding current and are cut
Only)；Gate transistor-Select Gate Transistor are selected, are generally connected with control gate transistor, " 2T sudden strains of a muscle are collectively forming
Memory cell ", by selecting gate transistor, the flash cell that can be selected or cancel selected fixing address is operated, for
The embedded PMOS flash memories that this special project is related to, selection gate transistor is PMOS；Control gate transistor-Control Gate
The unit of " 0/1 " is stored on Transistor, i.e. ordinary meaning.By concrete operations so that different electricity are presented in the transistor
Characteristic (such as different threshold voltages), so as to represent " 0 " or " 1 "；Floating boom-Floating Gate, are generally embedded in control gate
Similar sandwich structure is formed between the control gate and silicon substrate of transistor.
The content of the invention
It is an object of the invention to provide a kind of flash memory and its read method, 3T PMOS flash memories of the invention can be from entirety
The upper reading efficiency for improving flash memory, effectively reduces and reads power consumption, overcome existing 2T PMOS flash memories pipe discharge and recharge in read operation
Overlong time, dynamic current are excessive, read the too high shortcoming of power consumption.
In order to solve the above technical problems, embodiments of the present invention disclose a kind of flash memory, the array of the flash memory is included extremely
A few sector, each sector includes N-type trap and multiple flash cells of rectangular array is connected into the N-type trap, wherein,
Each flash cell reads choosing comprising a selection grid PMOS transistor, a control gate PMOS transistor and one
Select grid PMOS transistor, selection grid PMOS transistor, control gate PMOS transistor and read selection grid PMOS transistor by the
One electrode and second electrode series winding connect；
The electrical thickness of gate oxide for reading selection grid PMOS transistor is less than the gate oxide of selection grid PMOS transistor
Electrical thickness, the channel length for reading selection grid PMOS transistor is less than the channel length of selection grid PMOS transistor, reads choosing
Select absolute value of the absolute value less than the threshold voltage of selection grid PMOS transistor of the threshold voltage of grid PMOS transistor；
First electrode is source electrode and second electrode is drain electrode, or first electrode is drain electrode and second electrode is source electrode.
Embodiments of the present invention also disclose a kind of read method of flash memory, and this method is used for flash memory as described above
Read operation, and in the rectangular array that connects into of flash cell of the flash memory, positioned at the selection grid PMOS crystal of same row
The second electrode of pipe is joined together to form the first control line, and the grid positioned at the selection grid PMOS transistor of same a line is connected to
The first electrode of the reading selection grid PMOS transistor formed together in the second control line, each sector is joined together to form one
Article the 3rd control line, the grid positioned at the reading selection grid PMOS transistor of same a line is joined together to form the 4th control line,
Grid positioned at the control gate PMOS transistor of same a line is joined together to form the 5th control line；
The read method comprises the following steps：
When performing read operation, the current potential for setting the N-type trap of each sector is supply voltage, each second control line
Current potential is -2~-0.5V, and the current potential of the first control line of the selected flash cell being read out is supply voltage, the 3rd control
The current potential of line, the 4th control line and the 5th control line is 0.
Compared with prior art, the main distinction and its effect are embodiment of the present invention：
The 3T PMOS flash memories of the present invention have the reading selection grid PMOS transistor for being exclusively used in reading, can be in read operation
When, the bias of fixed selection grid PMOS transistor is set, and is selected the grid voltage of gate transistor to become by reading and is brought progress address choosing
Take.Because reading selection gate transistor is only used for read operation, its structure setting is not by when programming operation and erasing operation
High pressure is limited, and can be set smaller than its electrical thickness of gate oxide and channel length etc. to select gate transistor, and related reading
Sense circuit can be made up of pure low-voltage device, and the reading efficiency of flash memory is improved on the whole, effectively reduced and read power consumption, overcome existing
Have the shortcomings that discharge and recharge overlong time, dynamic current are excessive during 2TPMOS flash memory read operations, it is too high to read power consumption.
The flash memory of the present invention can there is provided big reading electric current and reading as fast as possible as far as possible when being read
Speed, and greatly reduce reading power consumption.
Brief description of the drawings
Fig. 1 is a kind of cellular construction schematic diagram of NOR-type 2T PMOS flash memories in the prior art；
Fig. 2 is a kind of array schematic diagram of NOR-type 2T PMOS flash memories in the prior art；
Fig. 3 is a kind of array schematic diagram of 3T PMOS flash memories in first embodiment of the invention；
Fig. 4 is a kind of cellular construction schematic diagram of 3T PMOS flash memories in first embodiment of the invention.
Embodiment
In the following description, in order that reader more fully understands the application and proposes many ins and outs.But, this
Even if the those of ordinary skill in field is appreciated that many variations without these ins and outs and based on following embodiment
And modification, each claim of the application technical scheme claimed can also be realized.
To make the object, technical solutions and advantages of the present invention clearer, the implementation below in conjunction with accompanying drawing to the present invention
Mode is described in further detail.
In the embodiments of the present invention, in order to be consistent with language commonly used in the art, and the convenient understanding present invention, will
First control line is referred to as bit line (BL), and the second control line is referred to as selection grid line (SG), and the 3rd control line is referred to as source line (SL), the 4th
Control line is referred to as reading selection grid line (READ-SG), and the 5th control line is referred to as wordline (WL).
First embodiment of the invention is related to a kind of flash memory.Specifically, the array of the flash memory includes at least one sector, often
Individual sector includes N-type trap (DNW) and multiple flash cells of rectangular array is connected into the N-type trap, wherein, each flash memory
Unit includes a selection grid PMOS transistor, a control gate PMOS transistor and a reading selection grid PMOS transistor,
Selection grid PMOS transistor, control gate PMOS transistor and reading selection grid PMOS transistor pass through first electrode and second electrode
Series winding connects.The electrical thickness of gate oxide for reading selection grid PMOS transistor is less than the gate oxide electricity of selection grid PMOS transistor
Thickness is learned, the channel length for reading selection grid PMOS transistor is less than the channel length of selection grid PMOS transistor, reads selection
Absolute value of the absolute value of the threshold voltage of grid PMOS transistor less than the threshold voltage of selection grid PMOS transistor.And first electricity
Extremely source electrode and second electrode are drain electrode, or first electrode is drain electrode and second electrode is source electrode.
In the present invention, selection grid PMOS transistor, control gate PMOS transistor and reading selection grid PMOS transistor are led to
Cross first electrode and second electrode series winding connects and referred in each flash cell, three transistor series connection, and one of transistor
First electrode (or second electrode) and another transistor second electrode (or first electrode is connected).Such as, it is of the invention
In certain flash cell, the source electrode of selection grid PMOS transistor is connected with the drain electrode of control gate PMOS transistor, control gate PMOS
Drain electrode of the source electrode of transistor with reading selection grid PMOS transistor is connected；Or the source electrode and selection grid of control gate PMOS transistor
The drain electrode connection of PMOS transistor, drain electrode of the source electrode of selection grid PMOS transistor with reading selection grid PMOS transistor is connected
Deng.The transistor that control flash memory reads address selection is brought in addition, reading selection grid PMOS transistor and referring to become by grid voltage, specially
Read operation for flash memory.And control gate PMOS transistor is the PMOS transistor with floating boom.
As shown in figure 3, in the preference of the present invention, in flash cell, the first electricity of selection grid PMOS transistor
Pole is connected with the second electrode of control gate PMOS transistor, and the first electrode of control gate PMOS transistor is with reading selection grid crystal
The second electrode connection of pipe.Wherein, first electrode is source electrode and second electrode is drain electrode.Read the grid of selection grid PMOS transistor
Oxide layer electrical thickness is 4~10nm, and channel length is 100~200nm, and threshold voltage is -0.6~-0.3V, and saturation current is
150~300 μ A/ μm.The electrical thickness of gate oxide of selection grid PMOS transistor be 8~11nm, channel length be 100~
300nm, threshold voltage is -1.5~-0.8V, and saturation current is 80~100uA/um.
Furthermore, it is to be understood that in the other embodiment of the present invention, if simply reading examining for power consumption for reduction
Amount, the centre of selection gate transistor and control gate transistor can be located at by reading selection gate transistor, can not also be located at both
Between.During actual fabrication, limit and consider for a variety of other, such as：(a) it is placed on choosing selection gate transistor is read
Select in the middle of gate transistor and control gate transistor, be at this moment difficult the threshold voltage of control selections gate transistor, because selection grid is brilliant
The threshold value injection of body pipe and the threshold value injection of control gate transistor all can be toward the channel region diffusions for reading selection grid；(b) reading
Take selection gate transistor to be placed on the left side of selection gate transistor, be at this moment difficult that reduction selects the gate oxide electricity of gate transistor thick
Spend (integrity problem otherwise occurs), because " choosing reading selection gate transistor in the state of the unselected SG " of BL in programming
It must endure as the electric field masterpiece of GIDL (gated-induce drain leakage, grid induced drain leakage current) field effect
With；(c) in summary, the angle realized from practical application, it is preferable that read the optimal putting position of selection gate transistor
The both sides for being and selecting gate transistor to be located at control gate transistor respectively.
Furthermore, it is to be understood that it is simple from the angle of reading power consumption is improved, read the gate oxidation electricity of selection gate transistor
Learn thickness degree more Bao Yuehao, the more short better, threshold voltage of channel length the smaller the better.Such as, 55nm embedded flash memorys platform
Under technique, it may be considered that be used as reading selection grid PMOS transistor using the PMOS of 1.2V supply voltages.Compared to selection grid
PMOS transistor, the electrical thickness of gate oxide for reading selection grid PMOS transistor is reduced to 1~2nm, threshold value from more than 80nm
Voltage is reduced to -0.5V or so, saturation current more than -0.8V increases to 280 μ A/ μm or so, channel length from 100 μ A/ μm
Shorten to 1/3.
Certainly, actual process processing procedure will be realized serves as reading choosing using Low-Voltage Logic Devices (Core Logic Device)
Select gate transistor, it is necessary to make larger change, the cost of time and money is high.
Therefore, in another preference of the present invention, the cellular construction of 3T PMOS flash memories of the invention is with existing
Based on the cellular construction of NOR-type inserted 2 T PMOS flash memories, add read what selection grid PMOS transistor was realized wherein.
This structure is to have carried out image copying centered on control gate PMOS transistor, to selection grid PMOS transistor, forms reading
Selection grid PMOS transistor is taken, as shown in Figure 4.In order to optimize the performance for reading selection grid PMOS transistor, selection grid is read
Channel length is shortened 25~50nm, threshold value electricity by PMOS transistor on the basis of selection grid PMOS transistor device parameters
Pressure reduces -0.5~-0.3V.This 3T PMOS flash memory unit structures technique realization on existing 2T PMOS flash cells
Processing procedure is completely compatible, does not increase any processing step；Simultaneously because height of three devices on structure/height is similar, it is raw
The uniformity of production and the reliability of device have obtained good guarantee.
Furthermore, it is to be understood that in the present invention, reading selection grid PMOS transistor has a variety of implementations, is not limited to
The structure of above-mentioned " class 2T pMOS flash memories select gate transistor " based on 2T PMOS, can 1T NMOS or PMOS base
Added on plinth and read selection gate transistor, can also carried out on the basis of 2T NMOS；Can be flash memory or
E2PROM (band EEPROM) or OTP/MTP (disposable programmable memories/multiple programmable storage
Device).
3T PMOS flash memories in this preference need not change original erasing-programming/reading conditions, it is only necessary to which control is new
The reading selection grid PMOS transistor of addition, you can realize all operations of original 2T PMOS flash memories, and new quality is not introduced
Or integrity problem.The flash memory of generation switches scope with the bias for reducing selection grid when flash array is read, so as to lift reading
Charge/discharge rates, reduction dynamic during extract operation read electric current.In addition, 3T PMOS flash cells of the preference and existing
Some 2T pMOS flash cells are completely compatible in technique, in operating condition, in circuit design, can be according to the tools of SOC products
Body requires to carry out various combinations, so as to provide the wider scope of application and shorter Market Entry Time for final products.
In another preference, the present invention in embedded PMOS flash memories floating boom and control gate between using oxide-
Oxide is used between the isolation of Nitride Oxide (Oxide-Nitride-Oxide) insulation film, floating boom and silicon substrate
(Oxide) insulation film isolate, floating boom be in itself N-type or p-type doping polysilicon, can be used to store electric charge (be in this case
Electronics) so as to change the electrology characteristic of control gate transistor.
The 3T PMOS flash memories of the present invention have the reading selection grid PMOS transistor for being exclusively used in reading, can be in read operation
When, the bias of fixed selection grid PMOS transistor is set, and is become with bringing progress by reading the grid voltage of selection grid PMOS transistor
Location is chosen, and because the reading selection grid PMOS transistor is only used for read operation, its structure setting is not by programming operation and erasing
The parameters such as its electrical thickness of gate oxide, channel length and threshold voltage, can be set to be less than choosing by the high pressure limitation of operation
Grid PMOS transistor is selected, and related reading circuit can be made up of pure low-voltage device, and the reading effect of flash memory is improved on the whole
Rate, effectively reduces and reads power consumption, overcome existing 2T PMOS transistors discharge and recharge overlong time, dynamic current in read operation
The too high, shortcoming that reading power consumption is too high.
Second embodiment of the invention is related to a kind of read method of flash memory.This method is used for as described in embodiment 1
The read operation of flash memory.In the rectangular array that the flash cell of above-mentioned flash memory is connected into, positioned at the selection grid PMOS of same row
The second electrode of transistor is joined together to form the first control line, and the grid positioned at the selection grid PMOS transistor of same a line connects
It is connected together to form the second control line, the first electrode of the reading selection grid PMOS transistor in each sector links together shape
Into one article of the 3rd control line, the grid positioned at the reading selection grid PMOS transistor of same a line is joined together to form the 4th control
Line, the grid positioned at the control gate PMOS transistor of same a line is joined together to form the 5th control line.
The read method comprises the following steps：
When performing read operation, the current potential for setting the N-type trap of each sector is supply voltage, each second control line
Current potential is -2~-0.5V, and the current potential of the first control line of the selected flash cell being read out is supply voltage, the 3rd control
The current potential of line, the 4th control line and the 5th control line is 0；The first control for not being selected the flash cell being read out is set
Line, the 3rd control line, the current potential of the 4th control line and the 5th control line are 0, wherein, the flash cell being read out is not selected
There is the control line of same second and the first different control lines from the selected flash cell being read out；Setting is not selected
First control line of the flash cell being read out and the current potential of the 4th control line are supply voltage, the 3rd control line and the 5th control
The current potential of line processed is 0, wherein, the flash cell being read out is not selected with the selected flash cell being read out with same
One the first control line and the second different control lines；First control line of the not selected flash cell being read out of setting,
The current potential of 3rd control line and the 5th control line is 0, and the current potential of the 4th control line is supply voltage, wherein, it is not selected and carries out
The flash cell of reading has the first different control lines and the second different control from the selected flash cell being read out
Line.
The flash memory of the present invention can be when being read, it is possible to provide as big as possible reads electric current and reading as fast as possible
Speed is taken, and greatly reduces reading power consumption.
In addition, when above-mentioned flash memory performs erase and program operations, reading selection grid PMOS transistor and only serving transmission gate
Effect, for example, the present invention a preference in, its grid potential is set to supply voltage VCC, such as table 4 and the institute of table 5
Show：
Table 4.3T pMOS flash memories erasing operation bias sets table
Table 5.3T pMOS flash memory programmings operation bias sets table
If " read it is clear that 3T PMOS flash memory unit structures are not formed using " selection gate transistor " similar structures
Take selection gate transistor ", the specific bias of erasing-programming/read operation sets and must select gate transistor according to new reading
Characteristic is optimized and revised.But basic idea does not change, i.e., in operations with high pressure such as erasing-programmings, read choosing
Select gate transistor and only transmit purposes as voltage, it is to avoid any additional influence；In read operation, selection gate transistor is read
As laterally selection purposes, there is provided big reading electric current and reading speed as fast as possible as far as possible.
In addition, even with the flash cell of other erasing-programming physical mechanisms, no matter NMOS or PMOS, all
Can be by adding the method that a special reading selects gate transistor, to separate " read operation " and " erasing-programming height
Pressure " is required for the different of selection gate transistor, so as to reach the purpose of " low reading power consumption " or " ultrafast reading speed ".
It should be noted that in the claim and specification of this patent, such as first and second or the like relation
Term is used merely to make a distinction an entity or operation with another entity or operation, and not necessarily requires or imply
There is any this actual relation or order between these entities or operation.Moreover, term " comprising ", "comprising" or its
Any other variant is intended to including for nonexcludability so that process, method, article including a series of key elements or
Equipment not only includes those key elements, but also other key elements including being not expressly set out, or also include be this process,
Method, article or the intrinsic key element of equipment.In the absence of more restrictions, by wanting that sentence " including one " is limited
Element, it is not excluded that also there is other identical element in the process including the key element, method, article or equipment.
Although by referring to some of the preferred embodiment of the invention, being shown and described to the present invention,
It will be understood by those skilled in the art that can to it, various changes can be made in the form and details, without departing from this hair
Bright spirit and scope.
Claims (9)
1. a kind of read method of flash memory, it is characterised in that the array of the flash memory includes at least one sector, and each sector is included
N-type trap and multiple flash cells that rectangular array is connected into the N-type trap, wherein, each flash cell includes a choosing
Select grid PMOS transistor, a control gate PMOS transistor and a reading selection grid PMOS transistor, the selection grid PMOS
Transistor, control gate PMOS transistor and reading selection grid PMOS transistor are connect by first electrode and second electrode series winding, institute
State and read gate oxide electricity of the electrical thickness of gate oxide of selection grid PMOS transistor less than the selection grid PMOS transistor
Thickness is learned, the channel length of the reading selection grid PMOS transistor is less than the channel length of the selection grid PMOS transistor,
The absolute value of the threshold voltage for reading selection grid PMOS transistor is less than the threshold voltage of the selection grid PMOS transistor
Absolute value, the first electrode is source electrode and second electrode is drain electrode, or first electrode is drain electrode and second electrode is source electrode；
In the rectangular array that the flash cell of the flash memory is connected into, positioned at the second electricity of the selection grid PMOS transistor of same row
Pole is joined together to form the first control line, and is joined together to form positioned at the grid of the selection grid PMOS transistor of same a line
The first electrode of reading selection grid PMOS transistor in two control lines, each sector is joined together to form one article of the 3rd control
Line, the grid positioned at the reading selection grid PMOS transistor of same a line is joined together to form the 4th control line, positioned at same a line
The grid of control gate PMOS transistor be joined together to form the 5th control line；
The read method comprises the following steps：
When performing read operation, the current potential for setting the N-type trap of each sector is supply voltage, each second control
The current potential of line is -2~-0.5V, and the current potential of the first control line of the selected flash cell being read out is supply voltage, the 3rd
The current potential of control line, the 4th control line and the 5th control line is 0；
When performing read operation, it is power supply electricity to set the current potential for the 4th control line for not being selected the flash cell being read out
Pressure, wherein the flash cell being read out that is not selected has different second from the selected flash cell being read out
Control line.
2. the read method of flash memory according to claim 1, it is characterised in that when performing read operation, set not by
The current potential for choosing the first control line, the 3rd control line, the 4th control line and the 5th control line of the flash cell being read out is
0, wherein, the flash cell being read out that is not selected has same second with the selected flash cell being read out
Control line and the first different control lines.
3. the read method of flash memory according to claim 2, it is characterised in that when performing read operation, set not by
It is supply voltage, the 3rd control line and the to choose the first control line of the flash cell being read out and the current potential of the 4th control line
The current potential of five control lines is 0, wherein, it is described not to be selected the flash cell and the selected flash memory list being read out being read out
Member has the control line of same first and the second different control lines.
4. the read method of flash memory according to claim 3, it is characterised in that when performing read operation, set not by
The current potential for choosing the first control line, the 3rd control line and the 5th control line of the flash cell being read out is 0, the 4th control line
Current potential be supply voltage, wherein, it is described not to be selected the flash cell that is read out and the selected flash memory list being read out
Member has the first different control lines and the second different control lines.
5. the read method of flash memory according to claim 1, it is characterised in that in the flash cell, the selection
The first electrode of grid PMOS transistor is connected with the second electrode of control gate PMOS transistor, the control gate PMOS transistor
First electrode is connected with reading the second electrode of selection grid PMOS transistor.
6. the read method of flash memory according to claim 5, it is characterised in that the reading selection grid PMOS transistor
Electrical thickness of gate oxide is 4~10nm, and channel length is 100~200nm, and threshold voltage is -0.6~-0.3V.
7. the read method of flash memory according to claim 5, it is characterised in that the reading selection grid PMOS transistor
Saturation current is 150~300 μ A/ μm.
8. the read method of flash memory according to claim 5, it is characterised in that the grid oxygen of the selection grid PMOS transistor
It is 8~11nm to change layer electrical thickness, and channel length is 100~300nm, and threshold voltage is -1.5~-0.8V, and saturation current is 80
~100 μ A/ μm.
9. the read method of the flash memory according to any one of claim 1,5 to 8, it is characterised in that the first electrode
For source electrode, second electrode is drain electrode.
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| JP7065637B2 (en) * | 2018-02-22 | 2022-05-12 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| US11282844B2 (en) * | 2018-06-27 | 2022-03-22 | Ememory Technology Inc. | Erasable programmable non-volatile memory including two floating gate transistors with the same floating gate |
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