KR20170088265A - Nonvolatile memory cell having lateral coupling structure and memory cell array using the nonvolatile memory cell - Google Patents

Abstract

A nonvolatile memory cell includes: a selection transistor which has a selection gate terminal coupled to a word line and a source terminal coupled to a source line; a cell transistor which has a floating gate and a drain terminal coupled to a bit line, and shares a junction terminal with the selection transistor; a first coupling capacitor which is disposed in a first connection line between the word line and the floating gate; and a PN diode and a second coupling capacitor which are disposed in a second connection line between the word line and the floating gate. The anode and the cathode of the PN diode are coupled to the second coupling capacitor and the word line, respectively. The driving characteristics of a device can be improved.

Description

[0001] The present invention relates to a nonvolatile memory cell having a horizontal coupling structure and a memory cell array using the same,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory cell and a memory cell array using the same, and more particularly to a nonvolatile memory cell having a horizontal coupling structure and a memory cell array using the same.

Various structures have been proposed for nonvolatile memory devices capable of electrically programming and erasing data among nonvolatile memory devices in which data stored in memory cells are not erased even when power supply is interrupted. Conventionally, as a unit memory cell structure of a nonvolatile memory device, a stacked gate structure in which a floating gate for storing data and a control gate formed over a floating gate are sequentially stacked is employed. 2. Description of the Related Art [0002] With the recent miniaturization of electronic devices and the development of semiconductor device manufacturing technology, a system-on-chip (SOC) system in which various semiconductor elements, such as logic elements and memory elements, On chip has emerged as a key component of advanced digital products, and accordingly, there is a demand for a manufacturing technology of an embedded non-volatile memory device embedded in a system-on-chip (SOC).

In order to manufacture an embedded nonvolatile memory device, the logic devices and the nonvolatile memory device are fabricated in the same process step. Logic devices, such as MOS devices, typically employ transistors of a single gate structure, and therefore, when integrating a non-volatile memory device employing a stacked gate structure with the logic devices on the same substrate, It becomes complicated. In order to solve such a problem, a single poly nonvolatile memory device, which is a single gate structure, rather than an understandable stacked gate structure, has widened its application range as an embedded nonvolatile memory element. When a single poly nonvolatile memory device is employed, a system-on-a-chip (SOC) can be easily implemented by applying a general complementary metal oxide semiconductor (CMOS) manufacturing process applied to manufacture logic devices.

A problem to be solved by the present application is to provide a semiconductor memory device which has a horizontal coupling ratio between a select gate layer and a floating gate layer and a horizontal coupling ratio during erase operation during a program operation and a read operation, The present invention provides a nonvolatile memory cell having a horizontal coupling structure capable of improving the performance of a nonvolatile memory cell.

Another object of the present invention is to provide a memory cell array using such a nonvolatile memory cell.

A non-volatile memory cell according to an example of this disclosure includes a select transistor having a select gate terminal coupled to a word line, a source terminal coupled to a source line, a floating gate, and a drain terminal coupled to the bit line, A first coupling capacitor disposed in a first connection line between the word line and the floating gate and a second coupling capacitor disposed in a second connection line between the word line and the floating gate, And a second coupling capacitor. The anode and the cathode of the PN diode are coupled to the second coupling capacitor and the word line, respectively.

A nonvolatile memory cell according to an example of the present disclosure includes a first active region arranged to extend along a first direction, a first junction region of a first conductivity type disposed in the first active region, And a third junction region, a floating gate layer disposed to extend along the second direction so as to intersect with the first region of the first active region, and a floating gate layer extending along the second direction so as to intersect the second region of the first active region And a dielectric layer disposed between the floating gate layer and the select gate layer, wherein the select gate layer includes a select gate layer of a first conductivity type, a select gate layer of a second conductivity type, As shown in Fig.

A nonvolatile memory cell array according to an example of the present disclosure includes a plurality of active regions each extending in a first direction and arranged to be spaced apart from each other along a second direction, And a plurality of floating gate layers each disposed to be parallel with each of the select gate layers, and a plurality of floating gate layers, each of the plurality of select gate layers being disposed to be spaced apart from each other along the first direction, And a plurality of dielectric layers, each of the select gate layers being disposed between each of the select gate layers and each of the floating gate layers, wherein each of the select gate layers includes a select gate layer of a first conductivity type and a select gate layer of a second conductivity type And are arranged alternately along the second direction.

A nonvolatile memory cell array according to an example of the present disclosure is configured such that unit cells are arranged at each of intersections of rows separated by bit lines and source lines and columns separated by word lines. The unit cell includes a selection transistor having a selection gate terminal coupled to a word line and a source terminal coupled to a source line, a floating gate, and a drain terminal coupled to the bit line, A first coupling capacitor disposed in a first connection line between the word line and the floating gate and a PN diode and a second coupling capacitor disposed in a second connection line between the word line and the floating gate, . The anode and the cathode of the PN diode are coupled to the second coupling capacitor and the word line, respectively.

A nonvolatile memory cell according to another example of this disclosure includes a select transistor having a select gate terminal coupled to a program word line and a read / erase word line, a source terminal coupled to a source line, a floating gate, A first coupling capacitor disposed in a first connection line between the word line and the floating gate, and a second coupling capacitor disposed between the word line and the floating gate, the first coupling capacitor having a drain terminal coupled to the word line and the floating gate, 2 connection line, and a second coupling capacitor. The anode of the PN diode is coupled to the second coupling capacitor and the program word line, and the cathode of the PN diode is coupled to the select gate terminal and the read / erase word line.

A nonvolatile memory cell array according to another example of the present disclosure includes a plurality of memory cells arranged in rows and columns separated by bit lines and source lines and at intersections of columns separated by program word lines and read / Unit cells are arranged and configured. The unit cell has a select transistor having a select gate terminal coupled to the program word lines and the read / erase word lines, a source terminal coupled to the source line, a floating gate, and a drain terminal coupled to the bit line A first coupling capacitor disposed in a first connection line between the read / erase word line and the floating gate; a second coupling capacitor disposed between the program word line and the read / erase word line; And a second coupling capacitor arranged in series with the PN diode between the program word line and the floating gate. The anode of the PN diode is coupled to the second coupling capacitor and the program word line, and the cathode of the PN diode is coupled to the read / erase word line and select gate terminal.

According to various embodiments, the horizontal coupling ratio between the select gate layer and the floating gate layer during the program operation and the read operation and the horizontal coupling ratio during erase operation are different to improve the operation characteristics of the device Can be provided.

1 is an equivalent circuit diagram of a nonvolatile memory cell according to an example of the present disclosure.
2 is a layout diagram of a nonvolatile memory cell according to an example of the present disclosure.
3 is a cross-sectional view taken along the line I-I 'of FIG.
4 is a cross-sectional view taken along line II-II 'of FIG.
5 is a cross-sectional view taken along line III-III 'of FIG.
6 is a cross-sectional view for explaining a programming operation of a nonvolatile memory cell according to an example of the present disclosure.
7 is a plan view illustrating a coupling mechanism between a select gate layer and a floating gate layer in a programming operation of a nonvolatile memory cell according to an example of this disclosure;
8 is a cross-sectional view for explaining an erasing operation of a nonvolatile memory cell according to an example of the present disclosure.
9 is a plan view illustrating a coupling mechanism between a select gate layer and a floating gate layer in an erase operation of a nonvolatile memory cell according to an example of the present disclosure.
10 is a cross-sectional view illustrating a read operation of a non-volatile memory cell according to an example of the present disclosure.
11 is a layout diagram of a nonvolatile memory cell array according to an example of the present disclosure.
12 is an equivalent circuit diagram of a nonvolatile memory cell array according to an example of the present disclosure.
13 is a diagram for explaining a program operation for a selected unit cell of a nonvolatile memory cell array according to an example of this disclosure.
14 is a diagram for explaining an erase operation for a selected unit cell of a nonvolatile memory cell array according to an example of the present disclosure.
15 is a diagram for illustrating a read operation for a selected unit cell of a nonvolatile memory cell array according to an example of the present disclosure.
16 is an equivalent circuit diagram of a nonvolatile memory cell according to another example of the present disclosure.
17 is a layout diagram of a nonvolatile memory cell according to another example of the present disclosure.
18 is a cross-sectional view taken along the line IV-IV 'of FIG.
19 is a cross-sectional view taken along the line V-V 'in Fig.
20 is a cross-sectional view taken along the line VI-VI 'of FIG.
FIGS. 21 and 22 are cross-sectional views illustrating programming operation of a non-volatile memory cell according to another example of the present disclosure.
23 is a plan view illustrating a coupling mechanism between a select gate layer and a floating gate layer in a programming operation of a nonvolatile memory cell according to another example of the present disclosure.
24 is a cross-sectional view for explaining an erase operation of a nonvolatile memory cell according to another example of the present disclosure.
25 is a plan view illustrating a coupling mechanism between a select gate layer and a floating gate layer in an erase operation of a nonvolatile memory cell according to another example of the present disclosure.
26 is a cross-sectional view illustrating a read operation of a nonvolatile memory cell according to another example of the present disclosure.
27 is a plan view illustrating a coupling mechanism between a select gate layer and a floating gate layer in a read operation of a nonvolatile memory cell according to another example of the present disclosure.
28 is a layout diagram of a nonvolatile memory cell array according to another example of the present disclosure.
29 is an equivalent circuit diagram of a nonvolatile memory cell array according to another example of the present disclosure.
30 is a diagram showing a program operation for a selected unit cell of a nonvolatile memory cell array according to another example of this disclosure.
31 is a diagram for explaining an erasing operation for a selected unit cell of a nonvolatile memory cell array according to another example of this disclosure;
32 is a diagram showing a read operation for a selected unit cell of a nonvolatile memory cell array according to another example of the present disclosure.

In the description of the examples of the present application, descriptions such as " first "and" second "are for distinguishing members, and are not used to limit members or to denote specific orders. Further, the description that a substrate located on the "upper", "lower", or "side" of a member means a relative positional relationship means that the substrate is in direct contact with the member, or another member The present invention is not limited to a particular case. It is also to be understood that the description of "connected" or "connected" to one component may be directly or indirectly electrically or mechanically connected to another component, Separate components may be interposed to form a connection relationship or a connection relationship.

1 is an equivalent circuit diagram of a nonvolatile memory cell according to an example of the present disclosure. Referring to FIG. 1, an equivalent circuit 200 of a nonvolatile memory cell includes a cell transistor 210 and a selection transistor 220. In one example, both the cell transistor 210 and the selection transistor 220 may be configured as an N-channel type MOS transistor structure. The cell transistor 210 has a floating gate FG and a drain terminal D coupled to the bit line BL. The selection transistor 220 has a selection gate terminal SG coupled to the word line WL and a source terminal S coupled to the source line SL. The junction terminal J shared by the cell transistor 210 and the selection transistor 220 corresponds to the source terminal of the cell transistor 210 and the drain terminal of the selection transistor 220. [ A first coupling capacitor Cn is disposed in the first connection line 231 between the selection gate terminal SG and the floating gate FG. A PN diode D1 and a second coupling capacitor Cp are disposed in a second connection line 232 between the selection gate terminal SG and the floating gate FG. The first connection line 231 and the second connection line 232 have a mutually parallel connection relationship. Therefore, the first coupling capacitor Cn and the second coupling capacitor Cp also have a parallel connection relationship. The first coupling capacitor Cn and the second coupling capacitor Cp may have capacitances of different sizes. The first coupling capacitor Cn may have a relatively larger capacitance than the second coupling capacitor Cp. The anode and the cathode of the PN diode D1 are coupled to the second coupling capacitor Cp and the word line WL, respectively.

When a positive bias of a predetermined magnitude is applied to the select gate terminal SG through the word line WL, a reverse bias is applied to the PN diode D1, and the second connection line 232 is opened. Therefore, a coupling bias of a predetermined magnitude by the coupling operation of the first coupling capacitor Cn is induced in the floating gate FG. At this time, the magnitude of the coupling bias is affected by the first coupling ratio of the first coupling capacitor Cn. On the other hand, when a negative bias of a predetermined magnitude is applied to the select gate terminal SG through the word line WL, a forward bias is applied to the PN diode D1, and the word line WL and the second coupling capacitor Cp are short-circuited. Therefore, in addition to the coupling operation of the first coupling capacitor Cn, the floating gate FG is also induced with a coupling coupling of a predetermined magnitude by the coupling operation of the second coupling capacitor Cp. At this time, the magnitude of the coupling bias is affected by the first coupling ratio of the first coupling capacitor Cn and the second coupling ratio of the second coupling capacitor Cp.

In general, the threshold voltage variation ?? VT of the cell transistor 210 is defined as follows.

VT = ?? Q / Ccoupling (Equation 1)

Ccoupling denotes a floating gate FG of the cell transistor 210 and a selection gate terminal SG of the selection transistor 220. The floating gate FG of the cell transistor 210 and the selection gate terminal SG of the selection transistor 220 denote the charge variation in the floating gate FG of the cell transistor 210, ) ≪ / RTI > As shown in Formula 1, when the charge variation in the floating gate FG is the same, the capacitance between the floating gate FG and the selection gate terminal SG becomes large, and the threshold voltage variation ?? VT becomes small. On the other hand, if the capacitance between the floating gate FG and the selection gate terminal SG becomes small, the threshold voltage variation? VT becomes large.

As described above, in the nonvolatile memory cell according to the present embodiment, the magnitude of the coupling bias induced in the floating gate FG depends on whether the polarity of the bias applied to the word line WL is positive or negative Other coupling ratios are applied and determined. As the cell transistor 210 and the selection transistor 220 are all configured in an N-channel type MOS transistor structure, the program operation and the read operation can be performed by applying a positive bias to the word line WL. On the other hand, the erase operation can be performed by applying a negative bias to the word line WL. Therefore, the coupling bias induced in the floating gate FG of the cell transistor 210 during the program and read operations and the erase operation is determined by applying different coupling ratios. Particularly, in the erasing operation, the coupling operation of the first capacitor Cn and the second capacitor Cp are performed together, so that a high coupling ratio is applied. The erase operation is performed by a band-to-band tunneling (BTBT) mechanism. Generally, the same charge variation (" More time to derive the program Q, for example about 100 times more program time. However, in this example, the coupling operation of the second capacitor Cp is performed at the same time during the erase operation, so that the capacitance Ccoupling between the floating gate FG and the selection gate terminal SG can be increased , Thereby shortening the time required to represent the same threshold voltage variation (VT). In the read operation, a small coupling ratio due to the coupling operation due to only the first capacitor (Cn) is applied, thereby reducing the error range of the read operation due to the variation of the threshold voltage and suppressing the read disturb phenomenon .

2 is a layout diagram of a nonvolatile memory cell according to an example of the present disclosure. 3 to 5 are cross-sectional views taken along line I-I ', line II-II', and line III-III 'of FIG. 2, respectively. 2 to 5, a P-type semiconductor region, for example, a P-type well region 104, is disposed in an upper region of the substrate 102. [ In the upper region of the substrate 102, a trench isolation layer 106 which defines the first active region 111 and the second active region 112 is disposed. Both the first active region 111 and the second active region 112 are disposed in the P-type well region 104. The first active region 111 has a planar shape of a stripe shape extending long along the first direction. The second active region 112 may have a planar shape in the form of a box. The second active region 112 is arranged to be spaced apart from the first active region 111 along the first direction.

In the first active region 111, the N + -type first junction region 131, the N + -type second junction region 132, and the N + -type third junction region 133 are disposed apart from each other along the first direction. In one example, the N + -type first junction region 131 and the N + -type third junction region 133 may be a drain region and a source region, respectively. The N + -type first junction region 131 and the N + -type third junction region 133 are disposed at both edge portions of the first active region 111. The N + -type second junction region 132 is disposed between the N + -type first junction region 131 and the N + -type third junction region 133. The N + -type second junction region 132 is spaced apart from the N + -type first junction region 131 by the first channel region 141 along the first direction. The N + -type second junction region 132 is spaced apart from the N + -type third junction region 133 by the second channel region 142 along the first direction. A P + type contact region 134 is disposed in the second active region 112. The N + -type first junction region 131 and the N + -type third junction region 133 are coupled to the bit line BL and the source line SL, respectively. The P + type contact region 134 is coupled to ground.

The floating gate layer 152 and the select gate layer 162 are arranged to intersect the first active region 111. The floating gate layer 152 and the select gate layer 162 may each have a planar structure in the form of a stripe extending elongated along a second direction that intersects the first direction. The floating gate layer 152 and the select gate layer 162 are spaced apart along the first direction. The floating gate layer 152 overlaps the first channel region 141 of the first active region 111. The select gate layer 162 overlaps the second channel region 142 of the first active region 111. [ A first gate insulating layer 151 is disposed under the floating gate layer 152. A second gate insulating layer 161 is disposed under the select gate layer 162. The floating gate layer 152 has an isolated floating state without direct electrical coupling. While the select gate layer 162 is coupled to the word line WL. Floating gate layer 152 and select gate layer 162 are comprised of a single poly structure consisting of a single layer of polysilicon layer. The spacing between one side of the mutually opposing floating gate layer 152 and one side of the select gate layer 162 may be substantially constant along the second direction. A dielectric layer 170 is disposed between the floating gate layer 152 and the select gate layer 162.

The select gate layer 162 may include an N + type select gate layer 162N and a P + type select gate layer 162P that are separated along the second direction. The boundary between the N + type select gate layer 162N and the P + type select gate layer 162P is located on the trench isolation layer 106 spaced apart from one side of the first active region 111 by a predetermined distance. An N + type selection gate layer 162N is arranged in a region overlapping the first active region 111 from this boundary. A P + type selection gate layer 162P is disposed in a region not overlapping the first active region 111 from this boundary. 5, the first length L1 of the N + type select gate layer 162N, which is measured along the second direction overlapping with the floating gate layer 152, Type select gate layer 162P is greater than the second length L2 of the P + type select gate layer 162P measured along two directions. The N + type select gate layer 162N is coupled to the word line WL. Therefore, the P + type select gate layer 162P can be connected to the word line WL only through the N + type select gate layer 162N. The N + type select gate layer 162N and the P + type select gate layer 162P constitute the PN diode D1. The anode and the cathode of the PN diode D1 correspond to the P + type select gate layer 162P and the N + type select gate layer 162N, respectively. Therefore, when a positive bias is applied through the word line WL, a bias is not applied to the P + type selection gate layer 162P by the PN diode D1 to which a reverse bias is applied and only the N + type selection gate layer 162N is biased Is applied. On the other hand, when a negative bias is applied through the word line WL, a bias is applied to both the P + type select gate layer 162P and the N + type select gate layer 162P by the PN diode D1 which is forward-biased.

The floating gate layer 152 may include a first floating gate layer 152A and a second floating gate layer 152B. The dielectric layer 170 may include a first dielectric layer 170A and a second dielectric layer 170B. The first floating gate layer 152A and the first dielectric layer 170A may be defined as portions overlapping with the N + type select gate layer 162N along the first direction. The second floating gate layer 152B and the second dielectric layer 170B may be defined as a portion overlapping the P + type select gate layer 162P along the first direction. Therefore, the boundary line of the first floating gate layer 152A and the second floating gate layer 152B and the boundary line of the first dielectric layer 170A and the second dielectric layer 170B are the N + type select gate layer 162N and the P + And coincides with a line extending from the boundary line of the select gate layer 162P. The horizontal lamination structure of the first floating gate layer 152A, the first dielectric layer 170A, and the N + type select gate layer 162N constitutes the first coupling capacitor Cn. The horizontal stacking structure of the second floating gate layer 152B, the second dielectric layer 170B, and the P + type select gate layer 162P constitutes a second coupling capacitor Cp. Accordingly, the entire capacitor formed by the horizontal lamination structure of the floating gate layer 152, the dielectric layer 170, and the select gate layer 162 is connected to the first coupling capacitor Cn and the second coupling capacitor Cp, .

The nonvolatile memory device 100 according to this example may be an example for implementing the equivalent circuit 200 of the nonvolatile memory device of FIG. The N + -type first junction region 131, the N + -type second junction region 132, the first channel region 141, the first gate insulating layer 151, and the floating gate layer 152 are equivalent to those of FIG. 1 The cell transistor 210 can be configured in a circuit. The N + -type first junction region 131 and the N + -type second junction region 132 may correspond to the drain terminal D and the junction terminal J of the cell transistor 210, respectively. The floating gate layer 152 may correspond to the floating gate FG of the cell transistor 210 in the equivalent circuit of FIG. The N + -type second junction region 132, the N + -type third junction region 133, the second channel region 142, the second gate insulating layer 161, and the select gate layer 162 are equivalent to those of FIG. 1 The selection transistor 220 can be configured in the circuit. The N < + > -type third junction region 133 may correspond to the source terminal S of the selection transistor 220. [ The select gate layer 162 may correspond to the select gate terminal SG of the select transistor 220 in the equivalent circuit of Fig.

6 is a cross-sectional view for explaining a programming operation of a nonvolatile memory cell according to an example of the present disclosure. And FIG. 7 is a plan view illustrating a coupling mechanism between a select gate layer and a floating gate layer in a programming operation of a nonvolatile memory cell according to an example of this disclosure. In Fig. 6, the same reference numerals as those in Fig. 3 denote the same components. The program operation according to this example can be performed by a hot electron injection (HEI) mechanism. 6, a positive program voltage (+ Vpp) is applied to the word line WL and a positive program bit line voltage (+ Vpb) is applied to the bit line BL for a program operation for the nonvolatile memory cell. . A ground voltage, for example, 0 V, is applied to the source line SL. In one example, the positive program voltage (+ Vpp) and the positive program bit line voltage (+ Vpb) may be approximately + 9V and + 4.5V, respectively. The positive programming voltage (+ Vpp) applied through the word line WL causes the second channel region 142 between the second N + type junction region 132 and the third N + A selection transistor 182 is formed, and the selection transistor 220 is turned on. As a result, 0 V applied to the source line SL is induced in the second N + type junction region 132.

As shown in FIG. 7, as the positive program voltage (+ Vpp) is applied to the N + type select gate layer 162N from the word line WL, the PN diode D1 is applied with a reverse bias and is opened . Therefore, the positive program voltage (+ Vpp) from the word line WL is applied only to the N + type select gate layer 162N and not to the P + type select gate layer 162P. The bias voltage is not applied to the P + type select gate layer 162P, and thus the second coupling capacitor composed of the second floating gate layer 152B, the second dielectric layer 170B, and the P + type select gate layer 162P, (Cp) does not perform the coupling operation. The coupling bias induction to the floating gate layer 152 is thus accomplished by forming a first floating gate layer 152A, a first dielectric layer 170A, and an N + type select gate layer 162N The first coupling capacitor Cn has a coupling function. That is, the magnitude of the coupling bias induced in the floating gate layer 152 is determined by the magnitude of the positive program voltage (+ Vpp) and the coupling ratio of the first coupling capacitor Cn.

Referring again to FIG. 6, as the positive coupling programming voltage (+ Vc1) is induced in the floating gate layer 152, the voltage between the first N + type junction region 131 and the second N + type junction region 132 An inversion layer 181 is formed in the one-channel region 141. As a result, hot electrons are generated in the inversion layer 181 adjacent to the first junction region 131. These hot electrons are injected into the floating gate layer 152 through the first gate insulating layer 151 by the vertical electric field by the positive coupling program voltage (+ Vc1). As the hot electrons are implanted into the floating gate layer 152, the non-volatile memory cell is programmed and the threshold voltage value in the first channel region 141 is higher than before it was programmed.

8 is a cross-sectional view for explaining an erasing operation of a nonvolatile memory cell according to an example of the present disclosure. And FIG. 9 is a plan view illustrating a coupling mechanism between a select gate layer and a floating gate layer in an erasing operation of a non-volatile memory cell according to an example of the present disclosure. In Fig. 8, the same reference numerals as those in Fig. 3 denote the same components. The erase operation according to this example can be performed by a band-to-band tunneling (BTBT) mechanism. 8, a negative erase voltage (-Vee) is applied to the word line WL and a positive erase bit line voltage (-Vee) is applied to the bit line BL in order to erase the nonvolatile memory cell. + Veb) is applied. A ground voltage, for example, 0 V, is applied to the source line SL. In one example, the negative erase voltage (-Vee) and the positive erase bit line voltage (+ Veb) may be approximately -9V and + 6V, respectively. As the negative erase voltage (-Vee) is applied through the word line WL, the selection transistor 220 maintains the turn-off state. Thus, the second N + type junction region 132 remains in a floating state.

9, as the negative erase voltage -Vee from the word line WL is applied to the N + type select gate layer 162N, the PN diode D1 is short-circuited by applying a forward bias, do. Therefore, a negative erase voltage (-Vee) from the word line WL is applied to both the N + type select gate layer 162N and the P + type select gate layer 162P. The coupling bias induction to the floating gate layer 152 is thus accomplished by forming a first floating gate layer 152A, a first dielectric layer 170A, and an N + type select gate layer 162N The first coupling capacitor Cn has a coupling function. The coupling bias induction to the floating gate layer 152 may also be achieved by forming a second floating gate layer 152B, a second dielectric layer 170B and a P + type select gate layer 162P The second coupling capacitor Cp is also made by a coupling operation. That is, the magnitude of the coupling bias induced in the floating gate layer 152 is determined by the magnitude of the negative erase voltage -Vee, the coupling ratio of the first coupling capacitor Cn and the coupling ratio of the second coupling capacitor Cp, Is determined by the coupling ratio.

Referring again to FIG. 8, no inversion layer is formed in the first channel region 141 as the negative coupling-erase voltage (-Vc2) is induced in the floating gate layer 152. As the positive erase bit line voltage (+ Veb) from the bit line BL is applied to the first N + type junction region 131, the potential difference between the second channel region 142 and the N + type third junction region 133 A depletion is generated from the junction of Accordingly, an energy band bending greater than the energy gap occurs, so that electrons in the floating gate layer 152 pass through the first gate insulating layer 151 and are tunneled to the first N + type junction region 131 . As electrons in the floating gate layer 152 are tunneled, the non-volatile memory cell is in an erase state and the threshold voltage value in the first channel region 141 is lower than before erasing.

10 is a cross-sectional view illustrating a read operation of a non-volatile memory cell according to an example of the present disclosure. In Fig. 10, the same reference numerals as those in Fig. 3 denote the same components. 10, a positive read voltage (+ Vrr) is applied to the word line WL and a positive read bit line voltage (+ Vrb) is applied to the bit line BL for the read operation for the nonvolatile memory cell . A ground voltage, for example, 0 V, is applied to the source line SL. The positive read voltage + Vrr is a ratio of the threshold voltage magnitude in the first channel region 141 of the cell transistor 210 in the programmed state to the threshold voltage magnitude in the first channel region 141 of the cell transistor 210 in the erase state. Lt; RTI ID = 0.0 > of < / RTI > In one example, the positive lead voltage (+ Vrr) and the positive lead bit line voltage (+ Vrb) may be approximately + 4V and + 1V, respectively. The second channel region 142 between the second N + type junction region 132 and the third N + type junction region 133 is formed with the positive lead voltage (+ Vrr) applied through the word line WL, A selection transistor 182 is formed, and the selection transistor 220 is turned on. As a result, 0 V applied to the source line SL is induced in the second N + type junction region 132.

The positive lead voltage + Vrr from the word line WL is applied to the N + type select gate layer 162N from the word line WL as described with reference to Fig. Type select gate layer 162N is applied only to the N + type select gate layer 162N. Thus, the coupling bias induction to the floating gate layer 152 is effected by the coupling operation of the first coupling capacitor Cn. That is, the magnitude of the coupling bias induced in the floating gate layer 152 is determined by the magnitude of the positive lead voltage (+ Vrr) and the coupling ratio of the first coupling capacitor Cn. When the positive coupling lead voltage (+ Vc3) is induced in the floating gate layer 152, the first channel region 141 may have an inversion layer depending on the threshold voltage value of the first channel region 141, Do not. For example, even if a positive coupling lead voltage (+ Vc3) is applied to the floating gate layer 152 in a program state in which the threshold voltage value is increased, no inversion layer is formed in the first channel region 141. Therefore, no current flows between the bit line BL and the source line SL. On the other hand, in the erase state where the threshold voltage value is lowered, since the positive coupling lead voltage (+ Vc3) is applied to the floating gate layer 152, the inversion layer 141 is formed in the first channel region 131. Therefore, a current flows between the bit line BL and the source line SL each of which is applied with positive lead bit line voltages (+ Vrb) and 0 V, respectively. In this way, the status of the nonvolatile memory cell can be read by sensing the current flow between the bit line BL and the source line SL.

11 is a layout diagram of a nonvolatile memory cell array according to an example of the present disclosure. The nonvolatile memory cell array 400 according to this example has a matrix form in which each of the unit cells is disposed at each of intersections of two rows and four columns. However, this is only an example, and may have a matrix form consisting of more than two rows and more than four columns. Referring to FIG. 11, a first active region 411-10 and a second active region 411-20 are disposed in a P-type well region 404. The P-type well region 404 may be shared by all the unit cells. The first active region 411-10 and the second active region 411-20 have a stripe shape elongated along the first direction. The first active region 411-10 and the second active region 411-20 are arranged to be spaced apart from each other in a second direction intersecting the first direction. Although not shown in the drawing, the first active region 411-10 and the second active region 411-20 may be defined by the trench isolation layer. The first active region 411-10 is shared by the unit cells constituting the first row and the second active region 411-20 is shared by the unit cells constituting the second row.

A plurality of select gate layers 462 are spaced apart from one another along the first direction. The select gate layer 462 has a planar structure in the form of a stripe extending long along the second direction. Thus, the select gate layer 462 intersects the first active region 411-10 and the second active region 411-20. The select gate layer 462 is coupled to the unit cells constituting any one of the columns. The select gate layer 462 is formed by alternately arranging N + type select gate layers 462N doped with N + type and P + type select gate layers 462P doped with P + type along the second direction. One of the N + type select gate layers 462N overlaps the first active region 411-10 and the other overlaps the second active region 411-20. The N + type select gate layer 462N overlapping the first active region 411-10 is coupled to the unit cells constituting the first row. The N + type select gate layer 462N overlapping the second active region 411-20 is coupled to the unit cells constituting the second row. The P + type select gate layer 462P is disposed between the N + type select gate layers 462N and therefore does not overlap with the first active region 411-10 and the second active region 411-20. The P + type select gate layer 462P is commonly coupled to the unit cells constituting the first row and the unit cells constituting the second row. The N + type select gate layer 462N and the P + type select gate layer 462P can constitute a PN diode. Each of the N + type select gate layers 462N is commonly coupled to a word line of one of the word lines WL1-WL4 through a contact.

A plurality of first floating gate layers 452-1 and second floating gate layers 452-2 are disposed to be spaced apart from each other along the first direction. The first floating gate layer 452-1 and the second floating gate layer 452-2 are mutually spaced along the second direction. The first floating gate layer 452-1 is disposed in parallel with the select gate layer 462 while intersecting the first active region 411-10. Although not shown, a dielectric layer is disposed between the first floating gate layer 452-1 and the select gate layer 462 to form a coupling capacitor. The second floating gate layer 452-2 is disposed in parallel with the select gate layer 462 while intersecting the second active region 411-20. Although not shown in the drawing, a dielectric layer is disposed between the second floating gate layer 452-2 and the select gate layer 462 to constitute a coupling capacitor.

The first active region 411-10 includes a first N + type junction region 431, a second N + type junction region 432, and a third N + type junction region 432 separated by the select gate layer 462 and the first floating gate layer 452-1. ), And a third N + type junction region 433. The second active region 411-20 includes a first N + type junction region 431, a second N + type junction region 432, and a second N + type junction region 432 separated by the select gate layer 462 and the second floating gate layer 452-2. ), And a third N + type junction region 433. The first N + type junction region 431 is disposed in the region adjacent to the first floating gate layer 452-1. A second N + type junction region 432 is disposed between the first floating gate layer 452-1 and the select gate layer 462. [ The third N + type junction region 433 is disposed in the region adjacent to the select gate layer 462. [ The first N + type junction region 431 and the third N + type junction region 433 in the first active region 411-10 are coupled to the first bit line BL1 and the first source line SL1, respectively. The first N + type junction region 431 and the third N + type junction region 433 in the second active region 411-20 are coupled to the second bit line BL2 and the second source line SL2, respectively.

12 is an equivalent circuit diagram of a nonvolatile memory cell array according to an example of the present disclosure. Referring to FIG. 12, the equivalent circuit 500 of the nonvolatile memory cell array according to the present example has a matrix form in which each unit cell is disposed at each of intersections of two rows and four columns. However, this is only an example, and may have a matrix form consisting of more than two rows and more than four columns. The rows may be separated by the bit lines BL1 and BL2 and the source lines SL1 and SL2. The columns may be separated by the word lines WL1-WL4. Each of the plurality of unit cells 611-614 and 621-624 has the same configuration. For example, the unit cell 611 in the first row and the first column has the cell transistor 510-11 and the selection transistor 520-11. The cell transistor 510-11 and the selection transistor 520-11 may be formed of an N-channel type MOS transistor. The cell transistor 510-11 has a floating gate FG, a junction terminal J, and a drain terminal D. The selection transistor 520-11 has a selection gate terminal SG, a junction terminal J, and a source terminal S. The source terminal S and the drain terminal D are coupled to the first source line SL1 and the first bit line BL1, respectively. The junction terminal J has a floating state. The selection gate terminal SG is coupled to the first word line WL1. A first coupling capacitor Cn and a second coupling capacitor Cp are arranged in parallel between the floating gate FG and the selection gate terminal SG. A PN diode D1 is disposed between the selection gate terminal SG and the second coupling capacitor Cp. The anode and the cathode of the PN diode D1 are coupled to the second coupling capacitor Cp and the selection gate terminal SG, respectively.

The source terminals S of each of the unit cells 611-614 constituting the first row are commonly coupled to the first source line SL1. The drain terminal D of each of the unit cells 611-614 constituting the first row is commonly coupled to the first bit line BL1. The source terminals S of each of the unit cells 621-624 constituting the second row are commonly coupled to the second source line SL2. The drain terminal D of each of the unit cells 621-624 constituting the second row is commonly coupled to the second bit line BL2. The select gate terminals SG of the unit cells 611 and 621 constituting the first column are commonly coupled to the first word line WL1. The select gate terminals SG of the unit cells 612 and 622 constituting the second column are commonly coupled to the second word line WL2. The select gate terminals SG of the unit cells 613 and 623 constituting the third column are commonly coupled to the third word line WL3. The select gate terminals SG of the unit cells 614 and 624 constituting the fourth column are commonly coupled to the fourth word line WL4.

13 is a diagram for explaining a program operation for a selected unit cell of a nonvolatile memory cell array according to an example of this disclosure. In Fig. 13, the same reference numerals as those in Fig. 12 denote the same components. 13, in order to program the selection unit cell 611 of the first row and the first column, a positive program voltage (+ Vpp) is applied to the first word line WL1 coupled to the selection unit cell 611 And applies a ground voltage, for example, 0 V, to the remaining word lines WL2-WL4. Positive program bit line voltages (+ Vpb) and 0V are applied to the first bit line (BL1) and the first source line (SL1) coupled to the selection unit cell 611, respectively. And 0V is applied to the remaining second bit line BL2 and the second source line SL2. The positive program voltage (+ Vpp) from the first word line WL1 is applied to the select gate terminal SG of the select transistor 520-11 to turn on the select transistor 520-11. The positive programming voltage + Vpp applied to the selection gate terminal SG of the selection transistor 520-11 is set to the floating state of the cell transistor 510-11 by the coupling operation of the first coupling capacitor Cn, Causing the coupling voltage to be induced at the gate (FG). The PN diode D1 is opened as the reverse bias is applied. In such a bias condition, the cell transistor 510-11 is programmed by a hot electron injection (HEI) mechanism.

In the case of other unselected unit cells sharing the first bit line BL1 and the first source line SL1, such as the unselected unit cells 612 of the first row and the second column, with the selected unit cell 611, And 0V is applied to the second word line WL2 so that the selection transistor 510-12 maintains the turn-off state. Therefore, the coupling voltage is not induced in the floating gate FG of the cell transistor 520-12, and the unselected unit cell 612 is program inhibited. In the case of other unselected unit cells sharing the first word line WL1 with the selected unit cell 611, for example, the unselected unit cell 621 of the second row and the first column, As the positive program voltage (+ Vpp) is applied, the coupling voltage is induced in the floating gate FG of the cell transistor 510-21. Thus, both the cell transistor 510-21 and the selection transistor 520-21 are turned on. However, since there is no potential difference between the second bit line BL2 and the second source line SL2, hot electrons are not generated, and thus the unselected unit cell 621 is program inhibited.

14 is a diagram for explaining an erase operation for a selected unit cell of a nonvolatile memory cell array according to an example of the present disclosure. In Fig. 14, the same reference numerals as those in Fig. 12 denote the same components. 14, a negative erase voltage (-Vee) is applied to the first word line WL1 coupled to the selection unit cell 611 in order to erase the selection unit cell 611 of the first row and the first column. And applies a ground voltage, for example, 0V, to the remaining word lines WL2-WL4. A positive erase bit line voltage (+ Veb) and 0V are applied to the first bit line (BL1) and the first source line (SL1) coupled to the selection unit cell 611, respectively. And 0V is applied to the remaining second bit line BL2 and the second source line SL2. As the negative erase voltage -Vee is applied from the first word line WL1 to the select gate terminal SG of the select transistor 520-11, forward bias is applied to the PN diode D1, It is short. The coupling operation of the second coupling capacitor Cp is performed in addition to the coupling operation of the first coupling capacitor Cn so that the floating gate FG of the cell transistor 510-11 is negatively charged Coupling voltage is induced. Due to the potential difference between the negative coupling voltage of the floating gate FG and the positive erase bit line voltage (+ Veb) applied to the first bit line BL1, the cell transistor 510-11 performs band- (BTBT) mechanism.

In the case of other unselected unit cells sharing the first bit line BL1 and the first source line SL1, such as the unselected unit cells 612 of the first row and the second column, with the selected unit cell 611, And 0V is applied to the second word line WL2 so that the selection transistor 510-12 maintains the turn-off state. Therefore, the coupling voltage is not induced in the floating gate FG of the cell transistor 520-12. Therefore, only the potential difference of the positive erase bit line voltage (+ Veb) is generated between the floating gate FG of the cell transistor 520-12 and the first bit line BL1. This potential difference does not cause band-to-band tunneling (BTBT) in the cell transistor 520-12, so that the non-selected unit cell 612 is not erased. In the case of other unselected unit cells sharing the first word line WL1 with the selected unit cell 611, for example, the unselected unit cell 621 of the second row and the first column, As the negative bias voltage (-Vee) is applied, a negative coupling voltage is induced in the floating gate FG of the cell transistor 510-21. However, as 0V is applied to the second bit line BL2, a potential difference of the negative erase voltage -Vee is applied between the floating gate FG of the cell transistor 520-12 and the first bit line BL1 It only happens. This potential difference does not cause band-to-band tunneling (BTBT) in the cell transistor 520-12, so that the non-selected unit cell 612 is not erased.

Although it has been described in the present example that the unit cells 611 of a specific unit cell, for example, the first row and the first column, are selectively erased, erase operations can be collectively performed on all the unit cells, if necessary . To this end, a negative erase voltage -Vee is applied to all the word lines WL1-WL4 and a positive erase bit line voltage + Veb is applied to all the bit lines BL1 and BL2. And applies a ground voltage, for example, 0 V, to all the source lines SL1 and SL2. According to such a bias condition, the cell transistors of all the unit cells can be collectively erased by the above-described band-to-band tunneling (BTBT) mechanism.

15 is a diagram for illustrating a read operation for a selected unit cell of a nonvolatile memory cell array according to an example of the present disclosure. In Fig. 15, the same reference numerals as those in Fig. 12 denote the same components. 15, a positive read voltage + Vrr is applied to the first word line WL1 coupled to the selection unit cell 611 in order to read the selection unit cell 611 of the first row and the first column. And applies a ground voltage, for example, 0 V, to the remaining word lines WL2-WL4. The positive lead bit line voltages + Vrb and 0V are applied to the first bit line BL1 and the first source line SL1 coupled to the selection unit cell 611, respectively. And 0V is applied to the remaining second bit line BL2 and the second source line SL2.

The positive read voltage (+ Vrr) from the first word line WL1 turns on the selection transistor 520-11. The positive lead voltage (+ Vrr) causes the positive coupling voltage to be induced in the floating gate FG of the cell transistor 510-11 by the coupling operation of the first coupling capacitor Cn. The PN diode D1 is opened as the reverse bias is applied and the coupling operation by the second coupling capacitor Cp is not performed. As the positive coupling voltage is induced in the floating gate FG of the cell transistor 510-11, the cell transistor 510-11 is turned on according to the magnitude of the threshold voltage of the cell transistor 510-11, And maintains the turn-off state. When the cell transistor 510-11 is programmed, the cell transistor 510-11 maintains the turn-off state. On the other hand, when the cell transistor 510-11 is in an erased state, the cell transistor 510-11 is turned on. When the cell transistor 510-11 maintains the turn-off state, a current path is not formed between the first bit line BL1 and the first source line SL1. On the other hand, when the cell transistor 510-11 is turned on, a current path is formed between the first bit line BL1 and the first source line SL1. Since there is a potential difference between the positive read bit line voltage (+ Vrb) between the first bit line (BL1) and the first source line (SL1), a current flows through the current path. Thus, the state of the cell transistor 510-11 of the selected unit cell 611 can be read by sensing the current between the first bit line BL1 and the first source line SL1.

In the case of other unselected unit cells sharing the first bit line BL1 and the first source line SL1, such as the unselected unit cells 612 of the first row and the second column, with the selected unit cell 611, As 0V is applied to the second word line WL2, the cell transistor 510-12 and the selection transistor 520-12 of the non-selected unit cell 612 all remain turned off. The current path between the first bit line BL1 and the first source line SL1 by the unselected unit cell 612 is not formed and does not affect the read operation of the selected unit cell 611. [

16 is an equivalent circuit diagram of a nonvolatile memory cell according to another example of the present disclosure. 16, an equivalent circuit 2000 of a nonvolatile memory cell is composed of a cell transistor 2100 and a selection transistor 2200. [ In one example, the cell transistor 2100 and the selection transistor 2200 may all be configured as an N-channel type MOS transistor structure. The cell transistor 2100 has a floating gate FG and a drain terminal D coupled to the bit line BL. The selection transistor 2200 has a selection gate terminal SG coupled to the read / erase word line WL_RE and the program word line WL_P and a source terminal S coupled to the source line SL. The read / erase word line WL_RE is directly coupled to the select gate terminal SG, but the program word line WL_P is coupled through the PN diode D1. The junction terminal J shared by the cell transistor 2100 and the selection transistor 2200 corresponds to the source terminal of the cell transistor 2100 and the drain terminal of the selection transistor 2200. A first coupling capacitor Cn is disposed in the first connection line 2310 between the selection gate terminal SG and the floating gate FG. A PN diode D1 and a second coupling capacitor Cp are disposed in a second connection line 2320 between the selection gate terminal SG and the floating gate FG. The first connection line 2310 and the second connection line 2320 have mutually parallel connection relationship. Therefore, the first coupling capacitor Cn and the second coupling capacitor Cp also have a parallel connection relationship. The first coupling capacitor Cn and the second coupling capacitor Cp may have capacitances of different sizes. The first coupling capacitor Cn may have a relatively larger capacitance than the second coupling capacitor Cp. The anode of the PN diode D1 is coupled to the second coupling capacitor Cp and the program word line WL_P. The cathode of the PN diode D1 is coupled to the read / erase word line WL_RE.

When a positive bias of a predetermined magnitude is applied through the read / erase word line WL_RE, a reverse bias is applied to the PN diode D1, and the second connection line 2320 is opened. Therefore, a coupling bias of a predetermined magnitude by the coupling operation of the first coupling capacitor Cn is induced in the floating gate FG. At this time, the magnitude of the coupling bias is affected by the first coupling ratio of the first coupling capacitor Cn. On the other hand, when a positive bias of a predetermined magnitude is applied through the program word line WL_P or a negative bias of a predetermined magnitude is applied through the read / erase word line WL_RE, a forward bias is applied to the PN diode D1 And the second connection line 2320 is short-circuited. Therefore, in addition to the coupling operation of the first coupling capacitor Cn, the floating gate FG is also induced with a coupling coupling of a predetermined magnitude by the coupling operation of the second coupling capacitor Cp. At this time, the magnitude of the coupling bias is affected by the first coupling ratio of the first coupling capacitor Cn and the second coupling ratio of the second coupling capacitor Cp.

In the nonvolatile memory cell according to this example, different coupling ratios are applied during programming and erase operations and during the read operation. As the cell transistor 2100 and the selection transistor 2200 are both formed of an N-channel type MOS transistor structure, the program operation and the read operation are performed by applying a positive voltage to the program word line WL_P and the read / Bias is applied. On the other hand, the erase operation is performed by applying a negative bias to the read / erase word line WL_RE. The magnitude of the coupling bias induced in the floating gate FG of the cell transistor 2100 during the program and erase operation and the read operation in such an operation process is determined by applying different coupling ratios. In particular, since the coupling operation of the first capacitor Cn and the second capacitor Cp is performed at the same time during the program operation and the erase operation, a high coupling ratio is applied. On the other hand, during the read operation, a small coupling ratio due to the coupling operation due to only the first capacitor Cn is applied. The operation of the nonvolatile memory cell according to this embodiment will be described in more detail below.

17 is a layout diagram of a nonvolatile memory cell according to another example of the present disclosure. 18 to 20 are cross-sectional views taken along line IV-IV ', line V-V', and line III-III 'of FIG. 16, respectively. Referring to FIGS. 17 to 20, a P-type semiconductor region, for example, a P-type well region 1040 is disposed in an upper region of the substrate 1020. A trench isolation layer 1060 is defined in the upper region of the substrate 1020 to define a first active region 1110 and a second active region 1120. The first active region 1110 and the second active region 1120 are all disposed in the P-type well region 1040. The first active region 1110 has a planar shape of a stripe shape extending long along the first direction. The second active region 1120 may have a box-like planar shape. The second active region 1120 is spaced apart from the first active region 1110 along the first direction.

The first active region 1110 is disposed such that the N + type first junction region 1310, the N + type second junction region 1320, and the N + type third junction region 1330 are spaced apart from each other along the first direction. In one example, the N + -type first junction region 1310 and the N + -type third junction region 1330 may be a drain region and a source region, respectively. The N < + > -type first junction region 1310 and the N < + > -type third junction region 1330 are disposed at both edge portions of the first active region 1110. The N + -type second junction region 1320 is disposed between the N + -type first junction region 1310 and the N + -type third junction region 1330. The N + -type second junction region 1320 is spaced apart from the N + -type first junction region 1310 by the first channel region 1410 along the first direction. The N + -type second junction region 1320 is spaced apart from the N + -type third junction region 1330 by the second channel region 1420 along the first direction. A P + type contact region 1340 is disposed in the second active region 1120. The N + -type first junction region 1310 and the N + -type third junction region 1330 are coupled to the bit line BL and the source line SL, respectively. The P + type contact region 1340 is coupled to ground.

The floating gate layer 1520 and the select gate layer 1620 are disposed to intersect the first active region 1110. The floating gate layer 1520 and the select gate layer 1620 may each have a planar structure in the form of a stripe extending long along a second direction that intersects the first direction. The floating gate layer 1520 and the select gate layer 1620 are spaced apart along the first direction. The floating gate layer 1520 overlaps the first channel region 1410 of the first active region 1110. The select gate layer 1620 overlaps the second channel region 1420 of the first active region 1110. [ A first gate insulating layer 1510 is disposed under the floating gate layer 1520. A second gate insulating layer 1610 is disposed under the select gate layer 1620. The floating gate layer 1520 has an isolated floating state without direct electrical coupling. While the select gate layer 1620 is coupled to the program word line WL_P and the read / erase word line WL_RE. Floating gate layer 1520 and select gate layer 1620 are comprised of a single poly structure consisting of a single layer of polysilicon layer. The spacing between one side of the mutually opposing floating gate layer 1520 and one side of the select gate layer 1620 may be substantially constant along the second direction. A dielectric layer 1700 is disposed between the floating gate layer 1520 and the select gate layer 1620.

The select gate layer 1620 may include an N + type select gate layer 1620N and a P + type select gate layer 1620P that are separated along the second direction. The boundary between the N + type select gate layer 1620N and the P + type select gate layer 1620P is located on the trench isolation layer 1060 which is spaced apart from the one side of the first active region 1110 by a predetermined distance. An N + type select gate layer 1620N is arranged in a region overlapping the first active region 1110 from this boundary. A P + type selection gate layer 1620P is arranged in a region not overlapping the first active region 1110 from this boundary. 20, the first length L1 of the N + type select gate layer 1620N, which is measured along the second direction overlapping the floating gate layer 1520, Is greater than the second length L2 of the P + type select gate layer 1620P measured along two directions. P + type select gate layer 1620P is coupled to program word line WL_P. N + type select gate layer 1620N is coupled to the read / erase word line WL_RE. The P + type select gate layer 1620P and the N + type select gate layer 1620N constitute a PN diode D1. The anode and the cathode of the PN diode D1 correspond to the P + type select gate layer 1620P and the N + type select gate layer 1620N, respectively. Thus, the P + type select gate layer 1620P is directly applied with a bias of a predetermined magnitude from the program word line WL_P, and the N + type select gate layer 1620N is biased from the read / erase word line WL_RE . When a positive bias is applied through the read / erase word line WL_RE, a bias is not applied to the P + type select gate layer 1620P by the PN diode D1 which is reverse biased and the N + type select gate layer 1620N The bias is applied only to the gate electrode. On the other hand, when a positive bias is applied through the program word line WL_P or a negative bias is applied through the read / erase word line WL_RE, the P + type selection gate layer A bias is applied to both the N + type select gate layer 1620P and the N + type select gate layer 1620P.

The floating gate layer 1520 may include a first floating gate layer 1520A and a second floating gate layer 1520B. The dielectric layer 1700 may include a first dielectric layer 1700A and a second dielectric layer 1700B. The first floating gate layer 1520A and the first dielectric layer 1700A may be defined as portions overlapping with the N + type select gate layer 1620N along the first direction. The second floating gate layer 1520B and the second dielectric layer 1700B may be defined as a portion overlapping the P + type select gate layer 1620P along the first direction. Therefore, the boundary line between the first floating gate layer 1520A and the second floating gate layer 1520B and the boundary line between the first dielectric layer 1700A and the second dielectric layer 1700B are the N + type selection gate layer 1620N and the P + And coincides with a line extending from the boundary line of the select gate layer 1620P. The horizontal stacking structure of the first floating gate layer 1520A, the first dielectric layer 1700A, and the N + type select gate layer 1620N constitutes the first coupling capacitor Cn. The horizontal stacking structure of the second floating gate layer 1520B, the second dielectric layer 1700B, and the P + type select gate layer 1620P constitutes a second coupling capacitor Cp. Accordingly, the entire capacitor formed by the horizontal lamination structure of the floating gate layer 1520, the dielectric layer 1700, and the selection gate layer 1620 is formed by the first coupling capacitor Cn and the second coupling capacitor Cp, .

The nonvolatile memory device 1000 according to this example can be an example for implementing the equivalent circuit 2000 of the nonvolatile memory device of Fig. The N + -type first junction region 1310, the N + -type second junction region 1320, the first channel region 1410, the first gate insulating layer 1510, and the floating gate layer 1520 correspond to the equivalent The cell transistor 2100 can be configured in the circuit. The N + type first junction region 1310 and the N + type second junction region 1320 may correspond to the drain terminal D and the junction terminal J of the cell transistor 2100, respectively. The floating gate layer 1520 may correspond to the floating gate FG of the cell transistor 2100 in the equivalent circuit of Fig. The N + -type second junction region 1320, the N + -type third junction region 1330, the second channel region 1420, the second gate insulating layer 1610, and the select gate layer 1620 correspond to the equivalent The selection transistor 2200 can be configured in the circuit. The N < + > -type third junction region 1330 may correspond to the source terminal S of the selection transistor 2200. The select gate layer 1620 may correspond to the select gate terminal SG of the select transistor 2200 in the equivalent circuit of Fig.

FIGS. 21 and 22 are cross-sectional views illustrating programming operation of a non-volatile memory cell according to another example of the present disclosure. And FIG. 23 is a plan view illustrating a coupling mechanism between a select gate layer and a floating gate layer in a programming operation of a nonvolatile memory cell according to another example of this disclosure. The program operation according to this example can be performed by a hot electron injection (HEI) mechanism. First, referring to FIG. 21 and FIG. 22, a positive program voltage (+ Vpp) is applied to the program word line WL_P and a positive program bit line voltage (+ Vpb). A ground voltage, for example, 0 V, is applied to the source line SL. The read / erase word line WL_RE floats. In one example, the positive program voltage (+ Vpp) and the positive program bit line voltage (+ Vpb) may be approximately + 8V and + 4V, respectively. The second channel region 1420 between the second N + type junction region 1320 and the third N + type junction region 1330 is inverted by the positive program voltage (+ Vpp) applied through the program word line WL_P. A layer 1820 is formed, and the selection transistor 2200 is turned on. As a result, 0 V applied to the source line SL is induced in the second N + type junction region 1320.

As shown in FIG. 23, as the positive program voltage (+ Vpp) is applied to the P + type select gate layer 1620P from the program word line WL_P and the read / erase word line WL_RE is floated, (D1) is short-circuited by applying a forward bias. Thus, the positive program voltage (+ Vpp) from the program word line WL_P is applied to both the P + type select gate layer 1620P and the N + type select gate layer 1620N. The bias voltage is not applied to the P + type select gate layer 162P, and thus the second coupling capacitor composed of the second floating gate layer 152B, the second dielectric layer 170B, and the P + type select gate layer 162P, (Cp) does not perform the coupling operation. The coupling bias induction to the floating gate layer 1520 is thus accomplished by forming a first floating gate layer 1520A, a first dielectric layer 1700A, and an N + type select gate layer 1620N The first coupling capacitor Cn has a coupling function. The coupling bias induction to the floating gate layer 1520 may also be achieved by forming a second floating gate layer 1520B, a second dielectric layer 1700B, and a P + type select gate layer 1620P The second coupling capacitor Cp is also made by a coupling operation. In other words, the magnitude of the coupling bias induced in the floating gate layer 1520 depends on the magnitude of the positive program voltage (+ Vpp), the coupling ratio of the first coupling capacitor Cn and the coupling ratio of the second coupling capacitor Cp Lt; / RTI >

Referring again to Figures 21 and 22, as the positive coupling programming voltage (+ Vc1) is induced in the floating gate layer 1520, the first N + type junction region 1310 and the second N + type junction region 1320, An inversion layer 1810 is formed in the first channel region 1410 between the source and drain regions. Thus, hot electrons are generated in the inversion layer 1810 adjacent to the first junction region 1310. These hot electrons are injected into the floating gate layer 1520 through the first gate insulating layer 1510 by a vertical electric field due to the positive coupling programming voltage (+ Vc1). As the hot electrons are implanted into the floating gate layer 1520, the non-volatile memory cell is programmed and the threshold voltage value in the first channel region 1410 is higher than before it was programmed.

24 is a cross-sectional view for explaining an erase operation of a nonvolatile memory cell according to another example of the present disclosure. And Fig. 25 is a plan view showing a coupling mechanism between the select gate layer and the floating gate layer in erase operation of the non-volatile memory cell according to another example of this disclosure. The erase operation according to this example can be performed by a band-to-band tunneling (BTBT) mechanism. Referring to FIG. 24, a negative erase voltage (-Vee) is applied to the read / erase word line WL_RE for erase operation to the nonvolatile memory cell, and a positive erase voltage And applies a bit line voltage (+ Veb). A ground voltage, for example, 0 V, is applied to the source line SL. The program word line WL_P floats. In one example, the negative erase voltage (-Vee) and the positive erase bit line voltage (+ Veb) may be approximately -8V and + 5V, respectively. As the negative erase voltage (-Vee) is applied through the read / erase word line WL_RE, the selection transistor 2200 maintains the turn-off state. Thus, the second N + type junction region 1320 remains in a floating state.

25, a negative erase voltage (-Vee) is applied from the read / erase word line WL_RE to the N + type select gate layer 1620N, and the program word line WL_P is floated, Diode D1 is shorted by applying a forward bias. Therefore, a negative erase voltage (-Vee) from the read / erase word line WL_RE is applied to both the N + type select gate layer 1620N and the P + type select gate layer 1620P. The coupling bias induction to the floating gate layer 1520 is thus accomplished by forming a first floating gate layer 1520A, a first dielectric layer 1700A, and an N + type select gate layer 1620N The first coupling capacitor Cn has a coupling function. The coupling bias induction to the floating gate layer 1520 may also be achieved by forming a second floating gate layer 1520B, a second dielectric layer 1700B, and a P + type select gate layer 1620P And a second coupling capacitor Cp formed by a coupling capacitor Cp. In other words, the magnitude of the coupling bias induced in the floating gate layer 1520 depends on the magnitude of the negative erase voltage (-Vee), the coupling ratio of the first coupling capacitor Cn and the coupling ratio of the second coupling capacitor Cp, Is determined by the coupling ratio.

Referring again to FIG. 24, no inversion layer is formed in the first channel region 1410 as a negative coupling-erase voltage (-Vc2) is induced in the floating gate layer 1520. As the positive erase bit line voltage (+ Veb) from the bit line BL is applied to the first N + type junction region 1310, the second channel region 1420 and the N + type third junction region 1330 A depletion is generated from the junction of Accordingly, an energy band bending greater than the energy gap is generated, so that electrons in the floating gate layer 1520 pass through the first gate insulating layer 1510 and are tunneled to the first N + type junction region 1310 . As electrons in the floating gate layer 1520 are tunneled, the non-volatile memory cell is in an erase state and the threshold voltage value in the first channel region 1410 is lower than before erasing.

26 is a cross-sectional view illustrating a read operation of a nonvolatile memory cell according to another example of the present disclosure. And Fig. 25 is a plan view showing a coupling mechanism between the select gate layer and the floating gate layer in the read operation of the nonvolatile memory cell according to another example of this disclosure. 26, a positive read voltage (+ Vrr) is applied to the read / erase word line WL_RE and a positive read bit line voltage (+ Vrr) is applied to the bit line BL in order to perform a read operation for the nonvolatile memory cell. (+ Vrb). The program word line WL_P floats. A ground voltage, for example, 0 V, is applied to the source line SL. The positive read voltage + Vrr is a ratio of the threshold voltage magnitude in the first channel region 1410 of the cell transistor 2100 in the programmed state to the threshold voltage magnitude in the first channel region 1410 of the cell transistor 2100 in the erase state. Lt; RTI ID = 0.0 > of < / RTI > In one example, the positive lead voltage (+ Vrr) and the positive lead bit line voltage (+ Vrb) may be approximately + 3.3V and + 1V, respectively. The second channel region 1420 between the second N + type junction region 1320 and the third N + type junction region 1330 is formed by the positive lead voltage (+ Vrr) applied through the read / erase word line WL_RE. An inversion layer 1820 is formed, and the selection transistor 2200 is turned on. As a result, 0 V applied to the source line SL is induced in the second N + type junction region 1320.

27, a positive read voltage (+ Vrr) is applied to the N + type select gate layer 1620N from the read / erase word line WL_RE and the program word line WL_P is floated, (D1) is opened by applying a reverse bias. Therefore, the positive read voltage (+ Vrr) from the read / erase word line WL_RE is applied only to the N + type select gate layer 1620N and not to the P + type select gate layer 1620P. As the bias is not applied to the P + type select gate layer 1620P, a second coupling capacitor composed of the second floating gate layer 1520B, the second dielectric layer 1700B, and the P + type select gate layer 1620P, (Cp) does not perform the coupling operation. The coupling bias induction to the floating gate layer 1520 is thus accomplished by forming a first floating gate layer 1520A, a first dielectric layer 1700A, and an N + type select gate layer 1620N The first coupling capacitor Cn has a coupling function. That is, the magnitude of the coupling bias induced in the floating gate layer 1520 is determined by the magnitude of the positive lead voltage (+ Vrr) and the coupling ratio by the first coupling capacitor Cn.

When a positive coupling lead voltage (+ Vc3) is induced in the floating gate layer 1520, the first channel region 1410 may have an inversion layer according to the threshold voltage value of the first channel region 1410, Do not. For example, even if a positive coupling lead voltage (+ Vc3) is applied to the floating gate layer 1520 in a program state in which the threshold voltage value is increased, an inversion layer is not formed in the first channel region 1410. Therefore, no current flows between the bit line BL and the source line SL. On the other hand, in the erase state in which the threshold voltage value is lowered, since the positive coupling lead voltage (+ Vc3) is applied to the floating gate layer 1520, the inversion layer 1410 is formed in the first channel region 1310. Therefore, a current flows between the bit line BL and the source line SL each of which is applied with positive lead bit line voltages (+ Vrb) and 0 V, respectively. In this way, the status of the nonvolatile memory cell can be read by sensing the current flow between the bit line BL and the source line SL.

28 is a layout diagram of a nonvolatile memory cell array according to another example of the present disclosure. The nonvolatile memory cell array 4000 according to the present example has a matrix form in which each of the unit cells is disposed at each of intersections of two rows and four columns. However, this is only an example, and may have a matrix form consisting of more than two rows and more than four columns. Referring to FIG. 28, a first active region 4110-10 and a second active region 4110-20 are disposed in a P-type well region 4040. FIG. P-type well region 4040 may be shared by all the unit cells. The first active region 4110-10 and the second active region 4110-20 have a stripe shape elongated along the first direction. The first active region 4110-10 and the second active region 4110-20 are arranged to be spaced apart from each other in a second direction intersecting the first direction. Although not shown in the drawing, the first active region 4110-10 and the second active region 4110-20 can be defined by the trench isolation layer. The first active region 4110-10 is shared by the unit cells constituting the first row and the second active region 4110-20 is shared by the unit cells constituting the second row.

A plurality of select gate layers 4620 are spaced apart from one another along the first direction. The select gate layer 4620 has a planar structure in the form of a stripe extending elongated along the second direction. The select gate layer 4620 thereby intersects the first active region 4110-10 and the second active region 4110-20. The select gate layer 4620 is coupled to the unit cells constituting any one of the columns. The select gate layer 4620 is formed by alternately arranging N + type select gate layers 4620N doped with N + type and P + type select gate layers 4620P doped with P + type along the second direction. One of the N + type select gate layers 4620N overlaps the first active region 4110-10 and the other overlaps the second active region 4110-20. The N + type select gate layer 4602N overlapping the first active region 4110-10 is coupled to a unit cell constituting the first row. The N + type select gate layer 4620N overlapping the second active region 4110-20 is coupled to the unit cells constituting the second row. The P + type select gate layer 4620P is disposed between the N + type select gate layers 4620N and therefore does not overlap with the first active region 4110-10 and the second active region 4110-20. The P + type select gate layer 4620P is commonly coupled to the unit cells constituting the first row and the unit cells constituting the second row. The N + type select gate layer 4620N and the P + type select gate layer 4620P can constitute a PN diode. P + type select gate layer 4620P is coupled to one of the program word lines (WL_P1-WL_P4) via a contact. Each of the N + type select gate layers 4620N is commonly coupled to one of the read / erase word lines WL_RE1-WL_RE4 via a contact.

A plurality of first floating gate layers 4520-1 and second floating gate layers 4520-2 are disposed to be spaced apart from each other along the first direction. The first floating gate layer 4520-1 and the second floating gate layer 4520-2 are mutually spaced along the second direction. The first floating gate layer 4520-1 is disposed in parallel with the select gate layer 4620 while intersecting the first active region 4110-10. Although not shown in the drawing, a dielectric layer is disposed between the first floating gate layer 4520-1 and the selection gate layer 4620 to constitute a coupling capacitor. The second floating gate layer 4520-2 is disposed in parallel with the select gate layer 4620 while intersecting the second active region 4110-20. Although not shown in the figure, a dielectric layer is disposed between the second floating gate layer 4520-2 and the select gate layer 4620 to constitute a coupling capacitor.

The first active region 4110-10 includes a first N + type junction region 4310 separated by the select gate layer 4620 and the first floating gate layer 4520-1, a second N + type junction region 4320 ), And a third N + type junction region 4330. The second active region 4110-20 includes a first N + type junction region 4310 separated by the select gate layer 4620 and a second floating gate layer 4520-2, a second N + type junction region 4320 ), And a third N + type junction region 4330. The first N + type junction region 4310 is disposed in the region adjacent to the first floating gate layer 4520-1. A second N + type junction region 4320 is disposed between the first floating gate layer 4520-1 and the select gate layer 4620. [ The third N + type junction region 4330 is disposed in the region adjacent to the select gate layer 4620. The first N + type junction region 4310 and the third N + type junction region 4330 in the first active region 4110-10 are coupled to the first bit line BL1 and the first source line SL1, respectively. The first N + type junction region 4310 and the third N + type junction region 4330 in the second active region 4110-20 are coupled to the second bit line BL2 and the second source line SL2, respectively.

29 is an equivalent circuit diagram of a nonvolatile memory cell array according to another example of the present disclosure. 29, an equivalent circuit 5000 of the nonvolatile memory cell array according to the present example has a matrix form in which each unit cell is disposed at each of intersections of two rows and four columns. However, this is only an example, and may have a matrix form consisting of more than two rows and more than four columns. The rows may be separated by the bit lines BL1 and BL2 and the source lines SL1 and SL2. The columns may be separated by program word lines WL_P1-WL_P4 and read / erase word lines WL_RE1-WL_RE4. Each of the plurality of unit cells 6110 - 6140, 6210 - 6240 has the same configuration. For example, the unit cell 6110 in the first row and the first column has the cell transistor 5100-11 and the selection transistor 5200-11. The cell transistor 5100-11 and the selection transistor 5200-11 may be formed of an N-channel type MOS transistor. The cell transistor 5100-11 has a floating gate FG, a junction terminal J, and a drain terminal D. The selection transistor 5200-11 has a selection gate terminal SG, a junction terminal J, and a source terminal S. The source terminal S and the drain terminal D are coupled to the first source line SL1 and the first bit line BL1, respectively. The junction terminal J has a floating state. The select gate terminal SG is coupled to the first read / erase word line WL_RE1 and the first program word line WL_P1. The first read / erase word line WL_RE1 is directly coupled to the select gate terminal SG. The first program word line WL_P1 is coupled to the select gate terminal SG via the PN diode D1. A first coupling capacitor Cn and a second coupling capacitor Cp are arranged in parallel between the floating gate FG and the selection gate terminal SG. A PN diode D1 is disposed between the selection gate terminal SG and the second coupling capacitor Cp. The anode of the PN diode D1 is coupled to the first program word line WL_P1 and the second coupling capacitor Cp. The cathode of the PN diode D1 is coupled to the select gate terminal SG and the first read / erase word line WL_RE1.

The source terminals S of the unit cells 6110 - 6140 constituting the first row are commonly coupled to the first source line SL 1. The drain terminal D of each of the unit cells 6110 - 6140 constituting the first row is commonly coupled to the first bit line BL1. The source terminals S of each unit cell 6210-6240 constituting the second row are commonly coupled to the second source line SL2. The drain terminal D of each of the unit cells 6210-6240 constituting the second row is commonly coupled to the second bit line BL2. The select gate terminal SG of each of the unit cells 6110 and 6210 constituting the first column is coupled to the first read / erase word line WL_RE1 and the first program word line WL_P1. The select gate terminal SG of each of the unit cells 6120 and 6220 constituting the second column is coupled to the second read / erase word line WL_RE2 and the second program word line WL_P2. The select gate terminal SG of each of the unit cells 6130 and 6230 constituting the third column is coupled to the third read / erase word line WL_RE3 and the third program word line WL_P3. The select gate terminal SG of each of the unit cells 6140 and 6240 constituting the fourth column is coupled to the fourth read / erase word line WL_RE4 and the fourth program word line WL_P4.

30 is a diagram showing a program operation for a selected unit cell of a nonvolatile memory cell array according to another example of this disclosure. In Fig. 30, the same reference numerals as those in Fig. 29 denote the same components. 30, a positive program voltage (+ Vpp) is applied to the first program word line WL_P1 coupled to the selection unit cell 6110 to program the selection unit cell 6110 of the first row and first column And applies a ground voltage, for example, 0 V, to the remaining program word lines WL_P2-WL_P4. All the read / erase word lines WL_RE1-WL_RE4 float. Positive program bit line voltages (+ Vpb) and 0V are applied to the first bit line (BL1) and the first source line (SL1) coupled to the selection unit cell 6110, respectively. And 0V is applied to the remaining second bit line BL2 and the second source line SL2. The positive program voltage (+ Vpp) from the first program word line WL_P1 is applied to the select gate terminal SG of the select transistor 5200-11 to turn on the select transistor 5200-11. The positive program voltage (+ Vpp) applied to the selection gate terminal SG of the selection transistor 5200-11 is controlled by the coupling operation of the first coupling capacitor Cn and the second coupling capacitor Cp, So that the coupling voltage is induced in the floating gate FG of the cell transistor 5100-11. The PN diode D1 is short-circuited as the forward bias is applied. In such a bias condition, the cell transistor 5100-11 is programmed by a hot electron injection (HEI) mechanism.

In the case of other unselected unit cells sharing the first bit line BL1 and the first source line SL1, such as the unselected unit cells 6120 of the first row and the second column, with the selected unit cell 6110, 0 V is applied to the second program word line WL_P2 to keep the selection transistor 5100-12 in the turned off state. Therefore, the coupling voltage is not induced in the floating gate FG of the cell transistor 5200-12, and the unselected unit cell 6120 is program inhibited. In the case of other unselected unit cells sharing the first program word line WL_P1 with the selected unit cell 6110, such as the unselected unit cell 6210 of the second row and first column, the first program word line WL_P1 (+ Vpp) is applied to the floating gate FG of the cell transistor 5100-21, the coupling voltage is induced in the floating gate FG of the cell transistor 5100-21. As a result, both the cell transistor 5100-21 and the selection transistors 5200-21 are turned on. However, since there is no potential difference between the second bit line BL2 and the second source line SL2, hot electrons are not generated, and thus the unselected unit cell 6210 is program inhibited.

31 is a diagram showing an erasing operation for a selected unit cell of a nonvolatile memory cell array according to another example of this disclosure. 31, the same reference numerals as those in FIG. 29 denote the same elements. Referring to FIG. 31, in order to erase the selection unit cell 6110 of the first row and the first column, a negative erase voltage (Vref) is applied to the first read / erase word line WL_RE1 coupled to the selection unit cell 6110, (-Vee), and applies a ground voltage, for example, 0V, to the remaining read / erase word lines WL_RE2-WL_RE4. All program word lines (WL_P1-WL_P4) float. A positive erase bit line voltage (+ Veb) and 0V are applied to the first bit line (BL1) and the first source line (SL1) coupled to the selection unit cell 6110, respectively. And 0V is applied to the remaining second bit line BL2 and the second source line SL2. As the negative erase voltage -Vee is applied from the first read / erase word line WL_RE1 to the select gate terminal SG of the select transistor 5200-11, a forward bias is applied to the PN diode D1 And is thus short-circuited. Therefore, the coupling operation of the second coupling capacitor Cp is performed together with the coupling operation of the first coupling capacitor Cn in the same manner as the program operation, so that the floating gate FG of the cell transistor 5100-11 is connected to the negative couple The ring voltage is induced. Due to the potential difference between the negative coupling voltage of the floating gate FG and the positive erase bit line voltage (+ Veb) applied to the first bit line BL1, the cell transistor 5100-11 performs band- (BTBT) mechanism.

In the case of other unselected unit cells sharing the first bit line BL1 and the first source line SL1, such as the unselected unit cells 6120 of the first row and the second column, with the selected unit cell 6110, 0 V is applied to the first read / erase word line WL_RE1 to keep the selection transistor 5100-12 in the turn-off state. Therefore, the coupling voltage is not induced in the floating gate FG of the cell transistor 5200-12. Therefore, only a potential difference of the positive erase bit line voltage (+ Veb) is generated between the floating gate FG of the cell transistor 5200-12 and the first bit line BL1. This potential difference does not cause band-to-band tunneling (BTBT) in the cell transistor 5200-12, so that the non-selected unit cell 6120 is not erased. In the case of other unselected unit cells sharing the first read / erase word line WL_RE1, such as the unselected unit cells 6210 of the second row and the first column, the first read / A negative coupling voltage is induced in the floating gate FG of the cell transistor 5100-21 as the negative bias voltage -Vee is applied to the erase word line WL_RE1. However, as 0V is applied to the second bit line BL2, a potential difference of the negative erase voltage -Vee is applied between the floating gate FG of the cell transistor 5200-12 and the first bit line BL1 It only happens. This potential difference does not cause band-to-band tunneling (BTBT) in the cell transistor 5200-12, so that the non-selected unit cell 6120 is not erased.

Although it has been described in the present example that the unit cell 6110 of a specific unit cell, for example, the first row and the first column, is selectively erased, the erase operation can be collectively performed on all the unit cells, if necessary . To this end, a negative erase voltage -Vee is applied to all the read / erase word lines WL_RE1-WL_RE4 and a positive erase bit line voltage + Veb is applied to all the bit lines BL1 and BL2 . And applies a ground voltage, for example, 0 V, to all the source lines SL1 and SL2. According to such a bias condition, the cell transistors of all the unit cells can be collectively erased by the above-described band-to-band tunneling (BTBT) mechanism.

32 is a diagram showing a read operation for a selected unit cell of a nonvolatile memory cell array according to another example of the present disclosure. 32, the same reference numerals as those in FIG. 29 denote the same components. 32, a positive read voltage (+) is applied to the first read / erase word line (WL_RE1) coupled to the selection unit cell 6110 to read the selection unit cell 6110 of the first row and the first column, Vrr, and applies a ground voltage, e.g., 0 V, to the remaining read / erase word lines WL_RE2-WL_RE4. All program word lines (WL_P1-WL_P4) float. The positive lead bit line voltages + Vrb and 0V are applied to the first bit line BL1 and the first source line SL1 coupled to the selection unit cell 6110, respectively. And 0V is applied to the remaining second bit line BL2 and the second source line SL2.

The positive read voltage (+ Vrr) from the first read / erase word line WL_RE1 turns on the selection transistor 5200-11. Unlike the program operation and the erase operation, the positive read voltage (+ Vrr) is applied to the floating gate (FG) of the cell transistor 5100-11 by the coupling operation of the first coupling capacitor (Cn) ) To induce a positive coupling voltage. The PN diode D1 is opened as the reverse bias is applied and the coupling operation by the second coupling capacitor Cp is not performed. As the positive coupling voltage is induced in the floating gate FG of the cell transistor 5100-11, the cell transistor 5100-11 is turned on or off according to the magnitude of the threshold voltage of the cell transistor 5100-11, And maintains the turn-off state. When the cell transistor 5100-11 is programmed, the cell transistor 5100-11 maintains the turn-off state. On the other hand, when the cell transistor 5100-11 is in an erased state, the cell transistor 5100-11 is turned on. When the cell transistor 5100-11 maintains the turn-off state, a current path is not formed between the first bit line BL1 and the first source line SL1. On the other hand, when the cell transistor 5100-11 is turned on, a current path is formed between the first bit line BL1 and the first source line SL1. Since there is a potential difference between the positive read bit line voltage (+ Vrb) between the first bit line (BL1) and the first source line (SL1), a current flows through the current path. The state of the cell transistor 5100-11 of the selected unit cell 6110 can be read by sensing the current between the first bit line BL1 and the first source line SL1.

In the case of other unselected unit cells sharing the first bit line BL1 and the first source line SL1, such as the unselected unit cells 6120 of the first row and the second column, with the selected unit cell 6110, As 0V is applied to the second read / erase word line WL_RE2, the cell transistor 5100-12 and the selection transistor 5200-12 of the non-selected unit cell 6120 are all turned off. Therefore, the current path between the first bit line BL1 and the first source line SL1 by the non-selected unit cell 6120 is not formed, and does not affect the read operation of the selected unit cell 6110. [

Although the embodiments of the present application as described above illustrate and describe the drawings, it is intended to illustrate what is being suggested in the present application and is not intended to limit what is presented in the present application in a detailed form.

100 ... non-volatile memory cell 104 ... P-type well region
111 ... first active region 112 ... second active region
131 ... First N + type junction region 132 ... Second N + type junction region
133 ... third N + type junction region 134 ... P + type contact region
152 ... floating gate layer 152A ... first floating gate layer
152B ... second floating gate layer 162 ... select gate layer
162N ... N + type select gate layer 162P ... P + type select gate layer
170 ... Dielectric layer Cn ... First coupling capacitor
Cp ... second coupling capacitor D1 ... PN diode

Claims (35)

A select transistor having a select gate terminal coupled to a word line and a source terminal coupled to a source line;
A floating gate, a cell transistor having a drain terminal coupled to the bit line, and sharing a junction terminal with the selection transistor;
A first coupling capacitor disposed in a first connection line between the word line and the floating gate; And
A PN diode and a second coupling capacitor disposed in a second connection line between the word line and the floating gate,
Wherein the anode and the cathode of the PN diode are coupled to the second coupling capacitor and the word line, respectively. The method according to claim 1,
Wherein the first connection line and the second connection line are arranged in parallel relation to each other. The method according to claim 1,
Wherein the cell transistor and the select transistor are formed of N-channel MOS transistors. The method of claim 3,
Wherein the program operation and the read operation for the cell transistor are performed by applying a positive bias to the word line and the erase operation for the cell transistor is performed through a negative bias to the word line. The method according to claim 1,
Wherein the first coupling capacitor and the second coupling capacitor have capacitances of different magnitudes. The method according to claim 1,
Wherein the first coupling capacitor has a relatively larger capacitance than the second coupling capacitor. A first active region extending long along the first direction;
A first junction region, a second junction region, and a third junction region of a first conductivity type disposed in the first active region;
A floating gate layer disposed to extend along the second direction so as to intersect with the first region of the first active region;
A select gate layer disposed to extend along the second direction so as to intersect a second region of the first active region; And
And a dielectric layer disposed between the floating gate layer and the select gate layer,
Wherein the select gate layer is composed of a junction structure of a select gate layer of a first conductivity type and a select gate layer of a second conductivity type. 8. The method of claim 7,
Wherein the first conductivity type is an N-type and the second conductivity type is a P-type. 8. The method of claim 7,
The first region of the first active region is a first channel region between the first junction region and the second junction region of the first conductivity type,
And a second region of the first active region is a second channel region between the second junction region and the third junction region of the first conductivity type. 8. The method of claim 7,
The spacing between one side of the floating gate layer and one side of the select gate layer facing each other is substantially constant along the second direction. 8. The method of claim 7,
Wherein the select gate layer of the first conductivity type overlies the first region and the select gate layer of the second conductivity type is located so as not to overlap with the second region. 12. The method of claim 11,
The length of the select gate layer of the first conductivity type overlapping with the floating gate layer in the horizontal direction is set to be longer than the length of the select gate layer of the second conductivity type The length of the nonvolatile memory cell being longer than the length in the second direction. 12. The method of claim 11,
A word line coupled to the select gate layer of the first conductivity type;
A bit line coupled to a first junction region of the first conductivity type; And
And a source line coupled to the third junction region of the first conductivity type. 12. The method of claim 11,
A read / erase word line coupled to the select gate layer of the first conductivity type;
A program word line coupled to the select gate layer of the second conductivity type;
A bit line coupled to a first junction region of the first conductivity type; And
And a source line coupled to the third junction region of the first conductivity type. 8. The method of claim 7,
A first gate insulating layer disposed between the floating gate layer and the first channel region; And
And a second gate insulating layer disposed between the select gate layer and the second channel region. A plurality of active regions each extending lengthwise along a first direction and spaced apart along a second direction;
A plurality of select gate layers extending along the second direction such that each of the select gate layers crosses the active regions and are spaced apart from each other along the first direction;
A plurality of floating gate layers disposed such that each of the floating gate layers is parallel to each of the select gate layers; And
A plurality of dielectric layers each disposed between each of the select gate layers and each of the floating gate layers,
Wherein each of the select gate layers is constituted by alternately arranging a select gate layer of a first conductivity type and a select gate layer of a second conductivity type in the second direction. 17. The method of claim 16,
Wherein the select gate layer of the first conductivity type is positioned to overlap with the active regions and the select gate layer of the second conductivity type is located so as not to overlap the active region. 18. The method of claim 17,
Wherein each of the active regions comprises first junction regions of the first conductivity type, second junction regions, and third junction regions. 19. The method of claim 18,
Wherein the first conductivity type is an N-type and the second conductivity type is a P-type. 20. The method of claim 19,
A plurality of source lines, each of which is commonly coupled to the first junction regions of each of the active regions;
A plurality of bit lines, each of which is commonly coupled to the third junction regions of each of the active regions; And
Further comprising word lines each of which is coupled to a select gate layer of a first conductivity type of each of the select gate layers. 20. The method of claim 19,
A plurality of source lines, each of which is commonly coupled to the first junction regions of each of the active regions;
A plurality of bit lines, each of which is commonly coupled to the third junction regions of each of the active regions;
Lead / erase word lines, each of which is coupled to a select gate layer of a first conductivity type of each of the select gate layers; And
Further comprising program word lines, each of the program word lines being coupled to a select gate layer of a second conductivity type of each of the select gate layers. A nonvolatile memory cell array in which unit cells are arranged at each of intersections of rows separated by bit lines and source lines and columns separated by word lines,
The unit cell includes:
A select transistor having a select gate terminal coupled to the word line and a source terminal coupled to the source line;
A cell transistor having a floating gate, a drain terminal coupled to the bit line, and sharing a junction terminal with the select transistor;
A first coupling capacitor disposed in a first connection line between the word line and the floating gate; And
A PN diode and a second coupling capacitor disposed in a second connection line between the word line and the floating gate,
And an anode and a cathode of the PN diode are coupled to the second coupling capacitor and the word line, respectively. 23. The method of claim 22,
Wherein the first connection line and the second connection line are arranged in parallel relation to each other. 23. The method of claim 22,
And the cell transistor and the selection transistor are formed of N-channel type MOS transistors. 25. The method of claim 24,
Wherein the program operation and the read operation for the unit cell are performed by applying a positive bias to the word line and the erase operation for the unit cell is performed through a negative bias to the word line. A select transistor having a select gate terminal coupled to a program word line and a read / erase word line, and a source terminal coupled to a source line;
A floating gate, a cell transistor having a drain terminal coupled to the bit line, and sharing a junction terminal with the selection transistor;
A first coupling capacitor disposed in a first connection line between the word line and the floating gate; And
A PN diode and a second coupling capacitor disposed in a second connection line between the word line and the floating gate,
Wherein an anode of the PN diode is coupled to the second coupling capacitor and a program word line, and a cathode of the PN diode is coupled to the select gate terminal and the read / erase word line. 27. The method of claim 26,
Wherein the first connection line and the second connection line are arranged in parallel relation to each other. 27. The method of claim 26,
Wherein the cell transistor and the select transistor are formed of N-channel MOS transistors. 29. The method of claim 28,
Program operation for the cell transistor is performed by floating the read / erase word line and applying a positive bias to the program word line,
The erase operation for the cell transistor is performed by floating the program word line and applying a negative bias to the read / erase word line, and
Wherein the read operation for the cell transistor is performed by floating the program word line and applying a positive bias to the read / erase word line. 27. The method of claim 26,
Wherein the first coupling capacitor and the second coupling capacitor have capacitances of different magnitudes. 27. The method of claim 26,
Wherein the first coupling capacitor has a relatively larger capacitance than the second coupling capacitor. In a nonvolatile memory cell array in which unit cells are arranged in each of the rows separated by the bit lines and the source lines and the intersections of the columns separated by the program word lines and the read / erase word lines ,
The unit cell includes:
A select transistor having a select gate terminal coupled to the program word lines and the read / erase word lines, and a source terminal coupled to the source line;
A cell transistor having a floating gate, a drain terminal coupled to the bit line, and sharing a junction terminal with the select transistor;
A first coupling capacitor disposed in a first connection line between the read / erase word line and the floating gate;
A PN diode disposed between the program word line and the read / erase word line; And
And a second coupling capacitor disposed in series with the PN diode between the program word line and the floating gate,
Wherein an anode of the PN diode is coupled to the second coupling capacitor and a program word line, and a cathode of the PN diode is coupled to the read / erase word line and the select gate terminal. 33. The method of claim 32,
Wherein the first connection line and the second connection line are arranged in parallel relation to each other. 33. The method of claim 32,
And the cell transistor and the selection transistor are formed of N-channel type MOS transistors. 35. The method of claim 34,
Program operation for the unit cell is performed by floating the read / erase word line and applying a positive bias to the program word line,
The erase operation for the unit cell is performed by floating the program word line and applying a negative bias to the read / erase word line, and
Wherein the read operation for the unit cell is performed by floating the program word line and applying a positive bias to the read / erase word line.

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