CN114695370B - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
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- CN114695370B CN114695370B CN202210603975.8A CN202210603975A CN114695370B CN 114695370 B CN114695370 B CN 114695370B CN 202210603975 A CN202210603975 A CN 202210603975A CN 114695370 B CN114695370 B CN 114695370B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 238000000034 method Methods 0.000 claims description 45
- 239000000463 material Substances 0.000 claims description 23
- 230000008569 process Effects 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 description 13
- 238000004519 manufacturing process Methods 0.000 description 12
- 238000002513 implantation Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
Abstract
The invention relates to a semiconductor structure and a preparation method thereof. The semiconductor structure includes: a substrate having a select gate region and a control gate region; the first gate oxide layer is positioned on the upper surface of the selection gate area; the second gate oxide layer is positioned on the upper surface of the control gate region; the thickness of the second gate oxide layer is greater than that of the first gate oxide layer; the selective grid structure is positioned on the upper surface of the first grid oxide layer; and the control grid structure is positioned on the upper surface of the second grid oxide layer. The semiconductor structure reduces the thickness of the first gate oxide layer, can reduce the threshold voltage of the select gate transistor, and accordingly has smaller voltage switching during reading operation, reduces the power consumption of the reading operation, and can improve the reading speed.
Description
Technical Field
The present disclosure relates to integrated circuit technologies, and more particularly, to a semiconductor structure and a method for fabricating the same.
Background
With the development of integrated circuit technology, an Embedded Flash Memory (E-Flash) technology has appeared, which has the advantages of fast working speed, small Unit area, high integration level, good reliability, etc., and the Embedded Flash Memory can be usually Embedded in various Embedded chips, which can include a Micro Controller Unit (MCU) chip, a Subscriber Identity Module (SIM) chip, a bank card chip, etc. in an automobile.
In the conventional technology, an embedded flash memory generally includes a plurality of flash memory cells (cells), each of which includes a Select Gate Transistor (Select Gate Transistor) and a Control Gate Transistor (Control Gate Transistor), and a flash memory cell with a fixed address can be selected or deselected by the Select Gate Transistor to operate, the Control Gate Transistor is a cell storing "0/1" in a general sense, the Select Gate Transistor is connected in series with the Control Gate Transistor, and reading of any one of the flash memory cells can be achieved by setting different bias voltages to the Select Gate Transistor and the Control Gate Transistor. However, in the conventional technology, when a flash memory cell is read, the read power consumption of the select gate transistor is large (about 200 uA/MHZ), and the reading speed is slow.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a semiconductor structure and a method for fabricating the same, which address the problem of slow read speed in the prior art.
In order to achieve the above object, in one aspect, the present invention provides a semiconductor structure comprising:
a substrate having a select gate region and a control gate region;
the first gate oxide layer is positioned on the upper surface of the selection gate region;
a second gate oxide layer on the first gate oxide layer, the upper surface of the control gate region is positioned; the thickness of the second gate oxide layer is greater than that of the first gate oxide layer;
the selective gate structure is positioned on the upper surface of the first gate oxide layer;
and the control grid structure is positioned on the upper surface of the second grid oxide layer.
In one embodiment, the thickness of the first gate oxide layer is 30-90 angstroms, and the thickness of the second gate oxide layer is 60-120 angstroms.
In one of the embodiments, the first and second electrodes are,
the select gate structure includes: the first floating gate is positioned on the upper surface of the first gate oxide layer; the selection gate is positioned on the first floating gate and is contacted with the first floating gate;
the control gate structure includes: the second floating gate is positioned on the upper surface of the second gate oxide layer; the first inter-gate dielectric layer is positioned on the upper surface of the second floating gate; and the control gate is positioned on the upper surface of the first inter-gate dielectric layer.
In one embodiment, the select gate structure further includes a second inter-gate dielectric layer located on the upper surface of the first floating gate, an opening is formed in the second inter-gate dielectric layer, and at least the first floating gate is exposed out of the opening; the selection gate is positioned on the upper surface of the second inter-gate dielectric layer and fills the opening.
In one embodiment, the semiconductor structure further comprises:
the source region is positioned in the substrate and positioned on one side, far away from the selection gate structure, of the control gate structure;
and the drain region is positioned in the substrate and positioned on one side of the selection gate structure far away from the control gate structure.
The semiconductor structure of the invention comprises: a substrate having a select gate region and a control gate region; the first gate oxide layer is positioned on the upper surface of the selection gate region; the second gate oxide layer is positioned on the upper surface of the control gate region; the thickness of the second gate oxide layer is greater than that of the first gate oxide layer; the selective gate structure is positioned on the upper surface of the first gate oxide layer; and the control grid structure is positioned on the upper surface of the second grid oxide layer. The thickness of the first gate oxide layer is reduced, so that the threshold voltage of the select gate transistor can be reduced, voltage switching during reading is small, power consumption of reading is reduced, and reading speed can be improved.
The invention also provides a preparation method of the semiconductor structure, which comprises the following steps:
providing a substrate, wherein the substrate is provided with a selection gate region and a control gate region;
forming a first gate oxide layer on the upper surface of the selection gate region, and forming a second gate oxide layer on the upper surface of the control gate region; the thickness of the first gate oxide layer is smaller than that of the second gate oxide layer;
and forming a selection grid structure on the upper surface of the first grid oxide layer, and forming a control grid structure on the upper surface of the second grid oxide layer.
In one embodiment, the forming a first gate oxide layer on the upper surface of the selection gate region and a second gate oxide layer on the upper surface of the control gate region includes:
forming a first oxide layer on the upper surface of the control gate region;
forming a second oxide layer on the upper surface of the first oxide layer and the upper surface of the selection gate region; the second oxide layer positioned in the selection gate region is used as the first gate oxide layer; the second oxide layer and the first oxide layer located in the control gate region jointly form the second gate oxide layer.
In one embodiment, the forming a first oxide layer on the upper surface of the control gate region includes:
forming an oxide material layer on the upper surface of the substrate, wherein the oxide material layer covers the upper surfaces of the control gate region and the selection gate region;
and removing the oxide material layer outside the control gate region, wherein the oxide material layer remained in the control gate region is the first oxide layer.
In one embodiment, the forming a select gate structure on the upper surface of the first gate oxide layer and forming a control gate structure on the upper surface of the second gate oxide layer includes:
forming a first floating gate on the upper surface of the first gate oxide layer, and forming a second floating gate on the upper surface of the second gate oxide layer;
forming a first inter-gate dielectric layer on the upper surface of the second floating gate;
and forming a control gate on the upper surface of the first inter-gate dielectric layer, and forming a selection gate on the first floating gate, wherein the selection gate is in contact with the first floating gate.
In one embodiment, a second inter-gate dielectric layer is formed on the upper surface of the first floating gate while a first inter-gate dielectric layer is formed on the upper surface of the second floating gate, and the second inter-gate dielectric layer has an opening therein, wherein the opening at least exposes the first floating gate; the selection gate is positioned on the upper surface of the second inter-gate dielectric layer and fills the opening.
In one embodiment, after forming a select gate structure on the upper surface of the first gate oxide layer and forming a control gate structure on the upper surface of the second gate oxide layer, the method further includes:
and forming a source region and a drain region in the substrate, wherein the source region is positioned on one side of the control grid structure far away from the selection grid structure, and the drain region is positioned on one side of the selection grid structure far away from the control grid structure.
According to the preparation method of the semiconductor structure, a first gate oxide layer is formed on the upper surface of the selection gate region, and a second gate oxide layer is formed on the upper surface of the control gate region; the thickness of the first gate oxide layer is smaller than that of the second gate oxide layer, and the thickness of the first gate oxide layer is reduced, so that the threshold voltage of the selective gate transistor can be reduced, voltage switching during reading is small, power consumption of reading operation is reduced, and reading speed can be improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a flow chart of a method of fabricating a semiconductor structure provided in one embodiment;
fig. 2 is a schematic cross-sectional view of a structure obtained in step S101 in the method for manufacturing a semiconductor structure provided in an embodiment;
fig. 3 is a schematic cross-sectional view illustrating a structure obtained in step S102 in the method for fabricating a semiconductor structure according to an embodiment;
fig. 4 is a schematic cross-sectional view illustrating a structure obtained in step S103 in the method for manufacturing a semiconductor structure according to an embodiment;
fig. 5 is a schematic flow chart illustrating a process of forming a first gate oxide layer on the upper surface of the select gate region and forming a second gate oxide layer on the upper surface of the control gate region in the method for manufacturing a semiconductor structure according to an embodiment;
fig. 6 is a schematic cross-sectional view illustrating a structure obtained in step S501 in the method for manufacturing a semiconductor structure provided in an embodiment;
fig. 7 is a schematic cross-sectional view illustrating a structure obtained in step S502 of the method for fabricating a semiconductor structure according to an embodiment;
fig. 8 is a schematic flow chart illustrating a process of forming a first oxide layer on an upper surface of a control gate region in a method for fabricating a semiconductor structure according to an embodiment;
fig. 9 is a schematic cross-sectional view of the structure obtained in step S801 of the method for manufacturing a semiconductor structure provided in one embodiment;
fig. 10 is a schematic cross-sectional view illustrating a structure obtained in step S802 of a method for fabricating a semiconductor structure provided in an embodiment;
fig. 11 is a schematic flow chart illustrating a process of forming a select gate structure on an upper surface of a first gate oxide layer and forming a control gate structure on an upper surface of a second gate oxide layer in the method for manufacturing a semiconductor structure according to an embodiment;
fig. 12 is a schematic cross-sectional view of the structure obtained in step S1101 of the method for manufacturing a semiconductor structure provided in one embodiment;
fig. 13 is a schematic cross-sectional view illustrating a structure obtained in step S1102 in the method for fabricating a semiconductor structure according to an embodiment;
fig. 14 is a schematic cross-sectional view illustrating a structure obtained in step S1103 in the method for manufacturing a semiconductor structure provided in one embodiment;
fig. 15 is a schematic cross-sectional view illustrating a second inter-gate dielectric layer structure formed on the upper surface of the first floating gate while the first inter-gate dielectric layer structure is formed on the upper surface of the second floating gate in the method for manufacturing a semiconductor structure according to another embodiment;
fig. 16 is a schematic cross-sectional view illustrating the formation of source and drain structures in a substrate in a method for fabricating a semiconductor structure according to an embodiment.
Description of the reference numerals:
10-a substrate, 201-a first gate oxide layer, 301-a second gate oxide layer, 20-a selection gate structure, 30-a control gate structure, 40-a first oxide layer, 50-a second oxide layer, 60-an oxide material layer, 202-a first floating gate, 302-a second floating gate, 303-a first inter-gate dielectric layer, 203-a selection gate, 304-a control gate, 204-a second inter-gate dielectric layer, 70-a source region and 80-a drain region.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Embodiments of the present application are set forth in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention; for example, the first doping type may be made the second doping type, and similarly, the second doping type may be made the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
Spatial relational terms, such as "under," "below," "under," "over," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising," "includes" or "including," etc., specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations from the shapes shown are to be expected, for example, due to manufacturing techniques and/or tolerances. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing techniques. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
Referring to fig. 1, the present invention provides a method for fabricating a semiconductor structure, comprising the following steps:
s101: providing a substrate, wherein the substrate is provided with a selection gate region and a control gate region;
s102: forming a first gate oxide layer on the upper surface of the selection gate region, and forming a second gate oxide layer on the upper surface of the control gate region; the thickness of the first gate oxide layer is smaller than that of the second gate oxide layer;
s103: and forming a selection grid structure on the upper surface of the first grid oxide layer and forming a control grid structure on the upper surface of the second grid oxide layer.
It should be noted that, in the conventional technology, in the step S102, the first Gate oxide layer and the second Gate oxide layer are usually formed by using the same oxidation process, that is, the thicknesses of the first Gate oxide layer and the second Gate oxide layer in the conventional technology are usually the same, that is, the thicknesses of the Gate oxide layer of the Select Gate (SG) transistor and the Gate oxide layer of the Control Gate (CG) transistor are the same, and are about 95 angstroms. In the conventional technology, since the first gate oxide layer is thick, the threshold voltage of the select gate transistor is about-0.9V, when the select gate transistor is switched from Selected SG to Unselected SG, the voltage switching (voltage switching) is from-Vcc (power supply voltage) to Vcc, in this process, the read operation power consumption is large, which is about 200uA/MHZ, resulting in a slow read speed, which is about 40ns. The invention makes the thickness of the first gate oxide layer smaller than that of the second gate oxide layer, and can reduce the threshold voltage of the select gate transistor due to the reduction of the thickness of the first gate oxide layer, thereby the voltage switching during the reading operation is smaller, the power consumption of the reading operation is reduced, and the reading speed can be improved.
In one example, the first gate oxide layer has a thickness of 30 angstroms to 90 angstroms, and the second gate oxide layer has a thickness of 60 angstroms to 120 angstroms.
Specifically, the thickness of the first gate oxide layer may be 30 angstroms, 40 angstroms, 50 angstroms, 60 angstroms, 70 angstroms, 80 angstroms, or 90 angstroms, etc.; the thickness of the second gate oxide layer may be 60 angstroms, 80 angstroms, 95 angstroms, 110 angstroms, 120 angstroms, or the like.
In one example, the first gate oxide layer has a thickness of 60 angstroms, the second gate oxide layer has a thickness of 95 angstroms, the threshold voltage of the select gate transistor is about-0.5V, and the select gate transistor is switched from 0V to Vcc when being selected to be unselected, wherein the read operation power consumption is small, about 100uA/MHZ, and the read speed is about 20ns, thereby improving the read speed.
The preparation method of the semiconductor structure comprises the steps of forming a first gate oxide layer on the upper surface of a selection gate region and forming a second gate oxide layer on the upper surface of a control gate region; the thickness of the first gate oxide layer is smaller than that of the second gate oxide layer, and the thickness of the first gate oxide layer is reduced, so that the threshold voltage of the selective gate transistor can be reduced, voltage switching during reading is small, power consumption of reading operation is reduced, and reading speed can be improved.
In step S101, referring to step S101 of fig. 1 and fig. 2, a substrate 10 is provided, the substrate 10 having a select gate region (not shown) and a control gate region (not shown).
The material of the substrate 10 may include silicon carbide (SiC), silicon (Si), gallium nitride (GaN), diamond, and the like, which is not limited herein.
In step S102, please refer to step S102 in fig. 1 and fig. 3, a first gate oxide layer 201 is formed on the upper surface of the select gate region, and a second gate oxide layer 301 is formed on the upper surface of the control gate region; the thickness of the first gate oxide layer 201 is less than the thickness of the second gate oxide layer 301.
In step S103, please refer to step S103 in fig. 1 and fig. 4, a select gate structure 20 is formed on the upper surface of the first gate oxide 201, and a control gate structure 30 is formed on the upper surface of the second gate oxide 301.
In one embodiment, as shown in fig. 5, forming a first gate oxide layer on the upper surface of the select gate region and a second gate oxide layer on the upper surface of the control gate region may include the steps of:
s501: forming a first oxide layer on the upper surface of the control gate region;
s502: forming a second oxide layer on the upper surface of the first oxide layer and the upper surface of the selection gate region; the second oxide layer positioned in the selection gate area is used as a first gate oxide layer; the second oxide layer and the first oxide layer in the control gate region jointly form a second gate oxide layer.
In step S501, referring to step S501 in fig. 5 and fig. 6, a first oxide layer 40 is formed on the upper surface of the control gate region.
In step S502, please refer to step S502 in fig. 5 and fig. 7, forming a second oxide layer 50 on the upper surface of the first oxide layer 40 and the upper surface of the select gate region; the second oxide layer 50 located in the selection gate region serves as a first gate oxide layer 201; the second oxide layer 50 in the control gate region and the first oxide layer 40 together form a second gate oxide layer 301.
It should be noted that the second oxide layer 50 located in the select gate region directly contacts the substrate 10 in the oxidation process, and the second oxide layer 50 located in the control gate region does not directly contact the substrate 10 but contacts the first oxide layer 40 in the oxidation process, so the thickness of the second oxide layer 50 located in the select gate region is slightly larger than the thickness of the second oxide layer 50 located in the control gate region, for example, if the thickness of the first oxide layer 40 is set to be 60 angstroms and the thickness of the second oxide layer 50 is set to be 60 angstroms in the thermal oxidation process, the thickness of the first gate oxide layer 201 finally located in the select gate region is set to be about 60 angstroms, and the thickness of the second gate oxide layer 301 formed by the second oxide layer 50 located in the control gate region and the first oxide layer 40 is set to be about 95 angstroms.
In one embodiment, as shown in fig. 8, forming the first oxide layer on the upper surface of the control gate region may include the following steps:
s801: forming an oxide material layer on the upper surface of the substrate, wherein the oxide material layer covers the upper surface of the control gate region and the upper surface of the selection gate region;
s802: and removing the oxide material layer outside the control gate region, wherein the oxide material layer remained in the control gate region is the first oxide layer.
In step S801, please refer to step S801 in fig. 8 and fig. 9, an oxide material layer 60 is formed on the upper surface of the substrate 10, and the oxide material layer 60 covers the upper surface of the control gate region and the upper surface of the select gate region.
Wherein the oxide material layer 60 may include a silicon dioxide layer or the like.
In step S802, please refer to step S802 in fig. 8 and fig. 10, the oxide material layer 60 outside the control gate region is removed, and the oxide material layer 60 remaining in the control gate region is the first oxide layer 40.
It should be noted that the process of step S802 can be implemented by designing an additional mask based on the conventional technique, and the additional mask can be directly modified based on the mask of the conventional technique during the design, and then the oxide material layer 60 in the select gate region and the oxide material layer 60 in the control gate region are removed by the subsequent exposure, patterning, etching, and other processes, so as to reduce the cost of designing the mask.
In one embodiment, as shown in fig. 11, forming a select gate structure on an upper surface of the first gate oxide layer and forming a control gate structure on an upper surface of the second gate oxide layer may comprise the steps of:
s1101: forming a first floating gate on the upper surface of the first gate oxide layer, and forming a second floating gate on the upper surface of the second gate oxide layer;
s1102: forming a first inter-gate dielectric layer on the upper surface of the second floating gate;
s1103: and forming a control gate on the upper surface of the first inter-gate dielectric layer, and forming a selection gate on the first floating gate, wherein the selection gate is in contact with the first floating gate.
In step S1101, referring to step S1101 in fig. 11 and fig. 12, a first floating gate 202 is formed on the upper surface of the first gate oxide 201, and a second floating gate 302 is formed on the upper surface of the second gate oxide 301.
In step S1102, referring to step S1102 in fig. 11 and fig. 13, a first inter-gate dielectric layer 303 is formed on the upper surface of the second floating gate 302.
The first inter-gate dielectric layer 303 may be an Oxide-Nitride-Oxide (ONO) layer.
In step S1103, please refer to step S1103 in fig. 11 and fig. 14, a control gate 304 is formed on the upper surface of the first inter-gate dielectric layer 303, and a select gate 203 is formed on the first floating gate 202, wherein the select gate 203 is in contact with the first floating gate 202.
In another embodiment, as shown in fig. 15, while forming the first inter-gate dielectric layer 303 on the upper surface of the second floating gate 302, the second inter-gate dielectric layer 204 is also formed on the upper surface of the first floating gate 202, and the second inter-gate dielectric layer 204 has an opening therein, the opening at least exposing the first floating gate 202; the select gate 203 is located on the upper surface of the second inter-gate dielectric layer 204 and fills the opening.
The second inter-gate dielectric layer 204 may be an Oxide-Nitride-Oxide (ONO) layer, the second inter-gate dielectric layer 204 and the first inter-gate dielectric layer 303 may be formed by a same process, and the second inter-gate dielectric layer 204 is etched to form an opening, which at least exposes the first floating gate 202, so that the select gate 203 contacts the first floating gate 202 through the opening.
In one embodiment, as shown in fig. 16, after forming the select gate structure 20 on the upper surface of the first gate oxide layer 201 and the control gate structure 30 on the upper surface of the second gate oxide layer 301, the method may further include: a source region 70 and a drain region 80 are formed in the substrate 10, the source region 70 being located on a side of the control gate structure 30 away from the select gate structure 20, and the drain region 80 being located on a side of the select gate structure 20 away from the control gate structure 30.
The present invention also provides a semiconductor structure, with continued reference to fig. 14, the semiconductor structure comprising: a substrate 10, the substrate 10 having a select gate region and a control gate region; a first gate oxide layer 201 on the upper surface of the select gate region; a second gate oxide layer 301 on the upper surface of the control gate region; the thickness of the second gate oxide layer 301 is larger than that of the first gate oxide layer 201; a select gate structure 20 located on the upper surface of the first gate oxide 201; and the control gate structure 30 is positioned on the upper surface of the second gate oxide layer 301.
It should be noted that, in the conventional technology, the first gate oxide layer 201 and the second gate oxide layer 301 are usually formed by the same oxidation process, that is, the thicknesses of the first gate oxide layer 201 and the second gate oxide layer 301 in the conventional technology are usually the same, that is, the thicknesses of the gate oxide layer of the select gate transistor and the gate oxide layer of the control gate transistor are the same, and are about 95 angstroms. In the conventional technology, since the first gate oxide layer 201 is thick, the threshold voltage of the select gate transistor is about-0.9V, and when the select gate transistor is switched from being selected to being unselected, the voltage is switched from-Vcc to Vcc, and the power consumption of the read operation in the process is large, about 200uA/MHZ, thereby resulting in a slow read speed, about 40ns. The thickness of the first gate oxide layer 201 is smaller than that of the second gate oxide layer 301, and the thickness of the first gate oxide layer 201 is reduced, so that the threshold voltage of the select gate transistor can be reduced, voltage switching during reading is small, power consumption of reading operation is reduced, and reading speed can be improved.
The semiconductor structure of the present invention includes: a substrate 10, the substrate 10 having a select gate region and a control gate region; a first gate oxide layer 201 on the upper surface of the select gate region; a second gate oxide layer 301 on the upper surface of the control gate region; the thickness of the second gate oxide layer 301 is larger than that of the first gate oxide layer 201; a select gate structure 20 located on the upper surface of the first gate oxide 201; and the control gate structure 30 is positioned on the upper surface of the second gate oxide layer 301. The thickness of the first gate oxide layer 201 is reduced, so that the threshold voltage of the select gate transistor can be reduced, voltage switching during reading is small, power consumption of reading is reduced, and reading speed can be improved.
In one embodiment, the thickness of the first gate oxide layer 201 is 30-90 angstroms, and the thickness of the second gate oxide layer 301 is 60-120 angstroms.
Specifically, the thickness of the first gate oxide layer 201 may be 30 angstroms, 40 angstroms, 50 angstroms, 60 angstroms, 70 angstroms, 80 angstroms, or 90 angstroms, etc.; the thickness of the second gate oxide layer 301 can be 60 angstroms, 80 angstroms, 95 angstroms, 110 angstroms, 120 angstroms, or the like.
In one example, the thickness of the first gate oxide layer 201 is 60 angstroms, the thickness of the second gate oxide layer 301 is 95 angstroms, the threshold voltage of the select gate transistor is about-0.5V, when the select gate transistor is switched from being selected to being not selected, the voltage is switched from 0V to Vcc, the power consumption of the read operation is small in the process, about 100uA/MHZ, and the read speed is about 20ns, so that the read speed can be improved.
In one embodiment, referring to fig. 14, the select gate structure 20 includes: a first floating gate 202 located on the upper surface of the first gate oxide layer 201; a select gate 203 on the first floating gate 202 and contacting the first floating gate 202; the control gate structure 30 includes: a second floating gate 302 positioned on the upper surface of the second gate oxide layer 301; a first inter-gate dielectric layer 303 located on the upper surface of the second floating gate 302; and the control gate 304 is positioned on the upper surface of the first inter-gate dielectric layer 303.
The first inter-gate dielectric layer 303 may be an Oxide-Nitride-Oxide (ONO) layer.
In one embodiment, referring to fig. 15, the select gate structure 20 further includes a second inter-gate dielectric layer 204 disposed on the upper surface of the first floating gate 202, wherein an opening is formed in the second inter-gate dielectric layer 204, and at least the first floating gate 202 is exposed through the opening; select gate 203 is located on the top surface of second inter-gate dielectric layer 204 and fills the opening.
The second inter-gate dielectric layer 204 may be an Oxide-Nitride-Oxide (ONO) layer, the second inter-gate dielectric layer 204 and the first inter-gate dielectric layer 303 may be formed by a same process, and the second inter-gate dielectric layer 204 is etched to form an opening, which at least exposes the first floating gate 202, so that the select gate 203 contacts the first floating gate 202 through the opening.
In one embodiment, referring to fig. 16, the semiconductor structure further comprises: a source region 70 located in the substrate 10 and located at a side of the control gate structure 30 away from the select gate structure 20; and a drain region 80 located in the substrate 10 and on a side of the select gate structure 20 away from the control gate structure 30.
In the description herein, references to "some embodiments," "other embodiments," "desired embodiments," or the like, mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, a schematic description of the above terminology may not necessarily refer to the same embodiment or example.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features of the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above examples only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent application shall be subject to the appended claims.
Claims (10)
1. A semiconductor structure, comprising:
a substrate having a select gate region and a control gate region;
the first gate oxide layer is positioned on the upper surface of the selection gate region;
the second gate oxide layer is positioned on the upper surface of the control gate region; the thickness of the second gate oxide layer is greater than that of the first gate oxide layer;
the first gate oxide layer comprises a second oxide layer positioned in the selection gate region, and the second gate oxide layer comprises a first oxide layer positioned in the control gate region and a second oxide layer positioned on the upper surface of the first oxide layer in the control gate region; the thickness of the second oxide layer positioned in the selection gate region is slightly larger than that of the second oxide layer positioned in the control gate region;
the selective gate structure is positioned on the upper surface of the first gate oxide layer;
the select gate structure includes: the first floating gate is positioned on the upper surface of the first gate oxide layer; the selection gate is positioned on the first floating gate and is contacted with the first floating gate; the selective grid structure also comprises a second inter-grid dielectric layer which is positioned on the upper surface of the first floating grid, an opening is formed in the second inter-grid dielectric layer, and at least the first floating grid is exposed out of the opening; the selection gate is positioned on the upper surface of the second inter-gate dielectric layer and fills the opening;
the control grid structure is positioned on the upper surface of the second grid oxide layer;
the control gate structure includes: the second floating gate is positioned on the upper surface of the second gate oxide layer; the first inter-gate dielectric layer is positioned on the upper surface of the second floating gate; and the control gate is positioned on the upper surface of the first inter-gate dielectric layer.
2. The semiconductor structure of claim 1, wherein the first gate oxide layer has a thickness of 30 to 90 angstroms and the second gate oxide layer has a thickness of 60 to 120 angstroms.
3. The semiconductor structure of claim 1, wherein the first inter-gate dielectric layer is an oxide-nitride-oxide layer.
4. The semiconductor structure of any one of claims 1 to 3, further comprising:
the source region is positioned in the substrate and positioned on one side, far away from the selection gate structure, of the control gate structure;
and the drain region is positioned in the substrate and positioned on one side of the selection gate structure far away from the control gate structure.
5. A method for fabricating a semiconductor structure, the method comprising:
providing a substrate, wherein the substrate is provided with a selection gate region and a control gate region;
forming a first oxide layer on the upper surface of the control gate region;
forming a second oxide layer on the upper surface of the first oxide layer and the upper surface of the selection gate region, wherein the thickness of the second oxide layer in the selection gate region is slightly greater than that of the second oxide layer in the control gate region; the second oxide layer positioned in the selection gate region is used as a first gate oxide layer, and the second oxide layer positioned in the control gate region and the first oxide layer jointly form a second gate oxide layer;
the thickness of the first gate oxide layer is smaller than that of the second gate oxide layer;
forming a first floating gate on the upper surface of the first gate oxide layer, and forming a second floating gate on the upper surface of the second gate oxide layer;
forming a first inter-gate dielectric layer on the upper surface of the second floating gate; meanwhile, a second inter-grid dielectric layer is formed on the upper surface of the first floating grid, an opening is formed in the second inter-grid dielectric layer, and at least the first floating grid is exposed out of the opening; the selection gate is positioned on the upper surface of the second inter-gate dielectric layer and fills the opening;
and forming a control gate on the upper surface of the first inter-gate dielectric layer, and forming a selection gate on the first floating gate, wherein the selection gate is in contact with the first floating gate.
6. The method of claim 5, wherein the second inter-gate dielectric layer is an oxide-nitride-oxide layer.
7. The method of claim 5, wherein forming a first oxide layer on the upper surface of the control gate region comprises:
forming an oxide material layer on the upper surface of the substrate, wherein the oxide material layer covers the upper surfaces of the control gate region and the selection gate region;
and removing the oxide material layer outside the control gate region, wherein the oxide material layer remained in the control gate region is the first oxide layer.
8. The method of claim 7, wherein the oxide material layer is a silicon dioxide layer.
9. The method of claim 5, wherein the first oxide layer and the second oxide layer are formed by a thermal oxidation process.
10. The method of claim 5, further comprising, after forming a select gate structure on an upper surface of said first gate oxide layer and a control gate structure on an upper surface of said second gate oxide layer:
and forming a source region and a drain region in the substrate, wherein the source region is positioned on one side of the control grid structure far away from the selection grid structure, and the drain region is positioned on one side of the selection grid structure far away from the control grid structure.
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