CN109148599B - Floating gate type split gate flash memory and manufacturing method thereof - Google Patents
Floating gate type split gate flash memory and manufacturing method thereof Download PDFInfo
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- 238000000034 method Methods 0.000 claims abstract description 56
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 24
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 14
- 238000001259 photo etching Methods 0.000 claims description 13
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
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- H01L29/772—Field effect transistors
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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Abstract
The invention discloses a floating gate type split gate flash memory, and a unit structure comprises: the first grid structure, the second grid structure, the third grid structure and the source drain region are symmetrically arranged on two sides of the second grid structure; the first grid structure and the third grid structure are used as storage bits, the width of the polycrystalline silicon control grid is defined by the self-alignment of the first inner side wall, and the width of the polycrystalline silicon floating grid is defined by the self-alignment of the first inner side wall and a first outer side wall positioned outside the first inner side wall; and a second outer side wall is formed outside the outer side surface of the first outer side wall in a self-alignment mode, and the size of a source drain contact hole at the top of the shared source drain region is defined by self-alignment of the distance between the first outer side wall and the second outer side wall between the unit structures. The invention also discloses a manufacturing method of the floating gate type split gate flash memory. The invention can adopt the self-alignment process to realize the source drain contact holes, and adopts the self-alignment process to define the sizes of the polysilicon control gate and the polysilicon floating gate corresponding to the storage bit, thereby further reducing the area of the storage unit and improving the storage density.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuits, and more particularly, to a Floating-gate flash memory. The invention also relates to a manufacturing method of the floating gate type split gate flash memory.
Background
The split-gate floating gate flash memory, i.e., the floating gate type split-gate flash memory technology, is widely used in various embedded electronic products such as financial IC cards, automotive electronics, and the like. The memory integration density is improved, so that the chip area is saved, and the manufacturing cost is reduced.
Two floating gates in a memory cell of the existing two-bit (bit) per memory cell (cell), namely a 2-bit/cell split-gate floating gate flash memory share one selection tube, which is beneficial to reducing the area of the memory cell.
The existing manufacturing process of the 2-bit/cell split-gate floating gate flash memory is a triple self-alignment process, the size of the device can be well reduced by the existing method, and the sizes (sizes) of a control gate, a selection gate and a floating gate are not limited by photoetching. However, as the size of the device is made smaller, the proportion of the size of the contact hole of the memory cell to the area of the whole memory cell is larger and larger, because the contact hole of the source and the drain is not self-aligned etched. If the source drain contact hole can be realized in a self-alignment mode, the area of a single storage unit can be further reduced, and the cost is reduced.
Disclosure of Invention
The invention aims to solve the technical problem of providing a floating gate type split gate flash memory, which can realize source and drain contact holes by adopting a self-alignment process, and can further reduce the area of a storage unit and improve the storage density by adopting the self-alignment process to define the sizes of a polysilicon control gate and a polysilicon floating gate corresponding to storage bits. Therefore, the invention also provides a manufacturing method of the floating gate type split gate flash memory.
In order to solve the above technical problem, the cell structure of the floating gate type split gate flash memory provided by the present invention comprises: the semiconductor device comprises a first grid structure, a second grid structure, a third grid structure, a first source drain region and a second source drain region.
The area between the first source drain area and the second source drain area is a grid area, the first grid structure, the second grid structure and the third grid structure are sequentially and transversely arranged in the grid area, and the first grid structure and the third grid structure are symmetrically arranged on two sides of the second grid structure.
The first grid structure is formed by superposing a first grid dielectric layer, a polycrystalline silicon floating grid, a second grid dielectric layer, a polycrystalline silicon control grid, a first inner side wall and a first outer side wall which are formed on the surface of the semiconductor substrate on the first side of the second grid structure; a first bit of information is stored by the polysilicon floating gate of the first gate structure.
The third grid structure is formed by superposing a first grid dielectric layer, a polycrystalline silicon floating grid, a second grid dielectric layer, a polycrystalline silicon control grid, a first inner side wall and a first outer side wall which are formed on the surface of the semiconductor substrate on the second side of the second grid structure; a second bit of information is stored by the polysilicon floating gate of the third gate structure.
In the gate region, a second opening formed by enclosing the inner side surface of the second gate dielectric layer and the inner side surface of the polysilicon control gate is defined by self-aligning a first opening, and the first opening is formed by photoetching and etching the first dielectric layer; the first inner side wall is formed on the inner side face of the superposed structure of the first opening and the second opening, and the material of the first dielectric layer is different from that of the first inner side wall and has different etching rates.
And a third opening is formed by the inner side surface of the first inner side wall in a surrounding manner, and a fourth opening formed by the inner side surface of the first gate dielectric layer and the inner side surface of the polysilicon floating gate in a surrounding manner is defined by the third opening in a self-aligned manner.
And the overlapping area of the fourth opening and the third opening defines a forming area of the second gate structure in a self-alignment manner, and the second gate structure comprises a third gate dielectric layer formed on the bottom surface and the side surface of the fourth opening and the side surface of the third opening and a polysilicon selection gate filled in the overlapping area of the fourth opening and the third opening.
The first dielectric layer is removed in a self-aligning mode after the polycrystalline silicon selection gate is formed, the outer side face of the first inner side wall is exposed in a self-aligning mode, the first outer side wall is formed on the corresponding outer side face of the first inner side wall in a self-aligning mode, the first outer side wall is made of different materials and has different etching rates.
And the outer side surfaces of the first outer side wall are self-aligned to define the corresponding outer side surfaces of the first gate dielectric layer, the polysilicon floating gate, the second gate dielectric layer and the polysilicon control gate.
And the second outer side wall is formed on the outer side surfaces of the first gate dielectric layer, the polycrystalline silicon floating gate, the second gate dielectric layer and the polycrystalline silicon control gate in a self-aligned mode and the outer side surface of the first outer side wall.
The first source-drain regions are self-aligned with the outer side faces of the second outer side walls corresponding to the first grid structures, and the second source-drain regions are self-aligned with the outer side faces of the second outer side walls corresponding to the third grid structures.
And forming corresponding source drain contact holes on the tops of the first source drain region and the second source drain region respectively.
The first source-drain region is shared by two adjacent unit structures or the second source-drain region is shared by two adjacent unit structures, the corresponding source-drain contact holes are shared by the two adjacent unit structures, the bottom area of the source-drain contact holes is defined by the outer side faces of the superposed structure of the first outer side wall and the second outer side wall in a self-aligned mode, the top of each source-drain contact hole penetrates through the interlayer film, the first outer side wall is made of a material different from that of the interlayer film and has different etching rates, and the second outer side wall is made of a material different from that of the interlayer film and has different etching rates.
In a further improvement, the semiconductor substrate is a silicon substrate.
In a further improvement, the first dielectric layer is made of silicon nitride.
The first inner side wall is made of silicon oxide.
The first outer side wall is made of silicon nitride.
The second outer side wall is made of silicon nitride.
The material of the interlayer film is silicon oxide.
In a further improvement, the first gate dielectric layer is made of an oxide layer.
The second gate dielectric layer is composed of an oxide layer, a nitride layer and an oxide layer which are sequentially stacked.
And the material oxide layer of the third gate dielectric layer.
The first source drain region comprises a lightly doped drain region, the second source drain region comprises a lightly doped drain region, and the lightly doped drain region is self-aligned with the outer side face of the corresponding first outer side wall.
The further improvement is that a gate contact hole is formed at the top of the polysilicon selection gate; the gate contact hole penetrates through the interlayer film.
Word lines and bit lines formed by imaging of the front metal layer are formed on the surface of the interlayer film, the polycrystalline silicon selection gate is connected to the corresponding word line through the gate contact hole, the first source drain region is connected to the corresponding bit line through the source drain contact hole in the top, and the second source drain region is connected to the corresponding bit line through the source drain contact hole in the top.
In a further improvement, self-aligned metal silicide is formed at the bottom of both the gate contact hole and the source drain contact hole.
In order to solve the above technical problem, the method for manufacturing a floating gate type split gate flash memory provided by the present invention comprises the following steps:
the method comprises the following steps of firstly, sequentially forming a first gate dielectric layer and a first polycrystalline silicon layer on the surface of a semiconductor substrate;
and then, forming a shallow trench isolation structure, comprising the following steps: forming a hard mask layer on the surface of the first polycrystalline silicon layer, defining a forming region of a shallow trench by photoetching, etching the hard mask layer, the first polycrystalline silicon layer, the first gate dielectric layer and the semiconductor substrate in the forming region of the shallow trench in sequence, forming a shallow trench in the semiconductor substrate, filling an oxidation layer in the shallow trench to form a shallow trench isolation structure, and isolating an active region on the semiconductor substrate by the shallow trench isolation structure;
and after the active region is defined, removing the hard mask layer and sequentially forming a second gate dielectric layer, a second polysilicon layer and a first dielectric layer, wherein the second gate dielectric layer is superposed on the surface of the first polysilicon layer in the active region.
And secondly, forming a first opening in the first dielectric layer by adopting a photoetching definition and etching process, removing the first dielectric layer in the first opening and exposing the surface of the second polycrystalline silicon layer.
And thirdly, etching the second polycrystalline silicon layer and the second gate dielectric layer at the bottom of the first opening by taking the inner side surface of the first opening as a self-alignment condition to form a second opening.
And fourthly, forming a first inner side wall on the inner side surface of the superposed structure of the first opening and the second opening in a self-alignment manner by adopting a deposition and comprehensive anisotropic etching process, and enclosing a third opening by the first inner side wall, wherein the material of the first dielectric layer is different from that of the first inner side wall and has different etching rates.
And fifthly, etching the first polycrystalline silicon layer and the first gate dielectric layer at the bottom of the third opening by taking the inner side surface of the third opening as a self-alignment condition to form a fourth opening.
And sixthly, filling a third polycrystalline silicon layer in the superposed area of the fourth opening and the third opening, wherein the superposed area is provided with the third gate dielectric layer, and forming a polycrystalline silicon selection gate.
The second grid structure of the unit structure of the floating grid type split-grid flash memory comprises the third grid dielectric layer and the polysilicon selection grid.
And seventhly, removing the first dielectric layer in a self-alignment manner and exposing the outer side face of the first inner side wall in a self-alignment manner.
And step eight, forming a first outer side wall on the outer side surface of the first inner side wall in a self-alignment mode by adopting a deposition and comprehensive anisotropic etching process, wherein the material of the first outer side wall is different from that of the first inner side wall, and the material of the first outer side wall and the material of the first inner side wall have different etching rates.
And ninthly, etching the second polycrystalline silicon layer, the second gate dielectric layer, the first polycrystalline silicon layer and the first gate dielectric layer in sequence by taking the outer side surface of the first outer side wall as a self-alignment condition to form a first gate structure and a third gate structure.
In the unit structure, the first gate structure and the third gate structure are symmetrically arranged on two sides of the second gate structure.
The first grid structure is formed by superposing a first grid dielectric layer, a polycrystalline silicon floating grid, a second grid dielectric layer, a polycrystalline silicon control grid, a first inner side wall and a first outer side wall which are formed on the surface of the semiconductor substrate on the first side of the second grid structure; a first bit of information is stored by the polysilicon floating gate of the first gate structure.
The third grid structure is formed by superposing a first grid dielectric layer, a polycrystalline silicon floating grid, a second grid dielectric layer, a polycrystalline silicon control grid, a first inner side wall and a first outer side wall which are formed on the surface of the semiconductor substrate on the second side of the second grid structure; a second bit of information is stored by the polysilicon floating gate of the third gate structure.
The polycrystalline silicon floating gate is formed by the etched first polycrystalline silicon layer, the inner side face of the polycrystalline silicon floating gate is formed by the etching process of the first polycrystalline silicon layer in the fifth step, and the outer side face of the polycrystalline silicon floating gate is formed by the etching process of the first polycrystalline silicon layer in the ninth step.
The polycrystalline silicon control gate is composed of the etched second polycrystalline silicon layer, the inner side face of the polycrystalline silicon control gate is formed by the etching process of the second polycrystalline silicon layer in the third step, and the outer side face of the polycrystalline silicon control gate is formed by the etching process of the second polycrystalline silicon layer in the ninth step.
Step ten, forming a second outer side wall in a self-alignment manner on the outer side surfaces of the first gate dielectric layer, the polycrystalline silicon floating gate, the second gate dielectric layer, the polycrystalline silicon control gate and the outer side surface of the first outer side wall by adopting a deposition and comprehensive anisotropic etching process.
And eleventh, performing source-drain injection by taking the outer side face of the second outer side wall as a self-alignment condition to form a first source-drain region and a second source-drain region, wherein the first source-drain region is self-aligned with the outer side face of the second outer side wall corresponding to the first gate structure, and the second source-drain region is self-aligned with the outer side face of the second outer side wall corresponding to the third gate structure.
The unit structure of the floating gate type split gate flash memory comprises: the first gate structure, the second gate structure, the third gate structure, the first source drain region and the second source drain region.
The region between the first source-drain region and the second source-drain region is a gate region, and the first gate structure, the second gate structure and the third gate structure are sequentially and transversely arranged in the gate region.
Step twelve, forming an interlayer film to form a contact hole; the contact hole comprises a source drain contact hole positioned at the top of the first source drain region and the second source drain region; the contact hole also comprises a gate contact hole formed at the top of the polysilicon selection gate, and the gate contact hole penetrates through the interlayer film.
The first source-drain region is shared by two adjacent unit structures or the second source-drain region is shared by two adjacent unit structures, the corresponding source-drain contact holes are shared by the two adjacent unit structures, the bottom area of the source-drain contact holes is defined by the outer side faces of the superposed structure of the first outer side wall and the second outer side wall in a self-aligned mode, the top of each source-drain contact hole penetrates through the interlayer film, the first outer side wall is made of a material different from that of the interlayer film and has different etching rates, and the second outer side wall is made of a material different from that of the interlayer film and has different etching rates.
And step thirteen, forming a front metal layer on the surface of the interlayer film, imaging and forming word lines and bit lines consisting of the front metal layer.
The polysilicon selection gate is connected to a corresponding word line through the gate contact hole, the first source drain region is connected to a corresponding bit line through the source drain contact hole at the top, and the second source drain region is connected to a corresponding bit line through the source drain contact hole at the top.
In a further improvement, the semiconductor substrate is a silicon substrate.
In a further improvement, the first dielectric layer is made of silicon nitride.
The first inner side wall is made of silicon oxide.
The first outer side wall is made of silicon nitride.
The second outer side wall is made of silicon nitride.
The material of the interlayer film is silicon oxide.
In a further improvement, the first gate dielectric layer is made of an oxide layer.
The second gate dielectric layer is composed of an oxide layer, a nitride layer and an oxide layer which are sequentially stacked.
And the material oxide layer of the third gate dielectric layer.
The first source drain region comprises a lightly doped drain region, the second source drain region comprises a lightly doped drain region, the lightly doped drain region is formed by lightly doped drain injection after the etching process in the ninth step is completed and before the second outer side wall is formed in the tenth step, and the lightly doped drain injection takes the outer side face of the first outer side wall as a self-alignment condition.
In a further improvement, in the eighth step, the material deposition thickness of the first outer sidewall is
In a further improvement, in the sixth step, the third polysilicon layer is formed by a deposition process, the deposited third polysilicon layer completely fills a superposed region of the fourth opening and the third opening and extends out of the third opening, and the third gate dielectric layer also extends out of the third opening; and then, removing the third polysilicon layer and the third gate dielectric layer outside the third opening by taking the first dielectric layer as a stop layer and adopting a chemical mechanical polishing process, wherein the surfaces of the third polysilicon layer and the first dielectric layer in the third opening area are level and form the polysilicon selection gate.
And then, forming a thermal oxidation layer on the top surface of the polysilicon selection gate by adopting a thermal oxidation process.
In a further improvement, in the twelfth step, after the interlayer film is formed, a step of forming a self-aligned metal silicide at the bottoms of the gate contact hole and the source drain contact hole is further included.
In the invention, the inner side surface of the polysilicon control gate is defined by the inner side surface of the first opening in a self-aligning way, the inner side surface of the first opening is also the outer side surface of the first inner side wall and the inner side surface of the first outer side wall, and the outer side surface of the polysilicon control gate is defined by the outer side surface of the first outer side surface in a self-aligning way.
According to the invention, the inner side surface of the polysilicon floating gate is defined by the inner side surface of the first inner side wall in a self-aligned manner, the outer side surface of the polysilicon floating gate is defined by the outer side surface of the first outer side wall in a self-aligned manner, so that the width of the polysilicon floating gate is determined by the sum of the width of the first inner side wall and the width of the first outer side wall, and the first inner side wall and the first outer side wall are both formed by adopting a self-aligned process. The self-aligned structure of the polysilicon floating gate and the polysilicon control gate can greatly reduce the size of the cell structure, thereby reducing the area of the memory cell and improving the memory density.
The structure between the unit structures is also designed, and the second outer side wall is formed outside the first outer side wall, so that the width of the source drain contact hole can be defined by utilizing the self-alignment of the distance between the combined structures of the first outer side wall and the second outer side wall of the adjacent unit structures, and therefore, the bottom size of the source drain contact hole does not need to be defined by photoetching, the distance between the adjacent unit structures can be greatly reduced, and the area of a storage unit can be further reduced and the storage density can be improved.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIGS. 1A to 1E are unit structure diagrams of a device in each step of a conventional method for manufacturing a floating gate type split gate flash memory;
FIG. 2 is a diagram of a cell structure of a floating gate type split gate flash memory according to an embodiment of the present invention;
fig. 3A to 3H are unit structure diagrams of devices in steps of a method for manufacturing a floating gate type split gate flash memory according to an embodiment of the present invention.
Detailed Description
The existing manufacturing method of the floating gate type split gate flash memory comprises the following steps:
before describing the embodiment of the present invention in detail, a method for manufacturing a conventional floating gate type split gate flash memory will now be described, as shown in fig. 1A to 1E, which are unit structure diagrams of devices in each step of the method for manufacturing a conventional floating gate type split gate flash memory; the manufacturing method of the existing floating gate type split gate flash memory comprises the following steps:
step one, as shown in fig. 1A, a first gate dielectric layer, such as an oxide layer, and a polysilicon floating gate 302 are sequentially formed on a surface of a semiconductor substrate, such as a silicon substrate 301, and a silicon nitride layer 303a is formed on the surface of the polysilicon floating gate 302.
And step two, defining a Shallow Trench Isolation (STI) region, etching the silicon nitride layer 303a, the polysilicon floating gate 302, the first gate dielectric layer and the semiconductor substrate 301 in sequence to form a shallow trench 304, and filling an oxidation layer in the shallow trench 304 to form the STI. STI is used to define different active regions on the semiconductor substrate 301, and the floating gate type split gate flash memory is formed in the corresponding active region.
After that, the silicon nitride layer 303a is removed.
Step three, as shown in fig. 1B, the STI is not shown in fig. 1B, but the cell structure formed in the active region is directly shown.
Then, a second gate dielectric layer such as an ONO layer, a polysilicon control gate 305, and a silicon nitride layer 303 are sequentially formed to define a gate forming region, and the silicon nitride layer 303 in the gate forming region is removed to form a first opening.
And fourthly, forming a first inner side wall 306 on the inner side surface of the first opening, and enclosing the inner side wall of the first inner side wall 306 into a second opening.
The polysilicon control gate 305 and the ONO layer are sequentially etched with the second opening as a self-aligned condition and a third opening is formed.
Step five, as shown in fig. 1C, a second inner side wall 307 is formed on the inner side surfaces of the third opening and the second opening, and a fourth opening is surrounded by the inner side surface of the second inner side wall 307.
And sixthly, as shown in fig. 1D, sequentially forming a third gate dielectric layer such as an oxide layer 308 and a polysilicon select gate 309 in the fourth opening.
Step seven, as shown in fig. 1E, then, performing thermal oxidation on the top of the polysilicon select gate 309 to form a protection layer 310, and then removing the silicon nitride layer 303 in a self-aligned manner; and sequentially etching the polysilicon control gate 305, the second gate dielectric layer, the polysilicon floating gate 302 and the first gate dielectric layer by taking the outer side surface of the first inner side wall 306 as a self-alignment condition, and forming the outer side surface of the corresponding gate structure.
Step eight, as shown in fig. 1E, performing source-drain implantation to form a first source-drain region 311a and a second source-drain region 311b with the outer side of the corresponding gate structure as a self-aligned condition.
The method further comprises a step of forming corresponding source and drain contact holes on the tops of the first source and drain regions 311a and the second source and drain regions 311b, and a step of forming a gate contact hole on the top of the polysilicon select gate 309. Contact holes are also formed in the top of polysilicon control gate 305.
As can be seen from the above, the width of the polysilicon control gate 305 in the prior art method is defined by the width self-alignment of the first inner sidewall 306, and the width of the polysilicon floating gate 302 is defined by the width self-alignment of the first inner sidewall 306 and the second inner sidewall 307. The width of the entire gate region of the prior method is defined by the first opening formed in fig. 1B. Since the polysilicon floating gate 302 and the polysilicon control gate 305 can be defined by self-alignment, the gate area can be reduced, thereby increasing the storage density. However, in the existing method, the source-drain contact hole needs to be defined by photolithography, and along with the development of the process, the size of the source-drain contact hole becomes a factor that restricts the further reduction of the size of the memory cell structure and the further improvement of the memory density.
The floating gate type split gate flash memory of the embodiment of the invention comprises the following steps:
as shown in fig. 2, which is a structure diagram of a cell of a floating gate type split gate flash memory according to an embodiment of the present invention, the cell structure of the floating gate type split gate flash memory according to the embodiment of the present invention includes: a first gate structure 401, a second gate structure 402, a third gate structure 403, a first source drain region 13a and a second source drain region 13 b.
The region between the first source-drain region 13a and the second source-drain region 13b is a gate region, the first gate structure 401, the second gate structure 402 and the third gate structure 403 are sequentially and transversely arranged in the gate region, and the first gate structure 401 and the third gate structure 403 are symmetrically arranged on two sides of the second gate structure 402.
The first gate structure 401 is formed by overlapping a first gate dielectric layer 3, a polysilicon floating gate 4, a second gate dielectric layer 5, a polysilicon control gate 6, a first inner side wall 8 and a first outer side wall 7 which are formed on the surface of the semiconductor substrate 1 on the first side of the second gate structure 402; a first bit of information is stored by the polysilicon floating gate 4 of the first gate structure 401.
The third gate structure 403 is formed by overlapping a first gate dielectric layer 3, a polysilicon floating gate 4, a second gate dielectric layer 5, a polysilicon control gate 6, a first inner side wall 8 and a first outer side wall 7 which are formed on the surface of the semiconductor substrate 1 on the second side of the second gate structure 402; a second bit of information is stored by the polysilicon floating gate 4 of the third gate structure 403.
In the gate region, a second opening surrounded by the inner side surface of the second gate dielectric layer 5 and the inner side surface of the polysilicon control gate 6 is defined by self-aligning a first opening, the first opening is formed by photoetching and etching a first dielectric layer 101, and the first dielectric layer 101 is shown in fig. 3B; the first inner side wall 8 is formed on the inner side surface of the superposed structure of the first opening and the second opening, and the material of the first dielectric layer 101 is different from the material of the first inner side wall 8 and has different etching rates.
And a third opening is defined by the inner side surface of the first inner side wall 8 in a surrounding manner, and a fourth opening is defined by the inner side surface of the first gate dielectric layer 3 and the inner side surface of the polysilicon floating gate 4 in a self-aligned manner through the third opening.
The overlapping area of the fourth opening and the third opening defines a forming area of the second gate structure 402 in a self-aligned manner, and the second gate structure 402 includes a third gate dielectric layer 2 formed on the bottom surface and the side surface of the fourth opening and the side surface of the third opening, and a polysilicon select gate 10 filled in the overlapping area of the fourth opening and the third opening.
The first dielectric layer 101 is removed by self-alignment after the formation of the polysilicon select gate 10 and exposes the outer side of the first inner sidewall 8 by self-alignment, the first outer sidewall 7 is formed on the corresponding outer side of the first inner sidewall 8 by self-alignment, and the material of the first outer sidewall 7 is different from the material of the first inner sidewall 8 and has different etching rates.
The outer side surfaces of the first outer side walls 7 are self-aligned to define the corresponding outer side surfaces of the first gate dielectric layer 3, the polysilicon floating gate 4, the second gate dielectric layer 5 and the polysilicon control gate 6.
The second outer side wall 11 is formed on the outer side surfaces of the first gate dielectric layer 3, the polysilicon floating gate 4, the second gate dielectric layer 5 and the polysilicon control gate 6 and the outer side surface of the first outer side wall 7 in a self-aligned manner.
The first source-drain region 13a is self-aligned with the outer side surface of the second outer side wall 11 corresponding to the first gate structure 401, and the second source-drain region 13b is self-aligned with the outer side surface of the second outer side wall 11 corresponding to the third gate structure 403.
And corresponding source drain contact holes 15 are formed at the tops of the first source drain region 13a and the second source drain region 13b respectively.
The adjacent two unit structures share the first source-drain region 13a or share the second source-drain region 13b and share the corresponding source-drain contact hole 15, the bottom area of the shared source-drain contact hole 15 is defined by the outer side surface of the superposed structure of the adjacent two first outer side walls 7 and the second outer side wall 11 in a self-aligned manner, the top of the source-drain contact hole 15 penetrates through the interlayer film 14, the material of the first outer side wall 7 is different from that of the interlayer film 14, the material of the second outer side wall 11 is different from that of the interlayer film 14, and the material of the second outer side wall 11 is different from that of the interlayer film 14 and has different etching rates.
In the embodiment of the present invention, the semiconductor substrate 1 is a silicon substrate.
The first dielectric layer 101 is made of silicon nitride.
The first inner side wall 8 is made of silicon oxide.
The material of the first outer sidewall 7 is silicon nitride.
The second outer side wall 11 is made of silicon nitride. In the embodiment of the present invention, silicon oxide sidewalls 9 made of silicon oxide are further formed on the sides of the polysilicon control gate 6 and the polysilicon floating gate 4.
The material of the interlayer film 14 is silicon oxide.
The first gate dielectric layer 3 is made of an oxide layer.
The second gate dielectric layer 5 is formed by an ONO layer formed by an oxide layer, a nitride layer and an oxide layer which are sequentially stacked.
And the third gate dielectric layer 2 is made of an oxide layer.
The first source drain region 13a includes a lightly doped drain region 12a, the second source drain region 13b includes a lightly doped drain region 12b, and the lightly doped drain region is self-aligned with the outer side surface of the corresponding first outer side wall 7.
A gate contact hole 16 is formed at the top of the polysilicon selection gate 10; the gate contact hole 16 passes through the interlayer film 14. The gate contact hole 16 needs to be defined by a photolithography process.
A control gate contact is also formed on top of the polysilicon control 6, but the control gate contact is not at the cross-sectional position shown in fig. 2, so the control gate contact is not shown in fig. 2.
Word lines and bit lines formed by imaging of a front metal layer are formed on the surface of the interlayer film 14, the polysilicon select gate 10 is connected to the corresponding word line through the gate contact hole 16, the first source drain region 13a is connected to the corresponding bit line through the source drain contact hole 15 at the top, and the second source drain region 13b is connected to the corresponding bit line through the source drain contact hole 15 at the top.
Self-aligned metal silicide 17 is formed at the bottom of the gate contact hole 16 and the source drain contact hole 15.
In the embodiment of the present invention, the inner side surface of the polysilicon control gate 6 is defined by the inner side surface of the first opening in a self-aligned manner, the inner side surface of the first opening is also the outer side surface of the first inner side wall 8 and the inner side surface of the first outer side wall 7, and the outer side surface of the polysilicon control gate 6 is defined by the outer side surface of the first outer side surface in a self-aligned manner.
In the embodiment of the invention, the inner side surface of the polysilicon floating gate 4 is defined by the inner side surface of the first inner side wall 8 in a self-aligned manner, the outer side surface of the polysilicon floating gate 4 is defined by the outer side surface of the first outer side wall 7 in a self-aligned manner, so that the width of the polysilicon floating gate 4 is determined by the sum of the width of the first inner side wall 8 and the width of the first outer side wall 7, the first inner side wall 8 and the first outer side wall 7 are both formed by adopting a self-aligned process, the width of the polysilicon floating gate 4 in the embodiment of the invention is not required to be defined by adopting photoetching, and the width of the polysilicon floating gate can be reduced to be below the photoetching limit size. The self-aligned structure of the polysilicon floating gate 4 and the polysilicon control gate 6 can greatly reduce the size of the cell structure, thereby reducing the area of the memory cell and improving the memory density.
The embodiment of the invention also designs the structures between the unit structures, and the embodiment of the invention combines the first outer side wall 7 and then forms the second outer side wall 11, so that the width of the source/drain contact hole 15 can be defined by utilizing the self-alignment of the distance between the combined structures of the first outer side wall 7 and the second outer side wall 11 of the adjacent unit structures, therefore, the bottom size of the source/drain contact hole 15 in the embodiment of the invention does not need to be defined by photoetching, the distance between the adjacent unit structures can be greatly reduced, and the area of a storage unit can be further reduced and the storage density can be further improved.
The manufacturing method of the floating gate type split gate flash memory of the embodiment of the invention comprises the following steps:
as shown in fig. 3A to fig. 3H, the cell structure diagrams of the devices in the steps of the method for manufacturing the floating gate type split-gate flash memory according to the embodiment of the present invention are shown, and the method for manufacturing the floating gate type split-gate flash memory according to the embodiment of the present invention includes the following steps:
step one, as shown in fig. 3A, a first gate dielectric layer 3 and a first polysilicon layer 4 are sequentially formed on the surface of the semiconductor substrate 1.
And then, forming a shallow trench isolation structure, comprising the following steps: a hard mask layer 501 is formed on the surface of the first polysilicon layer 4, and the material of the hard mask layer 501 includes an oxide layer or a nitride layer, and generally, a structure of an oxide layer and a nitride layer is adopted. Defining a forming area of a shallow trench 502 by photoetching, etching a hard mask layer 501, the first polysilicon layer 4, the first gate dielectric layer 3 and the semiconductor substrate 1 in the forming area of the shallow trench in sequence, forming the shallow trench 502 in the semiconductor substrate 1, filling an oxidation layer in the shallow trench 502 to form a shallow trench isolation structure, and isolating an active area on the semiconductor substrate 1 by the shallow trench isolation structure;
after the active region is defined, the hard mask layer 501 is removed, and a second gate dielectric layer 5, a second polysilicon layer 5 and a first dielectric layer 101 are sequentially formed. As shown in fig. 3B, in the active region, the second gate dielectric layer 5 is overlapped on the surface of the first polysilicon layer 4. Fig. 3B does not show the structure of the sti region, but only shows the structure of the active region.
In the method of the embodiment of the invention, the semiconductor substrate 1 is a silicon substrate.
The first dielectric layer 101 is made of silicon nitride.
The first gate dielectric layer 3 is made of an oxide layer.
The second gate dielectric layer 5 is formed by an ONO layer formed by an oxide layer, a nitride layer and an oxide layer which are sequentially stacked.
Step two, as shown in fig. 3B, a first opening is formed in the first dielectric layer 101 by using a process of lithography definition plus etching, the first dielectric layer 101 in the first opening is removed, and the surface of the second polysilicon layer 5 is exposed.
And step three, as shown in fig. 3B, etching the second polysilicon layer 5 and the second gate dielectric layer 5 at the bottom of the first opening by taking the inner side surface of the first opening as a self-alignment condition to form a second opening.
Step four, as shown in fig. 3C, a first inner sidewall 8 is formed on the inner side surface of the stacked structure of the first opening and the second opening in a self-alignment manner by using a deposition and overall anisotropic etching process, a third opening is surrounded by the first inner sidewall 8, and the material of the first dielectric layer 101 is different from the material of the first inner sidewall 8 and has different etching rates.
In the embodiment of the present invention, the first inner sidewall 8 is made of silicon oxide.
And fifthly, as shown in fig. 3D, etching the first polysilicon layer 4 and the first gate dielectric layer 3 at the bottom of the third opening by taking the inner side surface of the third opening as a self-alignment condition to form a fourth opening.
And sixthly, as shown in fig. 3D, forming a third gate dielectric layer 2 on the bottom surface and the side surface of the fourth opening and the side surface of the third opening.
And the third gate dielectric layer 2 is made of an oxide layer.
As shown in fig. 3F, a third polysilicon layer 10 is filled in the overlapping region of the fourth opening and the third opening where the third gate dielectric layer 2 is formed, and a polysilicon select gate 10 is formed.
The second gate structure 402 of the cell structure of the floating gate type split gate flash memory includes the third gate dielectric layer 2 and the polysilicon select gate 10.
In the method according to the embodiment of the present invention, as shown in fig. 3E, the third polysilicon layer 10 is formed by a deposition process, the deposited third polysilicon layer 10 completely fills an overlapping region of the fourth opening and the third opening and extends to the outside of the third opening, and the third gate dielectric layer 2 also extends to the outside of the third opening.
Then, as shown in fig. 3F, the first dielectric layer 101 is used as a stop layer, and a chemical mechanical polishing process is used to remove both the third polysilicon layer 10 and the third gate dielectric layer 2 outside the third opening, and the surfaces of the third polysilicon layer 10 and the first dielectric layer 101 in the third opening region are leveled to form the polysilicon select gate 10.
Then, as shown in fig. 3F, a thermal oxide layer 102 is formed on the top surface of the polysilicon select gate 10 by using a thermal oxidation process, and the thermal oxide layer 2 is used as a protective layer for protecting the polysilicon select gate 10 in the subsequent step of removing the first dielectric layer 101.
Seventhly, as shown in fig. 3G, the first dielectric layer 101 is removed in a self-aligned manner, and the outer side of the first inner sidewall spacer 8 is exposed in a self-aligned manner.
Step eight, as shown in fig. 3G, a first outer sidewall 7 is formed on the outer side surface of the first inner sidewall 8 in a self-alignment manner by using a deposition and overall anisotropic etching process, and the material of the first outer sidewall 7 is different from the material of the first inner sidewall 8 and has different etching rates.
The material of the first outer sidewall 7 is silicon nitride.
The first outer side wall 7 is deposited with a material deposition thickness of
Step nine, as shown in fig. 3H, the outer side surface of the first outer sidewall 7 is self-aligned, and the second polysilicon layer 5, the second gate dielectric layer 5, the first polysilicon layer 4, and the first gate dielectric layer 3 are sequentially etched to form a first gate structure 401 and a third gate structure 403.
In the unit structure, the first gate structure 401 and the third gate structure 403 are symmetrically disposed at both sides of the second gate structure 402.
The first gate structure 401 is formed by overlapping a first gate dielectric layer 3, a polysilicon floating gate 4, a second gate dielectric layer 5, a polysilicon control gate 6, a first inner side wall 8 and a first outer side wall 7 which are formed on the surface of the semiconductor substrate 1 on the first side of the second gate structure 402; a first bit of information is stored by the polysilicon floating gate 4 of the first gate structure 401.
The third gate structure 403 is formed by overlapping a first gate dielectric layer 3, a polysilicon floating gate 4, a second gate dielectric layer 5, a polysilicon control gate 6, a first inner side wall 8 and a first outer side wall 7 which are formed on the surface of the semiconductor substrate 1 on the second side of the second gate structure 402; a second bit of information is stored by the polysilicon floating gate 4 of the third gate structure 403.
The polycrystalline silicon floating gate 4 is composed of the etched first polycrystalline silicon layer 4, the inner side face of the polycrystalline silicon floating gate 4 is formed by the etching process of the first polycrystalline silicon layer 4 in the fifth step, and the outer side face of the polycrystalline silicon floating gate 4 is formed by the etching process of the first polycrystalline silicon layer 4 in the ninth step.
The polysilicon control gate 6 is composed of the etched second polysilicon layer 5, the inner side surface of the polysilicon control gate 6 is formed by the etching process of the second polysilicon layer 5 in the third step, and the outer side surface of the polysilicon control gate 6 is formed by the etching process of the second polysilicon layer 5 in the ninth step.
Tenthly, as shown in fig. 3H, depositing and overall anisotropic etching processes are adopted to self-align the outer side surfaces of the first gate dielectric layer 3, the polysilicon floating gate 4, the second gate dielectric layer 5, the polysilicon control gate 6 and the first outer side wall 7 to form a second outer side wall 11.
The second outer side wall 11 is made of silicon nitride.
Eleventh, as shown in fig. 3H, source-drain implantation is performed with the outer side surface of the second outer sidewall 11 as a self-aligned condition to form a first source-drain region 13a and a second source-drain region 13b, where the first source-drain region 13a is self-aligned with the outer side surface of the second outer sidewall 11 corresponding to the first gate structure 401, and the second source-drain region 13b is self-aligned with the outer side surface of the second outer sidewall 11 corresponding to the third gate structure 403.
The unit structure of the floating gate type split gate flash memory comprises: the first gate structure 401, the second gate structure 402, the third gate structure 403, the first source drain region 13a, and the second source drain region 13 b.
The region between the first source-drain region 13a and the second source-drain region 13b is a gate region, and the first gate structure 401, the second gate structure 402 and the third gate structure 403 are sequentially and transversely arranged in the gate region.
In the method of the embodiment of the invention, the first source drain region 13a includes a lightly doped drain region 12a, the second source drain region 13b includes a lightly doped drain region 12b, the lightly doped drain regions 12a and 12b are formed by lightly doped drain implantation after the etching process of the ninth step is completed and before the second outer side wall 11 is formed in the tenth step, and the lightly doped drain implantation takes the outer side surface of the first outer side wall 7 as a self-alignment condition.
Step twelve, as shown in fig. 2, forming an interlayer film 14 to form a contact hole; the contact holes comprise source drain contact holes 15 positioned at the tops of the first source drain region 13a and the second source drain region 13 b; the contact hole further includes a gate contact hole 16 formed at the top of the polysilicon select gate 10, the gate contact hole 16 penetrating the interlayer film 14.
A control gate contact is also formed on top of the polysilicon control 6, but the control gate contact is not at the cross-sectional position shown in fig. 2, so the control gate contact is not shown in fig. 2.
The material of the interlayer film 14 is silicon oxide.
The adjacent two unit structures share the first source-drain region 13a or share the second source-drain region 13b and share the corresponding source-drain contact hole 15, the bottom area of the shared source-drain contact hole 15 is defined by the outer side surface of the superposed structure of the adjacent two first outer side walls 7 and the second outer side wall 11 in a self-aligned manner, the top of the source-drain contact hole 15 penetrates through the interlayer film 14, the material of the first outer side wall 7 is different from that of the interlayer film 14, the material of the second outer side wall 11 is different from that of the interlayer film 14, and the material of the second outer side wall 11 is different from that of the interlayer film 14 and has different etching rates.
In the method of the embodiment of the present invention, after the interlayer film 14 is formed, a step of forming a self-aligned metal silicide 17 at the bottoms of the gate contact hole 16 and the source drain contact hole 15 is further included.
And thirteen, forming a front metal layer on the surface of the interlayer film 14, imaging and forming word lines and bit lines consisting of the front metal layer.
The polysilicon select gate 10 is connected to a corresponding word line through the gate contact hole 16, the first source drain region 13a is connected to a corresponding bit line through the source drain contact hole 15 at the top, and the second source drain region 13b is connected to a corresponding bit line through the source drain contact hole 15 at the top.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (15)
1. A floating gate type split gate flash memory, wherein a cell structure of the floating gate type split gate flash memory comprises: the first grid structure, the second grid structure, the third grid structure, the first source drain region and the second source drain region;
the region between the first source drain region and the second source drain region is a gate region, the first gate structure, the second gate structure and the third gate structure are sequentially and transversely arranged in the gate region, and the first gate structure and the third gate structure are symmetrically arranged on two sides of the second gate structure;
the first grid structure is formed by superposing a first grid dielectric layer, a polycrystalline silicon floating grid, a second grid dielectric layer, a polycrystalline silicon control grid, a first inner side wall and a first outer side wall which are formed on the surface of the semiconductor substrate on the first side of the second grid structure; storing a first bit of information by a polysilicon floating gate of the first gate structure;
the third grid structure is formed by superposing a first grid dielectric layer, a polycrystalline silicon floating grid, a second grid dielectric layer, a polycrystalline silicon control grid, a first inner side wall and a first outer side wall which are formed on the surface of the semiconductor substrate on the second side of the second grid structure; storing second bit information by the polysilicon floating gate of the third gate structure;
in the gate region, a second opening formed by enclosing the inner side surface of the second gate dielectric layer and the inner side surface of the polysilicon control gate is defined by self-aligning a first opening, and the first opening is formed by photoetching and etching the first dielectric layer; the first inner side wall is formed on the inner side face of the superposed structure of the first opening and the second opening, and the material of the first dielectric layer is different from that of the first inner side wall and has different etching rates;
a third opening is formed by the inner side surface of the first inner side wall in a surrounding mode, and a fourth opening formed by the inner side surface of the first gate dielectric layer and the inner side surface of the polycrystalline silicon floating gate in a surrounding mode is defined by the third opening in a self-aligning mode;
the overlapped area of the fourth opening and the third opening defines a forming area of the second gate structure in a self-aligning way, and the second gate structure comprises a third gate dielectric layer formed on the bottom surface and the side surface of the fourth opening and the side surface of the third opening and a polysilicon selection gate filled in the overlapped area of the fourth opening and the third opening;
the first dielectric layer is removed in a self-alignment mode after the polycrystalline silicon selection gate is formed, the outer side face of the first inner side wall is exposed in a self-alignment mode, the first outer side wall is formed on the corresponding outer side face of the first inner side wall in a self-alignment mode, and the first outer side wall is made of different materials and has different etching rates;
the outer side surfaces of the first outer side wall are self-aligned to define the corresponding outer side surfaces of the first gate dielectric layer, the polycrystalline silicon floating gate, the second gate dielectric layer and the polycrystalline silicon control gate;
the second outer side wall is formed on the outer side surfaces of the first gate dielectric layer, the polycrystalline silicon floating gate, the second gate dielectric layer and the polycrystalline silicon control gate in a self-aligned mode and the outer side surface of the first outer side wall;
the first source drain region and the outer side face of the second outer side wall corresponding to the first grid structure are self-aligned, and the second source drain region and the outer side face of the second outer side wall corresponding to the third grid structure are self-aligned;
forming corresponding source drain contact holes on the tops of the first source drain region and the second source drain region respectively;
the first source-drain region is shared by two adjacent unit structures or the second source-drain region is shared by two adjacent unit structures, the corresponding source-drain contact holes are shared by the two adjacent unit structures, the bottom area of the source-drain contact holes is defined by the outer side faces of the superposed structure of the first outer side wall and the second outer side wall in a self-aligned mode, the top of each source-drain contact hole penetrates through the interlayer film, the first outer side wall is made of a material different from that of the interlayer film and has different etching rates, and the second outer side wall is made of a material different from that of the interlayer film and has different etching rates.
2. The floating gate type split gate flash memory of claim 1, wherein: the semiconductor substrate is a silicon substrate.
3. The floating gate type split gate flash memory of claim 2, wherein: the first dielectric layer is made of silicon nitride;
the first inner side wall is made of silicon oxide;
the first outer side wall is made of silicon nitride;
the second outer side wall is made of silicon nitride;
the material of the interlayer film is silicon oxide.
4. The floating gate type split gate flash memory of claim 2, wherein: the first gate dielectric layer is made of an oxide layer;
the second gate dielectric layer is composed of an oxide layer, a nitride layer and an oxide layer which are sequentially stacked;
and the material oxide layer of the third gate dielectric layer.
5. The floating gate type split gate flash memory of claim 1, wherein: the first source drain region comprises a lightly doped drain region, the second source drain region comprises a lightly doped drain region, and the lightly doped drain region is self-aligned with the outer side face of the corresponding first outer side wall.
6. The floating gate type split gate flash memory of claim 1, wherein: forming a gate contact hole at the top of the polysilicon selection gate; the gate contact hole penetrates through the interlayer film;
word lines and bit lines formed by imaging of the front metal layer are formed on the surface of the interlayer film, the polycrystalline silicon selection gate is connected to the corresponding word line through the gate contact hole, the first source drain region is connected to the corresponding bit line through the source drain contact hole in the top, and the second source drain region is connected to the corresponding bit line through the source drain contact hole in the top.
7. The floating gate type split gate flash memory of claim 6, wherein: and self-aligned metal silicide is formed at the bottoms of the gate contact hole and the source drain contact hole.
8. A manufacturing method of a floating gate type split gate flash memory is characterized by comprising the following steps:
the method comprises the following steps of firstly, sequentially forming a first gate dielectric layer and a first polycrystalline silicon layer on the surface of a semiconductor substrate;
and then, forming a shallow trench isolation structure, comprising the following steps: forming a hard mask layer on the surface of the first polycrystalline silicon layer, defining a forming region of a shallow trench by photoetching, etching the hard mask layer, the first polycrystalline silicon layer, the first gate dielectric layer and the semiconductor substrate in the forming region of the shallow trench in sequence, forming a shallow trench in the semiconductor substrate, filling an oxidation layer in the shallow trench to form a shallow trench isolation structure, and isolating an active region on the semiconductor substrate by the shallow trench isolation structure;
after the active region is defined, removing the hard mask layer and sequentially forming a second gate dielectric layer, a second polysilicon layer and a first dielectric layer, wherein the second gate dielectric layer is superposed on the surface of the first polysilicon layer in the active region;
step two, forming a first opening in the first dielectric layer by adopting a photoetching definition and etching process, removing the first dielectric layer in the first opening and exposing the surface of the second polycrystalline silicon layer;
etching the second polysilicon layer and the second gate dielectric layer at the bottom of the first opening by taking the inner side surface of the first opening as a self-alignment condition to form a second opening;
forming a first inner side wall on the inner side surface of the superposed structure of the first opening and the second opening in a self-alignment manner by adopting a deposition and comprehensive anisotropic etching process, and enclosing a third opening by the first inner side wall, wherein the material of the first dielectric layer is different from that of the first inner side wall and has different etching rates;
fifthly, etching the first polycrystalline silicon layer and the first gate dielectric layer at the bottom of the third opening by taking the inner side surface of the third opening as a self-alignment condition to form a fourth opening;
sixthly, forming a third gate dielectric layer on the bottom surface and the side surface of the fourth opening and the side surface of the third opening, and filling a third polycrystalline silicon layer in the superposed area of the fourth opening and the third opening, in which the third gate dielectric layer is formed, to form a polycrystalline silicon selection gate;
the second grid structure of the unit structure of the floating grid type split-grid flash memory comprises the third grid dielectric layer and the polysilicon selection grid;
seventhly, removing the first dielectric layer in a self-alignment manner and exposing the outer side face of the first inner side wall in a self-alignment manner;
step eight, forming a first outer side wall on the outer side surface of the first inner side wall in a self-alignment mode by adopting a deposition and comprehensive anisotropic etching process, wherein the material of the first outer side wall is different from that of the first inner side wall, and the first outer side wall and the first inner side wall have different etching rates;
step nine, the outer side surface of the first outer side wall is self-aligned, and the second polycrystalline silicon layer, the second gate dielectric layer, the first polycrystalline silicon layer and the first gate dielectric layer are sequentially etched to form a first gate structure and a third gate structure;
in the unit structure, the first gate structure and the third gate structure are symmetrically arranged on two sides of the second gate structure;
the first grid structure is formed by superposing a first grid dielectric layer, a polycrystalline silicon floating grid, a second grid dielectric layer, a polycrystalline silicon control grid, a first inner side wall and a first outer side wall which are formed on the surface of the semiconductor substrate on the first side of the second grid structure; storing a first bit of information by a polysilicon floating gate of the first gate structure;
the third grid structure is formed by superposing a first grid dielectric layer, a polycrystalline silicon floating grid, a second grid dielectric layer, a polycrystalline silicon control grid, a first inner side wall and a first outer side wall which are formed on the surface of the semiconductor substrate on the second side of the second grid structure; storing second bit information by the polysilicon floating gate of the third gate structure;
the polycrystalline silicon floating gate is composed of the etched first polycrystalline silicon layer, the inner side face of the polycrystalline silicon floating gate is formed by the etching process of the first polycrystalline silicon layer in the fifth step, and the outer side face of the polycrystalline silicon floating gate is formed by the etching process of the first polycrystalline silicon layer in the ninth step;
the polycrystalline silicon control gate is composed of the etched second polycrystalline silicon layer, the inner side face of the polycrystalline silicon control gate is formed by the etching process of the second polycrystalline silicon layer in the third step, and the outer side face of the polycrystalline silicon control gate is formed by the etching process of the second polycrystalline silicon layer in the ninth step;
step ten, forming a second outer side wall in a self-alignment manner on the outer side surfaces of the first gate dielectric layer, the polycrystalline silicon floating gate, the second gate dielectric layer and the polycrystalline silicon control gate and the outer side surface of the first outer side wall by adopting a deposition and comprehensive anisotropic etching process;
performing source-drain injection to form a first source-drain region and a second source-drain region under the self-alignment condition of the outer side face of the second outer side wall, wherein the first source-drain region is self-aligned with the outer side face of the second outer side wall corresponding to the first gate structure, and the second source-drain region is self-aligned with the outer side face of the second outer side wall corresponding to the third gate structure;
the unit structure of the floating gate type split gate flash memory comprises: the first gate structure, the second gate structure, the third gate structure, the first source drain region and the second source drain region;
the region between the first source drain region and the second source drain region is a gate region, and the first gate structure, the second gate structure and the third gate structure are sequentially and transversely arranged in the gate region;
step twelve, forming an interlayer film to form a contact hole; the contact hole comprises a source drain contact hole positioned at the top of the first source drain region and the second source drain region; the contact hole also comprises a gate contact hole formed at the top of the polysilicon selection gate, and the gate contact hole penetrates through the interlayer film;
the adjacent two unit structures share the first source drain region or the second source drain region and share the corresponding source drain contact hole, the bottom region of the shared source drain contact hole is defined by the outer side surfaces of the superposed structures of the adjacent two first outer side walls and the second outer side walls in a self-aligned mode, the top of the source drain contact hole penetrates through an interlayer film, the materials of the first outer side walls and the interlayer film are different, the etching rates are different, and the materials of the second outer side walls and the interlayer film are different and have different etching rates;
thirteenth, forming a front metal layer on the surface of the interlayer film, and imaging to form word lines and bit lines composed of the front metal layer;
the polysilicon selection gate is connected to a corresponding word line through the gate contact hole, the first source drain region is connected to a corresponding bit line through the source drain contact hole at the top, and the second source drain region is connected to a corresponding bit line through the source drain contact hole at the top.
9. The method of manufacturing a floating gate type split gate flash memory according to claim 8, wherein: the semiconductor substrate is a silicon substrate.
10. The method of manufacturing a floating gate type split gate flash memory according to claim 9, wherein: the first dielectric layer is made of silicon nitride;
the first inner side wall is made of silicon oxide;
the first outer side wall is made of silicon nitride;
the second outer side wall is made of silicon nitride;
the material of the interlayer film is silicon oxide.
11. The method of manufacturing a floating gate type split gate flash memory according to claim 9, wherein: the first gate dielectric layer is made of an oxide layer;
the second gate dielectric layer is composed of an oxide layer, a nitride layer and an oxide layer which are sequentially stacked;
and the material oxide layer of the third gate dielectric layer.
12. The method of manufacturing a floating gate type split gate flash memory according to claim 8, wherein: and the first source drain region comprises a lightly doped drain region, the second source drain region comprises a lightly doped drain region, the lightly doped drain region is formed by lightly doped drain injection after the etching process in the ninth step is completed and before the second outer side wall is formed in the tenth step, and the lightly doped drain injection takes the outer side surface of the first outer side wall as a self-alignment condition.
13. The method of manufacturing a floating gate type split gate flash memory according to claim 10, wherein: in step eight, the material deposition thickness of the first outer side wall is
14. The method of manufacturing a floating gate type split gate flash memory according to claim 8, wherein: in the sixth step, the third polysilicon layer is formed by adopting a deposition process, the deposited third polysilicon layer completely fills the superposed region of the fourth opening and the third opening and extends out of the third opening, and the third gate dielectric layer also extends out of the third opening; then, the first dielectric layer is used as a stop layer, a chemical mechanical polishing process is adopted to remove the third polycrystalline silicon layer and the third gate dielectric layer outside the third opening, the surfaces of the third polycrystalline silicon layer and the first dielectric layer in the third opening area are leveled, and the polycrystalline silicon selection gate is formed;
and then, forming a thermal oxidation layer on the top surface of the polysilicon selection gate by adopting a thermal oxidation process.
15. The method of manufacturing a floating gate type split gate flash memory according to claim 8, wherein: in the twelfth step, after the interlayer film is formed, a step of forming a self-aligned metal silicide at the bottoms of the gate contact hole and the source drain contact hole is further included.
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| CN112331654A (en) * | 2020-11-02 | 2021-02-05 | 上海华力微电子有限公司 | Method and structure for improving performance of reduced floating gate flash memory |
| CN113113415B (en) * | 2021-03-31 | 2022-09-20 | 华虹半导体(无锡)有限公司 | Floating gate type split gate flash memory device structure and manufacturing process thereof |
| CN113224068A (en) * | 2021-04-28 | 2021-08-06 | 华虹半导体(无锡)有限公司 | NORD flash memory device structure and manufacturing method thereof |
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