CN112331654A - Method and structure for improving performance of reduced floating gate flash memory - Google Patents
Method and structure for improving performance of reduced floating gate flash memory Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 39
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 110
- 229920005591 polysilicon Polymers 0.000 claims abstract description 96
- 239000010410 layer Substances 0.000 claims abstract description 66
- 238000003860 storage Methods 0.000 claims abstract description 31
- 239000011229 interlayer Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000004065 semiconductor Substances 0.000 claims abstract description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 15
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 239000010937 tungsten Substances 0.000 claims description 5
- 238000002347 injection Methods 0.000 claims description 4
- 239000007924 injection Substances 0.000 claims description 4
- 238000000206 photolithography Methods 0.000 claims description 2
- 239000007943 implant Substances 0.000 claims 1
- 125000006850 spacer group Chemical group 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 15
- 230000008569 process Effects 0.000 abstract description 14
- 238000007796 conventional method Methods 0.000 description 8
- 230000006872 improvement Effects 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 230000009467 reduction Effects 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 239000011800 void material Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-O hydridodioxygen(1+) Chemical compound [OH+]=O MYMOFIZGZYHOMD-UHFFFAOYSA-O 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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Abstract
The invention discloses a method and a structure for improving the performance of a reduced floating gate flash memory, wherein an active region is formed in a semiconductor substrate; forming a first grid structure of each flash memory unit in the storage area, wherein the first grid structure comprises a superposed structure formed by a first grid dielectric layer, a polycrystalline silicon floating grid, a second control grid dielectric layer and a polycrystalline silicon control grid; and forming a second grid structure of the logic device area, and simultaneously removing the polysilicon control grid in the first grid structure of each flash memory unit, so that the distance between the polysilicon control grids in the adjacent first grid structures of the source electrode lead-out area is greater than the distance between the polysilicon floating grids. The manufacturing process is completely compatible with the existing process, the opening width of the source electrode lead-out area is increased, the depth-to-width ratio of the source electrode lead-out area is reduced, the filling capacity of an interlayer medium is improved, short circuit between a contact hole and a polycrystalline silicon control grid and electric leakage between the polycrystalline silicon control grids are inhibited, and the reliability, durability and yield of the reduced storage unit are enhanced.
Description
Technical Field
The invention belongs to the manufacturing technology of semiconductor integrated circuits, in particular to a NOR Flash (NOR Flash), and particularly belongs to a structure and a method for improving the performance of a reduced floating gate Flash (NOR Flash).
Background
Flash memory has been widely used as the best choice for non-volatile memory applications due to its advantages of high density, low price, and electrically programmable and erasable. At present, flash memory units are mainly performed at 65nm technology nodes, and with the requirement of high-capacity flash memory, the number of chips on each silicon chip is reduced by using the nodes in the prior art. Meanwhile, the new technology nodes are mature day by day, and the flash memory unit is also urged to be produced by the high-node technology. This means that the size of the flash memory cell needs to be reduced, but reducing the active area width and the channel length of the flash memory cell affects the performance of the flash memory cell.
In the prior art node, the method for continuing to reduce the conventional NOR flash is mainly to make up for the reduction in size by optimizing the process. Currently, from 65nm NOR to 55 nm NOR to 50 nm NOR, the vertical reduction is mainly performed by reducing the distance between adjacent control gates, optimizing the contact hole to control gate dielectric and the filling conditions between subsequent control gates.
The layout structure of a normal NOR flash is shown in fig. 1, and includes three parts, namely a storage region, a source lead-out region and a control gate lead-out region. According to such a regular layout, the distance between the source and the control gate becomes smaller and there is a region surrounded by the control gate having four sides inclined after the reduction is continued. In the NOR Flash technology, a Self-aligned Source (Self-aligned) technology proposed to increase the density of Flash memory cells, such as the Source Self-aligned Process adopted in U.S. Pat. No. 5,120,671 (d.n. tang and w.j.lu, "Process for Self-Aligning a Source Region with a Field Oxide Region and a Poly-silicon Gate" U.S. patent 5,120,671, june9,1992), uses the control Gate of the Flash memory that has been formed to etch the Field oxygen on both sides of the Source Region in the Source Region row as the basis of alignment, so that after etching of the Field oxygen, ion implantation, i.e., SAS ion implantation, can be performed in the etched Region, and the implantation layer formed by SAS ion implantation can be connected with and form the Source Region row formed in the active Region, and this structure has become the mainstream Process of 65nm node.
Fig. 2 is a schematic electron microscope view of a device structure after SAS etching is completed, fig. 3 is an enlarged view of a dashed-line frame portion in fig. 2, and fig. 4 is an enlarged view of a solid-line frame portion in fig. 2. As can be seen from the comparison of the solid and dashed box portions in fig. 2, the above method consumes about 200 angstroms of silicon on top of the active area of the source region during the SAS etch. For the lead-out area of the area, the depth before the interlayer dielectric layer is filled is higher, the environment is complex, and the filling is not facilitated. FIG. 5A is a graph of the distribution of the breakdown voltage of each flash memory cell of a flash memory formed by a conventional method at different distances from the contact hole (CT) and the control gate; fig. 5B is a schematic diagram of a waveguide of breakdown voltage of each flash memory cell of a flash memory formed by a conventional method at different distances between a contact hole (CT) and a control gate. As shown in fig. 5A, the flash memory cells of the flash memory formed by the conventional method have a reduced breakdown voltage as the distance between the contact hole (CT) and the control gate is reduced. As shown in fig. 5B, each flash memory cell of the flash memory formed by the conventional method has an increased fluctuation in breakdown voltage as the distance between the contact hole (CT) and the control gate is reduced. The operating conditions of the conventional flash memory cell are shown in table 1.
Table 1 operating conditions of the conventional flash memory cell
| Operation of | Control grid/V | Drain electrode/V | Source/V | substrate/V |
| Programming | 9.5 | 3.9 | 0.0 | 0.0 |
| Erasing | -9.1 | Float in the air | 7.7 | 7.7 |
| Reading | 5.0 | 1.0 | 0.0 | 0.0 |
If the source lead-out region is subjected to interlayer dielectric layer filling, a void occurs, which causes short circuit (Bridge) between the contact hole and the control gate, and thus causes problems of Programming (PGM) and Erasing (ERS). Particularly for the erasing operation, the normal operation is that the control grid applies negative voltage, the substrate applies positive voltage, the source is in floating connection, and after the drain is in short circuit with the control grid, the junction of the source and the substrate is directly conducted, the voltage of the control grid cannot be kept, the erasing efficiency is reduced, even the operation cannot be carried out, and the operation and the reliability of the flash memory are influenced. Meanwhile, the source contact hole and the control gate are closer to each other, and the strong electric field in this region will cause damage and leakage of the medium and subsequent erase problems through the endurance (endplay) of multiple programming and erasing of the flash memory cell.
Disclosure of Invention
The invention aims to solve the technical problem of providing a method for improving the performance of a reduced floating gate Flash memory, which can solve the problem that the operation and the reliability of a Flash memory unit are reduced due to the short circuit of a contact hole and a control gate caused by a filling hole caused by insufficient filling capacity of an interlayer dielectric layer when a floating gate NOR Flash is continuously reduced in the manufacturing process of the conventional Flash memory. Meanwhile, the invention also provides a structure for improving the performance of the reduced floating gate flash memory.
In order to solve the above technical problem, the method for improving the performance of a reduced floating gate flash memory provided by the present invention includes a storage region and a logic device region, wherein the storage region includes a flash memory cell array formed by arranging a plurality of flash memory cells, and the method includes the following steps:
step S1, providing a semiconductor substrate, forming active regions in the semiconductor substrate, wherein the active regions in the flash memory cell array are in a strip structure and are arranged in parallel;
step S2, forming a first gate structure of each flash memory unit in the storage area, wherein the first gate structure comprises a superposed structure formed by a first gate dielectric layer, a polysilicon floating gate, a second control gate dielectric layer and a polysilicon control gate;
the polysilicon control gates of the flash memory cells in the same row are connected together to form a polysilicon control gate row, each active region is vertical to the polysilicon control gate row, the overlapping region of each polysilicon control gate row and the active region is the forming region of the first gate structure of the flash memory cell, and the polysilicon floating gate is positioned in the forming region of the first gate structure of the flash memory cell;
step S3, forming a second gate structure of the logic device region and simultaneously removing the polysilicon control gates in the first gate structures of the flash memory cells, so that the distance between the polysilicon control gates in the adjacent first gate structures of the source lead-out region is greater than the distance between the polysilicon floating gates, and the second gate structure is composed of a third gate dielectric layer and a polysilicon gate.
In a further improvement, in step S3, the polysilicon control gate in the first gate structure of each flash memory cell and the polysilicon gate in the second gate structure of the logic device region are simultaneously etched by using the same mask.
In a further improvement, the polysilicon gate in the second gate structure of the logic device region and the polysilicon control gate of the first gate structure of each flash memory cell are made of the same polysilicon.
In a further improvement, the method further comprises processing steps of SAS etching, source-drain injection, interlayer dielectric layer filling and tungsten plug filling after the step S3.
The further improvement is that the process step of forming a side wall on the side face of the first grid structure is further included between the source-drain injection and the filling of the interlayer dielectric layer.
In order to solve the above technical problem, the structure for improving the performance of a reduced floating gate flash memory provided by the present invention includes a storage region and a logic device region, wherein the storage region includes a flash memory cell array formed by arranging a plurality of flash memory cells;
an active area is formed on the surface of the semiconductor substrate of each flash memory unit in the flash memory unit array, and each active area is of a strip-shaped structure and is arranged in parallel;
the first grid structure of each flash memory unit comprises a superposed structure formed by a first grid dielectric layer, a polycrystalline silicon floating grid, a second control grid dielectric layer and a polycrystalline silicon control grid, and a side wall is formed on the side surface of the first grid structure;
the polysilicon control gates of the flash memory cells in the same row are connected together to form a polysilicon control gate row, each active region is vertical to the polysilicon control gate row, and the first gate structures of the flash memory cells are formed in the overlapping regions of the polysilicon control gate rows and the active regions;
the distance between the polysilicon control gates in the adjacent first gate structures of the source lead-out regions of the flash memory cells is larger than that between the polysilicon floating gates.
The further improvement is that the source region and the drain region of the flash memory cell are respectively formed in the active region at two sides of each first gate structure, and the source regions in the same row are connected together to form a source region row.
The further improvement is that a second gate structure is formed in a logic device area of the flash memory, and the second gate structure is composed of a third gate dielectric layer and a polysilicon gate.
In a further improvement, the polysilicon gate in the second gate structure of the logic device region and the polysilicon control gate in the first gate structure of the storage region are made of the same polysilicon.
The further improvement is that the first gate dielectric layer is made of silicon oxide, and the second control gate dielectric layer comprises a superposed structure formed by a silicon oxide layer, a silicon nitride layer and a silicon oxide layer.
Compared with the structure and the manufacturing method of the existing floating gate flash memory unit, in the manufacturing process of the flash memory, the active area of the storage area and the first gate structure of each flash memory unit are firstly formed, then the gate structure of the logic device area is formed, and meanwhile, part of polycrystalline silicon control gates of the first gate structures of the source lead-out area of each flash memory unit are synchronously removed, so that the opening width of the source lead-out area is increased, and a wide opening area is formed. The invention starts from improving the filling capacity of the interlayer dielectric layer of the source electrode lead-out area, increases the opening width of the source electrode lead-out area, and simultaneously keeps the filling depth of the source electrode lead-out area, so that the depth-to-width ratio of the area before filling the interlayer dielectric layer is reduced, the interlayer dielectric is easy to fill, the filling capacity of the interlayer dielectric at the position is improved, the short circuit between a contact hole and a polysilicon control gate and the electric leakage between the polysilicon control gates are inhibited, the reliability, the durability and the yield of the reduced storage unit are further enhanced, and an optimized structure and a larger process window are provided for further reducing the floating gate flash memory unit. Meanwhile, the manufacturing process of the invention is completely compatible with the existing process steps, and on the premise of improving the performance of the flash memory unit, a new mask and process steps are not required to be added, so that the increase of the production cost and the reduction of the production efficiency are not caused.
Drawings
FIG. 1 is a schematic diagram of a layout structure of a conventional floating gate NOR Flash;
FIG. 2 is a schematic diagram of an electron microscope after SAS etching is performed on a conventional floating gate flash memory cell;
FIG. 3 is an enlarged view of a dotted line portion of FIG. 2;
FIG. 4 is an enlarged view of the solid line portion of FIG. 2;
FIG. 5A is a graph of the distribution of the breakdown voltage of each flash memory cell of a flash memory formed by a conventional method at different distances from the contact hole (CT) and the control gate;
FIG. 5B is a schematic diagram of a waveguide of breakdown voltage of each flash memory cell of a flash memory formed by a conventional method at different distances from a contact hole (CT) and a control gate;
fig. 6A to 6E are device cross-sectional views along line AA in fig. 1 in the steps of forming the first gate structure of the active region and the Flash memory cell, etching the source, injecting SAS, forming the sidewall, filling the interlayer dielectric layer, and filling and grinding the tungsten plug in the conventional method for manufacturing the floating gate NOR Flash;
FIG. 7 is a schematic diagram of a layout structure of a floating gate NOR Flash according to the present invention;
FIGS. 8A-8E are schematic views of device structures in various steps according to embodiments of the present invention;
FIG. 9A is a diagram illustrating resistance values of control gates with different widths;
FIG. 9B is a standard deviation plot of the resistance of control gates of different widths;
FIG. 10 is a flow chart of a method of an embodiment of the present invention.
Detailed Description
Other advantages and effects of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein it is shown in the accompanying drawings, wherein the specific embodiments are by way of illustration. In the following description, specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced or applied in different embodiments, and the details may be based on different viewpoints and applications, and may be widely spread and replaced by those skilled in the art without departing from the spirit of the present invention.
The flash memory in the existing flash memory comprises a logic area and a storage area which are integrated on the same chip, wherein the storage area comprises a flash memory unit array formed by arranging a plurality of flash memory units. Fig. 6A to 6E are cross-sectional views of devices in the manufacturing processes of the conventional flash memory. The manufacturing method of the existing flash memory comprises the following steps:
first, as shown in fig. 6A, after an active region is formed on a surface of a semiconductor substrate, a first gate structure formed by stacking a first gate dielectric layer 1, a polysilicon Floating Gate (FG)2, a second control gate dielectric layer 3, and a polysilicon Control Gate (CG)4 is formed.
In the conventional method, the semiconductor substrate is a silicon substrate.
Forming field oxygen in the semiconductor substrate, and isolating the active region by the field oxygen. Generally, the field oxide is a shallow trench field oxide and is formed by a shallow trench isolation process. Of course, the field oxide may also be a local field oxide formed by a local field oxidation process.
The first gate dielectric layer 1 is made of silicon oxide, namely a tunneling oxide layer (TOX), and is formed by a thermal oxidation process.
The second control gate dielectric layer 3 is an ONO layer formed by overlapping a silicon oxide layer, a silicon nitride layer and a silicon oxide layer.
In the flash memory cell array, the area of the active region is shown as reference 101. As shown in fig. 1, the flash memory cells in the same column are located in the same active region 101, and the polysilicon control gates 4 of the flash memory cells in the same row are connected together to form a polysilicon control gate row 102. The polysilicon control gate 4 covers the polysilicon floating gate 2 from the top and the side, and the overlapping area of the polysilicon control gate 4 and the polysilicon floating gate 2 is the forming area of the first gate structure of the corresponding flash memory cell. In the width direction, the top surface size of the active region 101 and the top surface size of the polysilicon floating gate 2 are defined by the same photolithography process. The region covered by the first gate structure is a channel region, and the width direction of the channel region is the same as the width direction of the active region 101.
The source region and the drain region of the flash memory cell are formed in the active region 101 on both sides of the polysilicon control gate 4 of each first gate structure, and the source regions in the same row are connected together to form a source region row 103.
Next, as shown in fig. 6B, a source etching is performed by using the polysilicon control gate row 102 and the silicon of the active region in the same row corresponding to the source region as a self-aligned condition.
In the floating gate structure flash memory unit, the distance between the top surface of the first gate structure and the bottom surface of the source region is H, the distance between the first gate structures at two sides of the source region is D, and the depth-to-width ratio is H/D.
Then, as shown in fig. 6C, oxidation and SAS ion implantation are performed to form a source region 5, and then a sidewall 6 of the first gate structure is formed.
Next, as shown in fig. 6D, the interlayer dielectric layer 7 is filled in the storage region of the flash memory, and since silicon at the top of the active region is consumed by a certain thickness during the SAS etching process, the filling depth of the interlayer dielectric layer is relatively high, which is not favorable for filling, and a Void (Void) is easily generated in the source lead-out region, such as the dotted region shown in fig. 6D, which may cause the contact hole CT and the control gate to be short-circuited, thereby causing a problem in the erase operation and affecting the operation and reliability of the flash memory.
Finally, as shown in fig. 6E, tungsten plug 8 filling and grinding are performed in the storage area of the flash memory.
Fig. 10 is a flowchart of a method according to an embodiment of the present invention, and fig. 8A to 8E are schematic diagrams of device structures of steps according to an embodiment of the present invention. In the embodiment of the present invention, a floating gate flash memory includes a storage area and a logic device area, a plan layout of the flash memory is shown in fig. 7, the storage area includes a flash memory cell array formed by arranging a plurality of flash memory cells, and the method includes the following steps:
step S1, a semiconductor substrate is provided in which the active region 101 is formed.
The semiconductor substrate is a silicon substrate.
In the flash memory cell array, the active regions 101 are isolated by field oxide (not shown) formed on the surface of the silicon substrate, and the active regions 101 in the flash memory cell array are in a strip structure and are arranged in parallel.
Step S2, forming a first gate structure of each flash memory cell in the storage region, where the first gate structure includes a stacked structure formed by a first gate dielectric layer 1, a polysilicon floating gate 2, a second control gate dielectric layer 3, and a polysilicon control gate 4, as shown in fig. 8A.
In the embodiment of the invention, the first gate dielectric layer 1 is made of silicon oxide and is formed by a thermal oxidation process. The second control gate dielectric layer 3 is an ONO layer formed by overlapping a silicon oxide layer, a silicon nitride layer and a silicon oxide layer.
The polysilicon control gates 4 of the flash memory cells in the same row are connected together to form a polysilicon control gate row 102, each active region 101 is perpendicular to the polysilicon control gate row 102, the overlapping region of each polysilicon control gate row 102 and the active region 101 is the formation region of the first gate structure of the flash memory cell, and the polysilicon floating gate 2 is located in the formation region of the first gate structure of the flash memory cell.
Step S3, forming a second gate structure (not shown in the figure) of the logic device region and removing the polysilicon control gate 4 in the first gate structure of each flash memory cell at the same time, as shown in fig. 8B, so that the distance between the polysilicon control gates 4 in the adjacent first gate structures of the source lead-out region is greater than the distance between the polysilicon floating gates 2, and the second gate structure is composed of a third gate dielectric layer and a polysilicon gate.
In the method of the embodiment of the invention, the polysilicon control gate in the first gate structure of each flash memory unit and the polysilicon gate in the second gate structure of the logic device region are simultaneously etched by adopting the same mask. The manufacturing process of the embodiment of the invention is completely compatible with the existing process steps, does not need to add a new mask and process steps, and does not cause the increase of the production cost and the reduction of the production efficiency.
The polysilicon gate in the second gate structure of the logic device region and the polysilicon control gate of the first gate structure of each flash memory cell are made of the same polysilicon.
After the step S3, performing SAS etching according to the conventional process, as shown in fig. 8B; performing oxidation and SAS ion source-drain injection to form a source region 5, and then forming a side wall 6 of the first gate structure, as shown in FIG. 8C; filling the interlayer dielectric layer 7 in the storage region of the flash memory, as shown in fig. 8D; finally, tungsten plug 8 fill and grind is performed in the storage area of the flash memory as shown in fig. 8E.
In the manufacturing process of the flash memory, the active area of the storage area and the first gate structure of each flash memory unit are formed firstly, then the gate structure of the logic device area is formed, and simultaneously, part of polysilicon control gates of the first gate structures of the source lead-out areas of the flash memory units are removed synchronously, so that the opening width of the source lead-out areas is increased to D', and a wide opening area is formed.
The embodiment of the invention starts from improving the filling capacity of the interlayer dielectric layer of the source electrode lead-out area, increases the opening width of the source electrode lead-out area, and simultaneously keeps the filling depth H of the source electrode lead-out area, so that the depth-to-width ratio (H/D') of the area before the interlayer dielectric layer is filled is reduced, the interlayer dielectric is easily filled, the filling capacity of the interlayer dielectric at the position is improved, the short circuit between the contact hole 104 and the polycrystalline silicon control gate and the electric leakage between the polycrystalline silicon control gates are inhibited, the reliability, the durability and the yield of the reduced storage unit are further enhanced, and the optimized structure and the larger process window are provided for further reducing the floating gate flash memory unit.
Although the width between the polysilicon control gates becomes large, as shown in fig. 9A and 9B, the difference in resistance values and standard deviations between the control gates having different widths is small, and therefore the conduction of the control gates is not affected.
In the structure for improving the performance of the reduced floating gate flash memory according to the embodiment of the present invention, the flash memory includes a storage area and a logic device area, and the storage area includes a flash memory cell array formed by arranging a plurality of flash memory cells.
An active region 101 is formed on the surface of the semiconductor substrate of each flash memory cell in the flash memory cell array, and the active regions 101 are in a strip structure and are arranged in parallel.
The first grid structure of each flash memory unit comprises a superposed structure formed by a first grid dielectric layer 1, a polycrystalline silicon floating grid 2, a second control grid dielectric layer 3 and a polycrystalline silicon control grid 4, and a side wall 6 is formed on the side face of the first grid structure.
The first gate dielectric layer 1 is made of silicon oxide, and the second control gate dielectric layer 3 comprises a superposed structure formed by a silicon oxide layer, a silicon nitride layer and a silicon oxide layer.
The polysilicon control gates 4 of the flash memory cells in the same row are connected together to form a polysilicon control gate row 102, each active region 101 is perpendicular to the polysilicon control gate row 102, and the first gate structure of the flash memory cells is formed in the overlapping region of each polysilicon control gate row 102 and the active region 101.
The distance between the polysilicon control gates 4 in the adjacent first gate structures of the source lead-out regions of each flash memory cell is larger than the distance between the polysilicon floating gates 2.
The active regions 101 on two sides of each first gate structure respectively form a source region 5 and a drain region of a corresponding flash memory cell, and the source regions 5 in the same row are connected together to form a source region row 103.
And a second grid structure is formed in the logic device area of the flash memory, and the second grid structure consists of a third grid dielectric layer and a polysilicon grid.
The polysilicon gate in the second gate structure of the logic device region and the polysilicon control gate in the first gate structure of the storage region are made of the same polysilicon.
The present invention has been described in detail with reference to the specific embodiments, which are merely preferred embodiments of the present invention, and the present invention is not limited to the above embodiments. Equivalent alterations and modifications made by those skilled in the art without departing from the principle of the invention should be considered to be within the technical scope of the invention.
Claims (10)
1. A method for improving performance of a reduced floating gate flash memory, the flash memory comprising a storage region and a logic device region, the storage region comprising a flash memory cell array formed by arranging a plurality of flash memory cells, the method comprising the steps of:
step S1, providing a semiconductor substrate, forming active regions in the semiconductor substrate, wherein the active regions in the flash memory cell array are in a strip structure and are arranged in parallel;
step S2, forming a first gate structure of each flash memory unit in the storage area, wherein the first gate structure comprises a superposed structure formed by a first gate dielectric layer, a polysilicon floating gate, a second control gate dielectric layer and a polysilicon control gate;
the polysilicon control gates of the flash memory cells in the same row are connected together to form a polysilicon control gate row, each active region is vertical to the polysilicon control gate row, the overlapping region of each polysilicon control gate row and the active region is the forming region of the first gate structure of the flash memory cell, and the polysilicon floating gate is positioned in the forming region of the first gate structure of the flash memory cell;
step S3, forming a second gate structure of the logic device region and simultaneously removing the polysilicon control gates in the first gate structures of the flash memory cells, so that the distance between the polysilicon control gates in the adjacent first gate structures of the source lead-out region is greater than the distance between the polysilicon floating gates, and the second gate structure is composed of a third gate dielectric layer and a polysilicon gate.
2. The method of claim 1, wherein in step S3, the polysilicon control gate in the first gate structure of each flash memory cell and the polysilicon gate in the second gate structure of the logic device region are simultaneously etched by photolithography using a same mask.
3. The method of claim 2, wherein the polysilicon gate in the second gate structure of the logic device region is made of the same polysilicon as the polysilicon control gate of the first gate structure of each flash memory cell.
4. The method of claim 1, further comprising processing steps of SAS etching, source-drain injection, interlayer dielectric layer filling, and tungsten plug filling after step S3.
5. The method of claim 4, further comprising a step of forming a spacer on a side of the first gate structure between the source drain implant and the interlevel dielectric layer fill.
6. A structure for improving performance of a reduced floating gate flash memory, the flash memory including a storage region and a logic device region, the storage region including a flash memory cell array formed by arranging a plurality of flash memory cells,
an active area is formed on the surface of the semiconductor substrate of each flash memory unit in the flash memory unit array, and each active area is of a strip-shaped structure and is arranged in parallel;
the first grid structure of each flash memory unit comprises a superposed structure formed by a first grid dielectric layer, a polycrystalline silicon floating grid, a second control grid dielectric layer and a polycrystalline silicon control grid, and a side wall is formed on the side surface of the first grid structure;
the polysilicon control gates of the flash memory cells in the same row are connected together to form a polysilicon control gate row, each active region is vertical to the polysilicon control gate row, and the first gate structures of the flash memory cells are formed in the overlapping regions of the polysilicon control gate rows and the active regions;
the distance between the polysilicon control gates in the adjacent first gate structures of the source lead-out regions of the flash memory cells is larger than that between the polysilicon floating gates.
7. The structure of claim 6, wherein the active regions on two sides of each first gate structure respectively form a source region and a drain region of a corresponding flash memory cell, and the source regions in a same row are connected together to form a source region row.
8. The structure of claim 6, wherein a second gate structure is formed in the logic device region of the flash memory, and the second gate structure is composed of a third gate dielectric layer and a polysilicon gate.
9. The structure of claim 8, wherein the polysilicon gate in the second gate structure of the logic device region and the polysilicon control gate in the first gate structure of the storage region are made of the same polysilicon.
10. The structure of claim 8, wherein the first gate dielectric layer is made of silicon oxide, and the second control gate dielectric layer comprises a stacked structure of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010061397A (en) * | 1999-12-28 | 2001-07-07 | 박종섭 | Method of manufacturing a flash memory device |
| KR20100013966A (en) * | 2008-08-01 | 2010-02-10 | 주식회사 하이닉스반도체 | Flash memory device and manufacturing method thereof |
| JP2012222201A (en) * | 2011-04-11 | 2012-11-12 | Renesas Electronics Corp | Semiconductor device and semiconductor device manufacturing method |
| CN104157558A (en) * | 2013-05-15 | 2014-11-19 | 中芯国际集成电路制造(上海)有限公司 | Flash memory gate structure, preparation method and application |
| CN109148599A (en) * | 2018-09-29 | 2019-01-04 | 上海华虹宏力半导体制造有限公司 | Floating gate type grid flash memory and its manufacturing method |
| CN111048513A (en) * | 2019-12-23 | 2020-04-21 | 上海华力微电子有限公司 | Method for manufacturing floating gate type flash memory |
-
2020
- 2020-11-02 CN CN202011201698.5A patent/CN112331654A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010061397A (en) * | 1999-12-28 | 2001-07-07 | 박종섭 | Method of manufacturing a flash memory device |
| KR20100013966A (en) * | 2008-08-01 | 2010-02-10 | 주식회사 하이닉스반도체 | Flash memory device and manufacturing method thereof |
| JP2012222201A (en) * | 2011-04-11 | 2012-11-12 | Renesas Electronics Corp | Semiconductor device and semiconductor device manufacturing method |
| CN104157558A (en) * | 2013-05-15 | 2014-11-19 | 中芯国际集成电路制造(上海)有限公司 | Flash memory gate structure, preparation method and application |
| CN109148599A (en) * | 2018-09-29 | 2019-01-04 | 上海华虹宏力半导体制造有限公司 | Floating gate type grid flash memory and its manufacturing method |
| CN111048513A (en) * | 2019-12-23 | 2020-04-21 | 上海华力微电子有限公司 | Method for manufacturing floating gate type flash memory |
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