CN112151549A - Method for manufacturing NOR Flash - Google Patents
Method for manufacturing NOR Flash Download PDFInfo
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- CN112151549A CN112151549A CN202010884238.0A CN202010884238A CN112151549A CN 112151549 A CN112151549 A CN 112151549A CN 202010884238 A CN202010884238 A CN 202010884238A CN 112151549 A CN112151549 A CN 112151549A
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- shallow trench
- isolation structure
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- trench isolation
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- Non-Volatile Memory (AREA)
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Abstract
The invention provides a manufacturing method of NOR Flash, which comprises the following steps: providing a substrate; forming an active region in the substrate; etching an active area in a substrate to form a shallow trench, wherein a bulge is formed at the bottom of the shallow trench; filling oxide into the shallow trench to form a shallow trench isolation structure, wherein the protrusion enables the bottom of the shallow trench on two sides of the protrusion and the oxide to have a certain gap; and forming a floating gate and a control gate positioned on the floating gate on the surfaces of the shallow trench isolation structure and the substrate. After the control grid applies voltage, the voltage can not reach the two sides of the protrusion through the shallow trench isolation structure, therefore, voltage inversion layers can not be formed on the two sides of the protrusion and in the corners of the shallow trench, the depth and the length of the voltage inversion layers in the shallow trench region are reduced, meanwhile, the electric field at the corners of the shallow trench is also reduced, and the weak programming influence on an erasing unit is prevented.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of NOR Flash.
Background
Flash memory has been widely used as the best choice for non-volatile memory applications due to its high density, low cost, and electrically programmable, erasable advantages. At present, the flash memory unit is mainly carried out at a 65 nanometer technology node, and with the requirement on a high-capacity flash memory, the number of chips on each silicon chip is reduced by utilizing the node in the prior art. Meanwhile, the new technology nodes are mature day by day, and the flash memory unit is also urged to be produced by the high-node technology. This means that the size of the flash memory cell needs to be reduced, and the performance of the flash memory cell is affected by the reduced width of the active region and the reduced length of the channel of the flash memory cell.
The method for the node to continue to shrink the conventional NOR flash in the prior art mainly utilizes the optimization of the process to compensate the size reduction. The current lateral scaling from 65NOR to 55NOR, and thus to 50NOR, is achieved primarily by scaling down the active area of the memory cells, and the distance between them. As these physical dimensions shrink, the interference effects of small distances will cause continued shrinking to be impossible. The reduced distance of the active region of the memory cell causes depletion of the sidewall and bottom of the Shallow Trench Isolation (STI) under the control gate and even inversion, which will result in that when programming the memory cell therein, the adjacent erase cell is affected, resulting in weak programming of the erase cell, and the voltage distribution of the overall erase state is too wide, resulting in a reduced read window, as shown in fig. 1. In fig. 1, the shallow trench isolation structure is formed by a shallow trench filling oxide, the bottom of the shallow trench isolation structure is flat, when a high voltage is applied to the control gate 120, the bottom and the sidewall of the shallow trench isolation structure 110 both have a voltage inversion layer 130, and an electric field may also be formed at the corner 111 (the corner of the bottom and the sidewall) of the shallow trench isolation structure 110, resulting in partial oxide depletion of the bottom and the sidewall of the shallow trench isolation structure 110. It is easy to cause the erase cells adjacent to the programmed cells to be disturbed, with the risk of weak programming. And as the distance of the active region is reduced, the electric field at the corner of the bottom of the corresponding shallow trench isolation is increased, thereby intensifying the influence.
In the method for manufacturing the NOR Flash according to the present invention, the method for manufacturing the NOR Flash includes: providing a substrate; forming an active region in the substrate; etching an active area in a substrate to form a shallow trench, wherein a bulge is formed at the bottom of the shallow trench; filling oxide into the shallow trench to form a shallow trench isolation structure, wherein the protrusion enables the bottom of the shallow trench on two sides of the protrusion and the oxide to have a certain gap; and forming a floating gate and a control gate positioned on the floating gate on the surfaces of the shallow trench isolation structure and the substrate. The depth, the length and the electric field at the corner of an inversion layer of the shallow trench region are reduced through the special bottom structure of the shallow trench, and the special bottom structure of the source region is removed by combining the etching of a common self-aligned source (self-alignment-source), so that the resistance of the source is not influenced, and the reading of an erasing unit is not influenced. The bottom part of the STI is isolated in space by the non-flat structure of the bottom part of the STI, the influence of electric leakage caused by the inversion of a parasitic transistor generated by the control gate through the STI on unselected units is prevented, and the weak programming influence on an erasing unit is prevented. Meanwhile, the bottom active region of the self-aligned source region in the structure is removed during self-aligned source etching, and the resistance of the self-aligned source is not affected.
Disclosure of Invention
The invention aims to provide a manufacturing method of NOR Flash, which can reduce the depth and the length of a voltage inversion layer in a shallow groove region and reduce an electric field at the corner of the shallow groove, thereby preventing weak programming influence on an erasing unit.
In order to achieve the above object, the present invention provides a method for manufacturing NOR Flash, including:
providing a substrate;
forming an active region in the substrate;
etching an active area in a substrate to form a shallow trench, wherein a bulge is formed at the bottom of the shallow trench;
filling oxide into the shallow trench to form a shallow trench isolation structure, wherein the protrusion enables the bottom of the shallow trench on two sides of the protrusion and the oxide to have a certain gap;
and forming a floating gate and a control gate positioned on the floating gate on the surfaces of the shallow trench isolation structure and the substrate.
Optionally, in the method for manufacturing NOR Flash, the active region includes a high voltage P-type well region.
Optionally, in the manufacturing method of NOR Flash, a protrusion formed at the bottom of the shallow trench is an active region.
Optionally, in the NOR Flash manufacturing method, the protrusion is located at the middle position of the bottom of the shallow trench.
Optionally, in the method for manufacturing NOR Flash, the method for filling oxide into the shallow trench to form a shallow trench isolation structure includes:
forming an oxide layer on the substrate;
etching the oxide layer and the active area in the substrate to form a shallow trench;
and filling oxide into the shallow trench to form a shallow trench isolation structure.
Optionally, in the method for manufacturing NOR Flash, the method for forming the floating gate on the surface of the substrate and the shallow trench isolation structure includes:
forming a floating gate layer on the oxide layer and the surface of the shallow trench isolation structure;
and etching the floating gate layer to expose the surface of the shallow trench isolation structure to form a floating gate.
Optionally, in the manufacturing method of the NOR Flash, the manufacturing method of the NOR Flash further includes:
and forming an ONO layer on the surfaces of the floating gate and the shallow trench isolation structure, wherein the ONO layer covers the surfaces of the floating gate and the shallow trench isolation structure.
Optionally, in the method for manufacturing NOR Flash, the method for forming the control gate on the floating gate on the surface of the shallow trench isolation structure and the substrate includes:
forming a control gate layer on the ONO layer, wherein the control gate layer covers the ONO layer;
and etching the control gate layer to form a control gate.
Optionally, in the method for manufacturing NOR Flash, the oxide includes silicon dioxide.
Optionally, in the manufacturing method of NOR Flash, the floating gate and the control gate layer are made of polysilicon.
In the manufacturing method of the NOR Flash, a bulge is formed at the bottom of the shallow trench, and the bulge ensures that the bottom of the shallow trench at two sides of the bulge and the oxide in the shallow trench isolation structure have certain gaps. After the control grid applies voltage, the voltage can not reach the two sides of the protrusion through the shallow trench isolation structure, therefore, voltage inversion layers can not be formed on the two sides of the protrusion and in the corners of the shallow trench, the depth and the length of the voltage inversion layers in the shallow trench region are reduced, meanwhile, the electric field at the corners of the shallow trench is also reduced, and the weak programming influence on an erasing unit is prevented.
Drawings
FIG. 1 is a schematic diagram of the structure of a NOR Flash of the prior art;
FIG. 2 is a flowchart of a method of manufacturing NOR Flash according to an embodiment of the present invention;
fig. 3 to 6 are schematic structural views of a NOR Flash manufacturing method according to an embodiment of the present invention;
wherein: 110-shallow trench isolation structure, 111-corner, 120-control gate, 130-voltage inversion layer, 210-substrate, 220-active region, 230-oxide layer, 241-bulge, 240-shallow trench, 250-shallow trench isolation structure, 251-corner, 260-floating gate, 270-ONO layer and 280-control gate.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the following, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method.
Referring to fig. 2, the present invention provides a method for manufacturing NOR Flash, including:
s11: providing a substrate;
s12: forming an active region in the substrate;
s13: etching an active area in a substrate to form a shallow trench, wherein a bulge is formed at the bottom of the shallow trench;
s14: filling oxide into the shallow trench to form a shallow trench isolation structure, wherein the protrusion enables the bottom of the shallow trench on two sides of the protrusion and the oxide to have a certain gap;
s15: and forming a floating gate and a control gate positioned on the floating gate on the surfaces of the shallow trench isolation structure and the substrate.
Referring to fig. 3 and 4, a substrate 210 is provided, an active region 220 is formed in the substrate 210, the active region 220 may form an oxide layer 230 on the surface of the substrate 210 for a high voltage P-well (HVPW), the oxide layer 230 and the active region 220 are etched to form a shallow trench 240, the bottom of the shallow trench 240 has a protrusion 241, and the protrusion 241 is also a part of the active region 220, that is, when the active region 220 is etched to form the shallow trench 240, the active region 220 is etched to form the shape of the protrusion 241, and the protrusion 241 may be located in the middle of the bottom of the shallow trench 240. Next, an oxide, such as silicon dioxide, is filled into the shallow trench 240 to form a shallow trench isolation structure 250. The protrusion 241 makes the oxide on both sides of the protrusion 241 and the bottom of the shallow trench 240 have a certain space, i.e., there is a space to isolate the oxide on both sides of the protrusion 241 and the bottom of the shallow trench 240.
Referring to fig. 4, a floating gate layer is formed on the surface of the oxide layer 230 and the shallow trench isolation structure 250, and the floating gate layer covers the surface of the oxide layer 230 and the shallow trench isolation structure 250. The material of the floating gate layer may be polysilicon. The floating gate layer is then etched to expose the surface of the shallow trench isolation structure 250 to form a plurality of floating gates 260.
Referring to fig. 5, next, an ONO layer 270 is formed on the floating gate 260 and the shallow trench isolation structure 250, where the ONO layer is a silicon oxide-silicon nitride-silicon oxide layer, and the forming method may use a conventional method for depositing silicon oxide, silicon nitride and silicon oxide layers respectively, which is not described herein again.
Referring to fig. 6, next, a control gate layer is formed on the ONO layer 270, the material of the control gate layer may be polysilicon, the control gate layer covers the surface of the ONO layer 270, and the control gate layer forms a control gate 280. The regions (i.e., two sides of the protrusion) at the bottom of the shallow trench close to the corner 251 are spatially isolated by the non-planarized structure at the bottom of the shallow trench, so as to prevent the influence of the leakage caused by the inversion of the parasitic transistor generated by the control gate 280 through the shallow trench isolation structure 250 on the unselected cell and the weak programming influence on the erased cell.
Furthermore, in the subsequent forming process of the self-aligned source electrode, the bulge at the bottom of the shallow groove can be removed, so that the resistance of the self-aligned source electrode is not influenced, and the reading of the erasing unit is not influenced.
In summary, in the method for manufacturing NOR Flash provided in the embodiment of the present invention, the method for manufacturing NOR Flash includes: providing a substrate; forming an active region in the substrate; etching an active area in a substrate to form a shallow trench, wherein a bulge is formed at the bottom of the shallow trench; filling oxide into the shallow trench to form a shallow trench isolation structure, wherein the protrusion enables the bottom of the shallow trench on two sides of the protrusion and the oxide to have a certain gap; and forming a floating gate and a control gate positioned on the floating gate on the surfaces of the shallow trench isolation structure and the substrate. In the embodiment of the invention, the bulge is formed at the bottom of the shallow trench, and the bulge ensures that the bottom of the shallow trench at the two sides of the bulge and the oxide in the shallow trench isolation structure have certain gaps. After the control grid applies voltage, the voltage can not reach the two sides of the protrusion through the shallow trench isolation structure, therefore, voltage inversion layers can not be formed on the two sides of the protrusion and in the corners of the shallow trench, the depth and the length of the voltage inversion layers in the shallow trench region are reduced, meanwhile, the electric field at the corners of the shallow trench is also reduced, and the weak programming influence on an erasing unit is prevented.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method of manufacturing NOR Flash, comprising:
providing a substrate;
forming an active region in the substrate;
etching an active area in a substrate to form a shallow trench, wherein a bulge is formed at the bottom of the shallow trench;
filling oxide into the shallow trench to form a shallow trench isolation structure, wherein the protrusion enables the bottom of the shallow trench on two sides of the protrusion and the oxide to have a certain gap;
and forming a floating gate and a control gate positioned on the floating gate on the surfaces of the shallow trench isolation structure and the substrate.
2. The method for fabricating NOR Flash of claim 1 wherein the active region comprises a high voltage pwydrazine region.
3. The method for manufacturing NOR Flash of claim 1, wherein the protrusion formed at the bottom of the shallow trench is an active region.
4. The method for manufacturing NOR Flash of claim 3, wherein the protrusion is located at a middle position of the bottom of the shallow trench.
5. The method for fabricating NOR Flash of claim 1 wherein filling oxide into the shallow trench to form a shallow trench isolation structure comprises:
forming an oxide layer on the substrate;
etching the oxide layer and the active area in the substrate to form a shallow trench;
and filling oxide into the shallow trench to form a shallow trench isolation structure.
6. The method for manufacturing NOR Flash of claim 1, wherein the method for forming the floating gate on the surface of the substrate and the shallow trench isolation structure comprises:
forming a floating gate layer on the oxide layer and the surface of the shallow trench isolation structure;
and etching the floating gate layer to expose the surface of the shallow trench isolation structure to form a floating gate.
7. The method for manufacturing NOR Flash of claim 6, wherein the method for manufacturing NOR Flash further comprises:
and forming an ONO layer on the surfaces of the floating gate and the shallow trench isolation structure, wherein the ONO layer covers the surfaces of the floating gate and the shallow trench isolation structure.
8. The method for manufacturing NOR Flash of claim 7, wherein the method for forming the control gate on the floating gate on the surface of the shallow trench isolation structure and the substrate comprises:
forming a control gate layer on the ONO layer, wherein the control gate layer covers the ONO layer;
and etching the control gate layer to form a control gate.
9. The method for manufacturing NOR Flash of claim 1 wherein the oxide comprises silicon dioxide.
10. The method for manufacturing NOR Flash of claim 1, wherein the material of the floating gate and the control gate layer is polysilicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010884238.0A CN112151549A (en) | 2020-08-28 | 2020-08-28 | Method for manufacturing NOR Flash |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010884238.0A CN112151549A (en) | 2020-08-28 | 2020-08-28 | Method for manufacturing NOR Flash |
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| CN112151549A true CN112151549A (en) | 2020-12-29 |
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| CN202010884238.0A Pending CN112151549A (en) | 2020-08-28 | 2020-08-28 | Method for manufacturing NOR Flash |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5920787A (en) * | 1997-01-16 | 1999-07-06 | Vlsi Technology, Inc. | Soft edge induced local oxidation of silicon |
| KR20020083766A (en) * | 2001-04-30 | 2002-11-04 | 주식회사 하이닉스반도체 | Method for fabricating element isolating film of semiconductor device and structure of the same |
| CN1866523A (en) * | 2005-05-18 | 2006-11-22 | 三星电子株式会社 | Semiconductor device having shallow trench isolation structure and method of manufacturing the same |
-
2020
- 2020-08-28 CN CN202010884238.0A patent/CN112151549A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5920787A (en) * | 1997-01-16 | 1999-07-06 | Vlsi Technology, Inc. | Soft edge induced local oxidation of silicon |
| KR20020083766A (en) * | 2001-04-30 | 2002-11-04 | 주식회사 하이닉스반도체 | Method for fabricating element isolating film of semiconductor device and structure of the same |
| CN1866523A (en) * | 2005-05-18 | 2006-11-22 | 三星电子株式会社 | Semiconductor device having shallow trench isolation structure and method of manufacturing the same |
Non-Patent Citations (1)
| Title |
|---|
| 陈鸣: "《电子材料》", 北京邮电大学出版社, pages: 5 - 6 * |
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