CN113035879B - NOR FLASH forming method - Google Patents
NOR FLASH forming method Download PDFInfo
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- CN113035879B CN113035879B CN202110209856.XA CN202110209856A CN113035879B CN 113035879 B CN113035879 B CN 113035879B CN 202110209856 A CN202110209856 A CN 202110209856A CN 113035879 B CN113035879 B CN 113035879B
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- 238000000034 method Methods 0.000 title claims abstract description 52
- 239000010410 layer Substances 0.000 claims abstract description 91
- 238000002955 isolation Methods 0.000 claims abstract description 55
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 239000011229 interlayer Substances 0.000 claims abstract description 30
- 238000005530 etching Methods 0.000 claims description 7
- 150000002500 ions Chemical class 0.000 claims description 3
- 230000005641 tunneling Effects 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000011800 void material Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
- H10B41/44—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a control gate layer also being used as part of the peripheral transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention provides a method for forming NOR FLASH, which comprises the following steps: providing a substrate, wherein adjacent active areas and isolation areas are formed in the substrate, and the surface of the isolation area is higher than that of the active areas; forming a floating gate and a first control gate on the active region in sequence; forming a second control gate on the isolation region, wherein a gap is formed between the first control gate and the second control gate, and the first control gate and the second control gate are on the same height; and filling oxide in a gap between the first control gate and the second control gate to form an interlayer dielectric layer, wherein the surface of the interlayer dielectric layer is flat. The surface of the isolation region is higher than that of the active region, so that an interlayer dielectric layer between the first control gate (the active region control gate) and the second control gate (the isolation region control gate) is well filled, and the situation of a cavity cannot occur, thereby reducing the probability of occurrence of a problem in subsequent erasure.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for forming NOR FLASH.
Background
Flash memory has been widely used as the best choice for non-volatile memory applications due to its high density, low cost, electrically programmable and erasable advantages. At present, the flash memory unit is mainly performed at a 65 nanometer technology node, and with the requirement of a large-capacity flash memory, the number of chips on each silicon wafer is reduced by utilizing the prior technology node. Meanwhile, with the increasing maturity of new technology nodes, flash memory units are also urged to be produced by high-node technology. Meaning that the size of the flash memory cell needs to be reduced, however, reducing the active area width and the channel length of the flash memory cell both have an impact on the performance of the flash memory cell.
The method for continuously reducing the conventional NOR flash by the prior art nodes mainly utilizes the optimization of the process to compensate the reduction of the size. The current vertical scaling from 65nm NOR flash to 55nm NOR flash, and thus to 50nm NOR flash, is mainly performed by scaling the distance between adjacent control gates, and the filling conditions between subsequent control gates. In NOR Flash technology, a source self-aligned technology (self-aligned-source) proposed to increase the density of Flash memory cells uses an already formed Flash control gate as a basis for alignment, and this structure has become a mainstream process of 65nm node. The method consumes about 200A of silicon during etching in the source self-alignment technology, so that the depth of the active region control gate and the isolation region control gate before filling the interlayer dielectric layer is higher, the environment is complex, and the filling is not facilitated. For the area led out by the control gate, the part comprises the control gate in the active area and the isolation area, the active area of the small block and the irregular control gate, and the control gate heights of the active area control gate and the isolation area control gate also have areas with large depth-to-width ratio before the interlayer dielectric layers are filled, and the area with small control gate is very unfavorable for the filling between the subsequent interlayer dielectric layers. If a Void (Void) occurs, a larger possibility of leakage exists between the selected bit line (WL) and the unselected bit line, and a strong electric field of the active region control gate and the isolation region control gate can cause damage and leakage of a medium after the endurance (endurance) of programming and erasing of the memory cell for a plurality of times, and a problem of erasing can also be caused subsequently.
Disclosure of Invention
The invention aims to provide a method for forming NOR FLASH, which ensures that an interlayer dielectric layer between an active area control gate and an isolation area control gate is completely filled, the situation of a cavity is avoided, and the problem of erasure is reduced, and in order to achieve the aim, the invention provides a method for forming NOR FLASH, which comprises the following steps:
providing a substrate, wherein adjacent active areas and isolation areas are formed in the substrate, and the surface of the isolation area is higher than that of the active areas;
forming a floating gate and a first control gate on the active region in sequence;
forming a second control gate on the isolation region, wherein a gap is formed between the first control gate and the second control gate, and the first control gate and the second control gate are on the same height; and
And filling oxide in a gap between the first control gate and the second control gate to form an interlayer dielectric layer, wherein the surface of the interlayer dielectric layer is flat.
Optionally, in the method for forming a NOR FLASH, the isolation region includes a shallow trench isolation structure.
Optionally, in the method for forming a NOR FLASH, the method for forming the isolation region includes:
forming a trench in the substrate;
Filling the groove to form a shallow groove isolation structure; and
And etching part of the substrate so that the surface of the substrate is lower than the surface of the isolation region.
Optionally, in the method for forming a NOR FLASH, before forming a floating gate on the active area, the method further includes:
A tunnel oxide layer is formed on the substrate.
Optionally, in the method for forming a NOR FLASH, the method for forming a floating gate on the active region includes:
Forming a floating gate layer on the tunneling oxide layer; and
And etching the floating gate layer to form a floating gate.
Optionally, in the method for forming a NOR FLASH, after forming a floating gate on the active area, the method further includes:
a first ONO layer is formed over the floating gate.
Optionally, in the method for forming a NOR FLASH, the method for forming the first control gate on the floating gate includes:
forming a control gate layer on the first ONO layer; and
And etching the control gate layer to form a first control gate.
Optionally, in the method for forming a NOR FLASH, before forming the second control gate on the isolation region, the method further includes:
a second ONO layer is formed over the isolation region.
Optionally, in the method for forming a NOR FLASH, the method for forming a second control gate on the isolation region includes:
forming a control gate layer on the second ONO layer; and
And controlling the control gate layer to form a second control gate.
Optionally, in the method for forming a NOR FLASH, the method for forming an active region in the substrate includes:
Ions are implanted into the substrate to form an active region.
Optionally, in the method for forming the NOR FLASH, the interlayer dielectric layer further covers sidewalls of the tunnel oxide layer, the floating gate, the first ONO layer and the first control gate.
The method for forming the NOR FLASH provided by the invention comprises the following steps: providing a substrate, wherein adjacent active areas and isolation areas are formed in the substrate, and the surface of the isolation area is higher than that of the active areas; forming a floating gate and a first control gate on the active region in sequence; forming a second control gate on the isolation region, wherein a gap is formed between the first control gate and the second control gate, and the first control gate and the second control gate are on the same height; and filling oxide in a gap between the first control gate and the second control gate to form an interlayer dielectric layer, wherein the surface of the interlayer dielectric layer is flat. According to the invention, the surface of the isolation region is controlled to be higher than that of the active region, so that the first control gate and the second control gate are at the same height, no difference in height exists, and further, an interlayer dielectric layer between the first control gate (the active region control gate) and the second control gate (the isolation region control gate) is well filled, the situation of a cavity cannot occur, and the possibility of larger electric leakage between a selected bit line (WL) and an unselected bit line cannot be caused, so that the probability of occurrence of a problem in subsequent erasure is reduced.
Drawings
Fig. 1 is a flow chart of a method of forming NOR FLASH according to an embodiment of the present invention;
Fig. 2 to 5 are schematic diagrams of a method for forming NOR FLASH according to an embodiment of the present invention;
In the figure: 110-active region, 120-isolation region, 130-tunnel oxide layer, 140-floating gate, 150-first ONO layer, 160-first control gate, 170-second ONO layer, 180-second control gate, 190-interlayer dielectric layer.
Detailed Description
Specific embodiments of the present invention will be described in more detail below with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
In the following, the terms "first," "second," and the like are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological order. It is to be understood that such terms so used are interchangeable under appropriate circumstances. Similarly, if a method described herein comprises a series of steps, and the order of the steps presented herein is not necessarily the only order in which the steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method.
Referring to fig. 1, the present invention provides a method for forming a NOR FLASH, which includes:
S11: providing a substrate, wherein adjacent active areas and isolation areas are formed in the substrate, and the surface of the isolation area is higher than that of the active areas;
S12: forming a floating gate and a first control gate on the active region in sequence;
S13: forming a second control gate on the isolation region, wherein a gap is formed between the first control gate and the second control gate, and the first control gate and the second control gate are on the same height; and
S14: and filling oxide in a gap between the first control gate and the second control gate to form an interlayer dielectric layer, wherein the surface of the interlayer dielectric layer is flat.
Referring to fig. 2, a substrate, which may be a silicon substrate or a germanium substrate, is provided, and the embodiment of the invention provides a silicon substrate, for example, a wafer. The substrate is partially etched to form a trench in the substrate, the trench is filled with an oxide, such as silicon oxide, to form a shallow trench isolation structure, i.e., isolation region 120, and then the surface of the remaining substrate is partially etched to make the substrate surface lower than the surface of the shallow trench isolation structure. Next, ions are implanted into the substrate to form an active region 110, the active region 110 being adjacent to and in contact with the isolation region 120.
Next, referring to fig. 3 to 5, an oxide layer, which may be silicon oxide, is formed on the active region 110. The oxide layer is etched to form a tunnel oxide layer 130, a floating gate layer is formed on the tunnel oxide layer 130, the material of the floating gate layer may be polysilicon, and the floating gate layer is etched to form a floating gate 140. Next, a first ONO layer 150 is formed on the floating gate layer, where the first ONO layer 150 is a three-layer structure, i.e., a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, and the forming methods are respectively deposition methods. Next, a first control gate 160 is formed on the first ONO layer 150, specifically, a control gate layer is formed on the first ONO layer 150, the material of the control gate layer is polysilicon, and the control gate layer is etched to form the first control gate. Next, a second control gate 180 is formed on the isolation region 120, specifically, a second ONO layer 170 is formed on the surface of the isolation region 120, where the second ONO layer 170 is a three-layer structure, i.e., a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, and the forming method is a deposition method. A control gate layer is formed on the second ONO layer 170, the material of the control gate layer is polysilicon, and the control gate layer is etched to form the second control gate 180. The first control gate 170 and the second control gate 180 have a gap therebetween, and the first control gate 170 and the second control gate 180 are on the same plane, and finally an interlayer dielectric layer 190 is formed to cover the gap between the first control gate 170 and the second control gate 180 and the side wall of the first control gate 170, specifically, an oxide layer is formed to cover the gap between the first control gate 170 and the second control gate 180, and an interlayer dielectric layer 190 is etched to cover the gap between the first control gate 170 and the second control gate 180 and the side wall of the first control gate 170, and the interlayer dielectric layer 190 is formed. In the prior art, due to the fact that the height difference exists between the first control gate (the active area control gate) and the second control gate (the isolation area control gate), the formed gate interlayer dielectric layer is uneven, gaps are reserved in the middle of the gate interlayer dielectric layer, gaps are reserved between the two sides and the middle of the gate interlayer dielectric layer, holes are further formed in the gate interlayer dielectric layer, if the holes (Void) occur, larger leakage possibility exists between the selected bit line (WL) and the unselected bit line, and the problem is caused in subsequent erasure due to the fact that the durability (endurance) of programming and erasure of the memory cells is achieved for many times. In the embodiment of the invention, the interlayer dielectric layer between the first control gate (active area control gate) and the second control gate (isolation area control gate) is well filled, has no height difference and flat surface, and simultaneously, does not have the condition of a cavity, and does not cause larger possibility of leakage between the selected bit line (WL) and the unselected bit line, thereby reducing the probability of occurrence of problems in subsequent erasure.
In summary, in the method for forming NOR FLASH provided by the embodiment of the present invention, the method includes: providing a substrate, wherein adjacent active areas and isolation areas are formed in the substrate, and the surface of the isolation area is higher than that of the active areas; forming a floating gate and a first control gate on the active region in sequence; forming a second control gate on the isolation region, wherein a gap is formed between the first control gate and the second control gate, and the first control gate and the second control gate are on the same height; and filling oxide in a gap between the first control gate and the second control gate to form an interlayer dielectric layer, wherein the surface of the interlayer dielectric layer is flat. According to the invention, the surface of the isolation region is controlled to be higher than that of the active region, so that the first control gate and the second control gate are at the same height, no difference in height exists, and further, an interlayer dielectric layer between the first control gate (the active region control gate) and the second control gate (the isolation region control gate) is well filled, the situation of a cavity cannot occur, and the possibility of larger electric leakage between a selected bit line (WL) and an unselected bit line cannot be caused, so that the probability of occurrence of a problem in subsequent erasure is reduced.
The foregoing is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any person skilled in the art will make any equivalent substitution or modification to the technical solution and technical content disclosed in the invention without departing from the scope of the technical solution of the invention, and the technical solution of the invention is not departing from the scope of the invention.
Claims (11)
1. A method for forming NOR FLASH, comprising:
providing a substrate, wherein adjacent active areas and isolation areas are formed in the substrate, and the surface of the isolation area is higher than that of the active areas;
forming a floating gate and a first control gate on the active region in sequence;
forming a second control gate on the isolation region, wherein the second control gate is only on the isolation region in the direction perpendicular to the substrate, a gap is formed between the first control gate and the second control gate, and the first control gate and the second control gate are on the same height; and
And filling oxide in a gap between the first control gate and the second control gate to form an interlayer dielectric layer, wherein the surface of the interlayer dielectric layer is flat.
2. The method of claim 1, wherein the isolation region comprises a shallow trench isolation structure.
3. The method of forming NOR FLASH as claimed in claim 1, wherein said method of forming said isolation region comprises:
forming a trench in the substrate;
Filling the groove to form a shallow groove isolation structure; and
And etching part of the substrate so that the surface of the substrate is lower than the surface of the isolation region.
4. The method of claim 1, further comprising, prior to forming the floating gate on the active region:
A tunnel oxide layer is formed on the substrate.
5. The method of claim 4, wherein the method of forming a floating gate over the active region comprises:
Forming a floating gate layer on the tunneling oxide layer; and
And etching the floating gate layer to form a floating gate.
6. The method of claim 1, further comprising, after forming a floating gate on the active region:
a first ONO layer is formed over the floating gate.
7. The method of forming a NOR FLASH as claimed in claim 6, wherein forming a first control gate on said floating gate comprises:
forming a control gate layer on the first ONO layer; and
And etching the control gate layer to form a first control gate.
8. The method of forming a NOR FLASH as claimed in claim 1, further comprising, prior to forming a second control gate over said isolation region:
a second ONO layer is formed over the isolation region.
9. The method of forming a NOR FLASH as claimed in claim 8, wherein forming a second control gate over said isolation region comprises:
forming a control gate layer on the second ONO layer; and
And controlling the control gate layer to form a second control gate.
10. The method of forming a NOR FLASH as claimed in claim 1, wherein the method of forming an active region within said substrate comprises:
Ions are implanted into the substrate to form an active region.
11. The method of claim 1, wherein the interlayer dielectric layer further covers sidewalls of the tunnel oxide layer, the floating gate, the first ONO layer, and the first control gate.
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| CN202110209856.XA CN113035879B (en) | 2021-02-24 | 2021-02-24 | NOR FLASH forming method |
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| CN202110209856.XA CN113035879B (en) | 2021-02-24 | 2021-02-24 | NOR FLASH forming method |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6060358A (en) * | 1997-10-21 | 2000-05-09 | International Business Machines Corporation | Damascene NVRAM cell and method of manufacture |
| CN1289148A (en) * | 1999-08-31 | 2001-03-28 | 株式会社东芝 | Non-volatile semiconductor storage device and mfg. method thereof |
| CN105826271A (en) * | 2015-01-07 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Formation method of flash |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102011005719A1 (en) * | 2011-03-17 | 2012-09-20 | Globalfoundries Dresden Module One Llc & Co. Kg | Increased integrity of large ε metal gate stacks by reducing STI settlements by depositing a filler after STI fabrication |
| US9627392B2 (en) * | 2015-01-30 | 2017-04-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method to improve floating gate uniformity for non-volatile memory devices |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6060358A (en) * | 1997-10-21 | 2000-05-09 | International Business Machines Corporation | Damascene NVRAM cell and method of manufacture |
| CN1289148A (en) * | 1999-08-31 | 2001-03-28 | 株式会社东芝 | Non-volatile semiconductor storage device and mfg. method thereof |
| CN105826271A (en) * | 2015-01-07 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Formation method of flash |
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