CN117082857A - Manufacturing method of memory device - Google Patents
Manufacturing method of memory device Download PDFInfo
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- CN117082857A CN117082857A CN202311096706.8A CN202311096706A CN117082857A CN 117082857 A CN117082857 A CN 117082857A CN 202311096706 A CN202311096706 A CN 202311096706A CN 117082857 A CN117082857 A CN 117082857A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 96
- 229920005591 polysilicon Polymers 0.000 claims abstract description 96
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 70
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 35
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 35
- 238000005530 etching Methods 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 238000002955 isolation Methods 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims description 24
- 230000008569 process Effects 0.000 claims description 17
- 238000001039 wet etching Methods 0.000 claims description 6
- 230000015654 memory Effects 0.000 description 11
- 230000002093 peripheral effect Effects 0.000 description 7
- 238000000206 photolithography Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- SJHPCNCNNSSLPL-CSKARUKUSA-N (4e)-4-(ethoxymethylidene)-2-phenyl-1,3-oxazol-5-one Chemical group O1C(=O)C(=C/OCC)\N=C1C1=CC=CC=C1 SJHPCNCNNSSLPL-CSKARUKUSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005292 diamagnetic effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000006386 memory function Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000003826 tablet Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
Abstract
Disclosed is a method of fabricating a memory device, comprising: providing a substrate, wherein the substrate comprises a first area and a second area, the first area is used for integrating a cell device, the second area is used for integrating a logic device, a first oxide layer is formed on the substrate of the first area, a first polysilicon layer is formed on the first oxide layer, an isolation layer is formed on the first polysilicon layer, a second polysilicon layer is formed on the isolation layer, a second oxide layer is formed on the substrate of the second area, a third polysilicon layer is formed on the second oxide layer, and the height of the second polysilicon layer is higher than that of the third polysilicon layer; forming a silicon dioxide layer, wherein the silicon dioxide layer covers the second polysilicon layer and the third polysilicon layer; flattening and removing the silicon dioxide layer of the first area; reducing the thickness of the second polysilicon layer by etching; removing the residual silicon dioxide layer by etching; and removing the second polysilicon layer, the isolation layer and the first polysilicon layer of the target area in the first area through etching to form a groove.
Description
Technical Field
The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a manufacturing method of a memory device.
Background
Nonvolatile memory (NVM) is a widely used information memory that stores 0/1 information by storing charge on a Floating Gate (FG), which also has good diamagnetic interference when maintained without electricity.
In NVM memories, NOR flash (flash) is developed based on the tunnel oxide nonvolatile memory (programmable read-only memory tunnel oxide, ETOX) structure proposed by Intel corporation, and is a voltage controlled device, which uses hot electron injection to write data and erases data based on tunneling, and is characterized by a fast random reading speed. As an NVM memory, NOR flash memory has characteristics of high device density, low power consumption, and electrical rewritability, and is widely used in electronic products with a memory function, such as smart phones, tablet computers, digital cameras, universal serial bus flash memory (universal serial bus flash disk, USB flash memory, simply referred to as "USB flash disk"), and the like.
The structure of NOR flash memory is similar to metal-oxide-semiconductor field effect transistors (MOSFETs, hereinafter simply "MOS") which enable storage of charge by the addition of floating gates and dielectric layers, and are typically used to integrate arrays of cell devices and peripheral circuits on substrates of NOR flash memory. The access of charge in the floating gate causes a change in the threshold voltage of the device, thereby indicating the state of the cell device. An array of cell devices are connected together by lateral gates, called Word Lines (WL), and drains are connected to vertical metal through contact holes (via), called Bit Lines (BL). The sources of two adjacent cell devices are connected together to form a lateral source line.
In general, in the process of manufacturing a NOR flash memory device, after forming a Control Gate (CG) polysilicon layer, the height of the control gate polysilicon layer is higher than that of the polysilicon layer in a peripheral circuit area, which has a larger step difference, so that a subsequent dielectric layer is filled with a dielectric layer with a void (void) defect. In view of this, in the related art, an etching back process of the control gate polysilicon layer of the cell region is added in the process of manufacturing the NOR flash memory device to reduce the height of the control gate polysilicon, so that the difference in the heights of the polysilicon layers of the cell region and the peripheral circuit region can be reduced. However, the etching-back process requires an additional photolithography step (i.e., a mask is required to cover the peripheral circuit region to etch the cell region), which results in complex process and increased manufacturing cost.
Disclosure of Invention
The application provides a manufacturing method of a memory device, which can solve the problem of complex process caused by step difference of polysilicon layers of a cell device area and a peripheral circuit area which are eliminated by photoetching back etching in the related technology, and comprises the following steps:
providing a substrate, wherein the substrate comprises a first area and a second area from a top view, the first area is used for integrating a cell device, the second area is used for integrating a logic device, a first oxide layer is formed on the substrate of the first area, a first polysilicon layer is formed on the first oxide layer, an isolation layer is formed on the first polysilicon layer, a second polysilicon layer is formed on the isolation layer, a second oxide layer is formed on the substrate of the second area, a third polysilicon layer is formed on the second oxide layer, and the height of the second polysilicon layer is higher than that of the third polysilicon layer;
forming a silicon dioxide layer, wherein the silicon dioxide layer covers the second polysilicon layer and the third polysilicon layer;
flattening and removing the silicon dioxide layer of the first area;
reducing the thickness of the second polysilicon layer by etching;
removing the residual silicon dioxide layer by etching;
and removing the second polysilicon layer, the isolation layer and the first polysilicon layer of the target area in the first area through etching to form a groove, wherein the first oxide layer at the bottom of the groove is exposed.
In some embodiments, the removing the remaining silicon dioxide layer by etching includes:
and etching to remove the residual silicon dioxide layer by a wet etching process.
In some embodiments, the difference in height between the second polysilicon layer and the third polysilicon layer is 300 angstroms to 700 angstroms.
In some embodiments, the reducing the thickness of the second polysilicon layer by etching includes:
and etching through a wet etching process to reduce the thickness of the second polysilicon layer.
In some embodiments, the first region includes a first sub-region and a second sub-region, a trench is formed in a first polysilicon layer of the first sub-region, and a first STI structure is formed in a substrate at a bottom of the trench.
In some embodiments, a second STI structure is formed in the substrate of the second region, the second STI structure being annular in shape from a top view, and a region surrounded by the second STI structure being an active region of the logic device. .
The technical scheme of the application at least comprises the following advantages:
in the manufacturing process of the memory device, after the second polysilicon layer of the cell area and the third polysilicon layer of the peripheral circuit area are formed, the second polysilicon layer and the third polysilicon layer are covered by forming a silicon dioxide layer, flattening the silicon dioxide layer until the second polysilicon layer of the cell area is exposed, and etching the second polysilicon layer to thin the second polysilicon layer.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method of fabricating a memory device according to an exemplary embodiment of the present application;
fig. 2 to 7 are schematic views illustrating fabrication of a memory device according to an exemplary embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the application are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present application described below may be combined with each other as long as they do not collide with each other.
Referring to fig. 1, a flowchart of a method for manufacturing a memory device according to an exemplary embodiment of the present application is shown, and as shown in fig. 1, the method includes:
step S1, providing a substrate, wherein the substrate comprises a first area and a second area from the overlooking angle, the first area is used for integrating a cell device, the second area is used for integrating a logic device, a first oxide layer is formed on the substrate of the first area, a first polysilicon layer is formed on the first oxide layer, an isolation layer is formed on the first polysilicon layer, a second polysilicon layer is formed on the isolation layer, a second oxide layer is formed on the substrate of the second area, a third polysilicon layer is formed on the second oxide layer, and the height of the second polysilicon layer is higher than that of the third polysilicon layer.
Referring to fig. 2, a schematic cross-sectional view is shown prior to formation of a silicon dioxide layer. Exemplary, as shown in FIG. 2, the substrate 210 includes a first region 201 and a second region 202 from a top view, the first region 201 is used for integrating a cell device, the second region 202 is used for integrating a logic device, a first oxide layer 231 is formed on the substrate 210 of the first region 201, a first polysilicon layer 241 is formed on the first oxide layer 231, an isolation layer 250 is formed on the first polysilicon layer 241, a second polysilicon layer 242 is formed on the isolation layer 250, a second oxide layer 232 is formed on the substrate 210 of the second region 202, a third polysilicon layer 243 is formed on the second oxide layer 232, the first polysilicon layer 241 is used for forming a floating gate of the cell device, the second polysilicon layer 242 is used for forming a control gate of the cell device, the third polysilicon layer 243 is used for forming a gate of the logic device, the second polysilicon layer 243 is higher than the third polysilicon layer 243, and the difference between the second polysilicon layer 242 and the third polysilicon layer 243 is 300 angstromsTo 700 angstroms.
Wherein, the thickness of the second oxide layer 232 is greater than the thickness of the first oxide layer 231; the first region 201 includes a first sub-region 2011 and a second sub-region 2012, a trench is formed in the first polysilicon layer 241 of the first sub-region 2011, and a first STI structure 221 is formed in the substrate 210 at the bottom of the trench; the first oxide layer 231 and the second oxide layer 232 include silicon dioxide (SiO 2 ) The isolation layer 250 may include an oxide-nitride-oxide (ONO) layer; the second STI structure 222 is formed in the substrate 210 of the second region 202, the second STI structure 222 is annular in shape in a top view, and a region surrounded by the second STI structure 222 is an active area of the logic device.
A deep N-type well (DNW) region 211 is formed in the substrate 210, a first high voltage P-type well (HVPW) region 2121 is formed in the deep N-type well region 211 of the first region 201, and a threshold voltage adjustment implant (threshold voltage, CVT) region 214 is formed in the first high voltage P-type well region 2121; the second region 202 includes a third sub-region 2021 and a fourth sub-region 2022, a high voltage N-type well (HVNW) region 213 is formed in the deep N-type well region 211 of the third sub-region 2021, and a second high voltage P-type well region 2122 is formed in the deep N-type well region 211 of the fourth sub-region 2022.
And S2, forming a silicon dioxide layer, wherein the silicon dioxide layer covers the second polysilicon layer and the third polysilicon layer.
Referring to fig. 3, a schematic cross-sectional view after formation of a silicon dioxide layer is shown. Illustratively, as shown in fig. 3, the silicon dioxide layer 260 may be deposited by a chemical vapor deposition (chemical vapor deposition, CVD) process.
And S3, flattening and removing the silicon dioxide layer in the first area.
Referring to fig. 4, a schematic cross-sectional view of a planarized silicon dioxide layer is shown. Illustratively, as shown in fig. 4, planarization may be performed by a chemical mechanical polishing (chemical mechanical planarization, CMP) process until the second polysilicon layer 242 of the first region 201 is exposed.
And S4, reducing the thickness of the second polysilicon layer through etching.
Referring to fig. 5, a schematic cross-sectional view is shown after the thickness of the second polysilicon layer is reduced by etching. Illustratively, as shown in fig. 5, the thickness of the second polysilicon layer 242 may be reduced by etching through a wet etching process, in which the etched rate of silicon is greater than the etched rate of silicon dioxide, such that the reduced rate of the thickness of the second polysilicon layer 242 is greater than the reduced rate of the thickness of the silicon dioxide layer 260, and such that the upper surface of the second polysilicon layer 242 is flush with the upper surface of the silicon dioxide layer 260.
And S5, removing the residual silicon dioxide layer by etching.
Referring to fig. 6, a schematic cross-sectional view is shown after etching to remove the remaining silicon dioxide layer. Illustratively, as shown in fig. 6, the remaining silicon dioxide layer 260 may be etched away by a wet etching process in which the etched rate of silicon dioxide is greater than the etching rate of silicon, such that the remaining silicon dioxide layer 260 is removed.
And S6, removing the second polysilicon layer, the isolation layer and the first polysilicon layer of the target area in the first area through etching to form a groove, wherein the first oxide layer at the bottom of the groove is exposed.
Referring to fig. 7, a schematic cross-sectional view of the first region after etching to remove the second polysilicon layer, the isolation layer and the first polysilicon layer of the target region is shown. As shown in fig. 7, the photoresist may be covered by a photolithography process to expose the target area (the area corresponding to the trench 300), and etching is performed to remove the second polysilicon layer 242, the isolation layer 250 and the first polysilicon layer 241 of the target area in the first area 201, so as to form the trench 300, and the first oxide layer 231 at the bottom of the trench 300 is exposed, thereby removing the photoresist.
In summary, in the embodiment of the present application, after the second polysilicon layer of the cell region and the third polysilicon layer of the peripheral circuit region are formed in the manufacturing process of the memory device, the silicon dioxide layer is formed to cover the second polysilicon layer and the third polysilicon layer, and planarized until the second polysilicon layer of the cell region is exposed, and then the second polysilicon layer is etched to be thinned, so that the step difference between the polysilicon layers is reduced without an additional photolithography process, the problem of complex process caused by photolithography back etching in the related art is solved, and the manufacturing cost is reduced to a certain extent.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the application.
Claims (6)
1. A method of fabricating a memory device, comprising:
providing a substrate, wherein the substrate comprises a first area and a second area from a top view, the first area is used for integrating a cell device, the second area is used for integrating a logic device, a first oxide layer is formed on the substrate of the first area, a first polysilicon layer is formed on the first oxide layer, an isolation layer is formed on the first polysilicon layer, a second polysilicon layer is formed on the isolation layer, a second oxide layer is formed on the substrate of the second area, a third polysilicon layer is formed on the second oxide layer, and the height of the second polysilicon layer is higher than that of the third polysilicon layer;
forming a silicon dioxide layer, wherein the silicon dioxide layer covers the second polysilicon layer and the third polysilicon layer;
flattening and removing the silicon dioxide layer of the first area;
reducing the thickness of the second polysilicon layer by etching;
removing the residual silicon dioxide layer by etching;
and removing the second polysilicon layer, the isolation layer and the first polysilicon layer of the target area in the first area through etching to form a groove, wherein the first oxide layer at the bottom of the groove is exposed.
2. The method of claim 1, wherein the removing the remaining silicon dioxide layer by etching comprises:
and etching to remove the residual silicon dioxide layer by a wet etching process.
3. The method of claim 2, wherein a height difference between the second polysilicon layer and the third polysilicon layer is 300 angstroms to 700 angstroms.
4. The method of claim 3, wherein the reducing the thickness of the second polysilicon layer by etching comprises:
and etching through a wet etching process to reduce the thickness of the second polysilicon layer.
5. The method of any of claims 1 to 4, wherein the first region comprises a first sub-region and a second sub-region, a trench is formed in a first polysilicon layer of the first sub-region, and a first STI structure is formed in a substrate at a bottom of the trench.
6. The method of claim 5, wherein a second STI structure is formed in the substrate of the second region, the second STI structure being annular in shape from a top view, and a region surrounded by the second STI structure being an active area of the logic device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311096706.8A CN117082857A (en) | 2023-08-29 | 2023-08-29 | Manufacturing method of memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311096706.8A CN117082857A (en) | 2023-08-29 | 2023-08-29 | Manufacturing method of memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117082857A true CN117082857A (en) | 2023-11-17 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202311096706.8A Pending CN117082857A (en) | 2023-08-29 | 2023-08-29 | Manufacturing method of memory device |
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| CN (1) | CN117082857A (en) |
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- 2023-08-29 CN CN202311096706.8A patent/CN117082857A/en active Pending
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